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1#ifndef _ASM_X86_TLBFLUSH_H
2#define _ASM_X86_TLBFLUSH_H
3
4#include <linux/mm.h>
5#include <linux/sched.h>
6
7#include <asm/processor.h>
8#include <asm/cpufeature.h>
9#include <asm/special_insns.h>
10
11static inline void __invpcid(unsigned long pcid, unsigned long addr,
12 unsigned long type)
13{
14 struct { u64 d[2]; } desc = { { pcid, addr } };
15
16 /*
17 * The memory clobber is because the whole point is to invalidate
18 * stale TLB entries and, especially if we're flushing global
19 * mappings, we don't want the compiler to reorder any subsequent
20 * memory accesses before the TLB flush.
21 *
22 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
23 * invpcid (%rcx), %rax in long mode.
24 */
25 asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
26 : : "m" (desc), "a" (type), "c" (&desc) : "memory");
27}
28
29#define INVPCID_TYPE_INDIV_ADDR 0
30#define INVPCID_TYPE_SINGLE_CTXT 1
31#define INVPCID_TYPE_ALL_INCL_GLOBAL 2
32#define INVPCID_TYPE_ALL_NON_GLOBAL 3
33
34/* Flush all mappings for a given pcid and addr, not including globals. */
35static inline void invpcid_flush_one(unsigned long pcid,
36 unsigned long addr)
37{
38 __invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
39}
40
41/* Flush all mappings for a given PCID, not including globals. */
42static inline void invpcid_flush_single_context(unsigned long pcid)
43{
44 __invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
45}
46
47/* Flush all mappings, including globals, for all PCIDs. */
48static inline void invpcid_flush_all(void)
49{
50 __invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
51}
52
53/* Flush all mappings for all PCIDs except globals. */
54static inline void invpcid_flush_all_nonglobals(void)
55{
56 __invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
57}
58
59#ifdef CONFIG_PARAVIRT
60#include <asm/paravirt.h>
61#else
62#define __flush_tlb() __native_flush_tlb()
63#define __flush_tlb_global() __native_flush_tlb_global()
64#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
65#endif
66
67struct tlb_state {
68#ifdef CONFIG_SMP
69 struct mm_struct *active_mm;
70 int state;
71#endif
72
73 /*
74 * Access to this CR4 shadow and to H/W CR4 is protected by
75 * disabling interrupts when modifying either one.
76 */
77 unsigned long cr4;
78};
79DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
80
81/* Initialize cr4 shadow for this CPU. */
82static inline void cr4_init_shadow(void)
83{
84 this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
85}
86
87/* Set in this cpu's CR4. */
88static inline void cr4_set_bits(unsigned long mask)
89{
90 unsigned long cr4;
91
92 cr4 = this_cpu_read(cpu_tlbstate.cr4);
93 if ((cr4 | mask) != cr4) {
94 cr4 |= mask;
95 this_cpu_write(cpu_tlbstate.cr4, cr4);
96 __write_cr4(cr4);
97 }
98}
99
100/* Clear in this cpu's CR4. */
101static inline void cr4_clear_bits(unsigned long mask)
102{
103 unsigned long cr4;
104
105 cr4 = this_cpu_read(cpu_tlbstate.cr4);
106 if ((cr4 & ~mask) != cr4) {
107 cr4 &= ~mask;
108 this_cpu_write(cpu_tlbstate.cr4, cr4);
109 __write_cr4(cr4);
110 }
111}
112
113/* Read the CR4 shadow. */
114static inline unsigned long cr4_read_shadow(void)
115{
116 return this_cpu_read(cpu_tlbstate.cr4);
117}
118
119/*
120 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
121 * enable and PPro Global page enable), so that any CPU's that boot
122 * up after us can get the correct flags. This should only be used
123 * during boot on the boot cpu.
124 */
125extern unsigned long mmu_cr4_features;
126extern u32 *trampoline_cr4_features;
127
128static inline void cr4_set_bits_and_update_boot(unsigned long mask)
129{
130 mmu_cr4_features |= mask;
131 if (trampoline_cr4_features)
132 *trampoline_cr4_features = mmu_cr4_features;
133 cr4_set_bits(mask);
134}
135
136static inline void __native_flush_tlb(void)
137{
138 /*
139 * If current->mm == NULL then we borrow a mm which may change during a
140 * task switch and therefore we must not be preempted while we write CR3
141 * back:
142 */
143 preempt_disable();
144 native_write_cr3(native_read_cr3());
145 preempt_enable();
146}
147
148static inline void __native_flush_tlb_global_irq_disabled(void)
149{
150 unsigned long cr4;
151
152 cr4 = this_cpu_read(cpu_tlbstate.cr4);
153 /* clear PGE */
154 native_write_cr4(cr4 & ~X86_CR4_PGE);
155 /* write old PGE again and flush TLBs */
156 native_write_cr4(cr4);
157}
158
159static inline void __native_flush_tlb_global(void)
160{
161 unsigned long flags;
162
163 if (static_cpu_has(X86_FEATURE_INVPCID)) {
164 /*
165 * Using INVPCID is considerably faster than a pair of writes
166 * to CR4 sandwiched inside an IRQ flag save/restore.
167 */
168 invpcid_flush_all();
169 return;
170 }
171
172 /*
173 * Read-modify-write to CR4 - protect it from preemption and
174 * from interrupts. (Use the raw variant because this code can
175 * be called from deep inside debugging code.)
176 */
177 raw_local_irq_save(flags);
178
179 __native_flush_tlb_global_irq_disabled();
180
181 raw_local_irq_restore(flags);
182}
183
184static inline void __native_flush_tlb_single(unsigned long addr)
185{
186 asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
187}
188
189static inline void __flush_tlb_all(void)
190{
191 if (boot_cpu_has(X86_FEATURE_PGE))
192 __flush_tlb_global();
193 else
194 __flush_tlb();
195}
196
197static inline void __flush_tlb_one(unsigned long addr)
198{
199 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
200 __flush_tlb_single(addr);
201}
202
203#define TLB_FLUSH_ALL -1UL
204
205/*
206 * TLB flushing:
207 *
208 * - flush_tlb() flushes the current mm struct TLBs
209 * - flush_tlb_all() flushes all processes TLBs
210 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
211 * - flush_tlb_page(vma, vmaddr) flushes one page
212 * - flush_tlb_range(vma, start, end) flushes a range of pages
213 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
214 * - flush_tlb_others(cpumask, mm, start, end) flushes TLBs on other cpus
215 *
216 * ..but the i386 has somewhat limited tlb flushing capabilities,
217 * and page-granular flushes are available only on i486 and up.
218 */
219
220#ifndef CONFIG_SMP
221
222/* "_up" is for UniProcessor.
223 *
224 * This is a helper for other header functions. *Not* intended to be called
225 * directly. All global TLB flushes need to either call this, or to bump the
226 * vm statistics themselves.
227 */
228static inline void __flush_tlb_up(void)
229{
230 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
231 __flush_tlb();
232}
233
234static inline void flush_tlb_all(void)
235{
236 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
237 __flush_tlb_all();
238}
239
240static inline void flush_tlb(void)
241{
242 __flush_tlb_up();
243}
244
245static inline void local_flush_tlb(void)
246{
247 __flush_tlb_up();
248}
249
250static inline void flush_tlb_mm(struct mm_struct *mm)
251{
252 if (mm == current->active_mm)
253 __flush_tlb_up();
254}
255
256static inline void flush_tlb_page(struct vm_area_struct *vma,
257 unsigned long addr)
258{
259 if (vma->vm_mm == current->active_mm)
260 __flush_tlb_one(addr);
261}
262
263static inline void flush_tlb_range(struct vm_area_struct *vma,
264 unsigned long start, unsigned long end)
265{
266 if (vma->vm_mm == current->active_mm)
267 __flush_tlb_up();
268}
269
270static inline void flush_tlb_mm_range(struct mm_struct *mm,
271 unsigned long start, unsigned long end, unsigned long vmflag)
272{
273 if (mm == current->active_mm)
274 __flush_tlb_up();
275}
276
277static inline void native_flush_tlb_others(const struct cpumask *cpumask,
278 struct mm_struct *mm,
279 unsigned long start,
280 unsigned long end)
281{
282}
283
284static inline void reset_lazy_tlbstate(void)
285{
286}
287
288static inline void flush_tlb_kernel_range(unsigned long start,
289 unsigned long end)
290{
291 flush_tlb_all();
292}
293
294#else /* SMP */
295
296#include <asm/smp.h>
297
298#define local_flush_tlb() __flush_tlb()
299
300#define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
301
302#define flush_tlb_range(vma, start, end) \
303 flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
304
305extern void flush_tlb_all(void);
306extern void flush_tlb_current_task(void);
307extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
308extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
309 unsigned long end, unsigned long vmflag);
310extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
311
312#define flush_tlb() flush_tlb_current_task()
313
314void native_flush_tlb_others(const struct cpumask *cpumask,
315 struct mm_struct *mm,
316 unsigned long start, unsigned long end);
317
318#define TLBSTATE_OK 1
319#define TLBSTATE_LAZY 2
320
321static inline void reset_lazy_tlbstate(void)
322{
323 this_cpu_write(cpu_tlbstate.state, 0);
324 this_cpu_write(cpu_tlbstate.active_mm, &init_mm);
325}
326
327#endif /* SMP */
328
329#ifndef CONFIG_PARAVIRT
330#define flush_tlb_others(mask, mm, start, end) \
331 native_flush_tlb_others(mask, mm, start, end)
332#endif
333
334#endif /* _ASM_X86_TLBFLUSH_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_TLBFLUSH_H
3#define _ASM_X86_TLBFLUSH_H
4
5#include <linux/mm.h>
6#include <linux/sched.h>
7
8#include <asm/processor.h>
9#include <asm/cpufeature.h>
10#include <asm/special_insns.h>
11#include <asm/smp.h>
12#include <asm/invpcid.h>
13#include <asm/pti.h>
14#include <asm/processor-flags.h>
15
16void __flush_tlb_all(void);
17
18#define TLB_FLUSH_ALL -1UL
19#define TLB_GENERATION_INVALID 0
20
21void cr4_update_irqsoff(unsigned long set, unsigned long clear);
22unsigned long cr4_read_shadow(void);
23
24/* Set in this cpu's CR4. */
25static inline void cr4_set_bits_irqsoff(unsigned long mask)
26{
27 cr4_update_irqsoff(mask, 0);
28}
29
30/* Clear in this cpu's CR4. */
31static inline void cr4_clear_bits_irqsoff(unsigned long mask)
32{
33 cr4_update_irqsoff(0, mask);
34}
35
36/* Set in this cpu's CR4. */
37static inline void cr4_set_bits(unsigned long mask)
38{
39 unsigned long flags;
40
41 local_irq_save(flags);
42 cr4_set_bits_irqsoff(mask);
43 local_irq_restore(flags);
44}
45
46/* Clear in this cpu's CR4. */
47static inline void cr4_clear_bits(unsigned long mask)
48{
49 unsigned long flags;
50
51 local_irq_save(flags);
52 cr4_clear_bits_irqsoff(mask);
53 local_irq_restore(flags);
54}
55
56#ifndef MODULE
57/*
58 * 6 because 6 should be plenty and struct tlb_state will fit in two cache
59 * lines.
60 */
61#define TLB_NR_DYN_ASIDS 6
62
63struct tlb_context {
64 u64 ctx_id;
65 u64 tlb_gen;
66};
67
68struct tlb_state {
69 /*
70 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
71 * are on. This means that it may not match current->active_mm,
72 * which will contain the previous user mm when we're in lazy TLB
73 * mode even if we've already switched back to swapper_pg_dir.
74 *
75 * During switch_mm_irqs_off(), loaded_mm will be set to
76 * LOADED_MM_SWITCHING during the brief interrupts-off window
77 * when CR3 and loaded_mm would otherwise be inconsistent. This
78 * is for nmi_uaccess_okay()'s benefit.
79 */
80 struct mm_struct *loaded_mm;
81
82#define LOADED_MM_SWITCHING ((struct mm_struct *)1UL)
83
84 /* Last user mm for optimizing IBPB */
85 union {
86 struct mm_struct *last_user_mm;
87 unsigned long last_user_mm_spec;
88 };
89
90 u16 loaded_mm_asid;
91 u16 next_asid;
92
93 /*
94 * If set we changed the page tables in such a way that we
95 * needed an invalidation of all contexts (aka. PCIDs / ASIDs).
96 * This tells us to go invalidate all the non-loaded ctxs[]
97 * on the next context switch.
98 *
99 * The current ctx was kept up-to-date as it ran and does not
100 * need to be invalidated.
101 */
102 bool invalidate_other;
103
104 /*
105 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
106 * the corresponding user PCID needs a flush next time we
107 * switch to it; see SWITCH_TO_USER_CR3.
108 */
109 unsigned short user_pcid_flush_mask;
110
111 /*
112 * Access to this CR4 shadow and to H/W CR4 is protected by
113 * disabling interrupts when modifying either one.
114 */
115 unsigned long cr4;
116
117 /*
118 * This is a list of all contexts that might exist in the TLB.
119 * There is one per ASID that we use, and the ASID (what the
120 * CPU calls PCID) is the index into ctxts.
121 *
122 * For each context, ctx_id indicates which mm the TLB's user
123 * entries came from. As an invariant, the TLB will never
124 * contain entries that are out-of-date as when that mm reached
125 * the tlb_gen in the list.
126 *
127 * To be clear, this means that it's legal for the TLB code to
128 * flush the TLB without updating tlb_gen. This can happen
129 * (for now, at least) due to paravirt remote flushes.
130 *
131 * NB: context 0 is a bit special, since it's also used by
132 * various bits of init code. This is fine -- code that
133 * isn't aware of PCID will end up harmlessly flushing
134 * context 0.
135 */
136 struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
137};
138DECLARE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate);
139
140struct tlb_state_shared {
141 /*
142 * We can be in one of several states:
143 *
144 * - Actively using an mm. Our CPU's bit will be set in
145 * mm_cpumask(loaded_mm) and is_lazy == false;
146 *
147 * - Not using a real mm. loaded_mm == &init_mm. Our CPU's bit
148 * will not be set in mm_cpumask(&init_mm) and is_lazy == false.
149 *
150 * - Lazily using a real mm. loaded_mm != &init_mm, our bit
151 * is set in mm_cpumask(loaded_mm), but is_lazy == true.
152 * We're heuristically guessing that the CR3 load we
153 * skipped more than makes up for the overhead added by
154 * lazy mode.
155 */
156 bool is_lazy;
157};
158DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state_shared, cpu_tlbstate_shared);
159
160bool nmi_uaccess_okay(void);
161#define nmi_uaccess_okay nmi_uaccess_okay
162
163/* Initialize cr4 shadow for this CPU. */
164static inline void cr4_init_shadow(void)
165{
166 this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
167}
168
169extern unsigned long mmu_cr4_features;
170extern u32 *trampoline_cr4_features;
171
172extern void initialize_tlbstate_and_flush(void);
173
174/*
175 * TLB flushing:
176 *
177 * - flush_tlb_all() flushes all processes TLBs
178 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
179 * - flush_tlb_page(vma, vmaddr) flushes one page
180 * - flush_tlb_range(vma, start, end) flushes a range of pages
181 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
182 * - flush_tlb_multi(cpumask, info) flushes TLBs on multiple cpus
183 *
184 * ..but the i386 has somewhat limited tlb flushing capabilities,
185 * and page-granular flushes are available only on i486 and up.
186 */
187struct flush_tlb_info {
188 /*
189 * We support several kinds of flushes.
190 *
191 * - Fully flush a single mm. .mm will be set, .end will be
192 * TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
193 * which the IPI sender is trying to catch us up.
194 *
195 * - Partially flush a single mm. .mm will be set, .start and
196 * .end will indicate the range, and .new_tlb_gen will be set
197 * such that the changes between generation .new_tlb_gen-1 and
198 * .new_tlb_gen are entirely contained in the indicated range.
199 *
200 * - Fully flush all mms whose tlb_gens have been updated. .mm
201 * will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
202 * will be zero.
203 */
204 struct mm_struct *mm;
205 unsigned long start;
206 unsigned long end;
207 u64 new_tlb_gen;
208 unsigned int initiating_cpu;
209 u8 stride_shift;
210 u8 freed_tables;
211};
212
213void flush_tlb_local(void);
214void flush_tlb_one_user(unsigned long addr);
215void flush_tlb_one_kernel(unsigned long addr);
216void flush_tlb_multi(const struct cpumask *cpumask,
217 const struct flush_tlb_info *info);
218
219#ifdef CONFIG_PARAVIRT
220#include <asm/paravirt.h>
221#endif
222
223#define flush_tlb_mm(mm) \
224 flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL, true)
225
226#define flush_tlb_range(vma, start, end) \
227 flush_tlb_mm_range((vma)->vm_mm, start, end, \
228 ((vma)->vm_flags & VM_HUGETLB) \
229 ? huge_page_shift(hstate_vma(vma)) \
230 : PAGE_SHIFT, false)
231
232extern void flush_tlb_all(void);
233extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
234 unsigned long end, unsigned int stride_shift,
235 bool freed_tables);
236extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
237
238static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
239{
240 flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, PAGE_SHIFT, false);
241}
242
243static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
244{
245 /*
246 * Bump the generation count. This also serves as a full barrier
247 * that synchronizes with switch_mm(): callers are required to order
248 * their read of mm_cpumask after their writes to the paging
249 * structures.
250 */
251 return atomic64_inc_return(&mm->context.tlb_gen);
252}
253
254static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
255 struct mm_struct *mm)
256{
257 inc_mm_tlb_gen(mm);
258 cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
259}
260
261extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
262
263static inline bool pte_flags_need_flush(unsigned long oldflags,
264 unsigned long newflags,
265 bool ignore_access)
266{
267 /*
268 * Flags that require a flush when cleared but not when they are set.
269 * Only include flags that would not trigger spurious page-faults.
270 * Non-present entries are not cached. Hardware would set the
271 * dirty/access bit if needed without a fault.
272 */
273 const pteval_t flush_on_clear = _PAGE_DIRTY | _PAGE_PRESENT |
274 _PAGE_ACCESSED;
275 const pteval_t software_flags = _PAGE_SOFTW1 | _PAGE_SOFTW2 |
276 _PAGE_SOFTW3 | _PAGE_SOFTW4;
277 const pteval_t flush_on_change = _PAGE_RW | _PAGE_USER | _PAGE_PWT |
278 _PAGE_PCD | _PAGE_PSE | _PAGE_GLOBAL | _PAGE_PAT |
279 _PAGE_PAT_LARGE | _PAGE_PKEY_BIT0 | _PAGE_PKEY_BIT1 |
280 _PAGE_PKEY_BIT2 | _PAGE_PKEY_BIT3 | _PAGE_NX;
281 unsigned long diff = oldflags ^ newflags;
282
283 BUILD_BUG_ON(flush_on_clear & software_flags);
284 BUILD_BUG_ON(flush_on_clear & flush_on_change);
285 BUILD_BUG_ON(flush_on_change & software_flags);
286
287 /* Ignore software flags */
288 diff &= ~software_flags;
289
290 if (ignore_access)
291 diff &= ~_PAGE_ACCESSED;
292
293 /*
294 * Did any of the 'flush_on_clear' flags was clleared set from between
295 * 'oldflags' and 'newflags'?
296 */
297 if (diff & oldflags & flush_on_clear)
298 return true;
299
300 /* Flush on modified flags. */
301 if (diff & flush_on_change)
302 return true;
303
304 /* Ensure there are no flags that were left behind */
305 if (IS_ENABLED(CONFIG_DEBUG_VM) &&
306 (diff & ~(flush_on_clear | software_flags | flush_on_change))) {
307 VM_WARN_ON_ONCE(1);
308 return true;
309 }
310
311 return false;
312}
313
314/*
315 * pte_needs_flush() checks whether permissions were demoted and require a
316 * flush. It should only be used for userspace PTEs.
317 */
318static inline bool pte_needs_flush(pte_t oldpte, pte_t newpte)
319{
320 /* !PRESENT -> * ; no need for flush */
321 if (!(pte_flags(oldpte) & _PAGE_PRESENT))
322 return false;
323
324 /* PFN changed ; needs flush */
325 if (pte_pfn(oldpte) != pte_pfn(newpte))
326 return true;
327
328 /*
329 * check PTE flags; ignore access-bit; see comment in
330 * ptep_clear_flush_young().
331 */
332 return pte_flags_need_flush(pte_flags(oldpte), pte_flags(newpte),
333 true);
334}
335#define pte_needs_flush pte_needs_flush
336
337/*
338 * huge_pmd_needs_flush() checks whether permissions were demoted and require a
339 * flush. It should only be used for userspace huge PMDs.
340 */
341static inline bool huge_pmd_needs_flush(pmd_t oldpmd, pmd_t newpmd)
342{
343 /* !PRESENT -> * ; no need for flush */
344 if (!(pmd_flags(oldpmd) & _PAGE_PRESENT))
345 return false;
346
347 /* PFN changed ; needs flush */
348 if (pmd_pfn(oldpmd) != pmd_pfn(newpmd))
349 return true;
350
351 /*
352 * check PMD flags; do not ignore access-bit; see
353 * pmdp_clear_flush_young().
354 */
355 return pte_flags_need_flush(pmd_flags(oldpmd), pmd_flags(newpmd),
356 false);
357}
358#define huge_pmd_needs_flush huge_pmd_needs_flush
359
360#endif /* !MODULE */
361
362static inline void __native_tlb_flush_global(unsigned long cr4)
363{
364 native_write_cr4(cr4 ^ X86_CR4_PGE);
365 native_write_cr4(cr4);
366}
367#endif /* _ASM_X86_TLBFLUSH_H */