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1/*
2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#ifndef _PM8001_SAS_H_
42#define _PM8001_SAS_H_
43
44#include <linux/kernel.h>
45#include <linux/module.h>
46#include <linux/spinlock.h>
47#include <linux/delay.h>
48#include <linux/types.h>
49#include <linux/ctype.h>
50#include <linux/dma-mapping.h>
51#include <linux/pci.h>
52#include <linux/interrupt.h>
53#include <linux/workqueue.h>
54#include <scsi/libsas.h>
55#include <scsi/scsi_tcq.h>
56#include <scsi/sas_ata.h>
57#include <linux/atomic.h>
58#include "pm8001_defs.h"
59
60#define DRV_NAME "pm80xx"
61#define DRV_VERSION "0.1.38"
62#define PM8001_FAIL_LOGGING 0x01 /* Error message logging */
63#define PM8001_INIT_LOGGING 0x02 /* driver init logging */
64#define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */
65#define PM8001_IO_LOGGING 0x08 /* I/O path logging */
66#define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/
67#define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */
68#define PM8001_MSG_LOGGING 0x40 /* misc message logging */
69#define pm8001_printk(format, arg...) printk(KERN_INFO "pm80xx %s %d:" \
70 format, __func__, __LINE__, ## arg)
71#define PM8001_CHECK_LOGGING(HBA, LEVEL, CMD) \
72do { \
73 if (unlikely(HBA->logging_level & LEVEL)) \
74 do { \
75 CMD; \
76 } while (0); \
77} while (0);
78
79#define PM8001_EH_DBG(HBA, CMD) \
80 PM8001_CHECK_LOGGING(HBA, PM8001_EH_LOGGING, CMD)
81
82#define PM8001_INIT_DBG(HBA, CMD) \
83 PM8001_CHECK_LOGGING(HBA, PM8001_INIT_LOGGING, CMD)
84
85#define PM8001_DISC_DBG(HBA, CMD) \
86 PM8001_CHECK_LOGGING(HBA, PM8001_DISC_LOGGING, CMD)
87
88#define PM8001_IO_DBG(HBA, CMD) \
89 PM8001_CHECK_LOGGING(HBA, PM8001_IO_LOGGING, CMD)
90
91#define PM8001_FAIL_DBG(HBA, CMD) \
92 PM8001_CHECK_LOGGING(HBA, PM8001_FAIL_LOGGING, CMD)
93
94#define PM8001_IOCTL_DBG(HBA, CMD) \
95 PM8001_CHECK_LOGGING(HBA, PM8001_IOCTL_LOGGING, CMD)
96
97#define PM8001_MSG_DBG(HBA, CMD) \
98 PM8001_CHECK_LOGGING(HBA, PM8001_MSG_LOGGING, CMD)
99
100
101#define PM8001_USE_TASKLET
102#define PM8001_USE_MSIX
103#define PM8001_READ_VPD
104
105
106#define DEV_IS_EXPANDER(type) ((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))
107#define IS_SPCV_12G(dev) ((dev->device == 0X8074) \
108 || (dev->device == 0X8076) \
109 || (dev->device == 0X8077) \
110 || (dev->device == 0X8070) \
111 || (dev->device == 0X8072))
112
113#define PM8001_NAME_LENGTH 32/* generic length of strings */
114extern struct list_head hba_list;
115extern const struct pm8001_dispatch pm8001_8001_dispatch;
116extern const struct pm8001_dispatch pm8001_80xx_dispatch;
117
118struct pm8001_hba_info;
119struct pm8001_ccb_info;
120struct pm8001_device;
121/* define task management IU */
122struct pm8001_tmf_task {
123 u8 tmf;
124 u32 tag_of_task_to_be_managed;
125};
126struct pm8001_ioctl_payload {
127 u32 signature;
128 u16 major_function;
129 u16 minor_function;
130 u16 length;
131 u16 status;
132 u16 offset;
133 u16 id;
134 u8 *func_specific;
135};
136
137#define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
138#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
139#define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */
140#define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */
141#define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */
142#define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */
143#define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */
144#define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */
145#define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1
146#define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0
147#define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0
148#define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1
149#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
150#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3
151#define TYPE_GSM_SPACE 1
152#define TYPE_QUEUE 2
153#define TYPE_FATAL 3
154#define TYPE_NON_FATAL 4
155#define TYPE_INBOUND 1
156#define TYPE_OUTBOUND 2
157struct forensic_data {
158 u32 data_type;
159 union {
160 struct {
161 u32 direct_len;
162 u32 direct_offset;
163 void *direct_data;
164 } gsm_buf;
165 struct {
166 u16 queue_type;
167 u16 queue_index;
168 u32 direct_len;
169 void *direct_data;
170 } queue_buf;
171 struct {
172 u32 direct_len;
173 u32 direct_offset;
174 u32 read_len;
175 void *direct_data;
176 } data_buf;
177 };
178};
179
180/* bit31-26 - mask bar */
181#define SCRATCH_PAD0_BAR_MASK 0xFC000000
182/* bit25-0 - offset mask */
183#define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF
184/* if AAP error state */
185#define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF
186/* Inbound doorbell bit7 */
187#define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80
188/* Inbound doorbell bit7 SPCV */
189#define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80
190#define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */
191
192struct pm8001_dispatch {
193 char *name;
194 int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
195 int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
196 void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
197 int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
198 void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
199 irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
200 u32 (*is_our_interupt)(struct pm8001_hba_info *pm8001_ha);
201 int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
202 void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
203 void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
204 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
205 int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
206 struct pm8001_ccb_info *ccb);
207 int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
208 struct pm8001_ccb_info *ccb);
209 int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
210 struct pm8001_ccb_info *ccb);
211 int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
212 int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
213 int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
214 struct pm8001_device *pm8001_dev, u32 flag);
215 int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
216 int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
217 u32 phy_id, u32 phy_op);
218 int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
219 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag,
220 u32 cmd_tag);
221 int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
222 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf);
223 int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
224 int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
225 int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
226 void *payload);
227 int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
228 struct pm8001_device *pm8001_dev, u32 state);
229 int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
230 u32 state);
231 int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
232 u32 state);
233 int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
234};
235
236struct pm8001_chip_info {
237 u32 encrypt;
238 u32 n_phy;
239 const struct pm8001_dispatch *dispatch;
240};
241#define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch)
242
243struct pm8001_port {
244 struct asd_sas_port sas_port;
245 u8 port_attached;
246 u16 wide_port_phymap;
247 u8 port_state;
248 struct list_head list;
249};
250
251struct pm8001_phy {
252 struct pm8001_hba_info *pm8001_ha;
253 struct pm8001_port *port;
254 struct asd_sas_phy sas_phy;
255 struct sas_identify identify;
256 struct scsi_device *sdev;
257 u64 dev_sas_addr;
258 u32 phy_type;
259 struct completion *enable_completion;
260 u32 frame_rcvd_size;
261 u8 frame_rcvd[32];
262 u8 phy_attached;
263 u8 phy_state;
264 enum sas_linkrate minimum_linkrate;
265 enum sas_linkrate maximum_linkrate;
266};
267
268struct pm8001_device {
269 enum sas_device_type dev_type;
270 struct domain_device *sas_device;
271 u32 attached_phy;
272 u32 id;
273 struct completion *dcompletion;
274 struct completion *setds_completion;
275 u32 device_id;
276 u32 running_req;
277};
278
279struct pm8001_prd_imt {
280 __le32 len;
281 __le32 e;
282};
283
284struct pm8001_prd {
285 __le64 addr; /* 64-bit buffer address */
286 struct pm8001_prd_imt im_len; /* 64-bit length */
287} __attribute__ ((packed));
288/*
289 * CCB(Command Control Block)
290 */
291struct pm8001_ccb_info {
292 struct list_head entry;
293 struct sas_task *task;
294 u32 n_elem;
295 u32 ccb_tag;
296 dma_addr_t ccb_dma_handle;
297 struct pm8001_device *device;
298 struct pm8001_prd buf_prd[PM8001_MAX_DMA_SG];
299 struct fw_control_ex *fw_control_context;
300 u8 open_retry;
301};
302
303struct mpi_mem {
304 void *virt_ptr;
305 dma_addr_t phys_addr;
306 u32 phys_addr_hi;
307 u32 phys_addr_lo;
308 u32 total_len;
309 u32 num_elements;
310 u32 element_size;
311 u32 alignment;
312};
313
314struct mpi_mem_req {
315 /* The number of element in the mpiMemory array */
316 u32 count;
317 /* The array of structures that define memroy regions*/
318 struct mpi_mem region[USI_MAX_MEMCNT];
319};
320
321struct encrypt {
322 u32 cipher_mode;
323 u32 sec_mode;
324 u32 status;
325 u32 flag;
326};
327
328struct sas_phy_attribute_table {
329 u32 phystart1_16[16];
330 u32 outbound_hw_event_pid1_16[16];
331};
332
333union main_cfg_table {
334 struct {
335 u32 signature;
336 u32 interface_rev;
337 u32 firmware_rev;
338 u32 max_out_io;
339 u32 max_sgl;
340 u32 ctrl_cap_flag;
341 u32 gst_offset;
342 u32 inbound_queue_offset;
343 u32 outbound_queue_offset;
344 u32 inbound_q_nppd_hppd;
345 u32 outbound_hw_event_pid0_3;
346 u32 outbound_hw_event_pid4_7;
347 u32 outbound_ncq_event_pid0_3;
348 u32 outbound_ncq_event_pid4_7;
349 u32 outbound_tgt_ITNexus_event_pid0_3;
350 u32 outbound_tgt_ITNexus_event_pid4_7;
351 u32 outbound_tgt_ssp_event_pid0_3;
352 u32 outbound_tgt_ssp_event_pid4_7;
353 u32 outbound_tgt_smp_event_pid0_3;
354 u32 outbound_tgt_smp_event_pid4_7;
355 u32 upper_event_log_addr;
356 u32 lower_event_log_addr;
357 u32 event_log_size;
358 u32 event_log_option;
359 u32 upper_iop_event_log_addr;
360 u32 lower_iop_event_log_addr;
361 u32 iop_event_log_size;
362 u32 iop_event_log_option;
363 u32 fatal_err_interrupt;
364 u32 fatal_err_dump_offset0;
365 u32 fatal_err_dump_length0;
366 u32 fatal_err_dump_offset1;
367 u32 fatal_err_dump_length1;
368 u32 hda_mode_flag;
369 u32 anolog_setup_table_offset;
370 u32 rsvd[4];
371 } pm8001_tbl;
372
373 struct {
374 u32 signature;
375 u32 interface_rev;
376 u32 firmware_rev;
377 u32 max_out_io;
378 u32 max_sgl;
379 u32 ctrl_cap_flag;
380 u32 gst_offset;
381 u32 inbound_queue_offset;
382 u32 outbound_queue_offset;
383 u32 inbound_q_nppd_hppd;
384 u32 rsvd[8];
385 u32 crc_core_dump;
386 u32 rsvd1;
387 u32 upper_event_log_addr;
388 u32 lower_event_log_addr;
389 u32 event_log_size;
390 u32 event_log_severity;
391 u32 upper_pcs_event_log_addr;
392 u32 lower_pcs_event_log_addr;
393 u32 pcs_event_log_size;
394 u32 pcs_event_log_severity;
395 u32 fatal_err_interrupt;
396 u32 fatal_err_dump_offset0;
397 u32 fatal_err_dump_length0;
398 u32 fatal_err_dump_offset1;
399 u32 fatal_err_dump_length1;
400 u32 gpio_led_mapping;
401 u32 analog_setup_table_offset;
402 u32 int_vec_table_offset;
403 u32 phy_attr_table_offset;
404 u32 port_recovery_timer;
405 u32 interrupt_reassertion_delay;
406 u32 fatal_n_non_fatal_dump; /* 0x28 */
407 } pm80xx_tbl;
408};
409
410union general_status_table {
411 struct {
412 u32 gst_len_mpistate;
413 u32 iq_freeze_state0;
414 u32 iq_freeze_state1;
415 u32 msgu_tcnt;
416 u32 iop_tcnt;
417 u32 rsvd;
418 u32 phy_state[8];
419 u32 gpio_input_val;
420 u32 rsvd1[2];
421 u32 recover_err_info[8];
422 } pm8001_tbl;
423 struct {
424 u32 gst_len_mpistate;
425 u32 iq_freeze_state0;
426 u32 iq_freeze_state1;
427 u32 msgu_tcnt;
428 u32 iop_tcnt;
429 u32 rsvd[9];
430 u32 gpio_input_val;
431 u32 rsvd1[2];
432 u32 recover_err_info[8];
433 } pm80xx_tbl;
434};
435struct inbound_queue_table {
436 u32 element_pri_size_cnt;
437 u32 upper_base_addr;
438 u32 lower_base_addr;
439 u32 ci_upper_base_addr;
440 u32 ci_lower_base_addr;
441 u32 pi_pci_bar;
442 u32 pi_offset;
443 u32 total_length;
444 void *base_virt;
445 void *ci_virt;
446 u32 reserved;
447 __le32 consumer_index;
448 u32 producer_idx;
449};
450struct outbound_queue_table {
451 u32 element_size_cnt;
452 u32 upper_base_addr;
453 u32 lower_base_addr;
454 void *base_virt;
455 u32 pi_upper_base_addr;
456 u32 pi_lower_base_addr;
457 u32 ci_pci_bar;
458 u32 ci_offset;
459 u32 total_length;
460 void *pi_virt;
461 u32 interrup_vec_cnt_delay;
462 u32 dinterrup_to_pci_offset;
463 __le32 producer_index;
464 u32 consumer_idx;
465};
466struct pm8001_hba_memspace {
467 void __iomem *memvirtaddr;
468 u64 membase;
469 u32 memsize;
470};
471struct isr_param {
472 struct pm8001_hba_info *drv_inst;
473 u32 irq_id;
474};
475struct pm8001_hba_info {
476 char name[PM8001_NAME_LENGTH];
477 struct list_head list;
478 unsigned long flags;
479 spinlock_t lock;/* host-wide lock */
480 spinlock_t bitmap_lock;
481 struct pci_dev *pdev;/* our device */
482 struct device *dev;
483 struct pm8001_hba_memspace io_mem[6];
484 struct mpi_mem_req memoryMap;
485 struct encrypt encrypt_info; /* support encryption */
486 struct forensic_data forensic_info;
487 u32 fatal_bar_loc;
488 u32 forensic_last_offset;
489 u32 fatal_forensic_shift_offset;
490 u32 forensic_fatal_step;
491 u32 evtlog_ib_offset;
492 u32 evtlog_ob_offset;
493 void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
494 void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
495 void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
496 void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
497 void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
498 void __iomem *pspa_q_tbl_addr;
499 /*MPI SAS PHY attributes Queue Config Table Addr*/
500 void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */
501 void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */
502 union main_cfg_table main_cfg_tbl;
503 union general_status_table gs_tbl;
504 struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_SPCV_INB_NUM];
505 struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_SPCV_OUTB_NUM];
506 struct sas_phy_attribute_table phy_attr_table;
507 /* MPI SAS PHY attributes */
508 u8 sas_addr[SAS_ADDR_SIZE];
509 struct sas_ha_struct *sas;/* SCSI/SAS glue */
510 struct Scsi_Host *shost;
511 u32 chip_id;
512 const struct pm8001_chip_info *chip;
513 struct completion *nvmd_completion;
514 int tags_num;
515 unsigned long *tags;
516 struct pm8001_phy phy[PM8001_MAX_PHYS];
517 struct pm8001_port port[PM8001_MAX_PHYS];
518 u32 id;
519 u32 irq;
520 u32 iomb_size; /* SPC and SPCV IOMB size */
521 struct pm8001_device *devices;
522 struct pm8001_ccb_info *ccb_info;
523#ifdef PM8001_USE_MSIX
524 struct msix_entry msix_entries[PM8001_MAX_MSIX_VEC];
525 /*for msi-x interrupt*/
526 int number_of_intr;/*will be used in remove()*/
527#endif
528#ifdef PM8001_USE_TASKLET
529 struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC];
530#endif
531 u32 logging_level;
532 u32 fw_status;
533 u32 smp_exp_mode;
534 const struct firmware *fw_image;
535 struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
536};
537
538struct pm8001_work {
539 struct work_struct work;
540 struct pm8001_hba_info *pm8001_ha;
541 void *data;
542 int handler;
543};
544
545struct pm8001_fw_image_header {
546 u8 vender_id[8];
547 u8 product_id;
548 u8 hardware_rev;
549 u8 dest_partition;
550 u8 reserved;
551 u8 fw_rev[4];
552 __be32 image_length;
553 __be32 image_crc;
554 __be32 startup_entry;
555} __attribute__((packed, aligned(4)));
556
557
558/**
559 * FW Flash Update status values
560 */
561#define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
562#define FLASH_UPDATE_IN_PROGRESS 0x01
563#define FLASH_UPDATE_HDR_ERR 0x02
564#define FLASH_UPDATE_OFFSET_ERR 0x03
565#define FLASH_UPDATE_CRC_ERR 0x04
566#define FLASH_UPDATE_LENGTH_ERR 0x05
567#define FLASH_UPDATE_HW_ERR 0x06
568#define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
569#define FLASH_UPDATE_DISABLED 0x11
570
571#define NCQ_READ_LOG_FLAG 0x80000000
572#define NCQ_ABORT_ALL_FLAG 0x40000000
573#define NCQ_2ND_RLE_FLAG 0x20000000
574
575/* Device states */
576#define DS_OPERATIONAL 0x01
577#define DS_PORT_IN_RESET 0x02
578#define DS_IN_RECOVERY 0x03
579#define DS_IN_ERROR 0x04
580#define DS_NON_OPERATIONAL 0x07
581
582/**
583 * brief param structure for firmware flash update.
584 */
585struct fw_flash_updata_info {
586 u32 cur_image_offset;
587 u32 cur_image_len;
588 u32 total_image_len;
589 struct pm8001_prd sgl;
590};
591
592struct fw_control_info {
593 u32 retcode;/*ret code (status)*/
594 u32 phase;/*ret code phase*/
595 u32 phaseCmplt;/*percent complete for the current
596 update phase */
597 u32 version;/*Hex encoded firmware version number*/
598 u32 offset;/*Used for downloading firmware */
599 u32 len; /*len of buffer*/
600 u32 size;/* Used in OS VPD and Trace get size
601 operations.*/
602 u32 reserved;/* padding required for 64 bit
603 alignment */
604 u8 buffer[1];/* Start of buffer */
605};
606struct fw_control_ex {
607 struct fw_control_info *fw_control;
608 void *buffer;/* keep buffer pointer to be
609 freed when the response comes*/
610 void *virtAddr;/* keep virtual address of the data */
611 void *usrAddr;/* keep virtual address of the
612 user data */
613 dma_addr_t phys_addr;
614 u32 len; /* len of buffer */
615 void *payload; /* pointer to IOCTL Payload */
616 u8 inProgress;/*if 1 - the IOCTL request is in
617 progress */
618 void *param1;
619 void *param2;
620 void *param3;
621};
622
623/* pm8001 workqueue */
624extern struct workqueue_struct *pm8001_wq;
625
626/******************** function prototype *********************/
627int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
628void pm8001_tag_init(struct pm8001_hba_info *pm8001_ha);
629u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
630void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
631 struct sas_task *task, struct pm8001_ccb_info *ccb, u32 ccb_idx);
632int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
633 void *funcdata);
634void pm8001_scan_start(struct Scsi_Host *shost);
635int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
636int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags);
637int pm8001_abort_task(struct sas_task *task);
638int pm8001_abort_task_set(struct domain_device *dev, u8 *lun);
639int pm8001_clear_aca(struct domain_device *dev, u8 *lun);
640int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
641int pm8001_dev_found(struct domain_device *dev);
642void pm8001_dev_gone(struct domain_device *dev);
643int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
644int pm8001_I_T_nexus_reset(struct domain_device *dev);
645int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
646int pm8001_query_task(struct sas_task *task);
647void pm8001_open_reject_retry(
648 struct pm8001_hba_info *pm8001_ha,
649 struct sas_task *task_to_close,
650 struct pm8001_device *device_to_close);
651int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
652 dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
653 u32 mem_size, u32 align);
654
655void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
656int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
657 struct inbound_queue_table *circularQ,
658 u32 opCode, void *payload, u32 responseQueue);
659int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
660 u16 messageSize, void **messagePtr);
661u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
662 struct outbound_queue_table *circularQ, u8 bc);
663u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
664 struct outbound_queue_table *circularQ,
665 void **messagePtr1, u8 *pBC);
666int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
667 struct pm8001_device *pm8001_dev, u32 state);
668int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
669 void *payload);
670int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
671 void *fw_flash_updata_info, u32 tag);
672int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
673int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
674int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
675 struct pm8001_ccb_info *ccb,
676 struct pm8001_tmf_task *tmf);
677int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
678 struct pm8001_device *pm8001_dev,
679 u8 flag, u32 task_tag, u32 cmd_tag);
680int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
681void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
682void pm8001_work_fn(struct work_struct *work);
683int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
684 void *data, int handler);
685void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
686 void *piomb);
687void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
688 void *piomb);
689void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
690 void *piomb);
691int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
692 void *piomb);
693void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
694void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
695void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
696int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
697int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
698int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
699 void *piomb);
700int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb);
701int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
702struct sas_task *pm8001_alloc_task(void);
703void pm8001_task_done(struct sas_task *task);
704void pm8001_free_task(struct sas_task *task);
705void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
706struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
707 u32 device_id);
708int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
709
710int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
711void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
712 u32 length, u8 *buf);
713void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
714 u32 phy, u32 length, u32 *buf);
715int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
716ssize_t pm80xx_get_fatal_dump(struct device *cdev,
717 struct device_attribute *attr, char *buf);
718ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
719/* ctl shared API */
720extern struct device_attribute *pm8001_host_attrs[];
721
722static inline void
723pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha,
724 struct sas_task *task, struct pm8001_ccb_info *ccb,
725 u32 ccb_idx)
726{
727 pm8001_ccb_task_free(pm8001_ha, task, ccb, ccb_idx);
728 smp_mb(); /*in order to force CPU ordering*/
729 spin_unlock(&pm8001_ha->lock);
730 task->task_done(task);
731 spin_lock(&pm8001_ha->lock);
732}
733
734#endif
735
1/*
2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#ifndef _PM8001_SAS_H_
42#define _PM8001_SAS_H_
43
44#include <linux/kernel.h>
45#include <linux/module.h>
46#include <linux/spinlock.h>
47#include <linux/delay.h>
48#include <linux/types.h>
49#include <linux/ctype.h>
50#include <linux/dma-mapping.h>
51#include <linux/pci.h>
52#include <linux/interrupt.h>
53#include <linux/workqueue.h>
54#include <scsi/libsas.h>
55#include <scsi/scsi_tcq.h>
56#include <scsi/sas_ata.h>
57#include <linux/atomic.h>
58#include <linux/blk-mq.h>
59#include <linux/blk-mq-pci.h>
60#include "pm8001_defs.h"
61
62#define DRV_NAME "pm80xx"
63#define DRV_VERSION "0.1.40"
64#define PM8001_FAIL_LOGGING 0x01 /* Error message logging */
65#define PM8001_INIT_LOGGING 0x02 /* driver init logging */
66#define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */
67#define PM8001_IO_LOGGING 0x08 /* I/O path logging */
68#define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/
69#define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */
70#define PM8001_MSG_LOGGING 0x40 /* misc message logging */
71#define PM8001_DEV_LOGGING 0x80 /* development message logging */
72#define PM8001_DEVIO_LOGGING 0x100 /* development io message logging */
73#define PM8001_IOERR_LOGGING 0x200 /* development io err message logging */
74
75#define pm8001_info(HBA, fmt, ...) \
76 pr_info("%s:: %s %d: " fmt, \
77 (HBA)->name, __func__, __LINE__, ##__VA_ARGS__)
78
79#define pm8001_dbg(HBA, level, fmt, ...) \
80do { \
81 if (unlikely((HBA)->logging_level & PM8001_##level##_LOGGING)) \
82 pm8001_info(HBA, fmt, ##__VA_ARGS__); \
83} while (0)
84
85#define PM8001_USE_TASKLET
86#define PM8001_USE_MSIX
87#define PM8001_READ_VPD
88
89
90#define IS_SPCV_12G(dev) ((dev->device == 0X8074) \
91 || (dev->device == 0X8076) \
92 || (dev->device == 0X8077) \
93 || (dev->device == 0X8070) \
94 || (dev->device == 0X8072))
95
96#define PM8001_NAME_LENGTH 32/* generic length of strings */
97extern struct list_head hba_list;
98extern const struct pm8001_dispatch pm8001_8001_dispatch;
99extern const struct pm8001_dispatch pm8001_80xx_dispatch;
100
101struct pm8001_hba_info;
102struct pm8001_ccb_info;
103struct pm8001_device;
104
105struct pm8001_ioctl_payload {
106 u32 signature;
107 u16 major_function;
108 u16 minor_function;
109 u16 status;
110 u16 offset;
111 u16 id;
112 u32 wr_length;
113 u32 rd_length;
114 u8 *func_specific;
115};
116
117#define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF
118#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24)
119#define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */
120#define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */
121#define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */
122#define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */
123#define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */
124#define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */
125#define MPI_FATAL_EDUMP_TABLE_TOTAL_LEN 0x18 /* TOTALLEN */
126#define MPI_FATAL_EDUMP_TABLE_SIGNATURE 0x1C /* SIGNITURE */
127#define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1
128#define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0
129#define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0
130#define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1
131#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2
132#define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3
133#define TYPE_GSM_SPACE 1
134#define TYPE_QUEUE 2
135#define TYPE_FATAL 3
136#define TYPE_NON_FATAL 4
137#define TYPE_INBOUND 1
138#define TYPE_OUTBOUND 2
139struct forensic_data {
140 u32 data_type;
141 union {
142 struct {
143 u32 direct_len;
144 u32 direct_offset;
145 void *direct_data;
146 } gsm_buf;
147 struct {
148 u16 queue_type;
149 u16 queue_index;
150 u32 direct_len;
151 void *direct_data;
152 } queue_buf;
153 struct {
154 u32 direct_len;
155 u32 direct_offset;
156 u32 read_len;
157 void *direct_data;
158 } data_buf;
159 };
160};
161
162/* bit31-26 - mask bar */
163#define SCRATCH_PAD0_BAR_MASK 0xFC000000
164/* bit25-0 - offset mask */
165#define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF
166/* if AAP error state */
167#define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF
168/* Inbound doorbell bit7 */
169#define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80
170/* Inbound doorbell bit7 SPCV */
171#define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80
172#define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */
173
174struct pm8001_dispatch {
175 char *name;
176 int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
177 void (*chip_post_init)(struct pm8001_hba_info *pm8001_ha);
178 int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
179 void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
180 int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
181 void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
182 irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec);
183 u32 (*is_our_interrupt)(struct pm8001_hba_info *pm8001_ha);
184 int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec);
185 void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
186 void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec);
187 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
188 int (*smp_req)(struct pm8001_hba_info *pm8001_ha,
189 struct pm8001_ccb_info *ccb);
190 int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha,
191 struct pm8001_ccb_info *ccb);
192 int (*sata_req)(struct pm8001_hba_info *pm8001_ha,
193 struct pm8001_ccb_info *ccb);
194 int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
195 int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id);
196 int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha,
197 struct pm8001_device *pm8001_dev, u32 flag);
198 int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id);
199 int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha,
200 u32 phy_id, u32 phy_op);
201 int (*task_abort)(struct pm8001_hba_info *pm8001_ha,
202 struct pm8001_ccb_info *ccb);
203 int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha,
204 struct pm8001_ccb_info *ccb, struct sas_tmf_task *tmf);
205 int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
206 int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload);
207 int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha,
208 void *payload);
209 int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha,
210 struct pm8001_device *pm8001_dev, u32 state);
211 int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha,
212 u32 state);
213 int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha,
214 u32 state);
215 int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha);
216 int (*fatal_errors)(struct pm8001_hba_info *pm8001_ha);
217 void (*hw_event_ack_req)(struct pm8001_hba_info *pm8001_ha,
218 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0,
219 u32 param1);
220};
221
222struct pm8001_chip_info {
223 u32 encrypt;
224 u32 n_phy;
225 const struct pm8001_dispatch *dispatch;
226};
227#define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch)
228
229struct pm8001_port {
230 struct asd_sas_port sas_port;
231 u8 port_attached;
232 u16 wide_port_phymap;
233 u8 port_state;
234 u8 port_id;
235 struct list_head list;
236};
237
238struct pm8001_phy {
239 struct pm8001_hba_info *pm8001_ha;
240 struct pm8001_port *port;
241 struct asd_sas_phy sas_phy;
242 struct sas_identify identify;
243 struct scsi_device *sdev;
244 u64 dev_sas_addr;
245 u32 phy_type;
246 struct completion *enable_completion;
247 u32 frame_rcvd_size;
248 u8 frame_rcvd[32];
249 u8 phy_attached;
250 u8 phy_state;
251 enum sas_linkrate minimum_linkrate;
252 enum sas_linkrate maximum_linkrate;
253 struct completion *reset_completion;
254 bool port_reset_status;
255 bool reset_success;
256};
257
258/* port reset status */
259#define PORT_RESET_SUCCESS 0x00
260#define PORT_RESET_TMO 0x01
261
262struct pm8001_device {
263 enum sas_device_type dev_type;
264 struct domain_device *sas_device;
265 u32 attached_phy;
266 u32 id;
267 struct completion *dcompletion;
268 struct completion *setds_completion;
269 u32 device_id;
270 atomic_t running_req;
271};
272
273struct pm8001_prd_imt {
274 __le32 len;
275 __le32 e;
276};
277
278struct pm8001_prd {
279 __le64 addr; /* 64-bit buffer address */
280 struct pm8001_prd_imt im_len; /* 64-bit length */
281} __attribute__ ((packed));
282/*
283 * CCB(Command Control Block)
284 */
285struct pm8001_ccb_info {
286 struct sas_task *task;
287 u32 n_elem;
288 u32 ccb_tag;
289 dma_addr_t ccb_dma_handle;
290 struct pm8001_device *device;
291 struct pm8001_prd *buf_prd;
292 struct fw_control_ex *fw_control_context;
293 u8 open_retry;
294};
295
296struct mpi_mem {
297 void *virt_ptr;
298 dma_addr_t phys_addr;
299 u32 phys_addr_hi;
300 u32 phys_addr_lo;
301 u32 total_len;
302 u32 num_elements;
303 u32 element_size;
304 u32 alignment;
305};
306
307struct mpi_mem_req {
308 /* The number of element in the mpiMemory array */
309 u32 count;
310 /* The array of structures that define memroy regions*/
311 struct mpi_mem region[USI_MAX_MEMCNT];
312};
313
314struct encrypt {
315 u32 cipher_mode;
316 u32 sec_mode;
317 u32 status;
318 u32 flag;
319};
320
321struct sas_phy_attribute_table {
322 u32 phystart1_16[16];
323 u32 outbound_hw_event_pid1_16[16];
324};
325
326union main_cfg_table {
327 struct {
328 u32 signature;
329 u32 interface_rev;
330 u32 firmware_rev;
331 u32 max_out_io;
332 u32 max_sgl;
333 u32 ctrl_cap_flag;
334 u32 gst_offset;
335 u32 inbound_queue_offset;
336 u32 outbound_queue_offset;
337 u32 inbound_q_nppd_hppd;
338 u32 outbound_hw_event_pid0_3;
339 u32 outbound_hw_event_pid4_7;
340 u32 outbound_ncq_event_pid0_3;
341 u32 outbound_ncq_event_pid4_7;
342 u32 outbound_tgt_ITNexus_event_pid0_3;
343 u32 outbound_tgt_ITNexus_event_pid4_7;
344 u32 outbound_tgt_ssp_event_pid0_3;
345 u32 outbound_tgt_ssp_event_pid4_7;
346 u32 outbound_tgt_smp_event_pid0_3;
347 u32 outbound_tgt_smp_event_pid4_7;
348 u32 upper_event_log_addr;
349 u32 lower_event_log_addr;
350 u32 event_log_size;
351 u32 event_log_option;
352 u32 upper_iop_event_log_addr;
353 u32 lower_iop_event_log_addr;
354 u32 iop_event_log_size;
355 u32 iop_event_log_option;
356 u32 fatal_err_interrupt;
357 u32 fatal_err_dump_offset0;
358 u32 fatal_err_dump_length0;
359 u32 fatal_err_dump_offset1;
360 u32 fatal_err_dump_length1;
361 u32 hda_mode_flag;
362 u32 anolog_setup_table_offset;
363 u32 rsvd[4];
364 } pm8001_tbl;
365
366 struct {
367 u32 signature;
368 u32 interface_rev;
369 u32 firmware_rev;
370 u32 max_out_io;
371 u32 max_sgl;
372 u32 ctrl_cap_flag;
373 u32 gst_offset;
374 u32 inbound_queue_offset;
375 u32 outbound_queue_offset;
376 u32 inbound_q_nppd_hppd;
377 u32 rsvd[8];
378 u32 crc_core_dump;
379 u32 rsvd1;
380 u32 upper_event_log_addr;
381 u32 lower_event_log_addr;
382 u32 event_log_size;
383 u32 event_log_severity;
384 u32 upper_pcs_event_log_addr;
385 u32 lower_pcs_event_log_addr;
386 u32 pcs_event_log_size;
387 u32 pcs_event_log_severity;
388 u32 fatal_err_interrupt;
389 u32 fatal_err_dump_offset0;
390 u32 fatal_err_dump_length0;
391 u32 fatal_err_dump_offset1;
392 u32 fatal_err_dump_length1;
393 u32 gpio_led_mapping;
394 u32 analog_setup_table_offset;
395 u32 int_vec_table_offset;
396 u32 phy_attr_table_offset;
397 u32 port_recovery_timer;
398 u32 interrupt_reassertion_delay;
399 u32 fatal_n_non_fatal_dump; /* 0x28 */
400 u32 ila_version;
401 u32 inc_fw_version;
402 } pm80xx_tbl;
403};
404
405union general_status_table {
406 struct {
407 u32 gst_len_mpistate;
408 u32 iq_freeze_state0;
409 u32 iq_freeze_state1;
410 u32 msgu_tcnt;
411 u32 iop_tcnt;
412 u32 rsvd;
413 u32 phy_state[8];
414 u32 gpio_input_val;
415 u32 rsvd1[2];
416 u32 recover_err_info[8];
417 } pm8001_tbl;
418 struct {
419 u32 gst_len_mpistate;
420 u32 iq_freeze_state0;
421 u32 iq_freeze_state1;
422 u32 msgu_tcnt;
423 u32 iop_tcnt;
424 u32 rsvd[9];
425 u32 gpio_input_val;
426 u32 rsvd1[2];
427 u32 recover_err_info[8];
428 } pm80xx_tbl;
429};
430struct inbound_queue_table {
431 u32 element_pri_size_cnt;
432 u32 upper_base_addr;
433 u32 lower_base_addr;
434 u32 ci_upper_base_addr;
435 u32 ci_lower_base_addr;
436 u32 pi_pci_bar;
437 u32 pi_offset;
438 u32 total_length;
439 void *base_virt;
440 void *ci_virt;
441 u32 reserved;
442 __le32 consumer_index;
443 u32 producer_idx;
444 spinlock_t iq_lock;
445};
446struct outbound_queue_table {
447 u32 element_size_cnt;
448 u32 upper_base_addr;
449 u32 lower_base_addr;
450 void *base_virt;
451 u32 pi_upper_base_addr;
452 u32 pi_lower_base_addr;
453 u32 ci_pci_bar;
454 u32 ci_offset;
455 u32 total_length;
456 void *pi_virt;
457 u32 interrup_vec_cnt_delay;
458 u32 dinterrup_to_pci_offset;
459 __le32 producer_index;
460 u32 consumer_idx;
461 spinlock_t oq_lock;
462 unsigned long lock_flags;
463};
464struct pm8001_hba_memspace {
465 void __iomem *memvirtaddr;
466 u64 membase;
467 u32 memsize;
468};
469struct isr_param {
470 struct pm8001_hba_info *drv_inst;
471 u32 irq_id;
472};
473struct pm8001_hba_info {
474 char name[PM8001_NAME_LENGTH];
475 struct list_head list;
476 unsigned long flags;
477 spinlock_t lock;/* host-wide lock */
478 spinlock_t bitmap_lock;
479 struct pci_dev *pdev;/* our device */
480 struct device *dev;
481 struct pm8001_hba_memspace io_mem[6];
482 struct mpi_mem_req memoryMap;
483 struct encrypt encrypt_info; /* support encryption */
484 struct forensic_data forensic_info;
485 u32 fatal_bar_loc;
486 u32 forensic_last_offset;
487 u32 fatal_forensic_shift_offset;
488 u32 forensic_fatal_step;
489 u32 forensic_preserved_accumulated_transfer;
490 u32 evtlog_ib_offset;
491 u32 evtlog_ob_offset;
492 void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/
493 void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/
494 void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/
495 void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/
496 void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/
497 void __iomem *pspa_q_tbl_addr;
498 /*MPI SAS PHY attributes Queue Config Table Addr*/
499 void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */
500 void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */
501 union main_cfg_table main_cfg_tbl;
502 union general_status_table gs_tbl;
503 struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_INB_NUM];
504 struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_OUTB_NUM];
505 struct sas_phy_attribute_table phy_attr_table;
506 /* MPI SAS PHY attributes */
507 u8 sas_addr[SAS_ADDR_SIZE];
508 struct sas_ha_struct *sas;/* SCSI/SAS glue */
509 struct Scsi_Host *shost;
510 u32 chip_id;
511 const struct pm8001_chip_info *chip;
512 struct completion *nvmd_completion;
513 unsigned long *rsvd_tags;
514 struct pm8001_phy phy[PM8001_MAX_PHYS];
515 struct pm8001_port port[PM8001_MAX_PHYS];
516 u32 id;
517 u32 irq;
518 u32 iomb_size; /* SPC and SPCV IOMB size */
519 struct pm8001_device *devices;
520 struct pm8001_ccb_info *ccb_info;
521 u32 ccb_count;
522#ifdef PM8001_USE_MSIX
523 int number_of_intr;/*will be used in remove()*/
524 char intr_drvname[PM8001_MAX_MSIX_VEC]
525 [PM8001_NAME_LENGTH+1+3+1];
526#endif
527#ifdef PM8001_USE_TASKLET
528 struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC];
529#endif
530 u32 logging_level;
531 u32 link_rate;
532 u32 fw_status;
533 u32 smp_exp_mode;
534 bool controller_fatal_error;
535 const struct firmware *fw_image;
536 struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
537 u32 non_fatal_count;
538 u32 non_fatal_read_length;
539 u32 max_q_num;
540 u32 ib_offset;
541 u32 ob_offset;
542 u32 ci_offset;
543 u32 pi_offset;
544 u32 max_memcnt;
545};
546
547struct pm8001_work {
548 struct work_struct work;
549 struct pm8001_hba_info *pm8001_ha;
550 void *data;
551 int handler;
552};
553
554struct pm8001_fw_image_header {
555 u8 vender_id[8];
556 u8 product_id;
557 u8 hardware_rev;
558 u8 dest_partition;
559 u8 reserved;
560 u8 fw_rev[4];
561 __be32 image_length;
562 __be32 image_crc;
563 __be32 startup_entry;
564} __attribute__((packed, aligned(4)));
565
566
567/**
568 * FW Flash Update status values
569 */
570#define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00
571#define FLASH_UPDATE_IN_PROGRESS 0x01
572#define FLASH_UPDATE_HDR_ERR 0x02
573#define FLASH_UPDATE_OFFSET_ERR 0x03
574#define FLASH_UPDATE_CRC_ERR 0x04
575#define FLASH_UPDATE_LENGTH_ERR 0x05
576#define FLASH_UPDATE_HW_ERR 0x06
577#define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
578#define FLASH_UPDATE_DISABLED 0x11
579
580/* Device states */
581#define DS_OPERATIONAL 0x01
582#define DS_PORT_IN_RESET 0x02
583#define DS_IN_RECOVERY 0x03
584#define DS_IN_ERROR 0x04
585#define DS_NON_OPERATIONAL 0x07
586
587/**
588 * brief param structure for firmware flash update.
589 */
590struct fw_flash_updata_info {
591 u32 cur_image_offset;
592 u32 cur_image_len;
593 u32 total_image_len;
594 struct pm8001_prd sgl;
595};
596
597struct fw_control_info {
598 u32 retcode;/*ret code (status)*/
599 u32 phase;/*ret code phase*/
600 u32 phaseCmplt;/*percent complete for the current
601 update phase */
602 u32 version;/*Hex encoded firmware version number*/
603 u32 offset;/*Used for downloading firmware */
604 u32 len; /*len of buffer*/
605 u32 size;/* Used in OS VPD and Trace get size
606 operations.*/
607 u32 reserved;/* padding required for 64 bit
608 alignment */
609 u8 buffer[];/* Start of buffer */
610};
611struct fw_control_ex {
612 struct fw_control_info *fw_control;
613 void *buffer;/* keep buffer pointer to be
614 freed when the response comes*/
615 void *virtAddr;/* keep virtual address of the data */
616 void *usrAddr;/* keep virtual address of the
617 user data */
618 dma_addr_t phys_addr;
619 u32 len; /* len of buffer */
620 void *payload; /* pointer to IOCTL Payload */
621 u8 inProgress;/*if 1 - the IOCTL request is in
622 progress */
623 void *param1;
624 void *param2;
625 void *param3;
626};
627
628/* pm8001 workqueue */
629extern struct workqueue_struct *pm8001_wq;
630
631/******************** function prototype *********************/
632int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out);
633u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag);
634void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha,
635 struct pm8001_ccb_info *ccb);
636int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
637 void *funcdata);
638void pm8001_scan_start(struct Scsi_Host *shost);
639int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time);
640int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags);
641int pm8001_abort_task(struct sas_task *task);
642int pm8001_clear_task_set(struct domain_device *dev, u8 *lun);
643int pm8001_dev_found(struct domain_device *dev);
644void pm8001_dev_gone(struct domain_device *dev);
645int pm8001_lu_reset(struct domain_device *dev, u8 *lun);
646int pm8001_I_T_nexus_reset(struct domain_device *dev);
647int pm8001_I_T_nexus_event_handler(struct domain_device *dev);
648int pm8001_query_task(struct sas_task *task);
649void pm8001_port_formed(struct asd_sas_phy *sas_phy);
650void pm8001_open_reject_retry(
651 struct pm8001_hba_info *pm8001_ha,
652 struct sas_task *task_to_close,
653 struct pm8001_device *device_to_close);
654int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr,
655 dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo,
656 u32 mem_size, u32 align);
657
658void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha);
659int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
660 u32 q_index, u32 opCode, void *payload, size_t nb,
661 u32 responseQueue);
662int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
663 u16 messageSize, void **messagePtr);
664u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
665 struct outbound_queue_table *circularQ, u8 bc);
666u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
667 struct outbound_queue_table *circularQ,
668 void **messagePtr1, u8 *pBC);
669int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
670 struct pm8001_device *pm8001_dev, u32 state);
671int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
672 void *payload);
673int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
674 void *fw_flash_updata_info, u32 tag);
675int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
676int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload);
677int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
678 struct pm8001_ccb_info *ccb,
679 struct sas_tmf_task *tmf);
680int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
681 struct pm8001_ccb_info *ccb);
682int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id);
683void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd);
684void pm8001_work_fn(struct work_struct *work);
685int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha,
686 void *data, int handler);
687void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
688 void *piomb);
689void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
690 void *piomb);
691void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha,
692 void *piomb);
693int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha,
694 void *piomb);
695void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate);
696void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr);
697void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i);
698int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
699int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
700int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
701 void *piomb);
702int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb);
703int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb);
704struct sas_task *pm8001_alloc_task(void);
705void pm8001_free_task(struct sas_task *task);
706void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag);
707struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
708 u32 device_id);
709int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
710
711int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
712void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
713 u32 length, u8 *buf);
714void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
715 u32 phy, u32 length, u32 *buf);
716int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
717ssize_t pm80xx_get_fatal_dump(struct device *cdev,
718 struct device_attribute *attr, char *buf);
719ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
720 struct device_attribute *attr, char *buf);
721ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf);
722int pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha);
723void pm8001_free_dev(struct pm8001_device *pm8001_dev);
724/* ctl shared API */
725extern const struct attribute_group *pm8001_host_groups[];
726
727#define PM8001_INVALID_TAG ((u32)-1)
728
729/*
730 * Allocate a new tag and return the corresponding ccb after initializing it.
731 */
732static inline struct pm8001_ccb_info *
733pm8001_ccb_alloc(struct pm8001_hba_info *pm8001_ha,
734 struct pm8001_device *dev, struct sas_task *task)
735{
736 struct pm8001_ccb_info *ccb;
737 struct request *rq = NULL;
738 u32 tag;
739
740 if (task)
741 rq = sas_task_find_rq(task);
742
743 if (rq) {
744 tag = rq->tag + PM8001_RESERVE_SLOT;
745 } else if (pm8001_tag_alloc(pm8001_ha, &tag)) {
746 pm8001_dbg(pm8001_ha, FAIL, "Failed to allocate a tag\n");
747 return NULL;
748 }
749
750 ccb = &pm8001_ha->ccb_info[tag];
751 ccb->task = task;
752 ccb->n_elem = 0;
753 ccb->ccb_tag = tag;
754 ccb->device = dev;
755 ccb->fw_control_context = NULL;
756 ccb->open_retry = 0;
757
758 return ccb;
759}
760
761/*
762 * Free the tag of an initialized ccb.
763 */
764static inline void pm8001_ccb_free(struct pm8001_hba_info *pm8001_ha,
765 struct pm8001_ccb_info *ccb)
766{
767 u32 tag = ccb->ccb_tag;
768
769 /*
770 * Cleanup the ccb to make sure that a manual scan of the adapter
771 * ccb_info array can detect ccb's that are in use.
772 * C.f. pm8001_open_reject_retry()
773 */
774 ccb->task = NULL;
775 ccb->ccb_tag = PM8001_INVALID_TAG;
776 ccb->device = NULL;
777 ccb->fw_control_context = NULL;
778
779 pm8001_tag_free(pm8001_ha, tag);
780}
781
782static inline void pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha,
783 struct pm8001_ccb_info *ccb)
784{
785 struct sas_task *task = ccb->task;
786
787 pm8001_ccb_task_free(pm8001_ha, ccb);
788 smp_mb(); /*in order to force CPU ordering*/
789 task->task_done(task);
790}
791void pm8001_setds_completion(struct domain_device *dev);
792void pm8001_tmf_aborted(struct sas_task *task);
793
794#endif
795