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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28#include <drm/drmP.h>
29#include "ast_drv.h"
30
31
32#include <drm/drm_fb_helper.h>
33#include <drm/drm_crtc_helper.h>
34
35#include "ast_dram_tables.h"
36
37void ast_set_index_reg_mask(struct ast_private *ast,
38 uint32_t base, uint8_t index,
39 uint8_t mask, uint8_t val)
40{
41 u8 tmp;
42 ast_io_write8(ast, base, index);
43 tmp = (ast_io_read8(ast, base + 1) & mask) | val;
44 ast_set_index_reg(ast, base, index, tmp);
45}
46
47uint8_t ast_get_index_reg(struct ast_private *ast,
48 uint32_t base, uint8_t index)
49{
50 uint8_t ret;
51 ast_io_write8(ast, base, index);
52 ret = ast_io_read8(ast, base + 1);
53 return ret;
54}
55
56uint8_t ast_get_index_reg_mask(struct ast_private *ast,
57 uint32_t base, uint8_t index, uint8_t mask)
58{
59 uint8_t ret;
60 ast_io_write8(ast, base, index);
61 ret = ast_io_read8(ast, base + 1) & mask;
62 return ret;
63}
64
65static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
66{
67 struct device_node *np = dev->pdev->dev.of_node;
68 struct ast_private *ast = dev->dev_private;
69 uint32_t data, jregd0, jregd1;
70
71 /* Defaults */
72 ast->config_mode = ast_use_defaults;
73 *scu_rev = 0xffffffff;
74
75 /* Check if we have device-tree properties */
76 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
77 scu_rev)) {
78 /* We do, disable P2A access */
79 ast->config_mode = ast_use_dt;
80 DRM_INFO("Using device-tree for configuration\n");
81 return;
82 }
83
84 /* Not all families have a P2A bridge */
85 if (dev->pdev->device != PCI_CHIP_AST2000)
86 return;
87
88 /*
89 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
90 * is disabled. We force using P2A if VGA only mode bit
91 * is set D[7]
92 */
93 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
94 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
95 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
96 /* Double check it's actually working */
97 data = ast_read32(ast, 0xf004);
98 if (data != 0xFFFFFFFF) {
99 /* P2A works, grab silicon revision */
100 ast->config_mode = ast_use_p2a;
101
102 DRM_INFO("Using P2A bridge for configuration\n");
103
104 /* Read SCU7c (silicon revision register) */
105 ast_write32(ast, 0xf004, 0x1e6e0000);
106 ast_write32(ast, 0xf000, 0x1);
107 *scu_rev = ast_read32(ast, 0x1207c);
108 return;
109 }
110 }
111
112 /* We have a P2A bridge but it's disabled */
113 DRM_INFO("P2A bridge disabled, using default configuration\n");
114}
115
116static int ast_detect_chip(struct drm_device *dev, bool *need_post)
117{
118 struct ast_private *ast = dev->dev_private;
119 uint32_t jreg, scu_rev;
120
121 /*
122 * If VGA isn't enabled, we need to enable now or subsequent
123 * access to the scratch registers will fail. We also inform
124 * our caller that it needs to POST the chip
125 * (Assumption: VGA not enabled -> need to POST)
126 */
127 if (!ast_is_vga_enabled(dev)) {
128 ast_enable_vga(dev);
129 DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
130 *need_post = true;
131 } else
132 *need_post = false;
133
134
135 /* Enable extended register access */
136 ast_enable_mmio(dev);
137 ast_open_key(ast);
138
139 /* Find out whether P2A works or whether to use device-tree */
140 ast_detect_config_mode(dev, &scu_rev);
141
142 /* Identify chipset */
143 if (dev->pdev->device == PCI_CHIP_AST1180) {
144 ast->chip = AST1100;
145 DRM_INFO("AST 1180 detected\n");
146 } else {
147 if (dev->pdev->revision >= 0x30) {
148 ast->chip = AST2400;
149 DRM_INFO("AST 2400 detected\n");
150 } else if (dev->pdev->revision >= 0x20) {
151 ast->chip = AST2300;
152 DRM_INFO("AST 2300 detected\n");
153 } else if (dev->pdev->revision >= 0x10) {
154 switch (scu_rev & 0x0300) {
155 case 0x0200:
156 ast->chip = AST1100;
157 DRM_INFO("AST 1100 detected\n");
158 break;
159 case 0x0100:
160 ast->chip = AST2200;
161 DRM_INFO("AST 2200 detected\n");
162 break;
163 case 0x0000:
164 ast->chip = AST2150;
165 DRM_INFO("AST 2150 detected\n");
166 break;
167 default:
168 ast->chip = AST2100;
169 DRM_INFO("AST 2100 detected\n");
170 break;
171 }
172 ast->vga2_clone = false;
173 } else {
174 ast->chip = AST2000;
175 DRM_INFO("AST 2000 detected\n");
176 }
177 }
178
179 /* Check if we support wide screen */
180 switch (ast->chip) {
181 case AST1180:
182 ast->support_wide_screen = true;
183 break;
184 case AST2000:
185 ast->support_wide_screen = false;
186 break;
187 default:
188 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
189 if (!(jreg & 0x80))
190 ast->support_wide_screen = true;
191 else if (jreg & 0x01)
192 ast->support_wide_screen = true;
193 else {
194 ast->support_wide_screen = false;
195 if (ast->chip == AST2300 &&
196 (scu_rev & 0x300) == 0x0) /* ast1300 */
197 ast->support_wide_screen = true;
198 if (ast->chip == AST2400 &&
199 (scu_rev & 0x300) == 0x100) /* ast1400 */
200 ast->support_wide_screen = true;
201 }
202 break;
203 }
204
205 /* Check 3rd Tx option (digital output afaik) */
206 ast->tx_chip_type = AST_TX_NONE;
207
208 /*
209 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
210 * enabled, in that case, assume we have a SIL164 TMDS transmitter
211 *
212 * Don't make that assumption if we the chip wasn't enabled and
213 * is at power-on reset, otherwise we'll incorrectly "detect" a
214 * SIL164 when there is none.
215 */
216 if (!*need_post) {
217 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
218 if (jreg & 0x80)
219 ast->tx_chip_type = AST_TX_SIL164;
220 }
221
222 if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
223 /*
224 * On AST2300 and 2400, look the configuration set by the SoC in
225 * the SOC scratch register #1 bits 11:8 (interestingly marked
226 * as "reserved" in the spec)
227 */
228 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
229 switch (jreg) {
230 case 0x04:
231 ast->tx_chip_type = AST_TX_SIL164;
232 break;
233 case 0x08:
234 ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
235 if (ast->dp501_fw_addr) {
236 /* backup firmware */
237 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
238 kfree(ast->dp501_fw_addr);
239 ast->dp501_fw_addr = NULL;
240 }
241 }
242 /* fallthrough */
243 case 0x0c:
244 ast->tx_chip_type = AST_TX_DP501;
245 }
246 }
247
248 /* Print stuff for diagnostic purposes */
249 switch(ast->tx_chip_type) {
250 case AST_TX_SIL164:
251 DRM_INFO("Using Sil164 TMDS transmitter\n");
252 break;
253 case AST_TX_DP501:
254 DRM_INFO("Using DP501 DisplayPort transmitter\n");
255 break;
256 default:
257 DRM_INFO("Analog VGA only\n");
258 }
259 return 0;
260}
261
262static int ast_get_dram_info(struct drm_device *dev)
263{
264 struct device_node *np = dev->pdev->dev.of_node;
265 struct ast_private *ast = dev->dev_private;
266 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
267 uint32_t denum, num, div, ref_pll, dsel;
268
269 switch (ast->config_mode) {
270 case ast_use_dt:
271 /*
272 * If some properties are missing, use reasonable
273 * defaults for AST2400
274 */
275 if (of_property_read_u32(np, "aspeed,mcr-configuration",
276 &mcr_cfg))
277 mcr_cfg = 0x00000577;
278 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
279 &mcr_scu_mpll))
280 mcr_scu_mpll = 0x000050C0;
281 if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
282 &mcr_scu_strap))
283 mcr_scu_strap = 0;
284 break;
285 case ast_use_p2a:
286 ast_write32(ast, 0xf004, 0x1e6e0000);
287 ast_write32(ast, 0xf000, 0x1);
288 mcr_cfg = ast_read32(ast, 0x10004);
289 mcr_scu_mpll = ast_read32(ast, 0x10120);
290 mcr_scu_strap = ast_read32(ast, 0x10170);
291 break;
292 case ast_use_defaults:
293 default:
294 ast->dram_bus_width = 16;
295 ast->dram_type = AST_DRAM_1Gx16;
296 ast->mclk = 396;
297 return 0;
298 }
299
300 if (mcr_cfg & 0x40)
301 ast->dram_bus_width = 16;
302 else
303 ast->dram_bus_width = 32;
304
305 if (ast->chip == AST2300 || ast->chip == AST2400) {
306 switch (mcr_cfg & 0x03) {
307 case 0:
308 ast->dram_type = AST_DRAM_512Mx16;
309 break;
310 default:
311 case 1:
312 ast->dram_type = AST_DRAM_1Gx16;
313 break;
314 case 2:
315 ast->dram_type = AST_DRAM_2Gx16;
316 break;
317 case 3:
318 ast->dram_type = AST_DRAM_4Gx16;
319 break;
320 }
321 } else {
322 switch (mcr_cfg & 0x0c) {
323 case 0:
324 case 4:
325 ast->dram_type = AST_DRAM_512Mx16;
326 break;
327 case 8:
328 if (mcr_cfg & 0x40)
329 ast->dram_type = AST_DRAM_1Gx16;
330 else
331 ast->dram_type = AST_DRAM_512Mx32;
332 break;
333 case 0xc:
334 ast->dram_type = AST_DRAM_1Gx32;
335 break;
336 }
337 }
338
339 if (mcr_scu_strap & 0x2000)
340 ref_pll = 14318;
341 else
342 ref_pll = 12000;
343
344 denum = mcr_scu_mpll & 0x1f;
345 num = (mcr_scu_mpll & 0x3fe0) >> 5;
346 dsel = (mcr_scu_mpll & 0xc000) >> 14;
347 switch (dsel) {
348 case 3:
349 div = 0x4;
350 break;
351 case 2:
352 case 1:
353 div = 0x2;
354 break;
355 default:
356 div = 0x1;
357 break;
358 }
359 ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
360 return 0;
361}
362
363static void ast_user_framebuffer_destroy(struct drm_framebuffer *fb)
364{
365 struct ast_framebuffer *ast_fb = to_ast_framebuffer(fb);
366
367 drm_gem_object_unreference_unlocked(ast_fb->obj);
368 drm_framebuffer_cleanup(fb);
369 kfree(fb);
370}
371
372static const struct drm_framebuffer_funcs ast_fb_funcs = {
373 .destroy = ast_user_framebuffer_destroy,
374};
375
376
377int ast_framebuffer_init(struct drm_device *dev,
378 struct ast_framebuffer *ast_fb,
379 const struct drm_mode_fb_cmd2 *mode_cmd,
380 struct drm_gem_object *obj)
381{
382 int ret;
383
384 drm_helper_mode_fill_fb_struct(&ast_fb->base, mode_cmd);
385 ast_fb->obj = obj;
386 ret = drm_framebuffer_init(dev, &ast_fb->base, &ast_fb_funcs);
387 if (ret) {
388 DRM_ERROR("framebuffer init failed %d\n", ret);
389 return ret;
390 }
391 return 0;
392}
393
394static struct drm_framebuffer *
395ast_user_framebuffer_create(struct drm_device *dev,
396 struct drm_file *filp,
397 const struct drm_mode_fb_cmd2 *mode_cmd)
398{
399 struct drm_gem_object *obj;
400 struct ast_framebuffer *ast_fb;
401 int ret;
402
403 obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]);
404 if (obj == NULL)
405 return ERR_PTR(-ENOENT);
406
407 ast_fb = kzalloc(sizeof(*ast_fb), GFP_KERNEL);
408 if (!ast_fb) {
409 drm_gem_object_unreference_unlocked(obj);
410 return ERR_PTR(-ENOMEM);
411 }
412
413 ret = ast_framebuffer_init(dev, ast_fb, mode_cmd, obj);
414 if (ret) {
415 drm_gem_object_unreference_unlocked(obj);
416 kfree(ast_fb);
417 return ERR_PTR(ret);
418 }
419 return &ast_fb->base;
420}
421
422static const struct drm_mode_config_funcs ast_mode_funcs = {
423 .fb_create = ast_user_framebuffer_create,
424};
425
426static u32 ast_get_vram_info(struct drm_device *dev)
427{
428 struct ast_private *ast = dev->dev_private;
429 u8 jreg;
430 u32 vram_size;
431 ast_open_key(ast);
432
433 vram_size = AST_VIDMEM_DEFAULT_SIZE;
434 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
435 switch (jreg & 3) {
436 case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
437 case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
438 case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
439 case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
440 }
441
442 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
443 switch (jreg & 0x03) {
444 case 1:
445 vram_size -= 0x100000;
446 break;
447 case 2:
448 vram_size -= 0x200000;
449 break;
450 case 3:
451 vram_size -= 0x400000;
452 break;
453 }
454
455 return vram_size;
456}
457
458int ast_driver_load(struct drm_device *dev, unsigned long flags)
459{
460 struct ast_private *ast;
461 bool need_post;
462 int ret = 0;
463
464 ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL);
465 if (!ast)
466 return -ENOMEM;
467
468 dev->dev_private = ast;
469 ast->dev = dev;
470
471 ast->regs = pci_iomap(dev->pdev, 1, 0);
472 if (!ast->regs) {
473 ret = -EIO;
474 goto out_free;
475 }
476
477 /*
478 * If we don't have IO space at all, use MMIO now and
479 * assume the chip has MMIO enabled by default (rev 0x20
480 * and higher).
481 */
482 if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
483 DRM_INFO("platform has no IO space, trying MMIO\n");
484 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
485 }
486
487 /* "map" IO regs if the above hasn't done so already */
488 if (!ast->ioregs) {
489 ast->ioregs = pci_iomap(dev->pdev, 2, 0);
490 if (!ast->ioregs) {
491 ret = -EIO;
492 goto out_free;
493 }
494 }
495
496 ast_detect_chip(dev, &need_post);
497
498 if (ast->chip != AST1180) {
499 ret = ast_get_dram_info(dev);
500 if (ret)
501 goto out_free;
502 ast->vram_size = ast_get_vram_info(dev);
503 DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size);
504 }
505
506 if (need_post)
507 ast_post_gpu(dev);
508
509 ret = ast_mm_init(ast);
510 if (ret)
511 goto out_free;
512
513 drm_mode_config_init(dev);
514
515 dev->mode_config.funcs = (void *)&ast_mode_funcs;
516 dev->mode_config.min_width = 0;
517 dev->mode_config.min_height = 0;
518 dev->mode_config.preferred_depth = 24;
519 dev->mode_config.prefer_shadow = 1;
520 dev->mode_config.fb_base = pci_resource_start(ast->dev->pdev, 0);
521
522 if (ast->chip == AST2100 ||
523 ast->chip == AST2200 ||
524 ast->chip == AST2300 ||
525 ast->chip == AST2400 ||
526 ast->chip == AST1180) {
527 dev->mode_config.max_width = 1920;
528 dev->mode_config.max_height = 2048;
529 } else {
530 dev->mode_config.max_width = 1600;
531 dev->mode_config.max_height = 1200;
532 }
533
534 ret = ast_mode_init(dev);
535 if (ret)
536 goto out_free;
537
538 ret = ast_fbdev_init(dev);
539 if (ret)
540 goto out_free;
541
542 return 0;
543out_free:
544 kfree(ast);
545 dev->dev_private = NULL;
546 return ret;
547}
548
549int ast_driver_unload(struct drm_device *dev)
550{
551 struct ast_private *ast = dev->dev_private;
552
553 kfree(ast->dp501_fw_addr);
554 ast_mode_fini(dev);
555 ast_fbdev_fini(dev);
556 drm_mode_config_cleanup(dev);
557
558 ast_mm_fini(ast);
559 pci_iounmap(dev->pdev, ast->ioregs);
560 pci_iounmap(dev->pdev, ast->regs);
561 kfree(ast);
562 return 0;
563}
564
565int ast_gem_create(struct drm_device *dev,
566 u32 size, bool iskernel,
567 struct drm_gem_object **obj)
568{
569 struct ast_bo *astbo;
570 int ret;
571
572 *obj = NULL;
573
574 size = roundup(size, PAGE_SIZE);
575 if (size == 0)
576 return -EINVAL;
577
578 ret = ast_bo_create(dev, size, 0, 0, &astbo);
579 if (ret) {
580 if (ret != -ERESTARTSYS)
581 DRM_ERROR("failed to allocate GEM object\n");
582 return ret;
583 }
584 *obj = &astbo->gem;
585 return 0;
586}
587
588int ast_dumb_create(struct drm_file *file,
589 struct drm_device *dev,
590 struct drm_mode_create_dumb *args)
591{
592 int ret;
593 struct drm_gem_object *gobj;
594 u32 handle;
595
596 args->pitch = args->width * ((args->bpp + 7) / 8);
597 args->size = args->pitch * args->height;
598
599 ret = ast_gem_create(dev, args->size, false,
600 &gobj);
601 if (ret)
602 return ret;
603
604 ret = drm_gem_handle_create(file, gobj, &handle);
605 drm_gem_object_unreference_unlocked(gobj);
606 if (ret)
607 return ret;
608
609 args->handle = handle;
610 return 0;
611}
612
613static void ast_bo_unref(struct ast_bo **bo)
614{
615 struct ttm_buffer_object *tbo;
616
617 if ((*bo) == NULL)
618 return;
619
620 tbo = &((*bo)->bo);
621 ttm_bo_unref(&tbo);
622 *bo = NULL;
623}
624
625void ast_gem_free_object(struct drm_gem_object *obj)
626{
627 struct ast_bo *ast_bo = gem_to_ast_bo(obj);
628
629 ast_bo_unref(&ast_bo);
630}
631
632
633static inline u64 ast_bo_mmap_offset(struct ast_bo *bo)
634{
635 return drm_vma_node_offset_addr(&bo->bo.vma_node);
636}
637int
638ast_dumb_mmap_offset(struct drm_file *file,
639 struct drm_device *dev,
640 uint32_t handle,
641 uint64_t *offset)
642{
643 struct drm_gem_object *obj;
644 struct ast_bo *bo;
645
646 obj = drm_gem_object_lookup(file, handle);
647 if (obj == NULL)
648 return -ENOENT;
649
650 bo = gem_to_ast_bo(obj);
651 *offset = ast_bo_mmap_offset(bo);
652
653 drm_gem_object_unreference_unlocked(obj);
654
655 return 0;
656
657}
658
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <linux/pci.h>
30
31#include <drm/drm_atomic_helper.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_drv.h>
34#include <drm/drm_gem.h>
35#include <drm/drm_managed.h>
36
37#include "ast_drv.h"
38
39void ast_set_index_reg_mask(struct ast_private *ast,
40 uint32_t base, uint8_t index,
41 uint8_t mask, uint8_t val)
42{
43 u8 tmp;
44 ast_io_write8(ast, base, index);
45 tmp = (ast_io_read8(ast, base + 1) & mask) | val;
46 ast_set_index_reg(ast, base, index, tmp);
47}
48
49uint8_t ast_get_index_reg(struct ast_private *ast,
50 uint32_t base, uint8_t index)
51{
52 uint8_t ret;
53 ast_io_write8(ast, base, index);
54 ret = ast_io_read8(ast, base + 1);
55 return ret;
56}
57
58uint8_t ast_get_index_reg_mask(struct ast_private *ast,
59 uint32_t base, uint8_t index, uint8_t mask)
60{
61 uint8_t ret;
62 ast_io_write8(ast, base, index);
63 ret = ast_io_read8(ast, base + 1) & mask;
64 return ret;
65}
66
67static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
68{
69 struct device_node *np = dev->dev->of_node;
70 struct ast_private *ast = to_ast_private(dev);
71 struct pci_dev *pdev = to_pci_dev(dev->dev);
72 uint32_t data, jregd0, jregd1;
73
74 /* Defaults */
75 ast->config_mode = ast_use_defaults;
76 *scu_rev = 0xffffffff;
77
78 /* Check if we have device-tree properties */
79 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
80 scu_rev)) {
81 /* We do, disable P2A access */
82 ast->config_mode = ast_use_dt;
83 drm_info(dev, "Using device-tree for configuration\n");
84 return;
85 }
86
87 /* Not all families have a P2A bridge */
88 if (pdev->device != PCI_CHIP_AST2000)
89 return;
90
91 /*
92 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
93 * is disabled. We force using P2A if VGA only mode bit
94 * is set D[7]
95 */
96 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
97 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
98 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
99 /* Patch AST2500 */
100 if (((pdev->revision & 0xF0) == 0x40)
101 && ((jregd0 & AST_VRAM_INIT_STATUS_MASK) == 0))
102 ast_patch_ahb_2500(ast);
103
104 /* Double check it's actually working */
105 data = ast_read32(ast, 0xf004);
106 if ((data != 0xFFFFFFFF) && (data != 0x00)) {
107 /* P2A works, grab silicon revision */
108 ast->config_mode = ast_use_p2a;
109
110 drm_info(dev, "Using P2A bridge for configuration\n");
111
112 /* Read SCU7c (silicon revision register) */
113 ast_write32(ast, 0xf004, 0x1e6e0000);
114 ast_write32(ast, 0xf000, 0x1);
115 *scu_rev = ast_read32(ast, 0x1207c);
116 return;
117 }
118 }
119
120 /* We have a P2A bridge but it's disabled */
121 drm_info(dev, "P2A bridge disabled, using default configuration\n");
122}
123
124static int ast_detect_chip(struct drm_device *dev, bool *need_post)
125{
126 struct ast_private *ast = to_ast_private(dev);
127 struct pci_dev *pdev = to_pci_dev(dev->dev);
128 uint32_t jreg, scu_rev;
129
130 /*
131 * If VGA isn't enabled, we need to enable now or subsequent
132 * access to the scratch registers will fail. We also inform
133 * our caller that it needs to POST the chip
134 * (Assumption: VGA not enabled -> need to POST)
135 */
136 if (!ast_is_vga_enabled(dev)) {
137 ast_enable_vga(dev);
138 drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
139 *need_post = true;
140 } else
141 *need_post = false;
142
143
144 /* Enable extended register access */
145 ast_open_key(ast);
146 ast_enable_mmio(dev);
147
148 /* Find out whether P2A works or whether to use device-tree */
149 ast_detect_config_mode(dev, &scu_rev);
150
151 /* Identify chipset */
152 if (pdev->revision >= 0x50) {
153 ast->chip = AST2600;
154 drm_info(dev, "AST 2600 detected\n");
155 } else if (pdev->revision >= 0x40) {
156 ast->chip = AST2500;
157 drm_info(dev, "AST 2500 detected\n");
158 } else if (pdev->revision >= 0x30) {
159 ast->chip = AST2400;
160 drm_info(dev, "AST 2400 detected\n");
161 } else if (pdev->revision >= 0x20) {
162 ast->chip = AST2300;
163 drm_info(dev, "AST 2300 detected\n");
164 } else if (pdev->revision >= 0x10) {
165 switch (scu_rev & 0x0300) {
166 case 0x0200:
167 ast->chip = AST1100;
168 drm_info(dev, "AST 1100 detected\n");
169 break;
170 case 0x0100:
171 ast->chip = AST2200;
172 drm_info(dev, "AST 2200 detected\n");
173 break;
174 case 0x0000:
175 ast->chip = AST2150;
176 drm_info(dev, "AST 2150 detected\n");
177 break;
178 default:
179 ast->chip = AST2100;
180 drm_info(dev, "AST 2100 detected\n");
181 break;
182 }
183 ast->vga2_clone = false;
184 } else {
185 ast->chip = AST2000;
186 drm_info(dev, "AST 2000 detected\n");
187 }
188
189 /* Check if we support wide screen */
190 switch (ast->chip) {
191 case AST2000:
192 ast->support_wide_screen = false;
193 break;
194 default:
195 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
196 if (!(jreg & 0x80))
197 ast->support_wide_screen = true;
198 else if (jreg & 0x01)
199 ast->support_wide_screen = true;
200 else {
201 ast->support_wide_screen = false;
202 if (ast->chip == AST2300 &&
203 (scu_rev & 0x300) == 0x0) /* ast1300 */
204 ast->support_wide_screen = true;
205 if (ast->chip == AST2400 &&
206 (scu_rev & 0x300) == 0x100) /* ast1400 */
207 ast->support_wide_screen = true;
208 if (ast->chip == AST2500 &&
209 scu_rev == 0x100) /* ast2510 */
210 ast->support_wide_screen = true;
211 if (ast->chip == AST2600) /* ast2600 */
212 ast->support_wide_screen = true;
213 }
214 break;
215 }
216
217 /* Check 3rd Tx option (digital output afaik) */
218 ast->tx_chip_types |= AST_TX_NONE_BIT;
219
220 /*
221 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
222 * enabled, in that case, assume we have a SIL164 TMDS transmitter
223 *
224 * Don't make that assumption if we the chip wasn't enabled and
225 * is at power-on reset, otherwise we'll incorrectly "detect" a
226 * SIL164 when there is none.
227 */
228 if (!*need_post) {
229 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
230 if (jreg & 0x80)
231 ast->tx_chip_types = AST_TX_SIL164_BIT;
232 }
233
234 if ((ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST2500)) {
235 /*
236 * On AST2300 and 2400, look the configuration set by the SoC in
237 * the SOC scratch register #1 bits 11:8 (interestingly marked
238 * as "reserved" in the spec)
239 */
240 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
241 switch (jreg) {
242 case 0x04:
243 ast->tx_chip_types = AST_TX_SIL164_BIT;
244 break;
245 case 0x08:
246 ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
247 if (ast->dp501_fw_addr) {
248 /* backup firmware */
249 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
250 drmm_kfree(dev, ast->dp501_fw_addr);
251 ast->dp501_fw_addr = NULL;
252 }
253 }
254 fallthrough;
255 case 0x0c:
256 ast->tx_chip_types = AST_TX_DP501_BIT;
257 }
258 } else if (ast->chip == AST2600)
259 ast_dp_launch(&ast->base, 0);
260
261 /* Print stuff for diagnostic purposes */
262 if (ast->tx_chip_types & AST_TX_NONE_BIT)
263 drm_info(dev, "Using analog VGA\n");
264 if (ast->tx_chip_types & AST_TX_SIL164_BIT)
265 drm_info(dev, "Using Sil164 TMDS transmitter\n");
266 if (ast->tx_chip_types & AST_TX_DP501_BIT)
267 drm_info(dev, "Using DP501 DisplayPort transmitter\n");
268
269 return 0;
270}
271
272static int ast_get_dram_info(struct drm_device *dev)
273{
274 struct device_node *np = dev->dev->of_node;
275 struct ast_private *ast = to_ast_private(dev);
276 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
277 uint32_t denum, num, div, ref_pll, dsel;
278
279 switch (ast->config_mode) {
280 case ast_use_dt:
281 /*
282 * If some properties are missing, use reasonable
283 * defaults for AST2400
284 */
285 if (of_property_read_u32(np, "aspeed,mcr-configuration",
286 &mcr_cfg))
287 mcr_cfg = 0x00000577;
288 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
289 &mcr_scu_mpll))
290 mcr_scu_mpll = 0x000050C0;
291 if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
292 &mcr_scu_strap))
293 mcr_scu_strap = 0;
294 break;
295 case ast_use_p2a:
296 ast_write32(ast, 0xf004, 0x1e6e0000);
297 ast_write32(ast, 0xf000, 0x1);
298 mcr_cfg = ast_read32(ast, 0x10004);
299 mcr_scu_mpll = ast_read32(ast, 0x10120);
300 mcr_scu_strap = ast_read32(ast, 0x10170);
301 break;
302 case ast_use_defaults:
303 default:
304 ast->dram_bus_width = 16;
305 ast->dram_type = AST_DRAM_1Gx16;
306 if (ast->chip == AST2500)
307 ast->mclk = 800;
308 else
309 ast->mclk = 396;
310 return 0;
311 }
312
313 if (mcr_cfg & 0x40)
314 ast->dram_bus_width = 16;
315 else
316 ast->dram_bus_width = 32;
317
318 if (ast->chip == AST2500) {
319 switch (mcr_cfg & 0x03) {
320 case 0:
321 ast->dram_type = AST_DRAM_1Gx16;
322 break;
323 default:
324 case 1:
325 ast->dram_type = AST_DRAM_2Gx16;
326 break;
327 case 2:
328 ast->dram_type = AST_DRAM_4Gx16;
329 break;
330 case 3:
331 ast->dram_type = AST_DRAM_8Gx16;
332 break;
333 }
334 } else if (ast->chip == AST2300 || ast->chip == AST2400) {
335 switch (mcr_cfg & 0x03) {
336 case 0:
337 ast->dram_type = AST_DRAM_512Mx16;
338 break;
339 default:
340 case 1:
341 ast->dram_type = AST_DRAM_1Gx16;
342 break;
343 case 2:
344 ast->dram_type = AST_DRAM_2Gx16;
345 break;
346 case 3:
347 ast->dram_type = AST_DRAM_4Gx16;
348 break;
349 }
350 } else {
351 switch (mcr_cfg & 0x0c) {
352 case 0:
353 case 4:
354 ast->dram_type = AST_DRAM_512Mx16;
355 break;
356 case 8:
357 if (mcr_cfg & 0x40)
358 ast->dram_type = AST_DRAM_1Gx16;
359 else
360 ast->dram_type = AST_DRAM_512Mx32;
361 break;
362 case 0xc:
363 ast->dram_type = AST_DRAM_1Gx32;
364 break;
365 }
366 }
367
368 if (mcr_scu_strap & 0x2000)
369 ref_pll = 14318;
370 else
371 ref_pll = 12000;
372
373 denum = mcr_scu_mpll & 0x1f;
374 num = (mcr_scu_mpll & 0x3fe0) >> 5;
375 dsel = (mcr_scu_mpll & 0xc000) >> 14;
376 switch (dsel) {
377 case 3:
378 div = 0x4;
379 break;
380 case 2:
381 case 1:
382 div = 0x2;
383 break;
384 default:
385 div = 0x1;
386 break;
387 }
388 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
389 return 0;
390}
391
392/*
393 * Run this function as part of the HW device cleanup; not
394 * when the DRM device gets released.
395 */
396static void ast_device_release(void *data)
397{
398 struct ast_private *ast = data;
399
400 /* enable standard VGA decode */
401 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
402}
403
404struct ast_private *ast_device_create(const struct drm_driver *drv,
405 struct pci_dev *pdev,
406 unsigned long flags)
407{
408 struct drm_device *dev;
409 struct ast_private *ast;
410 bool need_post;
411 int ret = 0;
412
413 ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_private, base);
414 if (IS_ERR(ast))
415 return ast;
416 dev = &ast->base;
417
418 pci_set_drvdata(pdev, dev);
419
420 ret = drmm_mutex_init(dev, &ast->ioregs_lock);
421 if (ret)
422 return ERR_PTR(ret);
423
424 ast->regs = pcim_iomap(pdev, 1, 0);
425 if (!ast->regs)
426 return ERR_PTR(-EIO);
427
428 /*
429 * If we don't have IO space at all, use MMIO now and
430 * assume the chip has MMIO enabled by default (rev 0x20
431 * and higher).
432 */
433 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
434 drm_info(dev, "platform has no IO space, trying MMIO\n");
435 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
436 }
437
438 /* "map" IO regs if the above hasn't done so already */
439 if (!ast->ioregs) {
440 ast->ioregs = pcim_iomap(pdev, 2, 0);
441 if (!ast->ioregs)
442 return ERR_PTR(-EIO);
443 }
444
445 ast_detect_chip(dev, &need_post);
446
447 ret = ast_get_dram_info(dev);
448 if (ret)
449 return ERR_PTR(ret);
450
451 drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
452 ast->mclk, ast->dram_type, ast->dram_bus_width);
453
454 if (need_post)
455 ast_post_gpu(dev);
456
457 ret = ast_mm_init(ast);
458 if (ret)
459 return ERR_PTR(ret);
460
461 /* map reserved buffer */
462 ast->dp501_fw_buf = NULL;
463 if (ast->vram_size < pci_resource_len(pdev, 0)) {
464 ast->dp501_fw_buf = pci_iomap_range(pdev, 0, ast->vram_size, 0);
465 if (!ast->dp501_fw_buf)
466 drm_info(dev, "failed to map reserved buffer!\n");
467 }
468
469 ret = ast_mode_config_init(ast);
470 if (ret)
471 return ERR_PTR(ret);
472
473 ret = devm_add_action_or_reset(dev->dev, ast_device_release, ast);
474 if (ret)
475 return ERR_PTR(ret);
476
477 return ast;
478}