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1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_DPI_DEFS_H__
29#define __CVMX_DPI_DEFS_H__
30
31#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
32#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
33#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
37#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
41#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
42#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
43#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
44#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
45#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
46#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
47#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
48#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
49#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
50#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
51#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
52#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
53#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
54#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
55#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
56#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
57#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
58static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
59{
60 switch (cvmx_get_octeon_family()) {
61 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
62 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
63 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
64 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
65 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
66
67 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
68 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
69
70 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
71 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
72 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
73 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
74 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
75 }
76 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
77}
78
79#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
80
81union cvmx_dpi_bist_status {
82 uint64_t u64;
83 struct cvmx_dpi_bist_status_s {
84#ifdef __BIG_ENDIAN_BITFIELD
85 uint64_t reserved_47_63:17;
86 uint64_t bist:47;
87#else
88 uint64_t bist:47;
89 uint64_t reserved_47_63:17;
90#endif
91 } s;
92 struct cvmx_dpi_bist_status_s cn61xx;
93 struct cvmx_dpi_bist_status_cn63xx {
94#ifdef __BIG_ENDIAN_BITFIELD
95 uint64_t reserved_45_63:19;
96 uint64_t bist:45;
97#else
98 uint64_t bist:45;
99 uint64_t reserved_45_63:19;
100#endif
101 } cn63xx;
102 struct cvmx_dpi_bist_status_cn63xxp1 {
103#ifdef __BIG_ENDIAN_BITFIELD
104 uint64_t reserved_37_63:27;
105 uint64_t bist:37;
106#else
107 uint64_t bist:37;
108 uint64_t reserved_37_63:27;
109#endif
110 } cn63xxp1;
111 struct cvmx_dpi_bist_status_s cn66xx;
112 struct cvmx_dpi_bist_status_cn63xx cn68xx;
113 struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
114 struct cvmx_dpi_bist_status_s cnf71xx;
115};
116
117union cvmx_dpi_ctl {
118 uint64_t u64;
119 struct cvmx_dpi_ctl_s {
120#ifdef __BIG_ENDIAN_BITFIELD
121 uint64_t reserved_2_63:62;
122 uint64_t clk:1;
123 uint64_t en:1;
124#else
125 uint64_t en:1;
126 uint64_t clk:1;
127 uint64_t reserved_2_63:62;
128#endif
129 } s;
130 struct cvmx_dpi_ctl_cn61xx {
131#ifdef __BIG_ENDIAN_BITFIELD
132 uint64_t reserved_1_63:63;
133 uint64_t en:1;
134#else
135 uint64_t en:1;
136 uint64_t reserved_1_63:63;
137#endif
138 } cn61xx;
139 struct cvmx_dpi_ctl_s cn63xx;
140 struct cvmx_dpi_ctl_s cn63xxp1;
141 struct cvmx_dpi_ctl_s cn66xx;
142 struct cvmx_dpi_ctl_s cn68xx;
143 struct cvmx_dpi_ctl_s cn68xxp1;
144 struct cvmx_dpi_ctl_cn61xx cnf71xx;
145};
146
147union cvmx_dpi_dmax_counts {
148 uint64_t u64;
149 struct cvmx_dpi_dmax_counts_s {
150#ifdef __BIG_ENDIAN_BITFIELD
151 uint64_t reserved_39_63:25;
152 uint64_t fcnt:7;
153 uint64_t dbell:32;
154#else
155 uint64_t dbell:32;
156 uint64_t fcnt:7;
157 uint64_t reserved_39_63:25;
158#endif
159 } s;
160 struct cvmx_dpi_dmax_counts_s cn61xx;
161 struct cvmx_dpi_dmax_counts_s cn63xx;
162 struct cvmx_dpi_dmax_counts_s cn63xxp1;
163 struct cvmx_dpi_dmax_counts_s cn66xx;
164 struct cvmx_dpi_dmax_counts_s cn68xx;
165 struct cvmx_dpi_dmax_counts_s cn68xxp1;
166 struct cvmx_dpi_dmax_counts_s cnf71xx;
167};
168
169union cvmx_dpi_dmax_dbell {
170 uint64_t u64;
171 struct cvmx_dpi_dmax_dbell_s {
172#ifdef __BIG_ENDIAN_BITFIELD
173 uint64_t reserved_16_63:48;
174 uint64_t dbell:16;
175#else
176 uint64_t dbell:16;
177 uint64_t reserved_16_63:48;
178#endif
179 } s;
180 struct cvmx_dpi_dmax_dbell_s cn61xx;
181 struct cvmx_dpi_dmax_dbell_s cn63xx;
182 struct cvmx_dpi_dmax_dbell_s cn63xxp1;
183 struct cvmx_dpi_dmax_dbell_s cn66xx;
184 struct cvmx_dpi_dmax_dbell_s cn68xx;
185 struct cvmx_dpi_dmax_dbell_s cn68xxp1;
186 struct cvmx_dpi_dmax_dbell_s cnf71xx;
187};
188
189union cvmx_dpi_dmax_err_rsp_status {
190 uint64_t u64;
191 struct cvmx_dpi_dmax_err_rsp_status_s {
192#ifdef __BIG_ENDIAN_BITFIELD
193 uint64_t reserved_6_63:58;
194 uint64_t status:6;
195#else
196 uint64_t status:6;
197 uint64_t reserved_6_63:58;
198#endif
199 } s;
200 struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
201 struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
202 struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
203 struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
204 struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;
205};
206
207union cvmx_dpi_dmax_ibuff_saddr {
208 uint64_t u64;
209 struct cvmx_dpi_dmax_ibuff_saddr_s {
210#ifdef __BIG_ENDIAN_BITFIELD
211 uint64_t reserved_62_63:2;
212 uint64_t csize:14;
213 uint64_t reserved_41_47:7;
214 uint64_t idle:1;
215 uint64_t saddr:33;
216 uint64_t reserved_0_6:7;
217#else
218 uint64_t reserved_0_6:7;
219 uint64_t saddr:33;
220 uint64_t idle:1;
221 uint64_t reserved_41_47:7;
222 uint64_t csize:14;
223 uint64_t reserved_62_63:2;
224#endif
225 } s;
226 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
227#ifdef __BIG_ENDIAN_BITFIELD
228 uint64_t reserved_62_63:2;
229 uint64_t csize:14;
230 uint64_t reserved_41_47:7;
231 uint64_t idle:1;
232 uint64_t reserved_36_39:4;
233 uint64_t saddr:29;
234 uint64_t reserved_0_6:7;
235#else
236 uint64_t reserved_0_6:7;
237 uint64_t saddr:29;
238 uint64_t reserved_36_39:4;
239 uint64_t idle:1;
240 uint64_t reserved_41_47:7;
241 uint64_t csize:14;
242 uint64_t reserved_62_63:2;
243#endif
244 } cn61xx;
245 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
246 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
247 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
248 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
249 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
250 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;
251};
252
253union cvmx_dpi_dmax_iflight {
254 uint64_t u64;
255 struct cvmx_dpi_dmax_iflight_s {
256#ifdef __BIG_ENDIAN_BITFIELD
257 uint64_t reserved_3_63:61;
258 uint64_t cnt:3;
259#else
260 uint64_t cnt:3;
261 uint64_t reserved_3_63:61;
262#endif
263 } s;
264 struct cvmx_dpi_dmax_iflight_s cn61xx;
265 struct cvmx_dpi_dmax_iflight_s cn66xx;
266 struct cvmx_dpi_dmax_iflight_s cn68xx;
267 struct cvmx_dpi_dmax_iflight_s cn68xxp1;
268 struct cvmx_dpi_dmax_iflight_s cnf71xx;
269};
270
271union cvmx_dpi_dmax_naddr {
272 uint64_t u64;
273 struct cvmx_dpi_dmax_naddr_s {
274#ifdef __BIG_ENDIAN_BITFIELD
275 uint64_t reserved_40_63:24;
276 uint64_t addr:40;
277#else
278 uint64_t addr:40;
279 uint64_t reserved_40_63:24;
280#endif
281 } s;
282 struct cvmx_dpi_dmax_naddr_cn61xx {
283#ifdef __BIG_ENDIAN_BITFIELD
284 uint64_t reserved_36_63:28;
285 uint64_t addr:36;
286#else
287 uint64_t addr:36;
288 uint64_t reserved_36_63:28;
289#endif
290 } cn61xx;
291 struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
292 struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
293 struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
294 struct cvmx_dpi_dmax_naddr_s cn68xx;
295 struct cvmx_dpi_dmax_naddr_s cn68xxp1;
296 struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx;
297};
298
299union cvmx_dpi_dmax_reqbnk0 {
300 uint64_t u64;
301 struct cvmx_dpi_dmax_reqbnk0_s {
302#ifdef __BIG_ENDIAN_BITFIELD
303 uint64_t state:64;
304#else
305 uint64_t state:64;
306#endif
307 } s;
308 struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
309 struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
310 struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
311 struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
312 struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
313 struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
314 struct cvmx_dpi_dmax_reqbnk0_s cnf71xx;
315};
316
317union cvmx_dpi_dmax_reqbnk1 {
318 uint64_t u64;
319 struct cvmx_dpi_dmax_reqbnk1_s {
320#ifdef __BIG_ENDIAN_BITFIELD
321 uint64_t state:64;
322#else
323 uint64_t state:64;
324#endif
325 } s;
326 struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
327 struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
328 struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
329 struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
330 struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
331 struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
332 struct cvmx_dpi_dmax_reqbnk1_s cnf71xx;
333};
334
335union cvmx_dpi_dma_control {
336 uint64_t u64;
337 struct cvmx_dpi_dma_control_s {
338#ifdef __BIG_ENDIAN_BITFIELD
339 uint64_t reserved_62_63:2;
340 uint64_t dici_mode:1;
341 uint64_t pkt_en1:1;
342 uint64_t ffp_dis:1;
343 uint64_t commit_mode:1;
344 uint64_t pkt_hp:1;
345 uint64_t pkt_en:1;
346 uint64_t reserved_54_55:2;
347 uint64_t dma_enb:6;
348 uint64_t reserved_34_47:14;
349 uint64_t b0_lend:1;
350 uint64_t dwb_denb:1;
351 uint64_t dwb_ichk:9;
352 uint64_t fpa_que:3;
353 uint64_t o_add1:1;
354 uint64_t o_ro:1;
355 uint64_t o_ns:1;
356 uint64_t o_es:2;
357 uint64_t o_mode:1;
358 uint64_t reserved_0_13:14;
359#else
360 uint64_t reserved_0_13:14;
361 uint64_t o_mode:1;
362 uint64_t o_es:2;
363 uint64_t o_ns:1;
364 uint64_t o_ro:1;
365 uint64_t o_add1:1;
366 uint64_t fpa_que:3;
367 uint64_t dwb_ichk:9;
368 uint64_t dwb_denb:1;
369 uint64_t b0_lend:1;
370 uint64_t reserved_34_47:14;
371 uint64_t dma_enb:6;
372 uint64_t reserved_54_55:2;
373 uint64_t pkt_en:1;
374 uint64_t pkt_hp:1;
375 uint64_t commit_mode:1;
376 uint64_t ffp_dis:1;
377 uint64_t pkt_en1:1;
378 uint64_t dici_mode:1;
379 uint64_t reserved_62_63:2;
380#endif
381 } s;
382 struct cvmx_dpi_dma_control_s cn61xx;
383 struct cvmx_dpi_dma_control_cn63xx {
384#ifdef __BIG_ENDIAN_BITFIELD
385 uint64_t reserved_61_63:3;
386 uint64_t pkt_en1:1;
387 uint64_t ffp_dis:1;
388 uint64_t commit_mode:1;
389 uint64_t pkt_hp:1;
390 uint64_t pkt_en:1;
391 uint64_t reserved_54_55:2;
392 uint64_t dma_enb:6;
393 uint64_t reserved_34_47:14;
394 uint64_t b0_lend:1;
395 uint64_t dwb_denb:1;
396 uint64_t dwb_ichk:9;
397 uint64_t fpa_que:3;
398 uint64_t o_add1:1;
399 uint64_t o_ro:1;
400 uint64_t o_ns:1;
401 uint64_t o_es:2;
402 uint64_t o_mode:1;
403 uint64_t reserved_0_13:14;
404#else
405 uint64_t reserved_0_13:14;
406 uint64_t o_mode:1;
407 uint64_t o_es:2;
408 uint64_t o_ns:1;
409 uint64_t o_ro:1;
410 uint64_t o_add1:1;
411 uint64_t fpa_que:3;
412 uint64_t dwb_ichk:9;
413 uint64_t dwb_denb:1;
414 uint64_t b0_lend:1;
415 uint64_t reserved_34_47:14;
416 uint64_t dma_enb:6;
417 uint64_t reserved_54_55:2;
418 uint64_t pkt_en:1;
419 uint64_t pkt_hp:1;
420 uint64_t commit_mode:1;
421 uint64_t ffp_dis:1;
422 uint64_t pkt_en1:1;
423 uint64_t reserved_61_63:3;
424#endif
425 } cn63xx;
426 struct cvmx_dpi_dma_control_cn63xxp1 {
427#ifdef __BIG_ENDIAN_BITFIELD
428 uint64_t reserved_59_63:5;
429 uint64_t commit_mode:1;
430 uint64_t pkt_hp:1;
431 uint64_t pkt_en:1;
432 uint64_t reserved_54_55:2;
433 uint64_t dma_enb:6;
434 uint64_t reserved_34_47:14;
435 uint64_t b0_lend:1;
436 uint64_t dwb_denb:1;
437 uint64_t dwb_ichk:9;
438 uint64_t fpa_que:3;
439 uint64_t o_add1:1;
440 uint64_t o_ro:1;
441 uint64_t o_ns:1;
442 uint64_t o_es:2;
443 uint64_t o_mode:1;
444 uint64_t reserved_0_13:14;
445#else
446 uint64_t reserved_0_13:14;
447 uint64_t o_mode:1;
448 uint64_t o_es:2;
449 uint64_t o_ns:1;
450 uint64_t o_ro:1;
451 uint64_t o_add1:1;
452 uint64_t fpa_que:3;
453 uint64_t dwb_ichk:9;
454 uint64_t dwb_denb:1;
455 uint64_t b0_lend:1;
456 uint64_t reserved_34_47:14;
457 uint64_t dma_enb:6;
458 uint64_t reserved_54_55:2;
459 uint64_t pkt_en:1;
460 uint64_t pkt_hp:1;
461 uint64_t commit_mode:1;
462 uint64_t reserved_59_63:5;
463#endif
464 } cn63xxp1;
465 struct cvmx_dpi_dma_control_cn63xx cn66xx;
466 struct cvmx_dpi_dma_control_s cn68xx;
467 struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
468 struct cvmx_dpi_dma_control_s cnf71xx;
469};
470
471union cvmx_dpi_dma_engx_en {
472 uint64_t u64;
473 struct cvmx_dpi_dma_engx_en_s {
474#ifdef __BIG_ENDIAN_BITFIELD
475 uint64_t reserved_8_63:56;
476 uint64_t qen:8;
477#else
478 uint64_t qen:8;
479 uint64_t reserved_8_63:56;
480#endif
481 } s;
482 struct cvmx_dpi_dma_engx_en_s cn61xx;
483 struct cvmx_dpi_dma_engx_en_s cn63xx;
484 struct cvmx_dpi_dma_engx_en_s cn63xxp1;
485 struct cvmx_dpi_dma_engx_en_s cn66xx;
486 struct cvmx_dpi_dma_engx_en_s cn68xx;
487 struct cvmx_dpi_dma_engx_en_s cn68xxp1;
488 struct cvmx_dpi_dma_engx_en_s cnf71xx;
489};
490
491union cvmx_dpi_dma_ppx_cnt {
492 uint64_t u64;
493 struct cvmx_dpi_dma_ppx_cnt_s {
494#ifdef __BIG_ENDIAN_BITFIELD
495 uint64_t reserved_16_63:48;
496 uint64_t cnt:16;
497#else
498 uint64_t cnt:16;
499 uint64_t reserved_16_63:48;
500#endif
501 } s;
502 struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
503 struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
504 struct cvmx_dpi_dma_ppx_cnt_s cnf71xx;
505};
506
507union cvmx_dpi_engx_buf {
508 uint64_t u64;
509 struct cvmx_dpi_engx_buf_s {
510#ifdef __BIG_ENDIAN_BITFIELD
511 uint64_t reserved_37_63:27;
512 uint64_t compblks:5;
513 uint64_t reserved_9_31:23;
514 uint64_t base:5;
515 uint64_t blks:4;
516#else
517 uint64_t blks:4;
518 uint64_t base:5;
519 uint64_t reserved_9_31:23;
520 uint64_t compblks:5;
521 uint64_t reserved_37_63:27;
522#endif
523 } s;
524 struct cvmx_dpi_engx_buf_s cn61xx;
525 struct cvmx_dpi_engx_buf_cn63xx {
526#ifdef __BIG_ENDIAN_BITFIELD
527 uint64_t reserved_8_63:56;
528 uint64_t base:4;
529 uint64_t blks:4;
530#else
531 uint64_t blks:4;
532 uint64_t base:4;
533 uint64_t reserved_8_63:56;
534#endif
535 } cn63xx;
536 struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
537 struct cvmx_dpi_engx_buf_s cn66xx;
538 struct cvmx_dpi_engx_buf_s cn68xx;
539 struct cvmx_dpi_engx_buf_s cn68xxp1;
540 struct cvmx_dpi_engx_buf_s cnf71xx;
541};
542
543union cvmx_dpi_info_reg {
544 uint64_t u64;
545 struct cvmx_dpi_info_reg_s {
546#ifdef __BIG_ENDIAN_BITFIELD
547 uint64_t reserved_8_63:56;
548 uint64_t ffp:4;
549 uint64_t reserved_2_3:2;
550 uint64_t ncb:1;
551 uint64_t rsl:1;
552#else
553 uint64_t rsl:1;
554 uint64_t ncb:1;
555 uint64_t reserved_2_3:2;
556 uint64_t ffp:4;
557 uint64_t reserved_8_63:56;
558#endif
559 } s;
560 struct cvmx_dpi_info_reg_s cn61xx;
561 struct cvmx_dpi_info_reg_s cn63xx;
562 struct cvmx_dpi_info_reg_cn63xxp1 {
563#ifdef __BIG_ENDIAN_BITFIELD
564 uint64_t reserved_2_63:62;
565 uint64_t ncb:1;
566 uint64_t rsl:1;
567#else
568 uint64_t rsl:1;
569 uint64_t ncb:1;
570 uint64_t reserved_2_63:62;
571#endif
572 } cn63xxp1;
573 struct cvmx_dpi_info_reg_s cn66xx;
574 struct cvmx_dpi_info_reg_s cn68xx;
575 struct cvmx_dpi_info_reg_s cn68xxp1;
576 struct cvmx_dpi_info_reg_s cnf71xx;
577};
578
579union cvmx_dpi_int_en {
580 uint64_t u64;
581 struct cvmx_dpi_int_en_s {
582#ifdef __BIG_ENDIAN_BITFIELD
583 uint64_t reserved_28_63:36;
584 uint64_t sprt3_rst:1;
585 uint64_t sprt2_rst:1;
586 uint64_t sprt1_rst:1;
587 uint64_t sprt0_rst:1;
588 uint64_t reserved_23_23:1;
589 uint64_t req_badfil:1;
590 uint64_t req_inull:1;
591 uint64_t req_anull:1;
592 uint64_t req_undflw:1;
593 uint64_t req_ovrflw:1;
594 uint64_t req_badlen:1;
595 uint64_t req_badadr:1;
596 uint64_t dmadbo:8;
597 uint64_t reserved_2_7:6;
598 uint64_t nfovr:1;
599 uint64_t nderr:1;
600#else
601 uint64_t nderr:1;
602 uint64_t nfovr:1;
603 uint64_t reserved_2_7:6;
604 uint64_t dmadbo:8;
605 uint64_t req_badadr:1;
606 uint64_t req_badlen:1;
607 uint64_t req_ovrflw:1;
608 uint64_t req_undflw:1;
609 uint64_t req_anull:1;
610 uint64_t req_inull:1;
611 uint64_t req_badfil:1;
612 uint64_t reserved_23_23:1;
613 uint64_t sprt0_rst:1;
614 uint64_t sprt1_rst:1;
615 uint64_t sprt2_rst:1;
616 uint64_t sprt3_rst:1;
617 uint64_t reserved_28_63:36;
618#endif
619 } s;
620 struct cvmx_dpi_int_en_s cn61xx;
621 struct cvmx_dpi_int_en_cn63xx {
622#ifdef __BIG_ENDIAN_BITFIELD
623 uint64_t reserved_26_63:38;
624 uint64_t sprt1_rst:1;
625 uint64_t sprt0_rst:1;
626 uint64_t reserved_23_23:1;
627 uint64_t req_badfil:1;
628 uint64_t req_inull:1;
629 uint64_t req_anull:1;
630 uint64_t req_undflw:1;
631 uint64_t req_ovrflw:1;
632 uint64_t req_badlen:1;
633 uint64_t req_badadr:1;
634 uint64_t dmadbo:8;
635 uint64_t reserved_2_7:6;
636 uint64_t nfovr:1;
637 uint64_t nderr:1;
638#else
639 uint64_t nderr:1;
640 uint64_t nfovr:1;
641 uint64_t reserved_2_7:6;
642 uint64_t dmadbo:8;
643 uint64_t req_badadr:1;
644 uint64_t req_badlen:1;
645 uint64_t req_ovrflw:1;
646 uint64_t req_undflw:1;
647 uint64_t req_anull:1;
648 uint64_t req_inull:1;
649 uint64_t req_badfil:1;
650 uint64_t reserved_23_23:1;
651 uint64_t sprt0_rst:1;
652 uint64_t sprt1_rst:1;
653 uint64_t reserved_26_63:38;
654#endif
655 } cn63xx;
656 struct cvmx_dpi_int_en_cn63xx cn63xxp1;
657 struct cvmx_dpi_int_en_s cn66xx;
658 struct cvmx_dpi_int_en_cn63xx cn68xx;
659 struct cvmx_dpi_int_en_cn63xx cn68xxp1;
660 struct cvmx_dpi_int_en_s cnf71xx;
661};
662
663union cvmx_dpi_int_reg {
664 uint64_t u64;
665 struct cvmx_dpi_int_reg_s {
666#ifdef __BIG_ENDIAN_BITFIELD
667 uint64_t reserved_28_63:36;
668 uint64_t sprt3_rst:1;
669 uint64_t sprt2_rst:1;
670 uint64_t sprt1_rst:1;
671 uint64_t sprt0_rst:1;
672 uint64_t reserved_23_23:1;
673 uint64_t req_badfil:1;
674 uint64_t req_inull:1;
675 uint64_t req_anull:1;
676 uint64_t req_undflw:1;
677 uint64_t req_ovrflw:1;
678 uint64_t req_badlen:1;
679 uint64_t req_badadr:1;
680 uint64_t dmadbo:8;
681 uint64_t reserved_2_7:6;
682 uint64_t nfovr:1;
683 uint64_t nderr:1;
684#else
685 uint64_t nderr:1;
686 uint64_t nfovr:1;
687 uint64_t reserved_2_7:6;
688 uint64_t dmadbo:8;
689 uint64_t req_badadr:1;
690 uint64_t req_badlen:1;
691 uint64_t req_ovrflw:1;
692 uint64_t req_undflw:1;
693 uint64_t req_anull:1;
694 uint64_t req_inull:1;
695 uint64_t req_badfil:1;
696 uint64_t reserved_23_23:1;
697 uint64_t sprt0_rst:1;
698 uint64_t sprt1_rst:1;
699 uint64_t sprt2_rst:1;
700 uint64_t sprt3_rst:1;
701 uint64_t reserved_28_63:36;
702#endif
703 } s;
704 struct cvmx_dpi_int_reg_s cn61xx;
705 struct cvmx_dpi_int_reg_cn63xx {
706#ifdef __BIG_ENDIAN_BITFIELD
707 uint64_t reserved_26_63:38;
708 uint64_t sprt1_rst:1;
709 uint64_t sprt0_rst:1;
710 uint64_t reserved_23_23:1;
711 uint64_t req_badfil:1;
712 uint64_t req_inull:1;
713 uint64_t req_anull:1;
714 uint64_t req_undflw:1;
715 uint64_t req_ovrflw:1;
716 uint64_t req_badlen:1;
717 uint64_t req_badadr:1;
718 uint64_t dmadbo:8;
719 uint64_t reserved_2_7:6;
720 uint64_t nfovr:1;
721 uint64_t nderr:1;
722#else
723 uint64_t nderr:1;
724 uint64_t nfovr:1;
725 uint64_t reserved_2_7:6;
726 uint64_t dmadbo:8;
727 uint64_t req_badadr:1;
728 uint64_t req_badlen:1;
729 uint64_t req_ovrflw:1;
730 uint64_t req_undflw:1;
731 uint64_t req_anull:1;
732 uint64_t req_inull:1;
733 uint64_t req_badfil:1;
734 uint64_t reserved_23_23:1;
735 uint64_t sprt0_rst:1;
736 uint64_t sprt1_rst:1;
737 uint64_t reserved_26_63:38;
738#endif
739 } cn63xx;
740 struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
741 struct cvmx_dpi_int_reg_s cn66xx;
742 struct cvmx_dpi_int_reg_cn63xx cn68xx;
743 struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
744 struct cvmx_dpi_int_reg_s cnf71xx;
745};
746
747union cvmx_dpi_ncbx_cfg {
748 uint64_t u64;
749 struct cvmx_dpi_ncbx_cfg_s {
750#ifdef __BIG_ENDIAN_BITFIELD
751 uint64_t reserved_6_63:58;
752 uint64_t molr:6;
753#else
754 uint64_t molr:6;
755 uint64_t reserved_6_63:58;
756#endif
757 } s;
758 struct cvmx_dpi_ncbx_cfg_s cn61xx;
759 struct cvmx_dpi_ncbx_cfg_s cn66xx;
760 struct cvmx_dpi_ncbx_cfg_s cn68xx;
761 struct cvmx_dpi_ncbx_cfg_s cnf71xx;
762};
763
764union cvmx_dpi_pint_info {
765 uint64_t u64;
766 struct cvmx_dpi_pint_info_s {
767#ifdef __BIG_ENDIAN_BITFIELD
768 uint64_t reserved_14_63:50;
769 uint64_t iinfo:6;
770 uint64_t reserved_6_7:2;
771 uint64_t sinfo:6;
772#else
773 uint64_t sinfo:6;
774 uint64_t reserved_6_7:2;
775 uint64_t iinfo:6;
776 uint64_t reserved_14_63:50;
777#endif
778 } s;
779 struct cvmx_dpi_pint_info_s cn61xx;
780 struct cvmx_dpi_pint_info_s cn63xx;
781 struct cvmx_dpi_pint_info_s cn63xxp1;
782 struct cvmx_dpi_pint_info_s cn66xx;
783 struct cvmx_dpi_pint_info_s cn68xx;
784 struct cvmx_dpi_pint_info_s cn68xxp1;
785 struct cvmx_dpi_pint_info_s cnf71xx;
786};
787
788union cvmx_dpi_pkt_err_rsp {
789 uint64_t u64;
790 struct cvmx_dpi_pkt_err_rsp_s {
791#ifdef __BIG_ENDIAN_BITFIELD
792 uint64_t reserved_1_63:63;
793 uint64_t pkterr:1;
794#else
795 uint64_t pkterr:1;
796 uint64_t reserved_1_63:63;
797#endif
798 } s;
799 struct cvmx_dpi_pkt_err_rsp_s cn61xx;
800 struct cvmx_dpi_pkt_err_rsp_s cn63xx;
801 struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
802 struct cvmx_dpi_pkt_err_rsp_s cn66xx;
803 struct cvmx_dpi_pkt_err_rsp_s cn68xx;
804 struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
805 struct cvmx_dpi_pkt_err_rsp_s cnf71xx;
806};
807
808union cvmx_dpi_req_err_rsp {
809 uint64_t u64;
810 struct cvmx_dpi_req_err_rsp_s {
811#ifdef __BIG_ENDIAN_BITFIELD
812 uint64_t reserved_8_63:56;
813 uint64_t qerr:8;
814#else
815 uint64_t qerr:8;
816 uint64_t reserved_8_63:56;
817#endif
818 } s;
819 struct cvmx_dpi_req_err_rsp_s cn61xx;
820 struct cvmx_dpi_req_err_rsp_s cn63xx;
821 struct cvmx_dpi_req_err_rsp_s cn63xxp1;
822 struct cvmx_dpi_req_err_rsp_s cn66xx;
823 struct cvmx_dpi_req_err_rsp_s cn68xx;
824 struct cvmx_dpi_req_err_rsp_s cn68xxp1;
825 struct cvmx_dpi_req_err_rsp_s cnf71xx;
826};
827
828union cvmx_dpi_req_err_rsp_en {
829 uint64_t u64;
830 struct cvmx_dpi_req_err_rsp_en_s {
831#ifdef __BIG_ENDIAN_BITFIELD
832 uint64_t reserved_8_63:56;
833 uint64_t en:8;
834#else
835 uint64_t en:8;
836 uint64_t reserved_8_63:56;
837#endif
838 } s;
839 struct cvmx_dpi_req_err_rsp_en_s cn61xx;
840 struct cvmx_dpi_req_err_rsp_en_s cn63xx;
841 struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
842 struct cvmx_dpi_req_err_rsp_en_s cn66xx;
843 struct cvmx_dpi_req_err_rsp_en_s cn68xx;
844 struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
845 struct cvmx_dpi_req_err_rsp_en_s cnf71xx;
846};
847
848union cvmx_dpi_req_err_rst {
849 uint64_t u64;
850 struct cvmx_dpi_req_err_rst_s {
851#ifdef __BIG_ENDIAN_BITFIELD
852 uint64_t reserved_8_63:56;
853 uint64_t qerr:8;
854#else
855 uint64_t qerr:8;
856 uint64_t reserved_8_63:56;
857#endif
858 } s;
859 struct cvmx_dpi_req_err_rst_s cn61xx;
860 struct cvmx_dpi_req_err_rst_s cn63xx;
861 struct cvmx_dpi_req_err_rst_s cn63xxp1;
862 struct cvmx_dpi_req_err_rst_s cn66xx;
863 struct cvmx_dpi_req_err_rst_s cn68xx;
864 struct cvmx_dpi_req_err_rst_s cn68xxp1;
865 struct cvmx_dpi_req_err_rst_s cnf71xx;
866};
867
868union cvmx_dpi_req_err_rst_en {
869 uint64_t u64;
870 struct cvmx_dpi_req_err_rst_en_s {
871#ifdef __BIG_ENDIAN_BITFIELD
872 uint64_t reserved_8_63:56;
873 uint64_t en:8;
874#else
875 uint64_t en:8;
876 uint64_t reserved_8_63:56;
877#endif
878 } s;
879 struct cvmx_dpi_req_err_rst_en_s cn61xx;
880 struct cvmx_dpi_req_err_rst_en_s cn63xx;
881 struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
882 struct cvmx_dpi_req_err_rst_en_s cn66xx;
883 struct cvmx_dpi_req_err_rst_en_s cn68xx;
884 struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
885 struct cvmx_dpi_req_err_rst_en_s cnf71xx;
886};
887
888union cvmx_dpi_req_err_skip_comp {
889 uint64_t u64;
890 struct cvmx_dpi_req_err_skip_comp_s {
891#ifdef __BIG_ENDIAN_BITFIELD
892 uint64_t reserved_24_63:40;
893 uint64_t en_rst:8;
894 uint64_t reserved_8_15:8;
895 uint64_t en_rsp:8;
896#else
897 uint64_t en_rsp:8;
898 uint64_t reserved_8_15:8;
899 uint64_t en_rst:8;
900 uint64_t reserved_24_63:40;
901#endif
902 } s;
903 struct cvmx_dpi_req_err_skip_comp_s cn61xx;
904 struct cvmx_dpi_req_err_skip_comp_s cn66xx;
905 struct cvmx_dpi_req_err_skip_comp_s cn68xx;
906 struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
907 struct cvmx_dpi_req_err_skip_comp_s cnf71xx;
908};
909
910union cvmx_dpi_req_gbl_en {
911 uint64_t u64;
912 struct cvmx_dpi_req_gbl_en_s {
913#ifdef __BIG_ENDIAN_BITFIELD
914 uint64_t reserved_8_63:56;
915 uint64_t qen:8;
916#else
917 uint64_t qen:8;
918 uint64_t reserved_8_63:56;
919#endif
920 } s;
921 struct cvmx_dpi_req_gbl_en_s cn61xx;
922 struct cvmx_dpi_req_gbl_en_s cn63xx;
923 struct cvmx_dpi_req_gbl_en_s cn63xxp1;
924 struct cvmx_dpi_req_gbl_en_s cn66xx;
925 struct cvmx_dpi_req_gbl_en_s cn68xx;
926 struct cvmx_dpi_req_gbl_en_s cn68xxp1;
927 struct cvmx_dpi_req_gbl_en_s cnf71xx;
928};
929
930union cvmx_dpi_sli_prtx_cfg {
931 uint64_t u64;
932 struct cvmx_dpi_sli_prtx_cfg_s {
933#ifdef __BIG_ENDIAN_BITFIELD
934 uint64_t reserved_25_63:39;
935 uint64_t halt:1;
936 uint64_t qlm_cfg:4;
937 uint64_t reserved_17_19:3;
938 uint64_t rd_mode:1;
939 uint64_t reserved_14_15:2;
940 uint64_t molr:6;
941 uint64_t mps_lim:1;
942 uint64_t reserved_5_6:2;
943 uint64_t mps:1;
944 uint64_t mrrs_lim:1;
945 uint64_t reserved_2_2:1;
946 uint64_t mrrs:2;
947#else
948 uint64_t mrrs:2;
949 uint64_t reserved_2_2:1;
950 uint64_t mrrs_lim:1;
951 uint64_t mps:1;
952 uint64_t reserved_5_6:2;
953 uint64_t mps_lim:1;
954 uint64_t molr:6;
955 uint64_t reserved_14_15:2;
956 uint64_t rd_mode:1;
957 uint64_t reserved_17_19:3;
958 uint64_t qlm_cfg:4;
959 uint64_t halt:1;
960 uint64_t reserved_25_63:39;
961#endif
962 } s;
963 struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
964 struct cvmx_dpi_sli_prtx_cfg_cn63xx {
965#ifdef __BIG_ENDIAN_BITFIELD
966 uint64_t reserved_25_63:39;
967 uint64_t halt:1;
968 uint64_t reserved_21_23:3;
969 uint64_t qlm_cfg:1;
970 uint64_t reserved_17_19:3;
971 uint64_t rd_mode:1;
972 uint64_t reserved_14_15:2;
973 uint64_t molr:6;
974 uint64_t mps_lim:1;
975 uint64_t reserved_5_6:2;
976 uint64_t mps:1;
977 uint64_t mrrs_lim:1;
978 uint64_t reserved_2_2:1;
979 uint64_t mrrs:2;
980#else
981 uint64_t mrrs:2;
982 uint64_t reserved_2_2:1;
983 uint64_t mrrs_lim:1;
984 uint64_t mps:1;
985 uint64_t reserved_5_6:2;
986 uint64_t mps_lim:1;
987 uint64_t molr:6;
988 uint64_t reserved_14_15:2;
989 uint64_t rd_mode:1;
990 uint64_t reserved_17_19:3;
991 uint64_t qlm_cfg:1;
992 uint64_t reserved_21_23:3;
993 uint64_t halt:1;
994 uint64_t reserved_25_63:39;
995#endif
996 } cn63xx;
997 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
998 struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
999 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
1000 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
1001 struct cvmx_dpi_sli_prtx_cfg_s cnf71xx;
1002};
1003
1004union cvmx_dpi_sli_prtx_err {
1005 uint64_t u64;
1006 struct cvmx_dpi_sli_prtx_err_s {
1007#ifdef __BIG_ENDIAN_BITFIELD
1008 uint64_t addr:61;
1009 uint64_t reserved_0_2:3;
1010#else
1011 uint64_t reserved_0_2:3;
1012 uint64_t addr:61;
1013#endif
1014 } s;
1015 struct cvmx_dpi_sli_prtx_err_s cn61xx;
1016 struct cvmx_dpi_sli_prtx_err_s cn63xx;
1017 struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
1018 struct cvmx_dpi_sli_prtx_err_s cn66xx;
1019 struct cvmx_dpi_sli_prtx_err_s cn68xx;
1020 struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
1021 struct cvmx_dpi_sli_prtx_err_s cnf71xx;
1022};
1023
1024union cvmx_dpi_sli_prtx_err_info {
1025 uint64_t u64;
1026 struct cvmx_dpi_sli_prtx_err_info_s {
1027#ifdef __BIG_ENDIAN_BITFIELD
1028 uint64_t reserved_9_63:55;
1029 uint64_t lock:1;
1030 uint64_t reserved_5_7:3;
1031 uint64_t type:1;
1032 uint64_t reserved_3_3:1;
1033 uint64_t reqq:3;
1034#else
1035 uint64_t reqq:3;
1036 uint64_t reserved_3_3:1;
1037 uint64_t type:1;
1038 uint64_t reserved_5_7:3;
1039 uint64_t lock:1;
1040 uint64_t reserved_9_63:55;
1041#endif
1042 } s;
1043 struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
1044 struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
1045 struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
1046 struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
1047 struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
1048 struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
1049 struct cvmx_dpi_sli_prtx_err_info_s cnf71xx;
1050};
1051
1052#endif
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_DPI_DEFS_H__
29#define __CVMX_DPI_DEFS_H__
30
31#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
32#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
33#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
37#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
41#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
42#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
43#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
44#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
45#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
46#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
47#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
48#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
49#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
50#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
51#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
52#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
53#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
54#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
55#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
56#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
57#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
58static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
59{
60 switch (cvmx_get_octeon_family()) {
61 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
62 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
63 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
64 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
65 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
66
67 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
68 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
69
70 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
71 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
72 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
73 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
74 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
75 }
76 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
77}
78
79#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
80
81union cvmx_dpi_bist_status {
82 uint64_t u64;
83 struct cvmx_dpi_bist_status_s {
84#ifdef __BIG_ENDIAN_BITFIELD
85 uint64_t reserved_47_63:17;
86 uint64_t bist:47;
87#else
88 uint64_t bist:47;
89 uint64_t reserved_47_63:17;
90#endif
91 } s;
92 struct cvmx_dpi_bist_status_cn63xx {
93#ifdef __BIG_ENDIAN_BITFIELD
94 uint64_t reserved_45_63:19;
95 uint64_t bist:45;
96#else
97 uint64_t bist:45;
98 uint64_t reserved_45_63:19;
99#endif
100 } cn63xx;
101 struct cvmx_dpi_bist_status_cn63xxp1 {
102#ifdef __BIG_ENDIAN_BITFIELD
103 uint64_t reserved_37_63:27;
104 uint64_t bist:37;
105#else
106 uint64_t bist:37;
107 uint64_t reserved_37_63:27;
108#endif
109 } cn63xxp1;
110};
111
112union cvmx_dpi_ctl {
113 uint64_t u64;
114 struct cvmx_dpi_ctl_s {
115#ifdef __BIG_ENDIAN_BITFIELD
116 uint64_t reserved_2_63:62;
117 uint64_t clk:1;
118 uint64_t en:1;
119#else
120 uint64_t en:1;
121 uint64_t clk:1;
122 uint64_t reserved_2_63:62;
123#endif
124 } s;
125 struct cvmx_dpi_ctl_cn61xx {
126#ifdef __BIG_ENDIAN_BITFIELD
127 uint64_t reserved_1_63:63;
128 uint64_t en:1;
129#else
130 uint64_t en:1;
131 uint64_t reserved_1_63:63;
132#endif
133 } cn61xx;
134};
135
136union cvmx_dpi_dmax_counts {
137 uint64_t u64;
138 struct cvmx_dpi_dmax_counts_s {
139#ifdef __BIG_ENDIAN_BITFIELD
140 uint64_t reserved_39_63:25;
141 uint64_t fcnt:7;
142 uint64_t dbell:32;
143#else
144 uint64_t dbell:32;
145 uint64_t fcnt:7;
146 uint64_t reserved_39_63:25;
147#endif
148 } s;
149};
150
151union cvmx_dpi_dmax_dbell {
152 uint64_t u64;
153 struct cvmx_dpi_dmax_dbell_s {
154#ifdef __BIG_ENDIAN_BITFIELD
155 uint64_t reserved_16_63:48;
156 uint64_t dbell:16;
157#else
158 uint64_t dbell:16;
159 uint64_t reserved_16_63:48;
160#endif
161 } s;
162};
163
164union cvmx_dpi_dmax_err_rsp_status {
165 uint64_t u64;
166 struct cvmx_dpi_dmax_err_rsp_status_s {
167#ifdef __BIG_ENDIAN_BITFIELD
168 uint64_t reserved_6_63:58;
169 uint64_t status:6;
170#else
171 uint64_t status:6;
172 uint64_t reserved_6_63:58;
173#endif
174 } s;
175};
176
177union cvmx_dpi_dmax_ibuff_saddr {
178 uint64_t u64;
179 struct cvmx_dpi_dmax_ibuff_saddr_s {
180#ifdef __BIG_ENDIAN_BITFIELD
181 uint64_t reserved_62_63:2;
182 uint64_t csize:14;
183 uint64_t reserved_41_47:7;
184 uint64_t idle:1;
185 uint64_t saddr:33;
186 uint64_t reserved_0_6:7;
187#else
188 uint64_t reserved_0_6:7;
189 uint64_t saddr:33;
190 uint64_t idle:1;
191 uint64_t reserved_41_47:7;
192 uint64_t csize:14;
193 uint64_t reserved_62_63:2;
194#endif
195 } s;
196 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
197#ifdef __BIG_ENDIAN_BITFIELD
198 uint64_t reserved_62_63:2;
199 uint64_t csize:14;
200 uint64_t reserved_41_47:7;
201 uint64_t idle:1;
202 uint64_t reserved_36_39:4;
203 uint64_t saddr:29;
204 uint64_t reserved_0_6:7;
205#else
206 uint64_t reserved_0_6:7;
207 uint64_t saddr:29;
208 uint64_t reserved_36_39:4;
209 uint64_t idle:1;
210 uint64_t reserved_41_47:7;
211 uint64_t csize:14;
212 uint64_t reserved_62_63:2;
213#endif
214 } cn61xx;
215};
216
217union cvmx_dpi_dmax_iflight {
218 uint64_t u64;
219 struct cvmx_dpi_dmax_iflight_s {
220#ifdef __BIG_ENDIAN_BITFIELD
221 uint64_t reserved_3_63:61;
222 uint64_t cnt:3;
223#else
224 uint64_t cnt:3;
225 uint64_t reserved_3_63:61;
226#endif
227 } s;
228};
229
230union cvmx_dpi_dmax_naddr {
231 uint64_t u64;
232 struct cvmx_dpi_dmax_naddr_s {
233#ifdef __BIG_ENDIAN_BITFIELD
234 uint64_t reserved_40_63:24;
235 uint64_t addr:40;
236#else
237 uint64_t addr:40;
238 uint64_t reserved_40_63:24;
239#endif
240 } s;
241 struct cvmx_dpi_dmax_naddr_cn61xx {
242#ifdef __BIG_ENDIAN_BITFIELD
243 uint64_t reserved_36_63:28;
244 uint64_t addr:36;
245#else
246 uint64_t addr:36;
247 uint64_t reserved_36_63:28;
248#endif
249 } cn61xx;
250};
251
252union cvmx_dpi_dmax_reqbnk0 {
253 uint64_t u64;
254 struct cvmx_dpi_dmax_reqbnk0_s {
255#ifdef __BIG_ENDIAN_BITFIELD
256 uint64_t state:64;
257#else
258 uint64_t state:64;
259#endif
260 } s;
261};
262
263union cvmx_dpi_dmax_reqbnk1 {
264 uint64_t u64;
265 struct cvmx_dpi_dmax_reqbnk1_s {
266#ifdef __BIG_ENDIAN_BITFIELD
267 uint64_t state:64;
268#else
269 uint64_t state:64;
270#endif
271 } s;
272};
273
274union cvmx_dpi_dma_control {
275 uint64_t u64;
276 struct cvmx_dpi_dma_control_s {
277#ifdef __BIG_ENDIAN_BITFIELD
278 uint64_t reserved_62_63:2;
279 uint64_t dici_mode:1;
280 uint64_t pkt_en1:1;
281 uint64_t ffp_dis:1;
282 uint64_t commit_mode:1;
283 uint64_t pkt_hp:1;
284 uint64_t pkt_en:1;
285 uint64_t reserved_54_55:2;
286 uint64_t dma_enb:6;
287 uint64_t reserved_34_47:14;
288 uint64_t b0_lend:1;
289 uint64_t dwb_denb:1;
290 uint64_t dwb_ichk:9;
291 uint64_t fpa_que:3;
292 uint64_t o_add1:1;
293 uint64_t o_ro:1;
294 uint64_t o_ns:1;
295 uint64_t o_es:2;
296 uint64_t o_mode:1;
297 uint64_t reserved_0_13:14;
298#else
299 uint64_t reserved_0_13:14;
300 uint64_t o_mode:1;
301 uint64_t o_es:2;
302 uint64_t o_ns:1;
303 uint64_t o_ro:1;
304 uint64_t o_add1:1;
305 uint64_t fpa_que:3;
306 uint64_t dwb_ichk:9;
307 uint64_t dwb_denb:1;
308 uint64_t b0_lend:1;
309 uint64_t reserved_34_47:14;
310 uint64_t dma_enb:6;
311 uint64_t reserved_54_55:2;
312 uint64_t pkt_en:1;
313 uint64_t pkt_hp:1;
314 uint64_t commit_mode:1;
315 uint64_t ffp_dis:1;
316 uint64_t pkt_en1:1;
317 uint64_t dici_mode:1;
318 uint64_t reserved_62_63:2;
319#endif
320 } s;
321 struct cvmx_dpi_dma_control_cn63xx {
322#ifdef __BIG_ENDIAN_BITFIELD
323 uint64_t reserved_61_63:3;
324 uint64_t pkt_en1:1;
325 uint64_t ffp_dis:1;
326 uint64_t commit_mode:1;
327 uint64_t pkt_hp:1;
328 uint64_t pkt_en:1;
329 uint64_t reserved_54_55:2;
330 uint64_t dma_enb:6;
331 uint64_t reserved_34_47:14;
332 uint64_t b0_lend:1;
333 uint64_t dwb_denb:1;
334 uint64_t dwb_ichk:9;
335 uint64_t fpa_que:3;
336 uint64_t o_add1:1;
337 uint64_t o_ro:1;
338 uint64_t o_ns:1;
339 uint64_t o_es:2;
340 uint64_t o_mode:1;
341 uint64_t reserved_0_13:14;
342#else
343 uint64_t reserved_0_13:14;
344 uint64_t o_mode:1;
345 uint64_t o_es:2;
346 uint64_t o_ns:1;
347 uint64_t o_ro:1;
348 uint64_t o_add1:1;
349 uint64_t fpa_que:3;
350 uint64_t dwb_ichk:9;
351 uint64_t dwb_denb:1;
352 uint64_t b0_lend:1;
353 uint64_t reserved_34_47:14;
354 uint64_t dma_enb:6;
355 uint64_t reserved_54_55:2;
356 uint64_t pkt_en:1;
357 uint64_t pkt_hp:1;
358 uint64_t commit_mode:1;
359 uint64_t ffp_dis:1;
360 uint64_t pkt_en1:1;
361 uint64_t reserved_61_63:3;
362#endif
363 } cn63xx;
364 struct cvmx_dpi_dma_control_cn63xxp1 {
365#ifdef __BIG_ENDIAN_BITFIELD
366 uint64_t reserved_59_63:5;
367 uint64_t commit_mode:1;
368 uint64_t pkt_hp:1;
369 uint64_t pkt_en:1;
370 uint64_t reserved_54_55:2;
371 uint64_t dma_enb:6;
372 uint64_t reserved_34_47:14;
373 uint64_t b0_lend:1;
374 uint64_t dwb_denb:1;
375 uint64_t dwb_ichk:9;
376 uint64_t fpa_que:3;
377 uint64_t o_add1:1;
378 uint64_t o_ro:1;
379 uint64_t o_ns:1;
380 uint64_t o_es:2;
381 uint64_t o_mode:1;
382 uint64_t reserved_0_13:14;
383#else
384 uint64_t reserved_0_13:14;
385 uint64_t o_mode:1;
386 uint64_t o_es:2;
387 uint64_t o_ns:1;
388 uint64_t o_ro:1;
389 uint64_t o_add1:1;
390 uint64_t fpa_que:3;
391 uint64_t dwb_ichk:9;
392 uint64_t dwb_denb:1;
393 uint64_t b0_lend:1;
394 uint64_t reserved_34_47:14;
395 uint64_t dma_enb:6;
396 uint64_t reserved_54_55:2;
397 uint64_t pkt_en:1;
398 uint64_t pkt_hp:1;
399 uint64_t commit_mode:1;
400 uint64_t reserved_59_63:5;
401#endif
402 } cn63xxp1;
403};
404
405union cvmx_dpi_dma_engx_en {
406 uint64_t u64;
407 struct cvmx_dpi_dma_engx_en_s {
408#ifdef __BIG_ENDIAN_BITFIELD
409 uint64_t reserved_8_63:56;
410 uint64_t qen:8;
411#else
412 uint64_t qen:8;
413 uint64_t reserved_8_63:56;
414#endif
415 } s;
416};
417
418union cvmx_dpi_dma_ppx_cnt {
419 uint64_t u64;
420 struct cvmx_dpi_dma_ppx_cnt_s {
421#ifdef __BIG_ENDIAN_BITFIELD
422 uint64_t reserved_16_63:48;
423 uint64_t cnt:16;
424#else
425 uint64_t cnt:16;
426 uint64_t reserved_16_63:48;
427#endif
428 } s;
429};
430
431union cvmx_dpi_engx_buf {
432 uint64_t u64;
433 struct cvmx_dpi_engx_buf_s {
434#ifdef __BIG_ENDIAN_BITFIELD
435 uint64_t reserved_37_63:27;
436 uint64_t compblks:5;
437 uint64_t reserved_9_31:23;
438 uint64_t base:5;
439 uint64_t blks:4;
440#else
441 uint64_t blks:4;
442 uint64_t base:5;
443 uint64_t reserved_9_31:23;
444 uint64_t compblks:5;
445 uint64_t reserved_37_63:27;
446#endif
447 } s;
448 struct cvmx_dpi_engx_buf_cn63xx {
449#ifdef __BIG_ENDIAN_BITFIELD
450 uint64_t reserved_8_63:56;
451 uint64_t base:4;
452 uint64_t blks:4;
453#else
454 uint64_t blks:4;
455 uint64_t base:4;
456 uint64_t reserved_8_63:56;
457#endif
458 } cn63xx;
459};
460
461union cvmx_dpi_info_reg {
462 uint64_t u64;
463 struct cvmx_dpi_info_reg_s {
464#ifdef __BIG_ENDIAN_BITFIELD
465 uint64_t reserved_8_63:56;
466 uint64_t ffp:4;
467 uint64_t reserved_2_3:2;
468 uint64_t ncb:1;
469 uint64_t rsl:1;
470#else
471 uint64_t rsl:1;
472 uint64_t ncb:1;
473 uint64_t reserved_2_3:2;
474 uint64_t ffp:4;
475 uint64_t reserved_8_63:56;
476#endif
477 } s;
478 struct cvmx_dpi_info_reg_cn63xxp1 {
479#ifdef __BIG_ENDIAN_BITFIELD
480 uint64_t reserved_2_63:62;
481 uint64_t ncb:1;
482 uint64_t rsl:1;
483#else
484 uint64_t rsl:1;
485 uint64_t ncb:1;
486 uint64_t reserved_2_63:62;
487#endif
488 } cn63xxp1;
489};
490
491union cvmx_dpi_int_en {
492 uint64_t u64;
493 struct cvmx_dpi_int_en_s {
494#ifdef __BIG_ENDIAN_BITFIELD
495 uint64_t reserved_28_63:36;
496 uint64_t sprt3_rst:1;
497 uint64_t sprt2_rst:1;
498 uint64_t sprt1_rst:1;
499 uint64_t sprt0_rst:1;
500 uint64_t reserved_23_23:1;
501 uint64_t req_badfil:1;
502 uint64_t req_inull:1;
503 uint64_t req_anull:1;
504 uint64_t req_undflw:1;
505 uint64_t req_ovrflw:1;
506 uint64_t req_badlen:1;
507 uint64_t req_badadr:1;
508 uint64_t dmadbo:8;
509 uint64_t reserved_2_7:6;
510 uint64_t nfovr:1;
511 uint64_t nderr:1;
512#else
513 uint64_t nderr:1;
514 uint64_t nfovr:1;
515 uint64_t reserved_2_7:6;
516 uint64_t dmadbo:8;
517 uint64_t req_badadr:1;
518 uint64_t req_badlen:1;
519 uint64_t req_ovrflw:1;
520 uint64_t req_undflw:1;
521 uint64_t req_anull:1;
522 uint64_t req_inull:1;
523 uint64_t req_badfil:1;
524 uint64_t reserved_23_23:1;
525 uint64_t sprt0_rst:1;
526 uint64_t sprt1_rst:1;
527 uint64_t sprt2_rst:1;
528 uint64_t sprt3_rst:1;
529 uint64_t reserved_28_63:36;
530#endif
531 } s;
532 struct cvmx_dpi_int_en_cn63xx {
533#ifdef __BIG_ENDIAN_BITFIELD
534 uint64_t reserved_26_63:38;
535 uint64_t sprt1_rst:1;
536 uint64_t sprt0_rst:1;
537 uint64_t reserved_23_23:1;
538 uint64_t req_badfil:1;
539 uint64_t req_inull:1;
540 uint64_t req_anull:1;
541 uint64_t req_undflw:1;
542 uint64_t req_ovrflw:1;
543 uint64_t req_badlen:1;
544 uint64_t req_badadr:1;
545 uint64_t dmadbo:8;
546 uint64_t reserved_2_7:6;
547 uint64_t nfovr:1;
548 uint64_t nderr:1;
549#else
550 uint64_t nderr:1;
551 uint64_t nfovr:1;
552 uint64_t reserved_2_7:6;
553 uint64_t dmadbo:8;
554 uint64_t req_badadr:1;
555 uint64_t req_badlen:1;
556 uint64_t req_ovrflw:1;
557 uint64_t req_undflw:1;
558 uint64_t req_anull:1;
559 uint64_t req_inull:1;
560 uint64_t req_badfil:1;
561 uint64_t reserved_23_23:1;
562 uint64_t sprt0_rst:1;
563 uint64_t sprt1_rst:1;
564 uint64_t reserved_26_63:38;
565#endif
566 } cn63xx;
567};
568
569union cvmx_dpi_int_reg {
570 uint64_t u64;
571 struct cvmx_dpi_int_reg_s {
572#ifdef __BIG_ENDIAN_BITFIELD
573 uint64_t reserved_28_63:36;
574 uint64_t sprt3_rst:1;
575 uint64_t sprt2_rst:1;
576 uint64_t sprt1_rst:1;
577 uint64_t sprt0_rst:1;
578 uint64_t reserved_23_23:1;
579 uint64_t req_badfil:1;
580 uint64_t req_inull:1;
581 uint64_t req_anull:1;
582 uint64_t req_undflw:1;
583 uint64_t req_ovrflw:1;
584 uint64_t req_badlen:1;
585 uint64_t req_badadr:1;
586 uint64_t dmadbo:8;
587 uint64_t reserved_2_7:6;
588 uint64_t nfovr:1;
589 uint64_t nderr:1;
590#else
591 uint64_t nderr:1;
592 uint64_t nfovr:1;
593 uint64_t reserved_2_7:6;
594 uint64_t dmadbo:8;
595 uint64_t req_badadr:1;
596 uint64_t req_badlen:1;
597 uint64_t req_ovrflw:1;
598 uint64_t req_undflw:1;
599 uint64_t req_anull:1;
600 uint64_t req_inull:1;
601 uint64_t req_badfil:1;
602 uint64_t reserved_23_23:1;
603 uint64_t sprt0_rst:1;
604 uint64_t sprt1_rst:1;
605 uint64_t sprt2_rst:1;
606 uint64_t sprt3_rst:1;
607 uint64_t reserved_28_63:36;
608#endif
609 } s;
610 struct cvmx_dpi_int_reg_cn63xx {
611#ifdef __BIG_ENDIAN_BITFIELD
612 uint64_t reserved_26_63:38;
613 uint64_t sprt1_rst:1;
614 uint64_t sprt0_rst:1;
615 uint64_t reserved_23_23:1;
616 uint64_t req_badfil:1;
617 uint64_t req_inull:1;
618 uint64_t req_anull:1;
619 uint64_t req_undflw:1;
620 uint64_t req_ovrflw:1;
621 uint64_t req_badlen:1;
622 uint64_t req_badadr:1;
623 uint64_t dmadbo:8;
624 uint64_t reserved_2_7:6;
625 uint64_t nfovr:1;
626 uint64_t nderr:1;
627#else
628 uint64_t nderr:1;
629 uint64_t nfovr:1;
630 uint64_t reserved_2_7:6;
631 uint64_t dmadbo:8;
632 uint64_t req_badadr:1;
633 uint64_t req_badlen:1;
634 uint64_t req_ovrflw:1;
635 uint64_t req_undflw:1;
636 uint64_t req_anull:1;
637 uint64_t req_inull:1;
638 uint64_t req_badfil:1;
639 uint64_t reserved_23_23:1;
640 uint64_t sprt0_rst:1;
641 uint64_t sprt1_rst:1;
642 uint64_t reserved_26_63:38;
643#endif
644 } cn63xx;
645};
646
647union cvmx_dpi_ncbx_cfg {
648 uint64_t u64;
649 struct cvmx_dpi_ncbx_cfg_s {
650#ifdef __BIG_ENDIAN_BITFIELD
651 uint64_t reserved_6_63:58;
652 uint64_t molr:6;
653#else
654 uint64_t molr:6;
655 uint64_t reserved_6_63:58;
656#endif
657 } s;
658};
659
660union cvmx_dpi_pint_info {
661 uint64_t u64;
662 struct cvmx_dpi_pint_info_s {
663#ifdef __BIG_ENDIAN_BITFIELD
664 uint64_t reserved_14_63:50;
665 uint64_t iinfo:6;
666 uint64_t reserved_6_7:2;
667 uint64_t sinfo:6;
668#else
669 uint64_t sinfo:6;
670 uint64_t reserved_6_7:2;
671 uint64_t iinfo:6;
672 uint64_t reserved_14_63:50;
673#endif
674 } s;
675};
676
677union cvmx_dpi_pkt_err_rsp {
678 uint64_t u64;
679 struct cvmx_dpi_pkt_err_rsp_s {
680#ifdef __BIG_ENDIAN_BITFIELD
681 uint64_t reserved_1_63:63;
682 uint64_t pkterr:1;
683#else
684 uint64_t pkterr:1;
685 uint64_t reserved_1_63:63;
686#endif
687 } s;
688};
689
690union cvmx_dpi_req_err_rsp {
691 uint64_t u64;
692 struct cvmx_dpi_req_err_rsp_s {
693#ifdef __BIG_ENDIAN_BITFIELD
694 uint64_t reserved_8_63:56;
695 uint64_t qerr:8;
696#else
697 uint64_t qerr:8;
698 uint64_t reserved_8_63:56;
699#endif
700 } s;
701};
702
703union cvmx_dpi_req_err_rsp_en {
704 uint64_t u64;
705 struct cvmx_dpi_req_err_rsp_en_s {
706#ifdef __BIG_ENDIAN_BITFIELD
707 uint64_t reserved_8_63:56;
708 uint64_t en:8;
709#else
710 uint64_t en:8;
711 uint64_t reserved_8_63:56;
712#endif
713 } s;
714};
715
716union cvmx_dpi_req_err_rst {
717 uint64_t u64;
718 struct cvmx_dpi_req_err_rst_s {
719#ifdef __BIG_ENDIAN_BITFIELD
720 uint64_t reserved_8_63:56;
721 uint64_t qerr:8;
722#else
723 uint64_t qerr:8;
724 uint64_t reserved_8_63:56;
725#endif
726 } s;
727};
728
729union cvmx_dpi_req_err_rst_en {
730 uint64_t u64;
731 struct cvmx_dpi_req_err_rst_en_s {
732#ifdef __BIG_ENDIAN_BITFIELD
733 uint64_t reserved_8_63:56;
734 uint64_t en:8;
735#else
736 uint64_t en:8;
737 uint64_t reserved_8_63:56;
738#endif
739 } s;
740};
741
742union cvmx_dpi_req_err_skip_comp {
743 uint64_t u64;
744 struct cvmx_dpi_req_err_skip_comp_s {
745#ifdef __BIG_ENDIAN_BITFIELD
746 uint64_t reserved_24_63:40;
747 uint64_t en_rst:8;
748 uint64_t reserved_8_15:8;
749 uint64_t en_rsp:8;
750#else
751 uint64_t en_rsp:8;
752 uint64_t reserved_8_15:8;
753 uint64_t en_rst:8;
754 uint64_t reserved_24_63:40;
755#endif
756 } s;
757};
758
759union cvmx_dpi_req_gbl_en {
760 uint64_t u64;
761 struct cvmx_dpi_req_gbl_en_s {
762#ifdef __BIG_ENDIAN_BITFIELD
763 uint64_t reserved_8_63:56;
764 uint64_t qen:8;
765#else
766 uint64_t qen:8;
767 uint64_t reserved_8_63:56;
768#endif
769 } s;
770};
771
772union cvmx_dpi_sli_prtx_cfg {
773 uint64_t u64;
774 struct cvmx_dpi_sli_prtx_cfg_s {
775#ifdef __BIG_ENDIAN_BITFIELD
776 uint64_t reserved_25_63:39;
777 uint64_t halt:1;
778 uint64_t qlm_cfg:4;
779 uint64_t reserved_17_19:3;
780 uint64_t rd_mode:1;
781 uint64_t reserved_14_15:2;
782 uint64_t molr:6;
783 uint64_t mps_lim:1;
784 uint64_t reserved_5_6:2;
785 uint64_t mps:1;
786 uint64_t mrrs_lim:1;
787 uint64_t reserved_2_2:1;
788 uint64_t mrrs:2;
789#else
790 uint64_t mrrs:2;
791 uint64_t reserved_2_2:1;
792 uint64_t mrrs_lim:1;
793 uint64_t mps:1;
794 uint64_t reserved_5_6:2;
795 uint64_t mps_lim:1;
796 uint64_t molr:6;
797 uint64_t reserved_14_15:2;
798 uint64_t rd_mode:1;
799 uint64_t reserved_17_19:3;
800 uint64_t qlm_cfg:4;
801 uint64_t halt:1;
802 uint64_t reserved_25_63:39;
803#endif
804 } s;
805 struct cvmx_dpi_sli_prtx_cfg_cn63xx {
806#ifdef __BIG_ENDIAN_BITFIELD
807 uint64_t reserved_25_63:39;
808 uint64_t halt:1;
809 uint64_t reserved_21_23:3;
810 uint64_t qlm_cfg:1;
811 uint64_t reserved_17_19:3;
812 uint64_t rd_mode:1;
813 uint64_t reserved_14_15:2;
814 uint64_t molr:6;
815 uint64_t mps_lim:1;
816 uint64_t reserved_5_6:2;
817 uint64_t mps:1;
818 uint64_t mrrs_lim:1;
819 uint64_t reserved_2_2:1;
820 uint64_t mrrs:2;
821#else
822 uint64_t mrrs:2;
823 uint64_t reserved_2_2:1;
824 uint64_t mrrs_lim:1;
825 uint64_t mps:1;
826 uint64_t reserved_5_6:2;
827 uint64_t mps_lim:1;
828 uint64_t molr:6;
829 uint64_t reserved_14_15:2;
830 uint64_t rd_mode:1;
831 uint64_t reserved_17_19:3;
832 uint64_t qlm_cfg:1;
833 uint64_t reserved_21_23:3;
834 uint64_t halt:1;
835 uint64_t reserved_25_63:39;
836#endif
837 } cn63xx;
838};
839
840union cvmx_dpi_sli_prtx_err {
841 uint64_t u64;
842 struct cvmx_dpi_sli_prtx_err_s {
843#ifdef __BIG_ENDIAN_BITFIELD
844 uint64_t addr:61;
845 uint64_t reserved_0_2:3;
846#else
847 uint64_t reserved_0_2:3;
848 uint64_t addr:61;
849#endif
850 } s;
851};
852
853union cvmx_dpi_sli_prtx_err_info {
854 uint64_t u64;
855 struct cvmx_dpi_sli_prtx_err_info_s {
856#ifdef __BIG_ENDIAN_BITFIELD
857 uint64_t reserved_9_63:55;
858 uint64_t lock:1;
859 uint64_t reserved_5_7:3;
860 uint64_t type:1;
861 uint64_t reserved_3_3:1;
862 uint64_t reqq:3;
863#else
864 uint64_t reqq:3;
865 uint64_t reserved_3_3:1;
866 uint64_t type:1;
867 uint64_t reserved_5_7:3;
868 uint64_t lock:1;
869 uint64_t reserved_9_63:55;
870#endif
871 } s;
872};
873
874#endif