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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 *
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
8 */
9
10#include <linux/err.h>
11#include <linux/errno.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/math64.h>
15#include <linux/module.h>
16#include <linux/mtd/mtd.h>
17#include <linux/mtd/spi-nor.h>
18#include <linux/mutex.h>
19#include <linux/of_platform.h>
20#include <linux/sched/task_stack.h>
21#include <linux/sizes.h>
22#include <linux/slab.h>
23#include <linux/spi/flash.h>
24
25#include "core.h"
26
27/* Define max times to check status register before we give up. */
28
29/*
30 * For everything but full-chip erase; probably could be much smaller, but kept
31 * around for safety for now
32 */
33#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
34
35/*
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
37 * for larger flash
38 */
39#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
40
41#define SPI_NOR_MAX_ADDR_NBYTES 4
42
43#define SPI_NOR_SRST_SLEEP_MIN 200
44#define SPI_NOR_SRST_SLEEP_MAX 400
45
46/**
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
48 * extension type.
49 * @nor: pointer to a 'struct spi_nor'
50 * @op: pointer to the 'struct spi_mem_op' whose properties
51 * need to be initialized.
52 *
53 * Right now, only "repeat" and "invert" are supported.
54 *
55 * Return: The opcode extension.
56 */
57static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
58 const struct spi_mem_op *op)
59{
60 switch (nor->cmd_ext_type) {
61 case SPI_NOR_EXT_INVERT:
62 return ~op->cmd.opcode;
63
64 case SPI_NOR_EXT_REPEAT:
65 return op->cmd.opcode;
66
67 default:
68 dev_err(nor->dev, "Unknown command extension type\n");
69 return 0;
70 }
71}
72
73/**
74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
75 * @nor: pointer to a 'struct spi_nor'
76 * @op: pointer to the 'struct spi_mem_op' whose properties
77 * need to be initialized.
78 * @proto: the protocol from which the properties need to be set.
79 */
80void spi_nor_spimem_setup_op(const struct spi_nor *nor,
81 struct spi_mem_op *op,
82 const enum spi_nor_protocol proto)
83{
84 u8 ext;
85
86 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
87
88 if (op->addr.nbytes)
89 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
90
91 if (op->dummy.nbytes)
92 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
93
94 if (op->data.nbytes)
95 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
96
97 if (spi_nor_protocol_is_dtr(proto)) {
98 /*
99 * SPIMEM supports mixed DTR modes, but right now we can only
100 * have all phases either DTR or STR. IOW, SPIMEM can have
101 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4
102 * phases to either DTR or STR.
103 */
104 op->cmd.dtr = true;
105 op->addr.dtr = true;
106 op->dummy.dtr = true;
107 op->data.dtr = true;
108
109 /* 2 bytes per clock cycle in DTR mode. */
110 op->dummy.nbytes *= 2;
111
112 ext = spi_nor_get_cmd_ext(nor, op);
113 op->cmd.opcode = (op->cmd.opcode << 8) | ext;
114 op->cmd.nbytes = 2;
115 }
116
117 if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16)
118 op->data.swap16 = true;
119}
120
121/**
122 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
123 * transfer
124 * @nor: pointer to 'struct spi_nor'
125 * @op: pointer to 'struct spi_mem_op' template for transfer
126 *
127 * If we have to use the bounce buffer, the data field in @op will be updated.
128 *
129 * Return: true if the bounce buffer is needed, false if not
130 */
131static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op)
132{
133 /* op->data.buf.in occupies the same memory as op->data.buf.out */
134 if (object_is_on_stack(op->data.buf.in) ||
135 !virt_addr_valid(op->data.buf.in)) {
136 if (op->data.nbytes > nor->bouncebuf_size)
137 op->data.nbytes = nor->bouncebuf_size;
138 op->data.buf.in = nor->bouncebuf;
139 return true;
140 }
141
142 return false;
143}
144
145/**
146 * spi_nor_spimem_exec_op() - execute a memory operation
147 * @nor: pointer to 'struct spi_nor'
148 * @op: pointer to 'struct spi_mem_op' template for transfer
149 *
150 * Return: 0 on success, -error otherwise.
151 */
152static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op)
153{
154 int error;
155
156 error = spi_mem_adjust_op_size(nor->spimem, op);
157 if (error)
158 return error;
159
160 return spi_mem_exec_op(nor->spimem, op);
161}
162
163int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
164 u8 *buf, size_t len)
165{
166 if (spi_nor_protocol_is_dtr(nor->reg_proto))
167 return -EOPNOTSUPP;
168
169 return nor->controller_ops->read_reg(nor, opcode, buf, len);
170}
171
172int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
173 const u8 *buf, size_t len)
174{
175 if (spi_nor_protocol_is_dtr(nor->reg_proto))
176 return -EOPNOTSUPP;
177
178 return nor->controller_ops->write_reg(nor, opcode, buf, len);
179}
180
181static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs)
182{
183 if (spi_nor_protocol_is_dtr(nor->reg_proto))
184 return -EOPNOTSUPP;
185
186 return nor->controller_ops->erase(nor, offs);
187}
188
189/**
190 * spi_nor_spimem_read_data() - read data from flash's memory region via
191 * spi-mem
192 * @nor: pointer to 'struct spi_nor'
193 * @from: offset to read from
194 * @len: number of bytes to read
195 * @buf: pointer to dst buffer
196 *
197 * Return: number of bytes read successfully, -errno otherwise
198 */
199static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
200 size_t len, u8 *buf)
201{
202 struct spi_mem_op op =
203 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
204 SPI_MEM_OP_ADDR(nor->addr_nbytes, from, 0),
205 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
206 SPI_MEM_OP_DATA_IN(len, buf, 0));
207 bool usebouncebuf;
208 ssize_t nbytes;
209 int error;
210
211 spi_nor_spimem_setup_op(nor, &op, nor->read_proto);
212
213 /* convert the dummy cycles to the number of bytes */
214 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
215 if (spi_nor_protocol_is_dtr(nor->read_proto))
216 op.dummy.nbytes *= 2;
217
218 usebouncebuf = spi_nor_spimem_bounce(nor, &op);
219
220 if (nor->dirmap.rdesc) {
221 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val,
222 op.data.nbytes, op.data.buf.in);
223 } else {
224 error = spi_nor_spimem_exec_op(nor, &op);
225 if (error)
226 return error;
227 nbytes = op.data.nbytes;
228 }
229
230 if (usebouncebuf && nbytes > 0)
231 memcpy(buf, op.data.buf.in, nbytes);
232
233 return nbytes;
234}
235
236/**
237 * spi_nor_read_data() - read data from flash memory
238 * @nor: pointer to 'struct spi_nor'
239 * @from: offset to read from
240 * @len: number of bytes to read
241 * @buf: pointer to dst buffer
242 *
243 * Return: number of bytes read successfully, -errno otherwise
244 */
245ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf)
246{
247 if (nor->spimem)
248 return spi_nor_spimem_read_data(nor, from, len, buf);
249
250 return nor->controller_ops->read(nor, from, len, buf);
251}
252
253/**
254 * spi_nor_spimem_write_data() - write data to flash memory via
255 * spi-mem
256 * @nor: pointer to 'struct spi_nor'
257 * @to: offset to write to
258 * @len: number of bytes to write
259 * @buf: pointer to src buffer
260 *
261 * Return: number of bytes written successfully, -errno otherwise
262 */
263static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
264 size_t len, const u8 *buf)
265{
266 struct spi_mem_op op =
267 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
268 SPI_MEM_OP_ADDR(nor->addr_nbytes, to, 0),
269 SPI_MEM_OP_NO_DUMMY,
270 SPI_MEM_OP_DATA_OUT(len, buf, 0));
271 ssize_t nbytes;
272 int error;
273
274 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
275 op.addr.nbytes = 0;
276
277 spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
278
279 if (spi_nor_spimem_bounce(nor, &op))
280 memcpy(nor->bouncebuf, buf, op.data.nbytes);
281
282 if (nor->dirmap.wdesc) {
283 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val,
284 op.data.nbytes, op.data.buf.out);
285 } else {
286 error = spi_nor_spimem_exec_op(nor, &op);
287 if (error)
288 return error;
289 nbytes = op.data.nbytes;
290 }
291
292 return nbytes;
293}
294
295/**
296 * spi_nor_write_data() - write data to flash memory
297 * @nor: pointer to 'struct spi_nor'
298 * @to: offset to write to
299 * @len: number of bytes to write
300 * @buf: pointer to src buffer
301 *
302 * Return: number of bytes written successfully, -errno otherwise
303 */
304ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
305 const u8 *buf)
306{
307 if (nor->spimem)
308 return spi_nor_spimem_write_data(nor, to, len, buf);
309
310 return nor->controller_ops->write(nor, to, len, buf);
311}
312
313/**
314 * spi_nor_read_any_reg() - read any register from flash memory, nonvolatile or
315 * volatile.
316 * @nor: pointer to 'struct spi_nor'.
317 * @op: SPI memory operation. op->data.buf must be DMA-able.
318 * @proto: SPI protocol to use for the register operation.
319 *
320 * Return: zero on success, -errno otherwise
321 */
322int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op,
323 enum spi_nor_protocol proto)
324{
325 if (!nor->spimem)
326 return -EOPNOTSUPP;
327
328 spi_nor_spimem_setup_op(nor, op, proto);
329 return spi_nor_spimem_exec_op(nor, op);
330}
331
332/**
333 * spi_nor_write_any_volatile_reg() - write any volatile register to flash
334 * memory.
335 * @nor: pointer to 'struct spi_nor'
336 * @op: SPI memory operation. op->data.buf must be DMA-able.
337 * @proto: SPI protocol to use for the register operation.
338 *
339 * Writing volatile registers are instant according to some manufacturers
340 * (Cypress, Micron) and do not need any status polling.
341 *
342 * Return: zero on success, -errno otherwise
343 */
344int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op *op,
345 enum spi_nor_protocol proto)
346{
347 int ret;
348
349 if (!nor->spimem)
350 return -EOPNOTSUPP;
351
352 ret = spi_nor_write_enable(nor);
353 if (ret)
354 return ret;
355 spi_nor_spimem_setup_op(nor, op, proto);
356 return spi_nor_spimem_exec_op(nor, op);
357}
358
359/**
360 * spi_nor_write_enable() - Set write enable latch with Write Enable command.
361 * @nor: pointer to 'struct spi_nor'.
362 *
363 * Return: 0 on success, -errno otherwise.
364 */
365int spi_nor_write_enable(struct spi_nor *nor)
366{
367 int ret;
368
369 if (nor->spimem) {
370 struct spi_mem_op op = SPI_NOR_WREN_OP;
371
372 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
373
374 ret = spi_mem_exec_op(nor->spimem, &op);
375 } else {
376 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN,
377 NULL, 0);
378 }
379
380 if (ret)
381 dev_dbg(nor->dev, "error %d on Write Enable\n", ret);
382
383 return ret;
384}
385
386/**
387 * spi_nor_write_disable() - Send Write Disable instruction to the chip.
388 * @nor: pointer to 'struct spi_nor'.
389 *
390 * Return: 0 on success, -errno otherwise.
391 */
392int spi_nor_write_disable(struct spi_nor *nor)
393{
394 int ret;
395
396 if (nor->spimem) {
397 struct spi_mem_op op = SPI_NOR_WRDI_OP;
398
399 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
400
401 ret = spi_mem_exec_op(nor->spimem, &op);
402 } else {
403 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI,
404 NULL, 0);
405 }
406
407 if (ret)
408 dev_dbg(nor->dev, "error %d on Write Disable\n", ret);
409
410 return ret;
411}
412
413/**
414 * spi_nor_read_id() - Read the JEDEC ID.
415 * @nor: pointer to 'struct spi_nor'.
416 * @naddr: number of address bytes to send. Can be zero if the operation
417 * does not need to send an address.
418 * @ndummy: number of dummy bytes to send after an opcode or address. Can
419 * be zero if the operation does not require dummy bytes.
420 * @id: pointer to a DMA-able buffer where the value of the JEDEC ID
421 * will be written.
422 * @proto: the SPI protocol for register operation.
423 *
424 * Return: 0 on success, -errno otherwise.
425 */
426int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
427 enum spi_nor_protocol proto)
428{
429 int ret;
430
431 if (nor->spimem) {
432 struct spi_mem_op op =
433 SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN);
434
435 spi_nor_spimem_setup_op(nor, &op, proto);
436 ret = spi_mem_exec_op(nor->spimem, &op);
437 } else {
438 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
439 SPI_NOR_MAX_ID_LEN);
440 }
441 return ret;
442}
443
444/**
445 * spi_nor_read_sr() - Read the Status Register.
446 * @nor: pointer to 'struct spi_nor'.
447 * @sr: pointer to a DMA-able buffer where the value of the
448 * Status Register will be written. Should be at least 2 bytes.
449 *
450 * Return: 0 on success, -errno otherwise.
451 */
452int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
453{
454 int ret;
455
456 if (nor->spimem) {
457 struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);
458
459 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
460 op.addr.nbytes = nor->params->rdsr_addr_nbytes;
461 op.dummy.nbytes = nor->params->rdsr_dummy;
462 /*
463 * We don't want to read only one byte in DTR mode. So,
464 * read 2 and then discard the second byte.
465 */
466 op.data.nbytes = 2;
467 }
468
469 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
470
471 ret = spi_mem_exec_op(nor->spimem, &op);
472 } else {
473 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
474 1);
475 }
476
477 if (ret)
478 dev_dbg(nor->dev, "error %d reading SR\n", ret);
479
480 return ret;
481}
482
483/**
484 * spi_nor_read_cr() - Read the Configuration Register using the
485 * SPINOR_OP_RDCR (35h) command.
486 * @nor: pointer to 'struct spi_nor'
487 * @cr: pointer to a DMA-able buffer where the value of the
488 * Configuration Register will be written.
489 *
490 * Return: 0 on success, -errno otherwise.
491 */
492int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
493{
494 int ret;
495
496 if (nor->spimem) {
497 struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);
498
499 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
500
501 ret = spi_mem_exec_op(nor->spimem, &op);
502 } else {
503 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
504 1);
505 }
506
507 if (ret)
508 dev_dbg(nor->dev, "error %d reading CR\n", ret);
509
510 return ret;
511}
512
513/**
514 * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode
515 * using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by
516 * Winbond and Macronix.
517 * @nor: pointer to 'struct spi_nor'.
518 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
519 * address mode.
520 *
521 * Return: 0 on success, -errno otherwise.
522 */
523int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable)
524{
525 int ret;
526
527 if (nor->spimem) {
528 struct spi_mem_op op = SPI_NOR_EN4B_EX4B_OP(enable);
529
530 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
531
532 ret = spi_mem_exec_op(nor->spimem, &op);
533 } else {
534 ret = spi_nor_controller_ops_write_reg(nor,
535 enable ? SPINOR_OP_EN4B :
536 SPINOR_OP_EX4B,
537 NULL, 0);
538 }
539
540 if (ret)
541 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
542
543 return ret;
544}
545
546/**
547 * spi_nor_set_4byte_addr_mode_wren_en4b_ex4b() - Set 4-byte address mode using
548 * SPINOR_OP_WREN followed by SPINOR_OP_EN4B or SPINOR_OP_EX4B. Typically used
549 * by ST and Micron flashes.
550 * @nor: pointer to 'struct spi_nor'.
551 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
552 * address mode.
553 *
554 * Return: 0 on success, -errno otherwise.
555 */
556int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable)
557{
558 int ret;
559
560 ret = spi_nor_write_enable(nor);
561 if (ret)
562 return ret;
563
564 ret = spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable);
565 if (ret)
566 return ret;
567
568 return spi_nor_write_disable(nor);
569}
570
571/**
572 * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using
573 * SPINOR_OP_BRWR. Typically used by Spansion flashes.
574 * @nor: pointer to 'struct spi_nor'.
575 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
576 * address mode.
577 *
578 * 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is
579 * used to enable/disable 4-byte address mode. When MSB is set to ‘1’, 4-byte
580 * address mode is active and A[30:24] bits are don’t care. Write instruction is
581 * SPINOR_OP_BRWR(17h) with 1 byte of data.
582 *
583 * Return: 0 on success, -errno otherwise.
584 */
585int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable)
586{
587 int ret;
588
589 nor->bouncebuf[0] = enable << 7;
590
591 if (nor->spimem) {
592 struct spi_mem_op op = SPI_NOR_BRWR_OP(nor->bouncebuf);
593
594 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
595
596 ret = spi_mem_exec_op(nor->spimem, &op);
597 } else {
598 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR,
599 nor->bouncebuf, 1);
600 }
601
602 if (ret)
603 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
604
605 return ret;
606}
607
608/**
609 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
610 * for new commands.
611 * @nor: pointer to 'struct spi_nor'.
612 *
613 * Return: 1 if ready, 0 if not ready, -errno on errors.
614 */
615int spi_nor_sr_ready(struct spi_nor *nor)
616{
617 int ret;
618
619 ret = spi_nor_read_sr(nor, nor->bouncebuf);
620 if (ret)
621 return ret;
622
623 return !(nor->bouncebuf[0] & SR_WIP);
624}
625
626/**
627 * spi_nor_use_parallel_locking() - Checks if RWW locking scheme shall be used
628 * @nor: pointer to 'struct spi_nor'.
629 *
630 * Return: true if parallel locking is enabled, false otherwise.
631 */
632static bool spi_nor_use_parallel_locking(struct spi_nor *nor)
633{
634 return nor->flags & SNOR_F_RWW;
635}
636
637/* Locking helpers for status read operations */
638static int spi_nor_rww_start_rdst(struct spi_nor *nor)
639{
640 struct spi_nor_rww *rww = &nor->rww;
641 int ret = -EAGAIN;
642
643 mutex_lock(&nor->lock);
644
645 if (rww->ongoing_io || rww->ongoing_rd)
646 goto busy;
647
648 rww->ongoing_io = true;
649 rww->ongoing_rd = true;
650 ret = 0;
651
652busy:
653 mutex_unlock(&nor->lock);
654 return ret;
655}
656
657static void spi_nor_rww_end_rdst(struct spi_nor *nor)
658{
659 struct spi_nor_rww *rww = &nor->rww;
660
661 mutex_lock(&nor->lock);
662
663 rww->ongoing_io = false;
664 rww->ongoing_rd = false;
665
666 mutex_unlock(&nor->lock);
667}
668
669static int spi_nor_lock_rdst(struct spi_nor *nor)
670{
671 if (spi_nor_use_parallel_locking(nor))
672 return spi_nor_rww_start_rdst(nor);
673
674 return 0;
675}
676
677static void spi_nor_unlock_rdst(struct spi_nor *nor)
678{
679 if (spi_nor_use_parallel_locking(nor)) {
680 spi_nor_rww_end_rdst(nor);
681 wake_up(&nor->rww.wait);
682 }
683}
684
685/**
686 * spi_nor_ready() - Query the flash to see if it is ready for new commands.
687 * @nor: pointer to 'struct spi_nor'.
688 *
689 * Return: 1 if ready, 0 if not ready, -errno on errors.
690 */
691static int spi_nor_ready(struct spi_nor *nor)
692{
693 int ret;
694
695 ret = spi_nor_lock_rdst(nor);
696 if (ret)
697 return 0;
698
699 /* Flashes might override the standard routine. */
700 if (nor->params->ready)
701 ret = nor->params->ready(nor);
702 else
703 ret = spi_nor_sr_ready(nor);
704
705 spi_nor_unlock_rdst(nor);
706
707 return ret;
708}
709
710/**
711 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
712 * Status Register until ready, or timeout occurs.
713 * @nor: pointer to "struct spi_nor".
714 * @timeout_jiffies: jiffies to wait until timeout.
715 *
716 * Return: 0 on success, -errno otherwise.
717 */
718static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
719 unsigned long timeout_jiffies)
720{
721 unsigned long deadline;
722 int timeout = 0, ret;
723
724 deadline = jiffies + timeout_jiffies;
725
726 while (!timeout) {
727 if (time_after_eq(jiffies, deadline))
728 timeout = 1;
729
730 ret = spi_nor_ready(nor);
731 if (ret < 0)
732 return ret;
733 if (ret)
734 return 0;
735
736 cond_resched();
737 }
738
739 dev_dbg(nor->dev, "flash operation timed out\n");
740
741 return -ETIMEDOUT;
742}
743
744/**
745 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
746 * flash to be ready, or timeout occurs.
747 * @nor: pointer to "struct spi_nor".
748 *
749 * Return: 0 on success, -errno otherwise.
750 */
751int spi_nor_wait_till_ready(struct spi_nor *nor)
752{
753 return spi_nor_wait_till_ready_with_timeout(nor,
754 DEFAULT_READY_WAIT_JIFFIES);
755}
756
757/**
758 * spi_nor_global_block_unlock() - Unlock Global Block Protection.
759 * @nor: pointer to 'struct spi_nor'.
760 *
761 * Return: 0 on success, -errno otherwise.
762 */
763int spi_nor_global_block_unlock(struct spi_nor *nor)
764{
765 int ret;
766
767 ret = spi_nor_write_enable(nor);
768 if (ret)
769 return ret;
770
771 if (nor->spimem) {
772 struct spi_mem_op op = SPI_NOR_GBULK_OP;
773
774 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
775
776 ret = spi_mem_exec_op(nor->spimem, &op);
777 } else {
778 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK,
779 NULL, 0);
780 }
781
782 if (ret) {
783 dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret);
784 return ret;
785 }
786
787 return spi_nor_wait_till_ready(nor);
788}
789
790/**
791 * spi_nor_write_sr() - Write the Status Register.
792 * @nor: pointer to 'struct spi_nor'.
793 * @sr: pointer to DMA-able buffer to write to the Status Register.
794 * @len: number of bytes to write to the Status Register.
795 *
796 * Return: 0 on success, -errno otherwise.
797 */
798int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
799{
800 int ret;
801
802 ret = spi_nor_write_enable(nor);
803 if (ret)
804 return ret;
805
806 if (nor->spimem) {
807 struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len);
808
809 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
810
811 ret = spi_mem_exec_op(nor->spimem, &op);
812 } else {
813 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,
814 len);
815 }
816
817 if (ret) {
818 dev_dbg(nor->dev, "error %d writing SR\n", ret);
819 return ret;
820 }
821
822 return spi_nor_wait_till_ready(nor);
823}
824
825/**
826 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
827 * ensure that the byte written match the received value.
828 * @nor: pointer to a 'struct spi_nor'.
829 * @sr1: byte value to be written to the Status Register.
830 *
831 * Return: 0 on success, -errno otherwise.
832 */
833static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
834{
835 int ret;
836
837 nor->bouncebuf[0] = sr1;
838
839 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
840 if (ret)
841 return ret;
842
843 ret = spi_nor_read_sr(nor, nor->bouncebuf);
844 if (ret)
845 return ret;
846
847 if (nor->bouncebuf[0] != sr1) {
848 dev_dbg(nor->dev, "SR1: read back test failed\n");
849 return -EIO;
850 }
851
852 return 0;
853}
854
855/**
856 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
857 * Status Register 2 in one shot. Ensure that the byte written in the Status
858 * Register 1 match the received value, and that the 16-bit Write did not
859 * affect what was already in the Status Register 2.
860 * @nor: pointer to a 'struct spi_nor'.
861 * @sr1: byte value to be written to the Status Register 1.
862 *
863 * Return: 0 on success, -errno otherwise.
864 */
865static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
866{
867 int ret;
868 u8 *sr_cr = nor->bouncebuf;
869 u8 cr_written;
870
871 /* Make sure we don't overwrite the contents of Status Register 2. */
872 if (!(nor->flags & SNOR_F_NO_READ_CR)) {
873 ret = spi_nor_read_cr(nor, &sr_cr[1]);
874 if (ret)
875 return ret;
876 } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 &&
877 spi_nor_get_protocol_width(nor->write_proto) == 4 &&
878 nor->params->quad_enable) {
879 /*
880 * If the Status Register 2 Read command (35h) is not
881 * supported, we should at least be sure we don't
882 * change the value of the SR2 Quad Enable bit.
883 *
884 * When the Quad Enable method is set and the buswidth is 4, we
885 * can safely assume that the value of the QE bit is one, as a
886 * consequence of the nor->params->quad_enable() call.
887 *
888 * According to the JESD216 revB standard, BFPT DWORDS[15],
889 * bits 22:20, the 16-bit Write Status (01h) command is
890 * available just for the cases in which the QE bit is
891 * described in SR2 at BIT(1).
892 */
893 sr_cr[1] = SR2_QUAD_EN_BIT1;
894 } else {
895 sr_cr[1] = 0;
896 }
897
898 sr_cr[0] = sr1;
899
900 ret = spi_nor_write_sr(nor, sr_cr, 2);
901 if (ret)
902 return ret;
903
904 ret = spi_nor_read_sr(nor, sr_cr);
905 if (ret)
906 return ret;
907
908 if (sr1 != sr_cr[0]) {
909 dev_dbg(nor->dev, "SR: Read back test failed\n");
910 return -EIO;
911 }
912
913 if (nor->flags & SNOR_F_NO_READ_CR)
914 return 0;
915
916 cr_written = sr_cr[1];
917
918 ret = spi_nor_read_cr(nor, &sr_cr[1]);
919 if (ret)
920 return ret;
921
922 if (cr_written != sr_cr[1]) {
923 dev_dbg(nor->dev, "CR: read back test failed\n");
924 return -EIO;
925 }
926
927 return 0;
928}
929
930/**
931 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
932 * Configuration Register in one shot. Ensure that the byte written in the
933 * Configuration Register match the received value, and that the 16-bit Write
934 * did not affect what was already in the Status Register 1.
935 * @nor: pointer to a 'struct spi_nor'.
936 * @cr: byte value to be written to the Configuration Register.
937 *
938 * Return: 0 on success, -errno otherwise.
939 */
940int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
941{
942 int ret;
943 u8 *sr_cr = nor->bouncebuf;
944 u8 sr_written;
945
946 /* Keep the current value of the Status Register 1. */
947 ret = spi_nor_read_sr(nor, sr_cr);
948 if (ret)
949 return ret;
950
951 sr_cr[1] = cr;
952
953 ret = spi_nor_write_sr(nor, sr_cr, 2);
954 if (ret)
955 return ret;
956
957 sr_written = sr_cr[0];
958
959 ret = spi_nor_read_sr(nor, sr_cr);
960 if (ret)
961 return ret;
962
963 if (sr_written != sr_cr[0]) {
964 dev_dbg(nor->dev, "SR: Read back test failed\n");
965 return -EIO;
966 }
967
968 if (nor->flags & SNOR_F_NO_READ_CR)
969 return 0;
970
971 ret = spi_nor_read_cr(nor, &sr_cr[1]);
972 if (ret)
973 return ret;
974
975 if (cr != sr_cr[1]) {
976 dev_dbg(nor->dev, "CR: read back test failed\n");
977 return -EIO;
978 }
979
980 return 0;
981}
982
983/**
984 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
985 * the byte written match the received value without affecting other bits in the
986 * Status Register 1 and 2.
987 * @nor: pointer to a 'struct spi_nor'.
988 * @sr1: byte value to be written to the Status Register.
989 *
990 * Return: 0 on success, -errno otherwise.
991 */
992int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
993{
994 if (nor->flags & SNOR_F_HAS_16BIT_SR)
995 return spi_nor_write_16bit_sr_and_check(nor, sr1);
996
997 return spi_nor_write_sr1_and_check(nor, sr1);
998}
999
1000/**
1001 * spi_nor_write_sr2() - Write the Status Register 2 using the
1002 * SPINOR_OP_WRSR2 (3eh) command.
1003 * @nor: pointer to 'struct spi_nor'.
1004 * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
1005 *
1006 * Return: 0 on success, -errno otherwise.
1007 */
1008static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
1009{
1010 int ret;
1011
1012 ret = spi_nor_write_enable(nor);
1013 if (ret)
1014 return ret;
1015
1016 if (nor->spimem) {
1017 struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2);
1018
1019 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1020
1021 ret = spi_mem_exec_op(nor->spimem, &op);
1022 } else {
1023 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,
1024 sr2, 1);
1025 }
1026
1027 if (ret) {
1028 dev_dbg(nor->dev, "error %d writing SR2\n", ret);
1029 return ret;
1030 }
1031
1032 return spi_nor_wait_till_ready(nor);
1033}
1034
1035/**
1036 * spi_nor_read_sr2() - Read the Status Register 2 using the
1037 * SPINOR_OP_RDSR2 (3fh) command.
1038 * @nor: pointer to 'struct spi_nor'.
1039 * @sr2: pointer to DMA-able buffer where the value of the
1040 * Status Register 2 will be written.
1041 *
1042 * Return: 0 on success, -errno otherwise.
1043 */
1044static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
1045{
1046 int ret;
1047
1048 if (nor->spimem) {
1049 struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2);
1050
1051 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1052
1053 ret = spi_mem_exec_op(nor->spimem, &op);
1054 } else {
1055 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,
1056 1);
1057 }
1058
1059 if (ret)
1060 dev_dbg(nor->dev, "error %d reading SR2\n", ret);
1061
1062 return ret;
1063}
1064
1065/**
1066 * spi_nor_erase_die() - Erase the entire die.
1067 * @nor: pointer to 'struct spi_nor'.
1068 * @addr: address of the die.
1069 * @die_size: size of the die.
1070 *
1071 * Return: 0 on success, -errno otherwise.
1072 */
1073static int spi_nor_erase_die(struct spi_nor *nor, loff_t addr, size_t die_size)
1074{
1075 bool multi_die = nor->mtd.size != die_size;
1076 int ret;
1077
1078 dev_dbg(nor->dev, " %lldKiB\n", (long long)(die_size >> 10));
1079
1080 if (nor->spimem) {
1081 struct spi_mem_op op =
1082 SPI_NOR_DIE_ERASE_OP(nor->params->die_erase_opcode,
1083 nor->addr_nbytes, addr, multi_die);
1084
1085 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1086
1087 ret = spi_mem_exec_op(nor->spimem, &op);
1088 } else {
1089 if (multi_die)
1090 return -EOPNOTSUPP;
1091
1092 ret = spi_nor_controller_ops_write_reg(nor,
1093 SPINOR_OP_CHIP_ERASE,
1094 NULL, 0);
1095 }
1096
1097 if (ret)
1098 dev_dbg(nor->dev, "error %d erasing chip\n", ret);
1099
1100 return ret;
1101}
1102
1103static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
1104{
1105 size_t i;
1106
1107 for (i = 0; i < size; i++)
1108 if (table[i][0] == opcode)
1109 return table[i][1];
1110
1111 /* No conversion found, keep input op code. */
1112 return opcode;
1113}
1114
1115u8 spi_nor_convert_3to4_read(u8 opcode)
1116{
1117 static const u8 spi_nor_3to4_read[][2] = {
1118 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
1119 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
1120 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
1121 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
1122 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
1123 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
1124 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
1125 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
1126
1127 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
1128 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
1129 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
1130 };
1131
1132 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
1133 ARRAY_SIZE(spi_nor_3to4_read));
1134}
1135
1136static u8 spi_nor_convert_3to4_program(u8 opcode)
1137{
1138 static const u8 spi_nor_3to4_program[][2] = {
1139 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
1140 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
1141 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
1142 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
1143 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
1144 };
1145
1146 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
1147 ARRAY_SIZE(spi_nor_3to4_program));
1148}
1149
1150static u8 spi_nor_convert_3to4_erase(u8 opcode)
1151{
1152 static const u8 spi_nor_3to4_erase[][2] = {
1153 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
1154 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
1155 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
1156 };
1157
1158 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
1159 ARRAY_SIZE(spi_nor_3to4_erase));
1160}
1161
1162static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)
1163{
1164 return !!nor->params->erase_map.uniform_region.erase_mask;
1165}
1166
1167static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
1168{
1169 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
1170 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
1171 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
1172
1173 if (!spi_nor_has_uniform_erase(nor)) {
1174 struct spi_nor_erase_map *map = &nor->params->erase_map;
1175 struct spi_nor_erase_type *erase;
1176 int i;
1177
1178 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1179 erase = &map->erase_type[i];
1180 erase->opcode =
1181 spi_nor_convert_3to4_erase(erase->opcode);
1182 }
1183 }
1184}
1185
1186static int spi_nor_prep(struct spi_nor *nor)
1187{
1188 int ret = 0;
1189
1190 if (nor->controller_ops && nor->controller_ops->prepare)
1191 ret = nor->controller_ops->prepare(nor);
1192
1193 return ret;
1194}
1195
1196static void spi_nor_unprep(struct spi_nor *nor)
1197{
1198 if (nor->controller_ops && nor->controller_ops->unprepare)
1199 nor->controller_ops->unprepare(nor);
1200}
1201
1202static void spi_nor_offset_to_banks(u64 bank_size, loff_t start, size_t len,
1203 u8 *first, u8 *last)
1204{
1205 /* This is currently safe, the number of banks being very small */
1206 *first = DIV_ROUND_DOWN_ULL(start, bank_size);
1207 *last = DIV_ROUND_DOWN_ULL(start + len - 1, bank_size);
1208}
1209
1210/* Generic helpers for internal locking and serialization */
1211static bool spi_nor_rww_start_io(struct spi_nor *nor)
1212{
1213 struct spi_nor_rww *rww = &nor->rww;
1214 bool start = false;
1215
1216 mutex_lock(&nor->lock);
1217
1218 if (rww->ongoing_io)
1219 goto busy;
1220
1221 rww->ongoing_io = true;
1222 start = true;
1223
1224busy:
1225 mutex_unlock(&nor->lock);
1226 return start;
1227}
1228
1229static void spi_nor_rww_end_io(struct spi_nor *nor)
1230{
1231 mutex_lock(&nor->lock);
1232 nor->rww.ongoing_io = false;
1233 mutex_unlock(&nor->lock);
1234}
1235
1236static int spi_nor_lock_device(struct spi_nor *nor)
1237{
1238 if (!spi_nor_use_parallel_locking(nor))
1239 return 0;
1240
1241 return wait_event_killable(nor->rww.wait, spi_nor_rww_start_io(nor));
1242}
1243
1244static void spi_nor_unlock_device(struct spi_nor *nor)
1245{
1246 if (spi_nor_use_parallel_locking(nor)) {
1247 spi_nor_rww_end_io(nor);
1248 wake_up(&nor->rww.wait);
1249 }
1250}
1251
1252/* Generic helpers for internal locking and serialization */
1253static bool spi_nor_rww_start_exclusive(struct spi_nor *nor)
1254{
1255 struct spi_nor_rww *rww = &nor->rww;
1256 bool start = false;
1257
1258 mutex_lock(&nor->lock);
1259
1260 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe)
1261 goto busy;
1262
1263 rww->ongoing_io = true;
1264 rww->ongoing_rd = true;
1265 rww->ongoing_pe = true;
1266 start = true;
1267
1268busy:
1269 mutex_unlock(&nor->lock);
1270 return start;
1271}
1272
1273static void spi_nor_rww_end_exclusive(struct spi_nor *nor)
1274{
1275 struct spi_nor_rww *rww = &nor->rww;
1276
1277 mutex_lock(&nor->lock);
1278 rww->ongoing_io = false;
1279 rww->ongoing_rd = false;
1280 rww->ongoing_pe = false;
1281 mutex_unlock(&nor->lock);
1282}
1283
1284int spi_nor_prep_and_lock(struct spi_nor *nor)
1285{
1286 int ret;
1287
1288 ret = spi_nor_prep(nor);
1289 if (ret)
1290 return ret;
1291
1292 if (!spi_nor_use_parallel_locking(nor))
1293 mutex_lock(&nor->lock);
1294 else
1295 ret = wait_event_killable(nor->rww.wait,
1296 spi_nor_rww_start_exclusive(nor));
1297
1298 return ret;
1299}
1300
1301void spi_nor_unlock_and_unprep(struct spi_nor *nor)
1302{
1303 if (!spi_nor_use_parallel_locking(nor)) {
1304 mutex_unlock(&nor->lock);
1305 } else {
1306 spi_nor_rww_end_exclusive(nor);
1307 wake_up(&nor->rww.wait);
1308 }
1309
1310 spi_nor_unprep(nor);
1311}
1312
1313/* Internal locking helpers for program and erase operations */
1314static bool spi_nor_rww_start_pe(struct spi_nor *nor, loff_t start, size_t len)
1315{
1316 struct spi_nor_rww *rww = &nor->rww;
1317 unsigned int used_banks = 0;
1318 bool started = false;
1319 u8 first, last;
1320 int bank;
1321
1322 mutex_lock(&nor->lock);
1323
1324 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe)
1325 goto busy;
1326
1327 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1328 for (bank = first; bank <= last; bank++) {
1329 if (rww->used_banks & BIT(bank))
1330 goto busy;
1331
1332 used_banks |= BIT(bank);
1333 }
1334
1335 rww->used_banks |= used_banks;
1336 rww->ongoing_pe = true;
1337 started = true;
1338
1339busy:
1340 mutex_unlock(&nor->lock);
1341 return started;
1342}
1343
1344static void spi_nor_rww_end_pe(struct spi_nor *nor, loff_t start, size_t len)
1345{
1346 struct spi_nor_rww *rww = &nor->rww;
1347 u8 first, last;
1348 int bank;
1349
1350 mutex_lock(&nor->lock);
1351
1352 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1353 for (bank = first; bank <= last; bank++)
1354 rww->used_banks &= ~BIT(bank);
1355
1356 rww->ongoing_pe = false;
1357
1358 mutex_unlock(&nor->lock);
1359}
1360
1361static int spi_nor_prep_and_lock_pe(struct spi_nor *nor, loff_t start, size_t len)
1362{
1363 int ret;
1364
1365 ret = spi_nor_prep(nor);
1366 if (ret)
1367 return ret;
1368
1369 if (!spi_nor_use_parallel_locking(nor))
1370 mutex_lock(&nor->lock);
1371 else
1372 ret = wait_event_killable(nor->rww.wait,
1373 spi_nor_rww_start_pe(nor, start, len));
1374
1375 return ret;
1376}
1377
1378static void spi_nor_unlock_and_unprep_pe(struct spi_nor *nor, loff_t start, size_t len)
1379{
1380 if (!spi_nor_use_parallel_locking(nor)) {
1381 mutex_unlock(&nor->lock);
1382 } else {
1383 spi_nor_rww_end_pe(nor, start, len);
1384 wake_up(&nor->rww.wait);
1385 }
1386
1387 spi_nor_unprep(nor);
1388}
1389
1390/* Internal locking helpers for read operations */
1391static bool spi_nor_rww_start_rd(struct spi_nor *nor, loff_t start, size_t len)
1392{
1393 struct spi_nor_rww *rww = &nor->rww;
1394 unsigned int used_banks = 0;
1395 bool started = false;
1396 u8 first, last;
1397 int bank;
1398
1399 mutex_lock(&nor->lock);
1400
1401 if (rww->ongoing_io || rww->ongoing_rd)
1402 goto busy;
1403
1404 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1405 for (bank = first; bank <= last; bank++) {
1406 if (rww->used_banks & BIT(bank))
1407 goto busy;
1408
1409 used_banks |= BIT(bank);
1410 }
1411
1412 rww->used_banks |= used_banks;
1413 rww->ongoing_io = true;
1414 rww->ongoing_rd = true;
1415 started = true;
1416
1417busy:
1418 mutex_unlock(&nor->lock);
1419 return started;
1420}
1421
1422static void spi_nor_rww_end_rd(struct spi_nor *nor, loff_t start, size_t len)
1423{
1424 struct spi_nor_rww *rww = &nor->rww;
1425 u8 first, last;
1426 int bank;
1427
1428 mutex_lock(&nor->lock);
1429
1430 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1431 for (bank = first; bank <= last; bank++)
1432 nor->rww.used_banks &= ~BIT(bank);
1433
1434 rww->ongoing_io = false;
1435 rww->ongoing_rd = false;
1436
1437 mutex_unlock(&nor->lock);
1438}
1439
1440static int spi_nor_prep_and_lock_rd(struct spi_nor *nor, loff_t start, size_t len)
1441{
1442 int ret;
1443
1444 ret = spi_nor_prep(nor);
1445 if (ret)
1446 return ret;
1447
1448 if (!spi_nor_use_parallel_locking(nor))
1449 mutex_lock(&nor->lock);
1450 else
1451 ret = wait_event_killable(nor->rww.wait,
1452 spi_nor_rww_start_rd(nor, start, len));
1453
1454 return ret;
1455}
1456
1457static void spi_nor_unlock_and_unprep_rd(struct spi_nor *nor, loff_t start, size_t len)
1458{
1459 if (!spi_nor_use_parallel_locking(nor)) {
1460 mutex_unlock(&nor->lock);
1461 } else {
1462 spi_nor_rww_end_rd(nor, start, len);
1463 wake_up(&nor->rww.wait);
1464 }
1465
1466 spi_nor_unprep(nor);
1467}
1468
1469/*
1470 * Initiate the erasure of a single sector
1471 */
1472int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
1473{
1474 int i;
1475
1476 if (nor->spimem) {
1477 struct spi_mem_op op =
1478 SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode,
1479 nor->addr_nbytes, addr);
1480
1481 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
1482
1483 return spi_mem_exec_op(nor->spimem, &op);
1484 } else if (nor->controller_ops->erase) {
1485 return spi_nor_controller_ops_erase(nor, addr);
1486 }
1487
1488 /*
1489 * Default implementation, if driver doesn't have a specialized HW
1490 * control
1491 */
1492 for (i = nor->addr_nbytes - 1; i >= 0; i--) {
1493 nor->bouncebuf[i] = addr & 0xff;
1494 addr >>= 8;
1495 }
1496
1497 return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode,
1498 nor->bouncebuf, nor->addr_nbytes);
1499}
1500
1501/**
1502 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1503 * @erase: pointer to a structure that describes a SPI NOR erase type
1504 * @dividend: dividend value
1505 * @remainder: pointer to u32 remainder (will be updated)
1506 *
1507 * Return: the result of the division
1508 */
1509static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
1510 u64 dividend, u32 *remainder)
1511{
1512 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1513 *remainder = (u32)dividend & erase->size_mask;
1514 return dividend >> erase->size_shift;
1515}
1516
1517/**
1518 * spi_nor_find_best_erase_type() - find the best erase type for the given
1519 * offset in the serial flash memory and the
1520 * number of bytes to erase. The region in
1521 * which the address fits is expected to be
1522 * provided.
1523 * @map: the erase map of the SPI NOR
1524 * @region: pointer to a structure that describes a SPI NOR erase region
1525 * @addr: offset in the serial flash memory
1526 * @len: number of bytes to erase
1527 *
1528 * Return: a pointer to the best fitted erase type, NULL otherwise.
1529 */
1530static const struct spi_nor_erase_type *
1531spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
1532 const struct spi_nor_erase_region *region,
1533 u64 addr, u32 len)
1534{
1535 const struct spi_nor_erase_type *erase;
1536 u32 rem;
1537 int i;
1538
1539 /*
1540 * Erase types are ordered by size, with the smallest erase type at
1541 * index 0.
1542 */
1543 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
1544 /* Does the erase region support the tested erase type? */
1545 if (!(region->erase_mask & BIT(i)))
1546 continue;
1547
1548 erase = &map->erase_type[i];
1549 if (!erase->size)
1550 continue;
1551
1552 /* Alignment is not mandatory for overlaid regions */
1553 if (region->overlaid && region->size <= len)
1554 return erase;
1555
1556 /* Don't erase more than what the user has asked for. */
1557 if (erase->size > len)
1558 continue;
1559
1560 spi_nor_div_by_erase_size(erase, addr, &rem);
1561 if (!rem)
1562 return erase;
1563 }
1564
1565 return NULL;
1566}
1567
1568/**
1569 * spi_nor_init_erase_cmd() - initialize an erase command
1570 * @region: pointer to a structure that describes a SPI NOR erase region
1571 * @erase: pointer to a structure that describes a SPI NOR erase type
1572 *
1573 * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1574 * otherwise.
1575 */
1576static struct spi_nor_erase_command *
1577spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
1578 const struct spi_nor_erase_type *erase)
1579{
1580 struct spi_nor_erase_command *cmd;
1581
1582 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
1583 if (!cmd)
1584 return ERR_PTR(-ENOMEM);
1585
1586 INIT_LIST_HEAD(&cmd->list);
1587 cmd->opcode = erase->opcode;
1588 cmd->count = 1;
1589
1590 if (region->overlaid)
1591 cmd->size = region->size;
1592 else
1593 cmd->size = erase->size;
1594
1595 return cmd;
1596}
1597
1598/**
1599 * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1600 * @erase_list: list of erase commands
1601 */
1602static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
1603{
1604 struct spi_nor_erase_command *cmd, *next;
1605
1606 list_for_each_entry_safe(cmd, next, erase_list, list) {
1607 list_del(&cmd->list);
1608 kfree(cmd);
1609 }
1610}
1611
1612/**
1613 * spi_nor_init_erase_cmd_list() - initialize erase command list
1614 * @nor: pointer to a 'struct spi_nor'
1615 * @erase_list: list of erase commands to be executed once we validate that the
1616 * erase can be performed
1617 * @addr: offset in the serial flash memory
1618 * @len: number of bytes to erase
1619 *
1620 * Builds the list of best fitted erase commands and verifies if the erase can
1621 * be performed.
1622 *
1623 * Return: 0 on success, -errno otherwise.
1624 */
1625static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
1626 struct list_head *erase_list,
1627 u64 addr, u32 len)
1628{
1629 const struct spi_nor_erase_map *map = &nor->params->erase_map;
1630 const struct spi_nor_erase_type *erase, *prev_erase = NULL;
1631 struct spi_nor_erase_region *region;
1632 struct spi_nor_erase_command *cmd = NULL;
1633 u64 region_end;
1634 unsigned int i;
1635 int ret = -EINVAL;
1636
1637 for (i = 0; i < map->n_regions && len; i++) {
1638 region = &map->regions[i];
1639 region_end = region->offset + region->size;
1640
1641 while (len && addr >= region->offset && addr < region_end) {
1642 erase = spi_nor_find_best_erase_type(map, region, addr,
1643 len);
1644 if (!erase)
1645 goto destroy_erase_cmd_list;
1646
1647 if (prev_erase != erase || erase->size != cmd->size ||
1648 region->overlaid) {
1649 cmd = spi_nor_init_erase_cmd(region, erase);
1650 if (IS_ERR(cmd)) {
1651 ret = PTR_ERR(cmd);
1652 goto destroy_erase_cmd_list;
1653 }
1654
1655 list_add_tail(&cmd->list, erase_list);
1656 } else {
1657 cmd->count++;
1658 }
1659
1660 len -= cmd->size;
1661 addr += cmd->size;
1662 prev_erase = erase;
1663 }
1664 }
1665
1666 return 0;
1667
1668destroy_erase_cmd_list:
1669 spi_nor_destroy_erase_cmd_list(erase_list);
1670 return ret;
1671}
1672
1673/**
1674 * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1675 * @nor: pointer to a 'struct spi_nor'
1676 * @addr: offset in the serial flash memory
1677 * @len: number of bytes to erase
1678 *
1679 * Build a list of best fitted erase commands and execute it once we validate
1680 * that the erase can be performed.
1681 *
1682 * Return: 0 on success, -errno otherwise.
1683 */
1684static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
1685{
1686 LIST_HEAD(erase_list);
1687 struct spi_nor_erase_command *cmd, *next;
1688 int ret;
1689
1690 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
1691 if (ret)
1692 return ret;
1693
1694 list_for_each_entry_safe(cmd, next, &erase_list, list) {
1695 nor->erase_opcode = cmd->opcode;
1696 while (cmd->count) {
1697 dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n",
1698 cmd->size, cmd->opcode, cmd->count);
1699
1700 ret = spi_nor_lock_device(nor);
1701 if (ret)
1702 goto destroy_erase_cmd_list;
1703
1704 ret = spi_nor_write_enable(nor);
1705 if (ret) {
1706 spi_nor_unlock_device(nor);
1707 goto destroy_erase_cmd_list;
1708 }
1709
1710 ret = spi_nor_erase_sector(nor, addr);
1711 spi_nor_unlock_device(nor);
1712 if (ret)
1713 goto destroy_erase_cmd_list;
1714
1715 ret = spi_nor_wait_till_ready(nor);
1716 if (ret)
1717 goto destroy_erase_cmd_list;
1718
1719 addr += cmd->size;
1720 cmd->count--;
1721 }
1722 list_del(&cmd->list);
1723 kfree(cmd);
1724 }
1725
1726 return 0;
1727
1728destroy_erase_cmd_list:
1729 spi_nor_destroy_erase_cmd_list(&erase_list);
1730 return ret;
1731}
1732
1733static int spi_nor_erase_dice(struct spi_nor *nor, loff_t addr,
1734 size_t len, size_t die_size)
1735{
1736 unsigned long timeout;
1737 int ret;
1738
1739 /*
1740 * Scale the timeout linearly with the size of the flash, with
1741 * a minimum calibrated to an old 2MB flash. We could try to
1742 * pull these from CFI/SFDP, but these values should be good
1743 * enough for now.
1744 */
1745 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1746 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1747 (unsigned long)(nor->mtd.size / SZ_2M));
1748
1749 do {
1750 ret = spi_nor_lock_device(nor);
1751 if (ret)
1752 return ret;
1753
1754 ret = spi_nor_write_enable(nor);
1755 if (ret) {
1756 spi_nor_unlock_device(nor);
1757 return ret;
1758 }
1759
1760 ret = spi_nor_erase_die(nor, addr, die_size);
1761
1762 spi_nor_unlock_device(nor);
1763 if (ret)
1764 return ret;
1765
1766 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1767 if (ret)
1768 return ret;
1769
1770 addr += die_size;
1771 len -= die_size;
1772
1773 } while (len);
1774
1775 return 0;
1776}
1777
1778/*
1779 * Erase an address range on the nor chip. The address range may extend
1780 * one or more erase sectors. Return an error if there is a problem erasing.
1781 */
1782static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1783{
1784 struct spi_nor *nor = mtd_to_spi_nor(mtd);
1785 u8 n_dice = nor->params->n_dice;
1786 bool multi_die_erase = false;
1787 u32 addr, len, rem;
1788 size_t die_size;
1789 int ret;
1790
1791 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1792 (long long)instr->len);
1793
1794 if (spi_nor_has_uniform_erase(nor)) {
1795 div_u64_rem(instr->len, mtd->erasesize, &rem);
1796 if (rem)
1797 return -EINVAL;
1798 }
1799
1800 addr = instr->addr;
1801 len = instr->len;
1802
1803 if (n_dice) {
1804 die_size = div_u64(mtd->size, n_dice);
1805 if (!(len & (die_size - 1)) && !(addr & (die_size - 1)))
1806 multi_die_erase = true;
1807 } else {
1808 die_size = mtd->size;
1809 }
1810
1811 ret = spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len);
1812 if (ret)
1813 return ret;
1814
1815 /* chip (die) erase? */
1816 if ((len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) ||
1817 multi_die_erase) {
1818 ret = spi_nor_erase_dice(nor, addr, len, die_size);
1819 if (ret)
1820 goto erase_err;
1821
1822 /* REVISIT in some cases we could speed up erasing large regions
1823 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
1824 * to use "small sector erase", but that's not always optimal.
1825 */
1826
1827 /* "sector"-at-a-time erase */
1828 } else if (spi_nor_has_uniform_erase(nor)) {
1829 while (len) {
1830 ret = spi_nor_lock_device(nor);
1831 if (ret)
1832 goto erase_err;
1833
1834 ret = spi_nor_write_enable(nor);
1835 if (ret) {
1836 spi_nor_unlock_device(nor);
1837 goto erase_err;
1838 }
1839
1840 ret = spi_nor_erase_sector(nor, addr);
1841 spi_nor_unlock_device(nor);
1842 if (ret)
1843 goto erase_err;
1844
1845 ret = spi_nor_wait_till_ready(nor);
1846 if (ret)
1847 goto erase_err;
1848
1849 addr += mtd->erasesize;
1850 len -= mtd->erasesize;
1851 }
1852
1853 /* erase multiple sectors */
1854 } else {
1855 ret = spi_nor_erase_multi_sectors(nor, addr, len);
1856 if (ret)
1857 goto erase_err;
1858 }
1859
1860 ret = spi_nor_write_disable(nor);
1861
1862erase_err:
1863 spi_nor_unlock_and_unprep_pe(nor, instr->addr, instr->len);
1864
1865 return ret;
1866}
1867
1868/**
1869 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
1870 * Register 1.
1871 * @nor: pointer to a 'struct spi_nor'
1872 *
1873 * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
1874 *
1875 * Return: 0 on success, -errno otherwise.
1876 */
1877int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
1878{
1879 int ret;
1880
1881 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1882 if (ret)
1883 return ret;
1884
1885 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
1886 return 0;
1887
1888 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
1889
1890 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
1891}
1892
1893/**
1894 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
1895 * Register 2.
1896 * @nor: pointer to a 'struct spi_nor'.
1897 *
1898 * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
1899 *
1900 * Return: 0 on success, -errno otherwise.
1901 */
1902int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
1903{
1904 int ret;
1905
1906 if (nor->flags & SNOR_F_NO_READ_CR)
1907 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
1908
1909 ret = spi_nor_read_cr(nor, nor->bouncebuf);
1910 if (ret)
1911 return ret;
1912
1913 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
1914 return 0;
1915
1916 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
1917
1918 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
1919}
1920
1921/**
1922 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
1923 * @nor: pointer to a 'struct spi_nor'
1924 *
1925 * Set the Quad Enable (QE) bit in the Status Register 2.
1926 *
1927 * This is one of the procedures to set the QE bit described in the SFDP
1928 * (JESD216 rev B) specification but no manufacturer using this procedure has
1929 * been identified yet, hence the name of the function.
1930 *
1931 * Return: 0 on success, -errno otherwise.
1932 */
1933int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
1934{
1935 u8 *sr2 = nor->bouncebuf;
1936 int ret;
1937 u8 sr2_written;
1938
1939 /* Check current Quad Enable bit value. */
1940 ret = spi_nor_read_sr2(nor, sr2);
1941 if (ret)
1942 return ret;
1943 if (*sr2 & SR2_QUAD_EN_BIT7)
1944 return 0;
1945
1946 /* Update the Quad Enable bit. */
1947 *sr2 |= SR2_QUAD_EN_BIT7;
1948
1949 ret = spi_nor_write_sr2(nor, sr2);
1950 if (ret)
1951 return ret;
1952
1953 sr2_written = *sr2;
1954
1955 /* Read back and check it. */
1956 ret = spi_nor_read_sr2(nor, sr2);
1957 if (ret)
1958 return ret;
1959
1960 if (*sr2 != sr2_written) {
1961 dev_dbg(nor->dev, "SR2: Read back test failed\n");
1962 return -EIO;
1963 }
1964
1965 return 0;
1966}
1967
1968static const struct spi_nor_manufacturer *manufacturers[] = {
1969 &spi_nor_atmel,
1970 &spi_nor_eon,
1971 &spi_nor_esmt,
1972 &spi_nor_everspin,
1973 &spi_nor_gigadevice,
1974 &spi_nor_intel,
1975 &spi_nor_issi,
1976 &spi_nor_macronix,
1977 &spi_nor_micron,
1978 &spi_nor_st,
1979 &spi_nor_spansion,
1980 &spi_nor_sst,
1981 &spi_nor_winbond,
1982 &spi_nor_xmc,
1983};
1984
1985static const struct flash_info spi_nor_generic_flash = {
1986 .name = "spi-nor-generic",
1987};
1988
1989static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
1990 const u8 *id)
1991{
1992 const struct flash_info *part;
1993 unsigned int i, j;
1994
1995 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
1996 for (j = 0; j < manufacturers[i]->nparts; j++) {
1997 part = &manufacturers[i]->parts[j];
1998 if (part->id &&
1999 !memcmp(part->id->bytes, id, part->id->len)) {
2000 nor->manufacturer = manufacturers[i];
2001 return part;
2002 }
2003 }
2004 }
2005
2006 return NULL;
2007}
2008
2009static const struct flash_info *spi_nor_detect(struct spi_nor *nor)
2010{
2011 const struct flash_info *info;
2012 u8 *id = nor->bouncebuf;
2013 int ret;
2014
2015 ret = spi_nor_read_id(nor, 0, 0, id, nor->reg_proto);
2016 if (ret) {
2017 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret);
2018 return ERR_PTR(ret);
2019 }
2020
2021 /* Cache the complete flash ID. */
2022 nor->id = devm_kmemdup(nor->dev, id, SPI_NOR_MAX_ID_LEN, GFP_KERNEL);
2023 if (!nor->id)
2024 return ERR_PTR(-ENOMEM);
2025
2026 info = spi_nor_match_id(nor, id);
2027
2028 /* Fallback to a generic flash described only by its SFDP data. */
2029 if (!info) {
2030 ret = spi_nor_check_sfdp_signature(nor);
2031 if (!ret)
2032 info = &spi_nor_generic_flash;
2033 }
2034
2035 if (!info) {
2036 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
2037 SPI_NOR_MAX_ID_LEN, id);
2038 return ERR_PTR(-ENODEV);
2039 }
2040 return info;
2041}
2042
2043static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
2044 size_t *retlen, u_char *buf)
2045{
2046 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2047 loff_t from_lock = from;
2048 size_t len_lock = len;
2049 ssize_t ret;
2050
2051 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
2052
2053 ret = spi_nor_prep_and_lock_rd(nor, from_lock, len_lock);
2054 if (ret)
2055 return ret;
2056
2057 while (len) {
2058 loff_t addr = from;
2059
2060 ret = spi_nor_read_data(nor, addr, len, buf);
2061 if (ret == 0) {
2062 /* We shouldn't see 0-length reads */
2063 ret = -EIO;
2064 goto read_err;
2065 }
2066 if (ret < 0)
2067 goto read_err;
2068
2069 WARN_ON(ret > len);
2070 *retlen += ret;
2071 buf += ret;
2072 from += ret;
2073 len -= ret;
2074 }
2075 ret = 0;
2076
2077read_err:
2078 spi_nor_unlock_and_unprep_rd(nor, from_lock, len_lock);
2079
2080 return ret;
2081}
2082
2083/*
2084 * Write an address range to the nor chip. Data must be written in
2085 * FLASH_PAGESIZE chunks. The address range may be any size provided
2086 * it is within the physical boundaries.
2087 */
2088static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
2089 size_t *retlen, const u_char *buf)
2090{
2091 struct spi_nor *nor = mtd_to_spi_nor(mtd);
2092 size_t i;
2093 ssize_t ret;
2094 u32 page_size = nor->params->page_size;
2095
2096 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2097
2098 ret = spi_nor_prep_and_lock_pe(nor, to, len);
2099 if (ret)
2100 return ret;
2101
2102 for (i = 0; i < len; ) {
2103 ssize_t written;
2104 loff_t addr = to + i;
2105 size_t page_offset = addr & (page_size - 1);
2106 /* the size of data remaining on the first page */
2107 size_t page_remain = min_t(size_t, page_size - page_offset, len - i);
2108
2109 ret = spi_nor_lock_device(nor);
2110 if (ret)
2111 goto write_err;
2112
2113 ret = spi_nor_write_enable(nor);
2114 if (ret) {
2115 spi_nor_unlock_device(nor);
2116 goto write_err;
2117 }
2118
2119 ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
2120 spi_nor_unlock_device(nor);
2121 if (ret < 0)
2122 goto write_err;
2123 written = ret;
2124
2125 ret = spi_nor_wait_till_ready(nor);
2126 if (ret)
2127 goto write_err;
2128 *retlen += written;
2129 i += written;
2130 }
2131
2132write_err:
2133 spi_nor_unlock_and_unprep_pe(nor, to, len);
2134
2135 return ret;
2136}
2137
2138static int spi_nor_check(struct spi_nor *nor)
2139{
2140 if (!nor->dev ||
2141 (!nor->spimem && !nor->controller_ops) ||
2142 (!nor->spimem && nor->controller_ops &&
2143 (!nor->controller_ops->read ||
2144 !nor->controller_ops->write ||
2145 !nor->controller_ops->read_reg ||
2146 !nor->controller_ops->write_reg))) {
2147 pr_err("spi-nor: please fill all the necessary fields!\n");
2148 return -EINVAL;
2149 }
2150
2151 if (nor->spimem && nor->controller_ops) {
2152 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n");
2153 return -EINVAL;
2154 }
2155
2156 return 0;
2157}
2158
2159void
2160spi_nor_set_read_settings(struct spi_nor_read_command *read,
2161 u8 num_mode_clocks,
2162 u8 num_wait_states,
2163 u8 opcode,
2164 enum spi_nor_protocol proto)
2165{
2166 read->num_mode_clocks = num_mode_clocks;
2167 read->num_wait_states = num_wait_states;
2168 read->opcode = opcode;
2169 read->proto = proto;
2170}
2171
2172void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
2173 enum spi_nor_protocol proto)
2174{
2175 pp->opcode = opcode;
2176 pp->proto = proto;
2177}
2178
2179static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2180{
2181 size_t i;
2182
2183 for (i = 0; i < size; i++)
2184 if (table[i][0] == (int)hwcaps)
2185 return table[i][1];
2186
2187 return -EINVAL;
2188}
2189
2190int spi_nor_hwcaps_read2cmd(u32 hwcaps)
2191{
2192 static const int hwcaps_read2cmd[][2] = {
2193 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2194 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2195 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2196 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2197 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2198 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2199 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2200 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2201 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2202 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2203 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2204 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2205 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2206 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2207 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
2208 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR },
2209 };
2210
2211 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2212 ARRAY_SIZE(hwcaps_read2cmd));
2213}
2214
2215int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
2216{
2217 static const int hwcaps_pp2cmd[][2] = {
2218 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2219 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2220 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2221 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2222 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2223 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2224 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
2225 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR },
2226 };
2227
2228 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2229 ARRAY_SIZE(hwcaps_pp2cmd));
2230}
2231
2232/**
2233 * spi_nor_spimem_check_op - check if the operation is supported
2234 * by controller
2235 *@nor: pointer to a 'struct spi_nor'
2236 *@op: pointer to op template to be checked
2237 *
2238 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2239 */
2240static int spi_nor_spimem_check_op(struct spi_nor *nor,
2241 struct spi_mem_op *op)
2242{
2243 /*
2244 * First test with 4 address bytes. The opcode itself might
2245 * be a 3B addressing opcode but we don't care, because
2246 * SPI controller implementation should not check the opcode,
2247 * but just the sequence.
2248 */
2249 op->addr.nbytes = 4;
2250 if (!spi_mem_supports_op(nor->spimem, op)) {
2251 if (nor->params->size > SZ_16M)
2252 return -EOPNOTSUPP;
2253
2254 /* If flash size <= 16MB, 3 address bytes are sufficient */
2255 op->addr.nbytes = 3;
2256 if (!spi_mem_supports_op(nor->spimem, op))
2257 return -EOPNOTSUPP;
2258 }
2259
2260 return 0;
2261}
2262
2263/**
2264 * spi_nor_spimem_check_readop - check if the read op is supported
2265 * by controller
2266 *@nor: pointer to a 'struct spi_nor'
2267 *@read: pointer to op template to be checked
2268 *
2269 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2270 */
2271static int spi_nor_spimem_check_readop(struct spi_nor *nor,
2272 const struct spi_nor_read_command *read)
2273{
2274 struct spi_mem_op op = SPI_NOR_READ_OP(read->opcode);
2275
2276 spi_nor_spimem_setup_op(nor, &op, read->proto);
2277
2278 /* convert the dummy cycles to the number of bytes */
2279 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
2280 op.dummy.buswidth / 8;
2281 if (spi_nor_protocol_is_dtr(nor->read_proto))
2282 op.dummy.nbytes *= 2;
2283
2284 return spi_nor_spimem_check_op(nor, &op);
2285}
2286
2287/**
2288 * spi_nor_spimem_check_pp - check if the page program op is supported
2289 * by controller
2290 *@nor: pointer to a 'struct spi_nor'
2291 *@pp: pointer to op template to be checked
2292 *
2293 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
2294 */
2295static int spi_nor_spimem_check_pp(struct spi_nor *nor,
2296 const struct spi_nor_pp_command *pp)
2297{
2298 struct spi_mem_op op = SPI_NOR_PP_OP(pp->opcode);
2299
2300 spi_nor_spimem_setup_op(nor, &op, pp->proto);
2301
2302 return spi_nor_spimem_check_op(nor, &op);
2303}
2304
2305/**
2306 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
2307 * based on SPI controller capabilities
2308 * @nor: pointer to a 'struct spi_nor'
2309 * @hwcaps: pointer to resulting capabilities after adjusting
2310 * according to controller and flash's capability
2311 */
2312static void
2313spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
2314{
2315 struct spi_nor_flash_parameter *params = nor->params;
2316 unsigned int cap;
2317
2318 /* X-X-X modes are not supported yet, mask them all. */
2319 *hwcaps &= ~SNOR_HWCAPS_X_X_X;
2320
2321 /*
2322 * If the reset line is broken, we do not want to enter a stateful
2323 * mode.
2324 */
2325 if (nor->flags & SNOR_F_BROKEN_RESET)
2326 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
2327
2328 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
2329 int rdidx, ppidx;
2330
2331 if (!(*hwcaps & BIT(cap)))
2332 continue;
2333
2334 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
2335 if (rdidx >= 0 &&
2336 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx]))
2337 *hwcaps &= ~BIT(cap);
2338
2339 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
2340 if (ppidx < 0)
2341 continue;
2342
2343 if (spi_nor_spimem_check_pp(nor,
2344 ¶ms->page_programs[ppidx]))
2345 *hwcaps &= ~BIT(cap);
2346 }
2347}
2348
2349/**
2350 * spi_nor_set_erase_type() - set a SPI NOR erase type
2351 * @erase: pointer to a structure that describes a SPI NOR erase type
2352 * @size: the size of the sector/block erased by the erase type
2353 * @opcode: the SPI command op code to erase the sector/block
2354 */
2355void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
2356 u8 opcode)
2357{
2358 erase->size = size;
2359 erase->opcode = opcode;
2360 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
2361 erase->size_shift = ffs(erase->size) - 1;
2362 erase->size_mask = (1 << erase->size_shift) - 1;
2363}
2364
2365/**
2366 * spi_nor_mask_erase_type() - mask out a SPI NOR erase type
2367 * @erase: pointer to a structure that describes a SPI NOR erase type
2368 */
2369void spi_nor_mask_erase_type(struct spi_nor_erase_type *erase)
2370{
2371 erase->size = 0;
2372}
2373
2374/**
2375 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2376 * @map: the erase map of the SPI NOR
2377 * @erase_mask: bitmask encoding erase types that can erase the entire
2378 * flash memory
2379 * @flash_size: the spi nor flash memory size
2380 */
2381void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2382 u8 erase_mask, u64 flash_size)
2383{
2384 map->uniform_region.offset = 0;
2385 map->uniform_region.size = flash_size;
2386 map->uniform_region.erase_mask = erase_mask;
2387 map->regions = &map->uniform_region;
2388 map->n_regions = 1;
2389}
2390
2391int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2392 const struct sfdp_parameter_header *bfpt_header,
2393 const struct sfdp_bfpt *bfpt)
2394{
2395 int ret;
2396
2397 if (nor->manufacturer && nor->manufacturer->fixups &&
2398 nor->manufacturer->fixups->post_bfpt) {
2399 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
2400 bfpt);
2401 if (ret)
2402 return ret;
2403 }
2404
2405 if (nor->info->fixups && nor->info->fixups->post_bfpt)
2406 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);
2407
2408 return 0;
2409}
2410
2411static int spi_nor_select_read(struct spi_nor *nor,
2412 u32 shared_hwcaps)
2413{
2414 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2415 const struct spi_nor_read_command *read;
2416
2417 if (best_match < 0)
2418 return -EINVAL;
2419
2420 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2421 if (cmd < 0)
2422 return -EINVAL;
2423
2424 read = &nor->params->reads[cmd];
2425 nor->read_opcode = read->opcode;
2426 nor->read_proto = read->proto;
2427
2428 /*
2429 * In the SPI NOR framework, we don't need to make the difference
2430 * between mode clock cycles and wait state clock cycles.
2431 * Indeed, the value of the mode clock cycles is used by a QSPI
2432 * flash memory to know whether it should enter or leave its 0-4-4
2433 * (Continuous Read / XIP) mode.
2434 * eXecution In Place is out of the scope of the mtd sub-system.
2435 * Hence we choose to merge both mode and wait state clock cycles
2436 * into the so called dummy clock cycles.
2437 */
2438 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2439 return 0;
2440}
2441
2442static int spi_nor_select_pp(struct spi_nor *nor,
2443 u32 shared_hwcaps)
2444{
2445 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2446 const struct spi_nor_pp_command *pp;
2447
2448 if (best_match < 0)
2449 return -EINVAL;
2450
2451 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2452 if (cmd < 0)
2453 return -EINVAL;
2454
2455 pp = &nor->params->page_programs[cmd];
2456 nor->program_opcode = pp->opcode;
2457 nor->write_proto = pp->proto;
2458 return 0;
2459}
2460
2461/**
2462 * spi_nor_select_uniform_erase() - select optimum uniform erase type
2463 * @map: the erase map of the SPI NOR
2464 *
2465 * Once the optimum uniform sector erase command is found, disable all the
2466 * other.
2467 *
2468 * Return: pointer to erase type on success, NULL otherwise.
2469 */
2470static const struct spi_nor_erase_type *
2471spi_nor_select_uniform_erase(struct spi_nor_erase_map *map)
2472{
2473 const struct spi_nor_erase_type *tested_erase, *erase = NULL;
2474 int i;
2475 u8 uniform_erase_type = map->uniform_region.erase_mask;
2476
2477 /*
2478 * Search for the biggest erase size, except for when compiled
2479 * to use 4k erases.
2480 */
2481 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2482 if (!(uniform_erase_type & BIT(i)))
2483 continue;
2484
2485 tested_erase = &map->erase_type[i];
2486
2487 /* Skip masked erase types. */
2488 if (!tested_erase->size)
2489 continue;
2490
2491 /*
2492 * If the current erase size is the 4k one, stop here,
2493 * we have found the right uniform Sector Erase command.
2494 */
2495 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_4K_SECTORS) &&
2496 tested_erase->size == SZ_4K) {
2497 erase = tested_erase;
2498 break;
2499 }
2500
2501 /*
2502 * Otherwise, the current erase size is still a valid candidate.
2503 * Select the biggest valid candidate.
2504 */
2505 if (!erase && tested_erase->size)
2506 erase = tested_erase;
2507 /* keep iterating to find the wanted_size */
2508 }
2509
2510 if (!erase)
2511 return NULL;
2512
2513 /* Disable all other Sector Erase commands. */
2514 map->uniform_region.erase_mask = BIT(erase - map->erase_type);
2515 return erase;
2516}
2517
2518static int spi_nor_select_erase(struct spi_nor *nor)
2519{
2520 struct spi_nor_erase_map *map = &nor->params->erase_map;
2521 const struct spi_nor_erase_type *erase = NULL;
2522 struct mtd_info *mtd = &nor->mtd;
2523 int i;
2524
2525 /*
2526 * The previous implementation handling Sector Erase commands assumed
2527 * that the SPI flash memory has an uniform layout then used only one
2528 * of the supported erase sizes for all Sector Erase commands.
2529 * So to be backward compatible, the new implementation also tries to
2530 * manage the SPI flash memory as uniform with a single erase sector
2531 * size, when possible.
2532 */
2533 if (spi_nor_has_uniform_erase(nor)) {
2534 erase = spi_nor_select_uniform_erase(map);
2535 if (!erase)
2536 return -EINVAL;
2537 nor->erase_opcode = erase->opcode;
2538 mtd->erasesize = erase->size;
2539 return 0;
2540 }
2541
2542 /*
2543 * For non-uniform SPI flash memory, set mtd->erasesize to the
2544 * maximum erase sector size. No need to set nor->erase_opcode.
2545 */
2546 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2547 if (map->erase_type[i].size) {
2548 erase = &map->erase_type[i];
2549 break;
2550 }
2551 }
2552
2553 if (!erase)
2554 return -EINVAL;
2555
2556 mtd->erasesize = erase->size;
2557 return 0;
2558}
2559
2560static int spi_nor_set_addr_nbytes(struct spi_nor *nor)
2561{
2562 if (nor->params->addr_nbytes) {
2563 nor->addr_nbytes = nor->params->addr_nbytes;
2564 } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
2565 /*
2566 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
2567 * in this protocol an odd addr_nbytes cannot be used because
2568 * then the address phase would only span a cycle and a half.
2569 * Half a cycle would be left over. We would then have to start
2570 * the dummy phase in the middle of a cycle and so too the data
2571 * phase, and we will end the transaction with half a cycle left
2572 * over.
2573 *
2574 * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to
2575 * avoid this situation.
2576 */
2577 nor->addr_nbytes = 4;
2578 } else if (nor->info->addr_nbytes) {
2579 nor->addr_nbytes = nor->info->addr_nbytes;
2580 } else {
2581 nor->addr_nbytes = 3;
2582 }
2583
2584 if (nor->addr_nbytes == 3 && nor->params->size > 0x1000000) {
2585 /* enable 4-byte addressing if the device exceeds 16MiB */
2586 nor->addr_nbytes = 4;
2587 }
2588
2589 if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) {
2590 dev_dbg(nor->dev, "The number of address bytes is too large: %u\n",
2591 nor->addr_nbytes);
2592 return -EINVAL;
2593 }
2594
2595 /* Set 4byte opcodes when possible. */
2596 if (nor->addr_nbytes == 4 && nor->flags & SNOR_F_4B_OPCODES &&
2597 !(nor->flags & SNOR_F_HAS_4BAIT))
2598 spi_nor_set_4byte_opcodes(nor);
2599
2600 return 0;
2601}
2602
2603static int spi_nor_setup(struct spi_nor *nor,
2604 const struct spi_nor_hwcaps *hwcaps)
2605{
2606 struct spi_nor_flash_parameter *params = nor->params;
2607 u32 ignored_mask, shared_mask;
2608 int err;
2609
2610 /*
2611 * Keep only the hardware capabilities supported by both the SPI
2612 * controller and the SPI flash memory.
2613 */
2614 shared_mask = hwcaps->mask & params->hwcaps.mask;
2615
2616 if (nor->spimem) {
2617 /*
2618 * When called from spi_nor_probe(), all caps are set and we
2619 * need to discard some of them based on what the SPI
2620 * controller actually supports (using spi_mem_supports_op()).
2621 */
2622 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);
2623 } else {
2624 /*
2625 * SPI n-n-n protocols are not supported when the SPI
2626 * controller directly implements the spi_nor interface.
2627 * Yet another reason to switch to spi-mem.
2628 */
2629 ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR;
2630 if (shared_mask & ignored_mask) {
2631 dev_dbg(nor->dev,
2632 "SPI n-n-n protocols are not supported.\n");
2633 shared_mask &= ~ignored_mask;
2634 }
2635 }
2636
2637 /* Select the (Fast) Read command. */
2638 err = spi_nor_select_read(nor, shared_mask);
2639 if (err) {
2640 dev_dbg(nor->dev,
2641 "can't select read settings supported by both the SPI controller and memory.\n");
2642 return err;
2643 }
2644
2645 /* Select the Page Program command. */
2646 err = spi_nor_select_pp(nor, shared_mask);
2647 if (err) {
2648 dev_dbg(nor->dev,
2649 "can't select write settings supported by both the SPI controller and memory.\n");
2650 return err;
2651 }
2652
2653 /* Select the Sector Erase command. */
2654 err = spi_nor_select_erase(nor);
2655 if (err) {
2656 dev_dbg(nor->dev,
2657 "can't select erase settings supported by both the SPI controller and memory.\n");
2658 return err;
2659 }
2660
2661 return spi_nor_set_addr_nbytes(nor);
2662}
2663
2664/**
2665 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
2666 * settings based on MFR register and ->default_init() hook.
2667 * @nor: pointer to a 'struct spi_nor'.
2668 */
2669static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
2670{
2671 if (nor->manufacturer && nor->manufacturer->fixups &&
2672 nor->manufacturer->fixups->default_init)
2673 nor->manufacturer->fixups->default_init(nor);
2674
2675 if (nor->info->fixups && nor->info->fixups->default_init)
2676 nor->info->fixups->default_init(nor);
2677}
2678
2679/**
2680 * spi_nor_no_sfdp_init_params() - Initialize the flash's parameters and
2681 * settings based on nor->info->sfdp_flags. This method should be called only by
2682 * flashes that do not define SFDP tables. If the flash supports SFDP but the
2683 * information is wrong and the settings from this function can not be retrieved
2684 * by parsing SFDP, one should instead use the fixup hooks and update the wrong
2685 * bits.
2686 * @nor: pointer to a 'struct spi_nor'.
2687 */
2688static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
2689{
2690 struct spi_nor_flash_parameter *params = nor->params;
2691 struct spi_nor_erase_map *map = ¶ms->erase_map;
2692 const struct flash_info *info = nor->info;
2693 const u8 no_sfdp_flags = info->no_sfdp_flags;
2694 u8 i, erase_mask;
2695
2696 if (no_sfdp_flags & SPI_NOR_DUAL_READ) {
2697 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2698 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],
2699 0, 8, SPINOR_OP_READ_1_1_2,
2700 SNOR_PROTO_1_1_2);
2701 }
2702
2703 if (no_sfdp_flags & SPI_NOR_QUAD_READ) {
2704 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2705 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],
2706 0, 8, SPINOR_OP_READ_1_1_4,
2707 SNOR_PROTO_1_1_4);
2708 }
2709
2710 if (no_sfdp_flags & SPI_NOR_OCTAL_READ) {
2711 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2712 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
2713 0, 8, SPINOR_OP_READ_1_1_8,
2714 SNOR_PROTO_1_1_8);
2715 }
2716
2717 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) {
2718 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
2719 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
2720 0, 20, SPINOR_OP_READ_FAST,
2721 SNOR_PROTO_8_8_8_DTR);
2722 }
2723
2724 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) {
2725 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
2726 /*
2727 * Since xSPI Page Program opcode is backward compatible with
2728 * Legacy SPI, use Legacy SPI opcode there as well.
2729 */
2730 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
2731 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
2732 }
2733
2734 /*
2735 * Sector Erase settings. Sort Erase Types in ascending order, with the
2736 * smallest erase size starting at BIT(0).
2737 */
2738 erase_mask = 0;
2739 i = 0;
2740 if (no_sfdp_flags & SECT_4K) {
2741 erase_mask |= BIT(i);
2742 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2743 SPINOR_OP_BE_4K);
2744 i++;
2745 }
2746 erase_mask |= BIT(i);
2747 spi_nor_set_erase_type(&map->erase_type[i],
2748 info->sector_size ?: SPI_NOR_DEFAULT_SECTOR_SIZE,
2749 SPINOR_OP_SE);
2750 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
2751}
2752
2753/**
2754 * spi_nor_init_flags() - Initialize NOR flags for settings that are not defined
2755 * in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP.
2756 * @nor: pointer to a 'struct spi_nor'
2757 */
2758static void spi_nor_init_flags(struct spi_nor *nor)
2759{
2760 struct device_node *np = spi_nor_get_flash_node(nor);
2761 const u16 flags = nor->info->flags;
2762
2763 if (of_property_read_bool(np, "broken-flash-reset"))
2764 nor->flags |= SNOR_F_BROKEN_RESET;
2765
2766 if (of_property_read_bool(np, "no-wp"))
2767 nor->flags |= SNOR_F_NO_WP;
2768
2769 if (flags & SPI_NOR_SWP_IS_VOLATILE)
2770 nor->flags |= SNOR_F_SWP_IS_VOLATILE;
2771
2772 if (flags & SPI_NOR_HAS_LOCK)
2773 nor->flags |= SNOR_F_HAS_LOCK;
2774
2775 if (flags & SPI_NOR_HAS_TB) {
2776 nor->flags |= SNOR_F_HAS_SR_TB;
2777 if (flags & SPI_NOR_TB_SR_BIT6)
2778 nor->flags |= SNOR_F_HAS_SR_TB_BIT6;
2779 }
2780
2781 if (flags & SPI_NOR_4BIT_BP) {
2782 nor->flags |= SNOR_F_HAS_4BIT_BP;
2783 if (flags & SPI_NOR_BP3_SR_BIT6)
2784 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
2785 }
2786
2787 if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 &&
2788 !nor->controller_ops)
2789 nor->flags |= SNOR_F_RWW;
2790}
2791
2792/**
2793 * spi_nor_init_fixup_flags() - Initialize NOR flags for settings that can not
2794 * be discovered by SFDP for this particular flash because the SFDP table that
2795 * indicates this support is not defined in the flash. In case the table for
2796 * this support is defined but has wrong values, one should instead use a
2797 * post_sfdp() hook to set the SNOR_F equivalent flag.
2798 * @nor: pointer to a 'struct spi_nor'
2799 */
2800static void spi_nor_init_fixup_flags(struct spi_nor *nor)
2801{
2802 const u8 fixup_flags = nor->info->fixup_flags;
2803
2804 if (fixup_flags & SPI_NOR_4B_OPCODES)
2805 nor->flags |= SNOR_F_4B_OPCODES;
2806
2807 if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE)
2808 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
2809}
2810
2811/**
2812 * spi_nor_late_init_params() - Late initialization of default flash parameters.
2813 * @nor: pointer to a 'struct spi_nor'
2814 *
2815 * Used to initialize flash parameters that are not declared in the JESD216
2816 * SFDP standard, or where SFDP tables are not defined at all.
2817 * Will replace the spi_nor_manufacturer_init_params() method.
2818 */
2819static int spi_nor_late_init_params(struct spi_nor *nor)
2820{
2821 struct spi_nor_flash_parameter *params = nor->params;
2822 int ret;
2823
2824 if (nor->manufacturer && nor->manufacturer->fixups &&
2825 nor->manufacturer->fixups->late_init) {
2826 ret = nor->manufacturer->fixups->late_init(nor);
2827 if (ret)
2828 return ret;
2829 }
2830
2831 /* Needed by some flashes late_init hooks. */
2832 spi_nor_init_flags(nor);
2833
2834 if (nor->info->fixups && nor->info->fixups->late_init) {
2835 ret = nor->info->fixups->late_init(nor);
2836 if (ret)
2837 return ret;
2838 }
2839
2840 if (!nor->params->die_erase_opcode)
2841 nor->params->die_erase_opcode = SPINOR_OP_CHIP_ERASE;
2842
2843 /* Default method kept for backward compatibility. */
2844 if (!params->set_4byte_addr_mode)
2845 params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;
2846
2847 spi_nor_init_fixup_flags(nor);
2848
2849 /*
2850 * NOR protection support. When locking_ops are not provided, we pick
2851 * the default ones.
2852 */
2853 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)
2854 spi_nor_init_default_locking_ops(nor);
2855
2856 if (params->n_banks > 1)
2857 params->bank_size = div_u64(params->size, params->n_banks);
2858
2859 return 0;
2860}
2861
2862/**
2863 * spi_nor_sfdp_init_params_deprecated() - Deprecated way of initializing flash
2864 * parameters and settings based on JESD216 SFDP standard.
2865 * @nor: pointer to a 'struct spi_nor'.
2866 *
2867 * The method has a roll-back mechanism: in case the SFDP parsing fails, the
2868 * legacy flash parameters and settings will be restored.
2869 */
2870static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor)
2871{
2872 struct spi_nor_flash_parameter sfdp_params;
2873
2874 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
2875
2876 if (spi_nor_parse_sfdp(nor)) {
2877 memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2878 nor->flags &= ~SNOR_F_4B_OPCODES;
2879 }
2880}
2881
2882/**
2883 * spi_nor_init_params_deprecated() - Deprecated way of initializing flash
2884 * parameters and settings.
2885 * @nor: pointer to a 'struct spi_nor'.
2886 *
2887 * The method assumes that flash doesn't support SFDP so it initializes flash
2888 * parameters in spi_nor_no_sfdp_init_params() which later on can be overwritten
2889 * when parsing SFDP, if supported.
2890 */
2891static void spi_nor_init_params_deprecated(struct spi_nor *nor)
2892{
2893 spi_nor_no_sfdp_init_params(nor);
2894
2895 spi_nor_manufacturer_init_params(nor);
2896
2897 if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ |
2898 SPI_NOR_QUAD_READ |
2899 SPI_NOR_OCTAL_READ |
2900 SPI_NOR_OCTAL_DTR_READ))
2901 spi_nor_sfdp_init_params_deprecated(nor);
2902}
2903
2904/**
2905 * spi_nor_init_default_params() - Default initialization of flash parameters
2906 * and settings. Done for all flashes, regardless is they define SFDP tables
2907 * or not.
2908 * @nor: pointer to a 'struct spi_nor'.
2909 */
2910static void spi_nor_init_default_params(struct spi_nor *nor)
2911{
2912 struct spi_nor_flash_parameter *params = nor->params;
2913 const struct flash_info *info = nor->info;
2914 struct device_node *np = spi_nor_get_flash_node(nor);
2915
2916 params->quad_enable = spi_nor_sr2_bit1_quad_enable;
2917 params->otp.org = info->otp;
2918
2919 /* Default to 16-bit Write Status (01h) Command */
2920 nor->flags |= SNOR_F_HAS_16BIT_SR;
2921
2922 /* Set SPI NOR sizes. */
2923 params->writesize = 1;
2924 params->size = info->size;
2925 params->bank_size = params->size;
2926 params->page_size = info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE;
2927 params->n_banks = info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS;
2928
2929 /* Default to Fast Read for non-DT and enable it if requested by DT. */
2930 if (!np || of_property_read_bool(np, "m25p,fast-read"))
2931 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2932
2933 /* (Fast) Read settings. */
2934 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2935 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],
2936 0, 0, SPINOR_OP_READ,
2937 SNOR_PROTO_1_1_1);
2938
2939 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
2940 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],
2941 0, 8, SPINOR_OP_READ_FAST,
2942 SNOR_PROTO_1_1_1);
2943 /* Page Program settings. */
2944 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2945 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
2946 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
2947
2948 if (info->flags & SPI_NOR_QUAD_PP) {
2949 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
2950 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
2951 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
2952 }
2953}
2954
2955/**
2956 * spi_nor_init_params() - Initialize the flash's parameters and settings.
2957 * @nor: pointer to a 'struct spi_nor'.
2958 *
2959 * The flash parameters and settings are initialized based on a sequence of
2960 * calls that are ordered by priority:
2961 *
2962 * 1/ Default flash parameters initialization. The initializations are done
2963 * based on nor->info data:
2964 * spi_nor_info_init_params()
2965 *
2966 * which can be overwritten by:
2967 * 2/ Manufacturer flash parameters initialization. The initializations are
2968 * done based on MFR register, or when the decisions can not be done solely
2969 * based on MFR, by using specific flash_info tweeks, ->default_init():
2970 * spi_nor_manufacturer_init_params()
2971 *
2972 * which can be overwritten by:
2973 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
2974 * should be more accurate that the above.
2975 * spi_nor_parse_sfdp() or spi_nor_no_sfdp_init_params()
2976 *
2977 * Please note that there is a ->post_bfpt() fixup hook that can overwrite
2978 * the flash parameters and settings immediately after parsing the Basic
2979 * Flash Parameter Table.
2980 * spi_nor_post_sfdp_fixups() is called after the SFDP tables are parsed.
2981 * It is used to tweak various flash parameters when information provided
2982 * by the SFDP tables are wrong.
2983 *
2984 * which can be overwritten by:
2985 * 4/ Late flash parameters initialization, used to initialize flash
2986 * parameters that are not declared in the JESD216 SFDP standard, or where SFDP
2987 * tables are not defined at all.
2988 * spi_nor_late_init_params()
2989 *
2990 * Return: 0 on success, -errno otherwise.
2991 */
2992static int spi_nor_init_params(struct spi_nor *nor)
2993{
2994 int ret;
2995
2996 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL);
2997 if (!nor->params)
2998 return -ENOMEM;
2999
3000 spi_nor_init_default_params(nor);
3001
3002 if (spi_nor_needs_sfdp(nor)) {
3003 ret = spi_nor_parse_sfdp(nor);
3004 if (ret) {
3005 dev_err(nor->dev, "BFPT parsing failed. Please consider using SPI_NOR_SKIP_SFDP when declaring the flash\n");
3006 return ret;
3007 }
3008 } else if (nor->info->no_sfdp_flags & SPI_NOR_SKIP_SFDP) {
3009 spi_nor_no_sfdp_init_params(nor);
3010 } else {
3011 spi_nor_init_params_deprecated(nor);
3012 }
3013
3014 ret = spi_nor_late_init_params(nor);
3015 if (ret)
3016 return ret;
3017
3018 if (WARN_ON(!is_power_of_2(nor->params->page_size)))
3019 return -EINVAL;
3020
3021 return 0;
3022}
3023
3024/** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O.
3025 * @nor: pointer to a 'struct spi_nor'
3026 * @enable: whether to enable or disable Octal DTR
3027 *
3028 * Return: 0 on success, -errno otherwise.
3029 */
3030static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
3031{
3032 int ret;
3033
3034 if (!nor->params->set_octal_dtr)
3035 return 0;
3036
3037 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
3038 nor->write_proto == SNOR_PROTO_8_8_8_DTR))
3039 return 0;
3040
3041 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
3042 return 0;
3043
3044 ret = nor->params->set_octal_dtr(nor, enable);
3045 if (ret)
3046 return ret;
3047
3048 if (enable)
3049 nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
3050 else
3051 nor->reg_proto = SNOR_PROTO_1_1_1;
3052
3053 return 0;
3054}
3055
3056/**
3057 * spi_nor_quad_enable() - enable Quad I/O if needed.
3058 * @nor: pointer to a 'struct spi_nor'
3059 *
3060 * Return: 0 on success, -errno otherwise.
3061 */
3062static int spi_nor_quad_enable(struct spi_nor *nor)
3063{
3064 if (!nor->params->quad_enable)
3065 return 0;
3066
3067 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
3068 spi_nor_get_protocol_width(nor->write_proto) == 4))
3069 return 0;
3070
3071 return nor->params->quad_enable(nor);
3072}
3073
3074/**
3075 * spi_nor_set_4byte_addr_mode() - Set address mode.
3076 * @nor: pointer to a 'struct spi_nor'.
3077 * @enable: enable/disable 4 byte address mode.
3078 *
3079 * Return: 0 on success, -errno otherwise.
3080 */
3081int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
3082{
3083 struct spi_nor_flash_parameter *params = nor->params;
3084 int ret;
3085
3086 if (enable) {
3087 /*
3088 * If the RESET# pin isn't hooked up properly, or the system
3089 * otherwise doesn't perform a reset command in the boot
3090 * sequence, it's impossible to 100% protect against unexpected
3091 * reboots (e.g., crashes). Warn the user (or hopefully, system
3092 * designer) that this is bad.
3093 */
3094 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
3095 "enabling reset hack; may not recover from unexpected reboots\n");
3096 }
3097
3098 ret = params->set_4byte_addr_mode(nor, enable);
3099 if (ret && ret != -EOPNOTSUPP)
3100 return ret;
3101
3102 if (enable) {
3103 params->addr_nbytes = 4;
3104 params->addr_mode_nbytes = 4;
3105 } else {
3106 params->addr_nbytes = 3;
3107 params->addr_mode_nbytes = 3;
3108 }
3109
3110 return 0;
3111}
3112
3113static int spi_nor_init(struct spi_nor *nor)
3114{
3115 int err;
3116
3117 err = spi_nor_set_octal_dtr(nor, true);
3118 if (err) {
3119 dev_dbg(nor->dev, "octal mode not supported\n");
3120 return err;
3121 }
3122
3123 err = spi_nor_quad_enable(nor);
3124 if (err) {
3125 dev_dbg(nor->dev, "quad mode not supported\n");
3126 return err;
3127 }
3128
3129 /*
3130 * Some SPI NOR flashes are write protected by default after a power-on
3131 * reset cycle, in order to avoid inadvertent writes during power-up.
3132 * Backward compatibility imposes to unlock the entire flash memory
3133 * array at power-up by default. Depending on the kernel configuration
3134 * (1) do nothing, (2) always unlock the entire flash array or (3)
3135 * unlock the entire flash array only when the software write
3136 * protection bits are volatile. The latter is indicated by
3137 * SNOR_F_SWP_IS_VOLATILE.
3138 */
3139 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) ||
3140 (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) &&
3141 nor->flags & SNOR_F_SWP_IS_VOLATILE))
3142 spi_nor_try_unlock_all(nor);
3143
3144 if (nor->addr_nbytes == 4 &&
3145 nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
3146 !(nor->flags & SNOR_F_4B_OPCODES))
3147 return spi_nor_set_4byte_addr_mode(nor, true);
3148
3149 return 0;
3150}
3151
3152/**
3153 * spi_nor_soft_reset() - Perform a software reset
3154 * @nor: pointer to 'struct spi_nor'
3155 *
3156 * Performs a "Soft Reset and Enter Default Protocol Mode" sequence which resets
3157 * the device to its power-on-reset state. This is useful when the software has
3158 * made some changes to device (volatile) registers and needs to reset it before
3159 * shutting down, for example.
3160 *
3161 * Not every flash supports this sequence. The same set of opcodes might be used
3162 * for some other operation on a flash that does not support this. Support for
3163 * this sequence can be discovered via SFDP in the BFPT table.
3164 *
3165 * Return: 0 on success, -errno otherwise.
3166 */
3167static void spi_nor_soft_reset(struct spi_nor *nor)
3168{
3169 struct spi_mem_op op;
3170 int ret;
3171
3172 op = (struct spi_mem_op)SPINOR_SRSTEN_OP;
3173
3174 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
3175
3176 ret = spi_mem_exec_op(nor->spimem, &op);
3177 if (ret) {
3178 if (ret != -EOPNOTSUPP)
3179 dev_warn(nor->dev, "Software reset failed: %d\n", ret);
3180 return;
3181 }
3182
3183 op = (struct spi_mem_op)SPINOR_SRST_OP;
3184
3185 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
3186
3187 ret = spi_mem_exec_op(nor->spimem, &op);
3188 if (ret) {
3189 dev_warn(nor->dev, "Software reset failed: %d\n", ret);
3190 return;
3191 }
3192
3193 /*
3194 * Software Reset is not instant, and the delay varies from flash to
3195 * flash. Looking at a few flashes, most range somewhere below 100
3196 * microseconds. So, sleep for a range of 200-400 us.
3197 */
3198 usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX);
3199}
3200
3201/* mtd suspend handler */
3202static int spi_nor_suspend(struct mtd_info *mtd)
3203{
3204 struct spi_nor *nor = mtd_to_spi_nor(mtd);
3205 int ret;
3206
3207 /* Disable octal DTR mode if we enabled it. */
3208 ret = spi_nor_set_octal_dtr(nor, false);
3209 if (ret)
3210 dev_err(nor->dev, "suspend() failed\n");
3211
3212 return ret;
3213}
3214
3215/* mtd resume handler */
3216static void spi_nor_resume(struct mtd_info *mtd)
3217{
3218 struct spi_nor *nor = mtd_to_spi_nor(mtd);
3219 struct device *dev = nor->dev;
3220 int ret;
3221
3222 /* re-initialize the nor chip */
3223 ret = spi_nor_init(nor);
3224 if (ret)
3225 dev_err(dev, "resume() failed\n");
3226}
3227
3228static int spi_nor_get_device(struct mtd_info *mtd)
3229{
3230 struct mtd_info *master = mtd_get_master(mtd);
3231 struct spi_nor *nor = mtd_to_spi_nor(master);
3232 struct device *dev;
3233
3234 if (nor->spimem)
3235 dev = nor->spimem->spi->controller->dev.parent;
3236 else
3237 dev = nor->dev;
3238
3239 if (!try_module_get(dev->driver->owner))
3240 return -ENODEV;
3241
3242 return 0;
3243}
3244
3245static void spi_nor_put_device(struct mtd_info *mtd)
3246{
3247 struct mtd_info *master = mtd_get_master(mtd);
3248 struct spi_nor *nor = mtd_to_spi_nor(master);
3249 struct device *dev;
3250
3251 if (nor->spimem)
3252 dev = nor->spimem->spi->controller->dev.parent;
3253 else
3254 dev = nor->dev;
3255
3256 module_put(dev->driver->owner);
3257}
3258
3259static void spi_nor_restore(struct spi_nor *nor)
3260{
3261 int ret;
3262
3263 /* restore the addressing mode */
3264 if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
3265 nor->flags & SNOR_F_BROKEN_RESET) {
3266 ret = spi_nor_set_4byte_addr_mode(nor, false);
3267 if (ret)
3268 /*
3269 * Do not stop the execution in the hope that the flash
3270 * will default to the 3-byte address mode after the
3271 * software reset.
3272 */
3273 dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", ret);
3274 }
3275
3276 if (nor->flags & SNOR_F_SOFT_RESET)
3277 spi_nor_soft_reset(nor);
3278}
3279
3280static const struct flash_info *spi_nor_match_name(struct spi_nor *nor,
3281 const char *name)
3282{
3283 unsigned int i, j;
3284
3285 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
3286 for (j = 0; j < manufacturers[i]->nparts; j++) {
3287 if (manufacturers[i]->parts[j].name &&
3288 !strcmp(name, manufacturers[i]->parts[j].name)) {
3289 nor->manufacturer = manufacturers[i];
3290 return &manufacturers[i]->parts[j];
3291 }
3292 }
3293 }
3294
3295 return NULL;
3296}
3297
3298static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
3299 const char *name)
3300{
3301 const struct flash_info *info = NULL;
3302
3303 if (name)
3304 info = spi_nor_match_name(nor, name);
3305 /*
3306 * Auto-detect if chip name wasn't specified or not found, or the chip
3307 * has an ID. If the chip supposedly has an ID, we also do an
3308 * auto-detection to compare it later.
3309 */
3310 if (!info || info->id) {
3311 const struct flash_info *jinfo;
3312
3313 jinfo = spi_nor_detect(nor);
3314 if (IS_ERR(jinfo))
3315 return jinfo;
3316
3317 /*
3318 * If caller has specified name of flash model that can normally
3319 * be detected using JEDEC, let's verify it.
3320 */
3321 if (info && jinfo != info)
3322 dev_warn(nor->dev, "found %s, expected %s\n",
3323 jinfo->name, info->name);
3324
3325 /* If info was set before, JEDEC knows better. */
3326 info = jinfo;
3327 }
3328
3329 return info;
3330}
3331
3332static u32
3333spi_nor_get_region_erasesize(const struct spi_nor_erase_region *region,
3334 const struct spi_nor_erase_type *erase_type)
3335{
3336 int i;
3337
3338 if (region->overlaid)
3339 return region->size;
3340
3341 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
3342 if (region->erase_mask & BIT(i))
3343 return erase_type[i].size;
3344 }
3345
3346 return 0;
3347}
3348
3349static int spi_nor_set_mtd_eraseregions(struct spi_nor *nor)
3350{
3351 const struct spi_nor_erase_map *map = &nor->params->erase_map;
3352 const struct spi_nor_erase_region *region = map->regions;
3353 struct mtd_erase_region_info *mtd_region;
3354 struct mtd_info *mtd = &nor->mtd;
3355 u32 erasesize, i;
3356
3357 mtd_region = devm_kcalloc(nor->dev, map->n_regions, sizeof(*mtd_region),
3358 GFP_KERNEL);
3359 if (!mtd_region)
3360 return -ENOMEM;
3361
3362 for (i = 0; i < map->n_regions; i++) {
3363 erasesize = spi_nor_get_region_erasesize(®ion[i],
3364 map->erase_type);
3365 if (!erasesize)
3366 return -EINVAL;
3367
3368 mtd_region[i].erasesize = erasesize;
3369 mtd_region[i].numblocks = div_u64(region[i].size, erasesize);
3370 mtd_region[i].offset = region[i].offset;
3371 }
3372
3373 mtd->numeraseregions = map->n_regions;
3374 mtd->eraseregions = mtd_region;
3375
3376 return 0;
3377}
3378
3379static int spi_nor_set_mtd_info(struct spi_nor *nor)
3380{
3381 struct mtd_info *mtd = &nor->mtd;
3382 struct device *dev = nor->dev;
3383
3384 spi_nor_set_mtd_locking_ops(nor);
3385 spi_nor_set_mtd_otp_ops(nor);
3386
3387 mtd->dev.parent = dev;
3388 if (!mtd->name)
3389 mtd->name = dev_name(dev);
3390 mtd->type = MTD_NORFLASH;
3391 mtd->flags = MTD_CAP_NORFLASH;
3392 /* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */
3393 if (nor->flags & SNOR_F_ECC)
3394 mtd->flags &= ~MTD_BIT_WRITEABLE;
3395 if (nor->info->flags & SPI_NOR_NO_ERASE)
3396 mtd->flags |= MTD_NO_ERASE;
3397 else
3398 mtd->_erase = spi_nor_erase;
3399 mtd->writesize = nor->params->writesize;
3400 mtd->writebufsize = nor->params->page_size;
3401 mtd->size = nor->params->size;
3402 mtd->_read = spi_nor_read;
3403 /* Might be already set by some SST flashes. */
3404 if (!mtd->_write)
3405 mtd->_write = spi_nor_write;
3406 mtd->_suspend = spi_nor_suspend;
3407 mtd->_resume = spi_nor_resume;
3408 mtd->_get_device = spi_nor_get_device;
3409 mtd->_put_device = spi_nor_put_device;
3410
3411 if (!spi_nor_has_uniform_erase(nor))
3412 return spi_nor_set_mtd_eraseregions(nor);
3413
3414 return 0;
3415}
3416
3417static int spi_nor_hw_reset(struct spi_nor *nor)
3418{
3419 struct gpio_desc *reset;
3420
3421 reset = devm_gpiod_get_optional(nor->dev, "reset", GPIOD_OUT_LOW);
3422 if (IS_ERR_OR_NULL(reset))
3423 return PTR_ERR_OR_ZERO(reset);
3424
3425 /*
3426 * Experimental delay values by looking at different flash device
3427 * vendors datasheets.
3428 */
3429 usleep_range(1, 5);
3430 gpiod_set_value_cansleep(reset, 1);
3431 usleep_range(100, 150);
3432 gpiod_set_value_cansleep(reset, 0);
3433 usleep_range(1000, 1200);
3434
3435 return 0;
3436}
3437
3438int spi_nor_scan(struct spi_nor *nor, const char *name,
3439 const struct spi_nor_hwcaps *hwcaps)
3440{
3441 const struct flash_info *info;
3442 struct device *dev = nor->dev;
3443 int ret;
3444
3445 ret = spi_nor_check(nor);
3446 if (ret)
3447 return ret;
3448
3449 /* Reset SPI protocol for all commands. */
3450 nor->reg_proto = SNOR_PROTO_1_1_1;
3451 nor->read_proto = SNOR_PROTO_1_1_1;
3452 nor->write_proto = SNOR_PROTO_1_1_1;
3453
3454 /*
3455 * We need the bounce buffer early to read/write registers when going
3456 * through the spi-mem layer (buffers have to be DMA-able).
3457 * For spi-mem drivers, we'll reallocate a new buffer if
3458 * nor->params->page_size turns out to be greater than PAGE_SIZE (which
3459 * shouldn't happen before long since NOR pages are usually less
3460 * than 1KB) after spi_nor_scan() returns.
3461 */
3462 nor->bouncebuf_size = PAGE_SIZE;
3463 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
3464 GFP_KERNEL);
3465 if (!nor->bouncebuf)
3466 return -ENOMEM;
3467
3468 ret = spi_nor_hw_reset(nor);
3469 if (ret)
3470 return ret;
3471
3472 info = spi_nor_get_flash_info(nor, name);
3473 if (IS_ERR(info))
3474 return PTR_ERR(info);
3475
3476 nor->info = info;
3477
3478 mutex_init(&nor->lock);
3479
3480 /* Init flash parameters based on flash_info struct and SFDP */
3481 ret = spi_nor_init_params(nor);
3482 if (ret)
3483 return ret;
3484
3485 if (spi_nor_use_parallel_locking(nor))
3486 init_waitqueue_head(&nor->rww.wait);
3487
3488 /*
3489 * Configure the SPI memory:
3490 * - select op codes for (Fast) Read, Page Program and Sector Erase.
3491 * - set the number of dummy cycles (mode cycles + wait states).
3492 * - set the SPI protocols for register and memory accesses.
3493 * - set the number of address bytes.
3494 */
3495 ret = spi_nor_setup(nor, hwcaps);
3496 if (ret)
3497 return ret;
3498
3499 /* Send all the required SPI flash commands to initialize device */
3500 ret = spi_nor_init(nor);
3501 if (ret)
3502 return ret;
3503
3504 /* No mtd_info fields should be used up to this point. */
3505 ret = spi_nor_set_mtd_info(nor);
3506 if (ret)
3507 return ret;
3508
3509 dev_dbg(dev, "Manufacturer and device ID: %*phN\n",
3510 SPI_NOR_MAX_ID_LEN, nor->id);
3511
3512 return 0;
3513}
3514EXPORT_SYMBOL_GPL(spi_nor_scan);
3515
3516static int spi_nor_create_read_dirmap(struct spi_nor *nor)
3517{
3518 struct spi_mem_dirmap_info info = {
3519 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
3520 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
3521 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
3522 SPI_MEM_OP_DATA_IN(0, NULL, 0)),
3523 .offset = 0,
3524 .length = nor->params->size,
3525 };
3526 struct spi_mem_op *op = &info.op_tmpl;
3527
3528 spi_nor_spimem_setup_op(nor, op, nor->read_proto);
3529
3530 /* convert the dummy cycles to the number of bytes */
3531 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;
3532 if (spi_nor_protocol_is_dtr(nor->read_proto))
3533 op->dummy.nbytes *= 2;
3534
3535 /*
3536 * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3537 * of data bytes is non-zero, the data buswidth won't be set here. So,
3538 * do it explicitly.
3539 */
3540 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
3541
3542 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3543 &info);
3544 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc);
3545}
3546
3547static int spi_nor_create_write_dirmap(struct spi_nor *nor)
3548{
3549 struct spi_mem_dirmap_info info = {
3550 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
3551 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
3552 SPI_MEM_OP_NO_DUMMY,
3553 SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
3554 .offset = 0,
3555 .length = nor->params->size,
3556 };
3557 struct spi_mem_op *op = &info.op_tmpl;
3558
3559 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
3560 op->addr.nbytes = 0;
3561
3562 spi_nor_spimem_setup_op(nor, op, nor->write_proto);
3563
3564 /*
3565 * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3566 * of data bytes is non-zero, the data buswidth won't be set here. So,
3567 * do it explicitly.
3568 */
3569 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
3570
3571 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3572 &info);
3573 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc);
3574}
3575
3576static int spi_nor_probe(struct spi_mem *spimem)
3577{
3578 struct spi_device *spi = spimem->spi;
3579 struct flash_platform_data *data = dev_get_platdata(&spi->dev);
3580 struct spi_nor *nor;
3581 /*
3582 * Enable all caps by default. The core will mask them after
3583 * checking what's really supported using spi_mem_supports_op().
3584 */
3585 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL };
3586 char *flash_name;
3587 int ret;
3588
3589 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);
3590 if (!nor)
3591 return -ENOMEM;
3592
3593 nor->spimem = spimem;
3594 nor->dev = &spi->dev;
3595 spi_nor_set_flash_node(nor, spi->dev.of_node);
3596
3597 spi_mem_set_drvdata(spimem, nor);
3598
3599 if (data && data->name)
3600 nor->mtd.name = data->name;
3601
3602 if (!nor->mtd.name)
3603 nor->mtd.name = spi_mem_get_name(spimem);
3604
3605 /*
3606 * For some (historical?) reason many platforms provide two different
3607 * names in flash_platform_data: "name" and "type". Quite often name is
3608 * set to "m25p80" and then "type" provides a real chip name.
3609 * If that's the case, respect "type" and ignore a "name".
3610 */
3611 if (data && data->type)
3612 flash_name = data->type;
3613 else if (!strcmp(spi->modalias, "spi-nor"))
3614 flash_name = NULL; /* auto-detect */
3615 else
3616 flash_name = spi->modalias;
3617
3618 ret = spi_nor_scan(nor, flash_name, &hwcaps);
3619 if (ret)
3620 return ret;
3621
3622 spi_nor_debugfs_register(nor);
3623
3624 /*
3625 * None of the existing parts have > 512B pages, but let's play safe
3626 * and add this logic so that if anyone ever adds support for such
3627 * a NOR we don't end up with buffer overflows.
3628 */
3629 if (nor->params->page_size > PAGE_SIZE) {
3630 nor->bouncebuf_size = nor->params->page_size;
3631 devm_kfree(nor->dev, nor->bouncebuf);
3632 nor->bouncebuf = devm_kmalloc(nor->dev,
3633 nor->bouncebuf_size,
3634 GFP_KERNEL);
3635 if (!nor->bouncebuf)
3636 return -ENOMEM;
3637 }
3638
3639 ret = spi_nor_create_read_dirmap(nor);
3640 if (ret)
3641 return ret;
3642
3643 ret = spi_nor_create_write_dirmap(nor);
3644 if (ret)
3645 return ret;
3646
3647 return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
3648 data ? data->nr_parts : 0);
3649}
3650
3651static int spi_nor_remove(struct spi_mem *spimem)
3652{
3653 struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3654
3655 spi_nor_restore(nor);
3656
3657 /* Clean up MTD stuff. */
3658 return mtd_device_unregister(&nor->mtd);
3659}
3660
3661static void spi_nor_shutdown(struct spi_mem *spimem)
3662{
3663 struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3664
3665 spi_nor_restore(nor);
3666}
3667
3668/*
3669 * Do NOT add to this array without reading the following:
3670 *
3671 * Historically, many flash devices are bound to this driver by their name. But
3672 * since most of these flash are compatible to some extent, and their
3673 * differences can often be differentiated by the JEDEC read-ID command, we
3674 * encourage new users to add support to the spi-nor library, and simply bind
3675 * against a generic string here (e.g., "jedec,spi-nor").
3676 *
3677 * Many flash names are kept here in this list to keep them available
3678 * as module aliases for existing platforms.
3679 */
3680static const struct spi_device_id spi_nor_dev_ids[] = {
3681 /*
3682 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
3683 * hack around the fact that the SPI core does not provide uevent
3684 * matching for .of_match_table
3685 */
3686 {"spi-nor"},
3687
3688 /*
3689 * Entries not used in DTs that should be safe to drop after replacing
3690 * them with "spi-nor" in platform data.
3691 */
3692 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
3693
3694 /*
3695 * Entries that were used in DTs without "jedec,spi-nor" fallback and
3696 * should be kept for backward compatibility.
3697 */
3698 {"at25df321a"}, {"at25df641"}, {"at26df081a"},
3699 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
3700 {"mx25l25635e"},{"mx66l51235l"},
3701 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
3702 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
3703 {"s25fl064k"},
3704 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
3705 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
3706 {"m25p64"}, {"m25p128"},
3707 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
3708 {"w25q80bl"}, {"w25q128"}, {"w25q256"},
3709
3710 /* Flashes that can't be detected using JEDEC */
3711 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
3712 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
3713 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
3714
3715 /* Everspin MRAMs (non-JEDEC) */
3716 { "mr25h128" }, /* 128 Kib, 40 MHz */
3717 { "mr25h256" }, /* 256 Kib, 40 MHz */
3718 { "mr25h10" }, /* 1 Mib, 40 MHz */
3719 { "mr25h40" }, /* 4 Mib, 40 MHz */
3720
3721 { },
3722};
3723MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);
3724
3725static const struct of_device_id spi_nor_of_table[] = {
3726 /*
3727 * Generic compatibility for SPI NOR that can be identified by the
3728 * JEDEC READ ID opcode (0x9F). Use this, if possible.
3729 */
3730 { .compatible = "jedec,spi-nor" },
3731 { /* sentinel */ },
3732};
3733MODULE_DEVICE_TABLE(of, spi_nor_of_table);
3734
3735/*
3736 * REVISIT: many of these chips have deep power-down modes, which
3737 * should clearly be entered on suspend() to minimize power use.
3738 * And also when they're otherwise idle...
3739 */
3740static struct spi_mem_driver spi_nor_driver = {
3741 .spidrv = {
3742 .driver = {
3743 .name = "spi-nor",
3744 .of_match_table = spi_nor_of_table,
3745 .dev_groups = spi_nor_sysfs_groups,
3746 },
3747 .id_table = spi_nor_dev_ids,
3748 },
3749 .probe = spi_nor_probe,
3750 .remove = spi_nor_remove,
3751 .shutdown = spi_nor_shutdown,
3752};
3753
3754static int __init spi_nor_module_init(void)
3755{
3756 return spi_mem_driver_register(&spi_nor_driver);
3757}
3758module_init(spi_nor_module_init);
3759
3760static void __exit spi_nor_module_exit(void)
3761{
3762 spi_mem_driver_unregister(&spi_nor_driver);
3763 spi_nor_debugfs_shutdown();
3764}
3765module_exit(spi_nor_module_exit);
3766
3767MODULE_LICENSE("GPL v2");
3768MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
3769MODULE_AUTHOR("Mike Lavender");
3770MODULE_DESCRIPTION("framework for SPI NOR");