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1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
5 * Copyright(c) 2016 Intel Deutschland GmbH
6 *
7 * Portions of this file are derived from the ipw3945 project, as well
8 * as portions of the ieee80211 subsystem header files.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called LICENSE.
25 *
26 * Contact Information:
27 * Intel Linux Wireless <linuxwifi@intel.com>
28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 *
30 *****************************************************************************/
31#ifndef __iwl_trans_int_pcie_h__
32#define __iwl_trans_int_pcie_h__
33
34#include <linux/spinlock.h>
35#include <linux/interrupt.h>
36#include <linux/skbuff.h>
37#include <linux/wait.h>
38#include <linux/pci.h>
39#include <linux/timer.h>
40#include <linux/cpu.h>
41
42#include "iwl-fh.h"
43#include "iwl-csr.h"
44#include "iwl-trans.h"
45#include "iwl-debug.h"
46#include "iwl-io.h"
47#include "iwl-op-mode.h"
48
49/* We need 2 entries for the TX command and header, and another one might
50 * be needed for potential data in the SKB's head. The remaining ones can
51 * be used for frags.
52 */
53#define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3)
54
55/*
56 * RX related structures and functions
57 */
58#define RX_NUM_QUEUES 1
59#define RX_POST_REQ_ALLOC 2
60#define RX_CLAIM_REQ_ALLOC 8
61#define RX_PENDING_WATERMARK 16
62
63struct iwl_host_cmd;
64
65/*This file includes the declaration that are internal to the
66 * trans_pcie layer */
67
68/**
69 * struct iwl_rx_mem_buffer
70 * @page_dma: bus address of rxb page
71 * @page: driver's pointer to the rxb page
72 * @invalid: rxb is in driver ownership - not owned by HW
73 * @vid: index of this rxb in the global table
74 */
75struct iwl_rx_mem_buffer {
76 dma_addr_t page_dma;
77 struct page *page;
78 u16 vid;
79 bool invalid;
80 struct list_head list;
81};
82
83/**
84 * struct isr_statistics - interrupt statistics
85 *
86 */
87struct isr_statistics {
88 u32 hw;
89 u32 sw;
90 u32 err_code;
91 u32 sch;
92 u32 alive;
93 u32 rfkill;
94 u32 ctkill;
95 u32 wakeup;
96 u32 rx;
97 u32 tx;
98 u32 unhandled;
99};
100
101/**
102 * struct iwl_rxq - Rx queue
103 * @id: queue index
104 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
105 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
106 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
107 * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd)
108 * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd)
109 * @read: Shared index to newest available Rx buffer
110 * @write: Shared index to oldest written Rx packet
111 * @free_count: Number of pre-allocated buffers in rx_free
112 * @used_count: Number of RBDs handled to allocator to use for allocation
113 * @write_actual:
114 * @rx_free: list of RBDs with allocated RB ready for use
115 * @rx_used: list of RBDs with no RB attached
116 * @need_update: flag to indicate we need to update read/write index
117 * @rb_stts: driver's pointer to receive buffer status
118 * @rb_stts_dma: bus address of receive buffer status
119 * @lock:
120 * @queue: actual rx queue. Not used for multi-rx queue.
121 *
122 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
123 */
124struct iwl_rxq {
125 int id;
126 void *bd;
127 dma_addr_t bd_dma;
128 __le32 *used_bd;
129 dma_addr_t used_bd_dma;
130 u32 read;
131 u32 write;
132 u32 free_count;
133 u32 used_count;
134 u32 write_actual;
135 u32 queue_size;
136 struct list_head rx_free;
137 struct list_head rx_used;
138 bool need_update;
139 struct iwl_rb_status *rb_stts;
140 dma_addr_t rb_stts_dma;
141 spinlock_t lock;
142 struct napi_struct napi;
143 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
144};
145
146/**
147 * struct iwl_rb_allocator - Rx allocator
148 * @req_pending: number of requests the allcator had not processed yet
149 * @req_ready: number of requests honored and ready for claiming
150 * @rbd_allocated: RBDs with pages allocated and ready to be handled to
151 * the queue. This is a list of &struct iwl_rx_mem_buffer
152 * @rbd_empty: RBDs with no page attached for allocator use. This is a list
153 * of &struct iwl_rx_mem_buffer
154 * @lock: protects the rbd_allocated and rbd_empty lists
155 * @alloc_wq: work queue for background calls
156 * @rx_alloc: work struct for background calls
157 */
158struct iwl_rb_allocator {
159 atomic_t req_pending;
160 atomic_t req_ready;
161 struct list_head rbd_allocated;
162 struct list_head rbd_empty;
163 spinlock_t lock;
164 struct workqueue_struct *alloc_wq;
165 struct work_struct rx_alloc;
166};
167
168struct iwl_dma_ptr {
169 dma_addr_t dma;
170 void *addr;
171 size_t size;
172};
173
174/**
175 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
176 * @index -- current index
177 */
178static inline int iwl_queue_inc_wrap(int index)
179{
180 return ++index & (TFD_QUEUE_SIZE_MAX - 1);
181}
182
183/**
184 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
185 * @index -- current index
186 */
187static inline int iwl_queue_dec_wrap(int index)
188{
189 return --index & (TFD_QUEUE_SIZE_MAX - 1);
190}
191
192struct iwl_cmd_meta {
193 /* only for SYNC commands, iff the reply skb is wanted */
194 struct iwl_host_cmd *source;
195 u32 flags;
196 u32 tbs;
197};
198
199
200#define TFD_TX_CMD_SLOTS 256
201#define TFD_CMD_SLOTS 32
202
203/*
204 * The FH will write back to the first TB only, so we need to copy some data
205 * into the buffer regardless of whether it should be mapped or not.
206 * This indicates how big the first TB must be to include the scratch buffer
207 * and the assigned PN.
208 * Since PN location is 16 bytes at offset 24, it's 40 now.
209 * If we make it bigger then allocations will be bigger and copy slower, so
210 * that's probably not useful.
211 */
212#define IWL_FIRST_TB_SIZE 40
213#define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)
214
215struct iwl_pcie_txq_entry {
216 struct iwl_device_cmd *cmd;
217 struct sk_buff *skb;
218 /* buffer to free after command completes */
219 const void *free_buf;
220 struct iwl_cmd_meta meta;
221};
222
223struct iwl_pcie_first_tb_buf {
224 u8 buf[IWL_FIRST_TB_SIZE_ALIGN];
225};
226
227/**
228 * struct iwl_txq - Tx Queue for DMA
229 * @q: generic Rx/Tx queue descriptor
230 * @tfds: transmit frame descriptors (DMA memory)
231 * @first_tb_bufs: start of command headers, including scratch buffers, for
232 * the writeback -- this is DMA memory and an array holding one buffer
233 * for each command on the queue
234 * @first_tb_dma: DMA address for the first_tb_bufs start
235 * @entries: transmit entries (driver state)
236 * @lock: queue lock
237 * @stuck_timer: timer that fires if queue gets stuck
238 * @trans_pcie: pointer back to transport (for timer)
239 * @need_update: indicates need to update read/write index
240 * @active: stores if queue is active
241 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID
242 * @wd_timeout: queue watchdog timeout (jiffies) - per queue
243 * @frozen: tx stuck queue timer is frozen
244 * @frozen_expiry_remainder: remember how long until the timer fires
245 * @write_ptr: 1-st empty entry (index) host_w
246 * @read_ptr: last used entry (index) host_r
247 * @dma_addr: physical addr for BD's
248 * @n_window: safe queue window
249 * @id: queue id
250 * @low_mark: low watermark, resume queue if free space more than this
251 * @high_mark: high watermark, stop queue if free space less than this
252 *
253 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
254 * descriptors) and required locking structures.
255 *
256 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware
257 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless
258 * there might be HW changes in the future). For the normal TX
259 * queues, n_window, which is the size of the software queue data
260 * is also 256; however, for the command queue, n_window is only
261 * 32 since we don't need so many commands pending. Since the HW
262 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.
263 * This means that we end up with the following:
264 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
265 * SW entries: | 0 | ... | 31 |
266 * where N is a number between 0 and 7. This means that the SW
267 * data is a window overlayed over the HW queue.
268 */
269struct iwl_txq {
270 void *tfds;
271 struct iwl_pcie_first_tb_buf *first_tb_bufs;
272 dma_addr_t first_tb_dma;
273 struct iwl_pcie_txq_entry *entries;
274 spinlock_t lock;
275 unsigned long frozen_expiry_remainder;
276 struct timer_list stuck_timer;
277 struct iwl_trans_pcie *trans_pcie;
278 bool need_update;
279 bool frozen;
280 u8 active;
281 bool ampdu;
282 bool block;
283 unsigned long wd_timeout;
284 struct sk_buff_head overflow_q;
285
286 int write_ptr;
287 int read_ptr;
288 dma_addr_t dma_addr;
289 int n_window;
290 u32 id;
291 int low_mark;
292 int high_mark;
293};
294
295static inline dma_addr_t
296iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx)
297{
298 return txq->first_tb_dma +
299 sizeof(struct iwl_pcie_first_tb_buf) * idx;
300}
301
302struct iwl_tso_hdr_page {
303 struct page *page;
304 u8 *pos;
305};
306
307/**
308 * enum iwl_shared_irq_flags - level of sharing for irq
309 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
310 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
311 */
312enum iwl_shared_irq_flags {
313 IWL_SHARED_IRQ_NON_RX = BIT(0),
314 IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
315};
316
317/**
318 * struct iwl_trans_pcie - PCIe transport specific data
319 * @rxq: all the RX queue data
320 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
321 * @global_table: table mapping received VID from hw to rxb
322 * @rba: allocator for RX replenishing
323 * @trans: pointer to the generic transport area
324 * @scd_base_addr: scheduler sram base address in SRAM
325 * @scd_bc_tbls: pointer to the byte count table of the scheduler
326 * @kw: keep warm address
327 * @pci_dev: basic pci-network driver stuff
328 * @hw_base: pci hardware address support
329 * @ucode_write_complete: indicates that the ucode has been copied.
330 * @ucode_write_waitq: wait queue for uCode load
331 * @cmd_queue - command queue number
332 * @rx_buf_size: Rx buffer size
333 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
334 * @scd_set_active: should the transport configure the SCD for HCMD queue
335 * @sw_csum_tx: if true, then the transport will compute the csum of the TXed
336 * frame.
337 * @rx_page_order: page order for receive buffer size
338 * @reg_lock: protect hw register access
339 * @mutex: to protect stop_device / start_fw / start_hw
340 * @cmd_in_flight: true when we have a host command in flight
341 * @fw_mon_phys: physical address of the buffer for the firmware monitor
342 * @fw_mon_page: points to the first page of the buffer for the firmware monitor
343 * @fw_mon_size: size of the buffer for the firmware monitor
344 * @msix_entries: array of MSI-X entries
345 * @msix_enabled: true if managed to enable MSI-X
346 * @shared_vec_mask: the type of causes the shared vector handles
347 * (see iwl_shared_irq_flags).
348 * @alloc_vecs: the number of interrupt vectors allocated by the OS
349 * @def_irq: default irq for non rx causes
350 * @fh_init_mask: initial unmasked fh causes
351 * @hw_init_mask: initial unmasked hw causes
352 * @fh_mask: current unmasked fh causes
353 * @hw_mask: current unmasked hw causes
354 */
355struct iwl_trans_pcie {
356 struct iwl_rxq *rxq;
357 struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE];
358 struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE];
359 struct iwl_rb_allocator rba;
360 struct iwl_trans *trans;
361
362 struct net_device napi_dev;
363
364 struct __percpu iwl_tso_hdr_page *tso_hdr_page;
365
366 /* INT ICT Table */
367 __le32 *ict_tbl;
368 dma_addr_t ict_tbl_dma;
369 int ict_index;
370 bool use_ict;
371 bool is_down;
372 struct isr_statistics isr_stats;
373
374 spinlock_t irq_lock;
375 struct mutex mutex;
376 u32 inta_mask;
377 u32 scd_base_addr;
378 struct iwl_dma_ptr scd_bc_tbls;
379 struct iwl_dma_ptr kw;
380
381 struct iwl_txq *txq;
382 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
383 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
384
385 /* PCI bus related data */
386 struct pci_dev *pci_dev;
387 void __iomem *hw_base;
388
389 bool ucode_write_complete;
390 wait_queue_head_t ucode_write_waitq;
391 wait_queue_head_t wait_command_queue;
392 wait_queue_head_t d0i3_waitq;
393
394 u8 page_offs, dev_cmd_offs;
395
396 u8 cmd_queue;
397 u8 cmd_fifo;
398 unsigned int cmd_q_wdg_timeout;
399 u8 n_no_reclaim_cmds;
400 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
401 u8 max_tbs;
402 u16 tfd_size;
403
404 enum iwl_amsdu_size rx_buf_size;
405 bool bc_table_dword;
406 bool scd_set_active;
407 bool sw_csum_tx;
408 u32 rx_page_order;
409
410 /*protect hw register */
411 spinlock_t reg_lock;
412 bool cmd_hold_nic_awake;
413 bool ref_cmd_in_flight;
414
415 dma_addr_t fw_mon_phys;
416 struct page *fw_mon_page;
417 u32 fw_mon_size;
418
419 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
420 bool msix_enabled;
421 u8 shared_vec_mask;
422 u32 alloc_vecs;
423 u32 def_irq;
424 u32 fh_init_mask;
425 u32 hw_init_mask;
426 u32 fh_mask;
427 u32 hw_mask;
428 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
429};
430
431static inline struct iwl_trans_pcie *
432IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
433{
434 return (void *)trans->trans_specific;
435}
436
437static inline struct iwl_trans *
438iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
439{
440 return container_of((void *)trans_pcie, struct iwl_trans,
441 trans_specific);
442}
443
444/*
445 * Convention: trans API functions: iwl_trans_pcie_XXX
446 * Other functions: iwl_pcie_XXX
447 */
448struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
449 const struct pci_device_id *ent,
450 const struct iwl_cfg *cfg);
451void iwl_trans_pcie_free(struct iwl_trans *trans);
452
453/*****************************************************
454* RX
455******************************************************/
456int iwl_pcie_rx_init(struct iwl_trans *trans);
457irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
458irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
459irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
460irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
461int iwl_pcie_rx_stop(struct iwl_trans *trans);
462void iwl_pcie_rx_free(struct iwl_trans *trans);
463
464/*****************************************************
465* ICT - interrupt handling
466******************************************************/
467irqreturn_t iwl_pcie_isr(int irq, void *data);
468int iwl_pcie_alloc_ict(struct iwl_trans *trans);
469void iwl_pcie_free_ict(struct iwl_trans *trans);
470void iwl_pcie_reset_ict(struct iwl_trans *trans);
471void iwl_pcie_disable_ict(struct iwl_trans *trans);
472
473/*****************************************************
474* TX / HCMD
475******************************************************/
476int iwl_pcie_tx_init(struct iwl_trans *trans);
477void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
478int iwl_pcie_tx_stop(struct iwl_trans *trans);
479void iwl_pcie_tx_free(struct iwl_trans *trans);
480void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
481 const struct iwl_trans_txq_scd_cfg *cfg,
482 unsigned int wdg_timeout);
483void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
484 bool configure_scd);
485void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
486 bool shared_mode);
487dma_addr_t iwl_trans_pcie_get_txq_byte_table(struct iwl_trans *trans, int txq);
488void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans,
489 struct iwl_txq *txq);
490int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
491 struct iwl_device_cmd *dev_cmd, int txq_id);
492void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
493int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
494void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
495 struct iwl_rx_cmd_buffer *rxb);
496void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
497 struct sk_buff_head *skbs);
498void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
499
500static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd,
501 u8 idx)
502{
503 if (trans->cfg->use_tfh) {
504 struct iwl_tfh_tfd *tfd = _tfd;
505 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
506
507 return le16_to_cpu(tb->tb_len);
508 } else {
509 struct iwl_tfd *tfd = _tfd;
510 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
511
512 return le16_to_cpu(tb->hi_n_len) >> 4;
513 }
514}
515
516/*****************************************************
517* Error handling
518******************************************************/
519void iwl_pcie_dump_csr(struct iwl_trans *trans);
520
521/*****************************************************
522* Helpers
523******************************************************/
524static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
525{
526 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
527
528 clear_bit(STATUS_INT_ENABLED, &trans->status);
529 if (!trans_pcie->msix_enabled) {
530 /* disable interrupts from uCode/NIC to host */
531 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
532
533 /* acknowledge/clear/reset any interrupts still pending
534 * from uCode or flow handler (Rx/Tx DMA) */
535 iwl_write32(trans, CSR_INT, 0xffffffff);
536 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
537 } else {
538 /* disable all the interrupt we might use */
539 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
540 trans_pcie->fh_init_mask);
541 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
542 trans_pcie->hw_init_mask);
543 }
544 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
545}
546
547static inline void iwl_disable_interrupts(struct iwl_trans *trans)
548{
549 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
550
551 spin_lock(&trans_pcie->irq_lock);
552 _iwl_disable_interrupts(trans);
553 spin_unlock(&trans_pcie->irq_lock);
554}
555
556static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
557{
558 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
559
560 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
561 set_bit(STATUS_INT_ENABLED, &trans->status);
562 if (!trans_pcie->msix_enabled) {
563 trans_pcie->inta_mask = CSR_INI_SET_MASK;
564 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
565 } else {
566 /*
567 * fh/hw_mask keeps all the unmasked causes.
568 * Unlike msi, in msix cause is enabled when it is unset.
569 */
570 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
571 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
572 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
573 ~trans_pcie->fh_mask);
574 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
575 ~trans_pcie->hw_mask);
576 }
577}
578
579static inline void iwl_enable_interrupts(struct iwl_trans *trans)
580{
581 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
582
583 spin_lock(&trans_pcie->irq_lock);
584 _iwl_enable_interrupts(trans);
585 spin_unlock(&trans_pcie->irq_lock);
586}
587static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
588{
589 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
590
591 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
592 trans_pcie->hw_mask = msk;
593}
594
595static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
596{
597 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
598
599 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
600 trans_pcie->fh_mask = msk;
601}
602
603static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
604{
605 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
606
607 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
608 if (!trans_pcie->msix_enabled) {
609 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
610 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
611 } else {
612 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
613 trans_pcie->hw_init_mask);
614 iwl_enable_fh_int_msk_msix(trans,
615 MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
616 }
617}
618
619static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
620{
621 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
622
623 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
624 if (!trans_pcie->msix_enabled) {
625 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
626 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
627 } else {
628 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
629 trans_pcie->fh_init_mask);
630 iwl_enable_hw_int_msk_msix(trans,
631 MSIX_HW_INT_CAUSES_REG_RF_KILL);
632 }
633}
634
635static inline void iwl_wake_queue(struct iwl_trans *trans,
636 struct iwl_txq *txq)
637{
638 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
639
640 if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) {
641 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id);
642 iwl_op_mode_queue_not_full(trans->op_mode, txq->id);
643 }
644}
645
646static inline void iwl_stop_queue(struct iwl_trans *trans,
647 struct iwl_txq *txq)
648{
649 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
650
651 if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) {
652 iwl_op_mode_queue_full(trans->op_mode, txq->id);
653 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id);
654 } else
655 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
656 txq->id);
657}
658
659static inline bool iwl_queue_used(const struct iwl_txq *q, int i)
660{
661 return q->write_ptr >= q->read_ptr ?
662 (i >= q->read_ptr && i < q->write_ptr) :
663 !(i < q->read_ptr && i >= q->write_ptr);
664}
665
666static inline u8 get_cmd_index(struct iwl_txq *q, u32 index)
667{
668 return index & (q->n_window - 1);
669}
670
671static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
672{
673 return !(iwl_read32(trans, CSR_GP_CNTRL) &
674 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
675}
676
677static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
678 u32 reg, u32 mask, u32 value)
679{
680 u32 v;
681
682#ifdef CONFIG_IWLWIFI_DEBUG
683 WARN_ON_ONCE(value & ~mask);
684#endif
685
686 v = iwl_read32(trans, reg);
687 v &= ~mask;
688 v |= value;
689 iwl_write32(trans, reg, v);
690}
691
692static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
693 u32 reg, u32 mask)
694{
695 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
696}
697
698static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
699 u32 reg, u32 mask)
700{
701 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
702}
703
704void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
705
706#ifdef CONFIG_IWLWIFI_DEBUGFS
707int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
708#else
709static inline int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
710{
711 return 0;
712}
713#endif
714
715int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans);
716int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans);
717
718void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable);
719
720#endif /* __iwl_trans_int_pcie_h__ */
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * The full GNU General Public License is included in this distribution in the
23 * file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *
63 *****************************************************************************/
64#ifndef __iwl_trans_int_pcie_h__
65#define __iwl_trans_int_pcie_h__
66
67#include <linux/spinlock.h>
68#include <linux/interrupt.h>
69#include <linux/skbuff.h>
70#include <linux/wait.h>
71#include <linux/pci.h>
72#include <linux/timer.h>
73#include <linux/cpu.h>
74
75#include "iwl-fh.h"
76#include "iwl-csr.h"
77#include "iwl-trans.h"
78#include "iwl-debug.h"
79#include "iwl-io.h"
80#include "iwl-op-mode.h"
81#include "iwl-drv.h"
82
83/* We need 2 entries for the TX command and header, and another one might
84 * be needed for potential data in the SKB's head. The remaining ones can
85 * be used for frags.
86 */
87#define IWL_PCIE_MAX_FRAGS(x) (x->max_tbs - 3)
88
89/*
90 * RX related structures and functions
91 */
92#define RX_NUM_QUEUES 1
93#define RX_POST_REQ_ALLOC 2
94#define RX_CLAIM_REQ_ALLOC 8
95#define RX_PENDING_WATERMARK 16
96#define FIRST_RX_QUEUE 512
97
98struct iwl_host_cmd;
99
100/*This file includes the declaration that are internal to the
101 * trans_pcie layer */
102
103/**
104 * struct iwl_rx_mem_buffer
105 * @page_dma: bus address of rxb page
106 * @page: driver's pointer to the rxb page
107 * @invalid: rxb is in driver ownership - not owned by HW
108 * @vid: index of this rxb in the global table
109 * @offset: indicates which offset of the page (in bytes)
110 * this buffer uses (if multiple RBs fit into one page)
111 */
112struct iwl_rx_mem_buffer {
113 dma_addr_t page_dma;
114 struct page *page;
115 u16 vid;
116 bool invalid;
117 struct list_head list;
118 u32 offset;
119};
120
121/**
122 * struct isr_statistics - interrupt statistics
123 *
124 */
125struct isr_statistics {
126 u32 hw;
127 u32 sw;
128 u32 err_code;
129 u32 sch;
130 u32 alive;
131 u32 rfkill;
132 u32 ctkill;
133 u32 wakeup;
134 u32 rx;
135 u32 tx;
136 u32 unhandled;
137};
138
139/**
140 * struct iwl_rx_transfer_desc - transfer descriptor
141 * @addr: ptr to free buffer start address
142 * @rbid: unique tag of the buffer
143 * @reserved: reserved
144 */
145struct iwl_rx_transfer_desc {
146 __le16 rbid;
147 __le16 reserved[3];
148 __le64 addr;
149} __packed;
150
151#define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0)
152
153/**
154 * struct iwl_rx_completion_desc - completion descriptor
155 * @reserved1: reserved
156 * @rbid: unique tag of the received buffer
157 * @flags: flags (0: fragmented, all others: reserved)
158 * @reserved2: reserved
159 */
160struct iwl_rx_completion_desc {
161 __le32 reserved1;
162 __le16 rbid;
163 u8 flags;
164 u8 reserved2[25];
165} __packed;
166
167/**
168 * struct iwl_rxq - Rx queue
169 * @id: queue index
170 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
171 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
172 * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's
173 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
174 * @ubd: driver's pointer to buffer of used receive buffer descriptors (rbd)
175 * @ubd_dma: physical address of buffer of used receive buffer descriptors (rbd)
176 * @tr_tail: driver's pointer to the transmission ring tail buffer
177 * @tr_tail_dma: physical address of the buffer for the transmission ring tail
178 * @cr_tail: driver's pointer to the completion ring tail buffer
179 * @cr_tail_dma: physical address of the buffer for the completion ring tail
180 * @read: Shared index to newest available Rx buffer
181 * @write: Shared index to oldest written Rx packet
182 * @free_count: Number of pre-allocated buffers in rx_free
183 * @used_count: Number of RBDs handled to allocator to use for allocation
184 * @write_actual:
185 * @rx_free: list of RBDs with allocated RB ready for use
186 * @rx_used: list of RBDs with no RB attached
187 * @need_update: flag to indicate we need to update read/write index
188 * @rb_stts: driver's pointer to receive buffer status
189 * @rb_stts_dma: bus address of receive buffer status
190 * @lock:
191 * @queue: actual rx queue. Not used for multi-rx queue.
192 * @next_rb_is_fragment: indicates that the previous RB that we handled set
193 * the fragmented flag, so the next one is still another fragment
194 *
195 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
196 */
197struct iwl_rxq {
198 int id;
199 void *bd;
200 dma_addr_t bd_dma;
201 union {
202 void *used_bd;
203 __le32 *bd_32;
204 struct iwl_rx_completion_desc *cd;
205 };
206 dma_addr_t used_bd_dma;
207 __le16 *tr_tail;
208 dma_addr_t tr_tail_dma;
209 __le16 *cr_tail;
210 dma_addr_t cr_tail_dma;
211 u32 read;
212 u32 write;
213 u32 free_count;
214 u32 used_count;
215 u32 write_actual;
216 u32 queue_size;
217 struct list_head rx_free;
218 struct list_head rx_used;
219 bool need_update, next_rb_is_fragment;
220 void *rb_stts;
221 dma_addr_t rb_stts_dma;
222 spinlock_t lock;
223 struct napi_struct napi;
224 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
225};
226
227/**
228 * struct iwl_rb_allocator - Rx allocator
229 * @req_pending: number of requests the allcator had not processed yet
230 * @req_ready: number of requests honored and ready for claiming
231 * @rbd_allocated: RBDs with pages allocated and ready to be handled to
232 * the queue. This is a list of &struct iwl_rx_mem_buffer
233 * @rbd_empty: RBDs with no page attached for allocator use. This is a list
234 * of &struct iwl_rx_mem_buffer
235 * @lock: protects the rbd_allocated and rbd_empty lists
236 * @alloc_wq: work queue for background calls
237 * @rx_alloc: work struct for background calls
238 */
239struct iwl_rb_allocator {
240 atomic_t req_pending;
241 atomic_t req_ready;
242 struct list_head rbd_allocated;
243 struct list_head rbd_empty;
244 spinlock_t lock;
245 struct workqueue_struct *alloc_wq;
246 struct work_struct rx_alloc;
247};
248
249/**
250 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
251 * @index -- current index
252 */
253static inline int iwl_queue_inc_wrap(struct iwl_trans *trans, int index)
254{
255 return ++index &
256 (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
257}
258
259/**
260 * iwl_get_closed_rb_stts - get closed rb stts from different structs
261 * @rxq - the rxq to get the rb stts from
262 */
263static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
264 struct iwl_rxq *rxq)
265{
266 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
267 __le16 *rb_stts = rxq->rb_stts;
268
269 return READ_ONCE(*rb_stts);
270 } else {
271 struct iwl_rb_status *rb_stts = rxq->rb_stts;
272
273 return READ_ONCE(rb_stts->closed_rb_num);
274 }
275}
276
277/**
278 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
279 * @index -- current index
280 */
281static inline int iwl_queue_dec_wrap(struct iwl_trans *trans, int index)
282{
283 return --index &
284 (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
285}
286
287static inline dma_addr_t
288iwl_pcie_get_first_tb_dma(struct iwl_txq *txq, int idx)
289{
290 return txq->first_tb_dma +
291 sizeof(struct iwl_pcie_first_tb_buf) * idx;
292}
293
294struct iwl_tso_hdr_page {
295 struct page *page;
296 u8 *pos;
297};
298
299#ifdef CONFIG_IWLWIFI_DEBUGFS
300/**
301 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
302 * debugfs file
303 *
304 * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed.
305 * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open.
306 * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is
307 * set the file can no longer be used.
308 */
309enum iwl_fw_mon_dbgfs_state {
310 IWL_FW_MON_DBGFS_STATE_CLOSED,
311 IWL_FW_MON_DBGFS_STATE_OPEN,
312 IWL_FW_MON_DBGFS_STATE_DISABLED,
313};
314#endif
315
316/**
317 * enum iwl_shared_irq_flags - level of sharing for irq
318 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
319 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
320 */
321enum iwl_shared_irq_flags {
322 IWL_SHARED_IRQ_NON_RX = BIT(0),
323 IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
324};
325
326/**
327 * enum iwl_image_response_code - image response values
328 * @IWL_IMAGE_RESP_DEF: the default value of the register
329 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully
330 * @IWL_IMAGE_RESP_FAIL: iml reading failed
331 */
332enum iwl_image_response_code {
333 IWL_IMAGE_RESP_DEF = 0,
334 IWL_IMAGE_RESP_SUCCESS = 1,
335 IWL_IMAGE_RESP_FAIL = 2,
336};
337
338/**
339 * struct cont_rec: continuous recording data structure
340 * @prev_wr_ptr: the last address that was read in monitor_data
341 * debugfs file
342 * @prev_wrap_cnt: the wrap count that was used during the last read in
343 * monitor_data debugfs file
344 * @state: the state of monitor_data debugfs file as described
345 * in &iwl_fw_mon_dbgfs_state enum
346 * @mutex: locked while reading from monitor_data debugfs file
347 */
348#ifdef CONFIG_IWLWIFI_DEBUGFS
349struct cont_rec {
350 u32 prev_wr_ptr;
351 u32 prev_wrap_cnt;
352 u8 state;
353 /* Used to sync monitor_data debugfs file with driver unload flow */
354 struct mutex mutex;
355};
356#endif
357
358/**
359 * struct iwl_trans_pcie - PCIe transport specific data
360 * @rxq: all the RX queue data
361 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
362 * @global_table: table mapping received VID from hw to rxb
363 * @rba: allocator for RX replenishing
364 * @ctxt_info: context information for FW self init
365 * @ctxt_info_gen3: context information for gen3 devices
366 * @prph_info: prph info for self init
367 * @prph_scratch: prph scratch for self init
368 * @ctxt_info_dma_addr: dma addr of context information
369 * @prph_info_dma_addr: dma addr of prph info
370 * @prph_scratch_dma_addr: dma addr of prph scratch
371 * @ctxt_info_dma_addr: dma addr of context information
372 * @init_dram: DRAM data of firmware image (including paging).
373 * Context information addresses will be taken from here.
374 * This is driver's local copy for keeping track of size and
375 * count for allocating and freeing the memory.
376 * @trans: pointer to the generic transport area
377 * @scd_base_addr: scheduler sram base address in SRAM
378 * @scd_bc_tbls: pointer to the byte count table of the scheduler
379 * @kw: keep warm address
380 * @pci_dev: basic pci-network driver stuff
381 * @hw_base: pci hardware address support
382 * @ucode_write_complete: indicates that the ucode has been copied.
383 * @ucode_write_waitq: wait queue for uCode load
384 * @cmd_queue - command queue number
385 * @def_rx_queue - default rx queue number
386 * @rx_buf_size: Rx buffer size
387 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
388 * @scd_set_active: should the transport configure the SCD for HCMD queue
389 * @sw_csum_tx: if true, then the transport will compute the csum of the TXed
390 * frame.
391 * @rx_page_order: page order for receive buffer size
392 * @rx_buf_bytes: RX buffer (RB) size in bytes
393 * @reg_lock: protect hw register access
394 * @mutex: to protect stop_device / start_fw / start_hw
395 * @cmd_in_flight: true when we have a host command in flight
396#ifdef CONFIG_IWLWIFI_DEBUGFS
397 * @fw_mon_data: fw continuous recording data
398#endif
399 * @msix_entries: array of MSI-X entries
400 * @msix_enabled: true if managed to enable MSI-X
401 * @shared_vec_mask: the type of causes the shared vector handles
402 * (see iwl_shared_irq_flags).
403 * @alloc_vecs: the number of interrupt vectors allocated by the OS
404 * @def_irq: default irq for non rx causes
405 * @fh_init_mask: initial unmasked fh causes
406 * @hw_init_mask: initial unmasked hw causes
407 * @fh_mask: current unmasked fh causes
408 * @hw_mask: current unmasked hw causes
409 * @in_rescan: true if we have triggered a device rescan
410 * @base_rb_stts: base virtual address of receive buffer status for all queues
411 * @base_rb_stts_dma: base physical address of receive buffer status
412 * @supported_dma_mask: DMA mask to validate the actual address against,
413 * will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device
414 * @alloc_page_lock: spinlock for the page allocator
415 * @alloc_page: allocated page to still use parts of
416 * @alloc_page_used: how much of the allocated page was already used (bytes)
417 */
418struct iwl_trans_pcie {
419 struct iwl_rxq *rxq;
420 struct iwl_rx_mem_buffer *rx_pool;
421 struct iwl_rx_mem_buffer **global_table;
422 struct iwl_rb_allocator rba;
423 union {
424 struct iwl_context_info *ctxt_info;
425 struct iwl_context_info_gen3 *ctxt_info_gen3;
426 };
427 struct iwl_prph_info *prph_info;
428 struct iwl_prph_scratch *prph_scratch;
429 dma_addr_t ctxt_info_dma_addr;
430 dma_addr_t prph_info_dma_addr;
431 dma_addr_t prph_scratch_dma_addr;
432 dma_addr_t iml_dma_addr;
433 struct iwl_trans *trans;
434
435 struct net_device napi_dev;
436
437 struct __percpu iwl_tso_hdr_page *tso_hdr_page;
438
439 /* INT ICT Table */
440 __le32 *ict_tbl;
441 dma_addr_t ict_tbl_dma;
442 int ict_index;
443 bool use_ict;
444 bool is_down, opmode_down;
445 s8 debug_rfkill;
446 struct isr_statistics isr_stats;
447
448 spinlock_t irq_lock;
449 struct mutex mutex;
450 u32 inta_mask;
451 u32 scd_base_addr;
452 struct iwl_dma_ptr scd_bc_tbls;
453 struct iwl_dma_ptr kw;
454 struct dma_pool *bc_pool;
455
456 struct iwl_txq *txq_memory;
457
458 /* PCI bus related data */
459 struct pci_dev *pci_dev;
460 void __iomem *hw_base;
461
462 bool ucode_write_complete;
463 bool sx_complete;
464 wait_queue_head_t ucode_write_waitq;
465 wait_queue_head_t wait_command_queue;
466 wait_queue_head_t sx_waitq;
467
468 u8 page_offs, dev_cmd_offs;
469
470 u8 def_rx_queue;
471 u8 n_no_reclaim_cmds;
472 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
473 u8 max_tbs;
474 u16 tfd_size;
475 u16 num_rx_bufs;
476
477 enum iwl_amsdu_size rx_buf_size;
478 bool bc_table_dword;
479 bool scd_set_active;
480 bool sw_csum_tx;
481 bool pcie_dbg_dumped_once;
482 u32 rx_page_order;
483 u32 rx_buf_bytes;
484 u32 supported_dma_mask;
485
486 /* allocator lock for the two values below */
487 spinlock_t alloc_page_lock;
488 struct page *alloc_page;
489 u32 alloc_page_used;
490
491 /*protect hw register */
492 spinlock_t reg_lock;
493 bool cmd_hold_nic_awake;
494
495#ifdef CONFIG_IWLWIFI_DEBUGFS
496 struct cont_rec fw_mon_data;
497#endif
498
499 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
500 bool msix_enabled;
501 u8 shared_vec_mask;
502 u32 alloc_vecs;
503 u32 def_irq;
504 u32 fh_init_mask;
505 u32 hw_init_mask;
506 u32 fh_mask;
507 u32 hw_mask;
508 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
509 u16 tx_cmd_queue_size;
510 bool in_rescan;
511
512 void *base_rb_stts;
513 dma_addr_t base_rb_stts_dma;
514};
515
516static inline struct iwl_trans_pcie *
517IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
518{
519 return (void *)trans->trans_specific;
520}
521
522static inline void iwl_pcie_clear_irq(struct iwl_trans *trans,
523 struct msix_entry *entry)
524{
525 /*
526 * Before sending the interrupt the HW disables it to prevent
527 * a nested interrupt. This is done by writing 1 to the corresponding
528 * bit in the mask register. After handling the interrupt, it should be
529 * re-enabled by clearing this bit. This register is defined as
530 * write 1 clear (W1C) register, meaning that it's being clear
531 * by writing 1 to the bit.
532 */
533 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry));
534}
535
536static inline struct iwl_trans *
537iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
538{
539 return container_of((void *)trans_pcie, struct iwl_trans,
540 trans_specific);
541}
542
543/*
544 * Convention: trans API functions: iwl_trans_pcie_XXX
545 * Other functions: iwl_pcie_XXX
546 */
547struct iwl_trans
548*iwl_trans_pcie_alloc(struct pci_dev *pdev,
549 const struct pci_device_id *ent,
550 const struct iwl_cfg_trans_params *cfg_trans);
551void iwl_trans_pcie_free(struct iwl_trans *trans);
552
553/*****************************************************
554* RX
555******************************************************/
556int iwl_pcie_rx_init(struct iwl_trans *trans);
557int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
558irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
559irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
560irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
561irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
562int iwl_pcie_rx_stop(struct iwl_trans *trans);
563void iwl_pcie_rx_free(struct iwl_trans *trans);
564void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
565void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
566int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget);
567void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
568 struct iwl_rxq *rxq);
569
570/*****************************************************
571* ICT - interrupt handling
572******************************************************/
573irqreturn_t iwl_pcie_isr(int irq, void *data);
574int iwl_pcie_alloc_ict(struct iwl_trans *trans);
575void iwl_pcie_free_ict(struct iwl_trans *trans);
576void iwl_pcie_reset_ict(struct iwl_trans *trans);
577void iwl_pcie_disable_ict(struct iwl_trans *trans);
578
579/*****************************************************
580* TX / HCMD
581******************************************************/
582/*
583 * We need this inline in case dma_addr_t is only 32-bits - since the
584 * hardware is always 64-bit, the issue can still occur in that case,
585 * so use u64 for 'phys' here to force the addition in 64-bit.
586 */
587static inline bool iwl_pcie_crosses_4g_boundary(u64 phys, u16 len)
588{
589 return upper_32_bits(phys) != upper_32_bits(phys + len);
590}
591
592int iwl_pcie_tx_init(struct iwl_trans *trans);
593int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id,
594 int queue_size);
595void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
596int iwl_pcie_tx_stop(struct iwl_trans *trans);
597void iwl_pcie_tx_free(struct iwl_trans *trans);
598bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
599 const struct iwl_trans_txq_scd_cfg *cfg,
600 unsigned int wdg_timeout);
601void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
602 bool configure_scd);
603void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
604 bool shared_mode);
605void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans,
606 struct iwl_txq *txq);
607int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
608 struct iwl_device_tx_cmd *dev_cmd, int txq_id);
609void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
610int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
611void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans,
612 struct iwl_txq *txq);
613void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
614 struct iwl_rx_cmd_buffer *rxb);
615void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
616 struct sk_buff_head *skbs);
617void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr);
618void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
619
620static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd,
621 u8 idx)
622{
623 if (trans->trans_cfg->use_tfh) {
624 struct iwl_tfh_tfd *tfd = _tfd;
625 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
626
627 return le16_to_cpu(tb->tb_len);
628 } else {
629 struct iwl_tfd *tfd = _tfd;
630 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
631
632 return le16_to_cpu(tb->hi_n_len) >> 4;
633 }
634}
635
636/*****************************************************
637* Error handling
638******************************************************/
639void iwl_pcie_dump_csr(struct iwl_trans *trans);
640
641/*****************************************************
642* Helpers
643******************************************************/
644static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
645{
646 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
647
648 clear_bit(STATUS_INT_ENABLED, &trans->status);
649 if (!trans_pcie->msix_enabled) {
650 /* disable interrupts from uCode/NIC to host */
651 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
652
653 /* acknowledge/clear/reset any interrupts still pending
654 * from uCode or flow handler (Rx/Tx DMA) */
655 iwl_write32(trans, CSR_INT, 0xffffffff);
656 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
657 } else {
658 /* disable all the interrupt we might use */
659 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
660 trans_pcie->fh_init_mask);
661 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
662 trans_pcie->hw_init_mask);
663 }
664 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
665}
666
667#define IWL_NUM_OF_COMPLETION_RINGS 31
668#define IWL_NUM_OF_TRANSFER_RINGS 527
669
670static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
671 int start)
672{
673 int i = 0;
674
675 while (start < fw->num_sec &&
676 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
677 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
678 start++;
679 i++;
680 }
681
682 return i;
683}
684
685static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
686{
687 struct iwl_self_init_dram *dram = &trans->init_dram;
688 int i;
689
690 if (!dram->fw) {
691 WARN_ON(dram->fw_cnt);
692 return;
693 }
694
695 for (i = 0; i < dram->fw_cnt; i++)
696 dma_free_coherent(trans->dev, dram->fw[i].size,
697 dram->fw[i].block, dram->fw[i].physical);
698
699 kfree(dram->fw);
700 dram->fw_cnt = 0;
701 dram->fw = NULL;
702}
703
704static inline void iwl_disable_interrupts(struct iwl_trans *trans)
705{
706 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
707
708 spin_lock(&trans_pcie->irq_lock);
709 _iwl_disable_interrupts(trans);
710 spin_unlock(&trans_pcie->irq_lock);
711}
712
713static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
714{
715 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
716
717 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
718 set_bit(STATUS_INT_ENABLED, &trans->status);
719 if (!trans_pcie->msix_enabled) {
720 trans_pcie->inta_mask = CSR_INI_SET_MASK;
721 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
722 } else {
723 /*
724 * fh/hw_mask keeps all the unmasked causes.
725 * Unlike msi, in msix cause is enabled when it is unset.
726 */
727 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
728 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
729 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
730 ~trans_pcie->fh_mask);
731 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
732 ~trans_pcie->hw_mask);
733 }
734}
735
736static inline void iwl_enable_interrupts(struct iwl_trans *trans)
737{
738 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
739
740 spin_lock(&trans_pcie->irq_lock);
741 _iwl_enable_interrupts(trans);
742 spin_unlock(&trans_pcie->irq_lock);
743}
744static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
745{
746 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
747
748 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
749 trans_pcie->hw_mask = msk;
750}
751
752static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
753{
754 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
755
756 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
757 trans_pcie->fh_mask = msk;
758}
759
760static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
761{
762 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
763
764 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
765 if (!trans_pcie->msix_enabled) {
766 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
767 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
768 } else {
769 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
770 trans_pcie->hw_init_mask);
771 iwl_enable_fh_int_msk_msix(trans,
772 MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
773 }
774}
775
776static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans)
777{
778 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
779
780 IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n");
781
782 if (!trans_pcie->msix_enabled) {
783 /*
784 * When we'll receive the ALIVE interrupt, the ISR will call
785 * iwl_enable_fw_load_int_ctx_info again to set the ALIVE
786 * interrupt (which is not really needed anymore) but also the
787 * RX interrupt which will allow us to receive the ALIVE
788 * notification (which is Rx) and continue the flow.
789 */
790 trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX;
791 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
792 } else {
793 iwl_enable_hw_int_msk_msix(trans,
794 MSIX_HW_INT_CAUSES_REG_ALIVE);
795 /*
796 * Leave all the FH causes enabled to get the ALIVE
797 * notification.
798 */
799 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask);
800 }
801}
802
803static inline u16 iwl_pcie_get_cmd_index(const struct iwl_txq *q, u32 index)
804{
805 return index & (q->n_window - 1);
806}
807
808static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans,
809 struct iwl_txq *txq, int idx)
810{
811 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
812
813 if (trans->trans_cfg->use_tfh)
814 idx = iwl_pcie_get_cmd_index(txq, idx);
815
816 return txq->tfds + trans_pcie->tfd_size * idx;
817}
818
819static inline const char *queue_name(struct device *dev,
820 struct iwl_trans_pcie *trans_p, int i)
821{
822 if (trans_p->shared_vec_mask) {
823 int vec = trans_p->shared_vec_mask &
824 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
825
826 if (i == 0)
827 return DRV_NAME ": shared IRQ";
828
829 return devm_kasprintf(dev, GFP_KERNEL,
830 DRV_NAME ": queue %d", i + vec);
831 }
832 if (i == 0)
833 return DRV_NAME ": default queue";
834
835 if (i == trans_p->alloc_vecs - 1)
836 return DRV_NAME ": exception";
837
838 return devm_kasprintf(dev, GFP_KERNEL,
839 DRV_NAME ": queue %d", i);
840}
841
842static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
843{
844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
845
846 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
847 if (!trans_pcie->msix_enabled) {
848 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
849 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
850 } else {
851 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
852 trans_pcie->fh_init_mask);
853 iwl_enable_hw_int_msk_msix(trans,
854 MSIX_HW_INT_CAUSES_REG_RF_KILL);
855 }
856
857 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) {
858 /*
859 * On 9000-series devices this bit isn't enabled by default, so
860 * when we power down the device we need set the bit to allow it
861 * to wake up the PCI-E bus for RF-kill interrupts.
862 */
863 iwl_set_bit(trans, CSR_GP_CNTRL,
864 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
865 }
866}
867
868void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans);
869
870static inline void iwl_wake_queue(struct iwl_trans *trans,
871 struct iwl_txq *txq)
872{
873 if (test_and_clear_bit(txq->id, trans->txqs.queue_stopped)) {
874 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id);
875 iwl_op_mode_queue_not_full(trans->op_mode, txq->id);
876 }
877}
878
879static inline void iwl_stop_queue(struct iwl_trans *trans,
880 struct iwl_txq *txq)
881{
882 if (!test_and_set_bit(txq->id, trans->txqs.queue_stopped)) {
883 iwl_op_mode_queue_full(trans->op_mode, txq->id);
884 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id);
885 } else
886 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
887 txq->id);
888}
889
890static inline bool iwl_queue_used(const struct iwl_txq *q, int i)
891{
892 int index = iwl_pcie_get_cmd_index(q, i);
893 int r = iwl_pcie_get_cmd_index(q, q->read_ptr);
894 int w = iwl_pcie_get_cmd_index(q, q->write_ptr);
895
896 return w >= r ?
897 (index >= r && index < w) :
898 !(index < r && index >= w);
899}
900
901static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
902{
903 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
904
905 lockdep_assert_held(&trans_pcie->mutex);
906
907 if (trans_pcie->debug_rfkill == 1)
908 return true;
909
910 return !(iwl_read32(trans, CSR_GP_CNTRL) &
911 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
912}
913
914static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
915 u32 reg, u32 mask, u32 value)
916{
917 u32 v;
918
919#ifdef CONFIG_IWLWIFI_DEBUG
920 WARN_ON_ONCE(value & ~mask);
921#endif
922
923 v = iwl_read32(trans, reg);
924 v &= ~mask;
925 v |= value;
926 iwl_write32(trans, reg, v);
927}
928
929static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
930 u32 reg, u32 mask)
931{
932 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
933}
934
935static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
936 u32 reg, u32 mask)
937{
938 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
939}
940
941static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
942{
943 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans));
944}
945
946void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
947void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
948void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans);
949
950#ifdef CONFIG_IWLWIFI_DEBUGFS
951void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
952#else
953static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { }
954#endif
955
956void iwl_pcie_rx_allocator_work(struct work_struct *data);
957
958/* common functions that are used by gen2 transport */
959int iwl_pcie_gen2_apm_init(struct iwl_trans *trans);
960void iwl_pcie_apm_config(struct iwl_trans *trans);
961int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
962void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
963bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
964void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
965 bool was_in_rfkill);
966void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq);
967int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q);
968void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
969void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
970int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
971 int slots_num, bool cmd_queue);
972int iwl_pcie_txq_alloc(struct iwl_trans *trans,
973 struct iwl_txq *txq, int slots_num, bool cmd_queue);
974int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
975 struct iwl_dma_ptr *ptr, size_t size);
976void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
977void iwl_pcie_apply_destination(struct iwl_trans *trans);
978void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
979 struct sk_buff *skb);
980#ifdef CONFIG_INET
981struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len,
982 struct sk_buff *skb);
983#endif
984
985/* common functions that are used by gen3 transport */
986void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
987
988/* transport gen 2 exported functions */
989int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
990 const struct fw_img *fw, bool run_in_rfkill);
991void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr);
992void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans,
993 struct iwl_txq *txq);
994int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans,
995 struct iwl_txq **intxq, int size,
996 unsigned int timeout);
997int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans,
998 struct iwl_txq *txq,
999 struct iwl_host_cmd *hcmd);
1000int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans,
1001 __le16 flags, u8 sta_id, u8 tid,
1002 int cmd_id, int size,
1003 unsigned int timeout);
1004void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue);
1005int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
1006 struct iwl_device_tx_cmd *dev_cmd, int txq_id);
1007int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
1008 struct iwl_host_cmd *cmd);
1009void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
1010void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
1011void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id);
1012void iwl_pcie_gen2_tx_free(struct iwl_trans *trans);
1013void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans);
1014void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1015 bool test, bool reset);
1016#endif /* __iwl_trans_int_pcie_h__ */