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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Broadcast Assist Unit definitions
7 *
8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef _ASM_X86_UV_UV_BAU_H
12#define _ASM_X86_UV_UV_BAU_H
13
14#include <linux/bitmap.h>
15#define BITSPERBYTE 8
16
17/*
18 * Broadcast Assist Unit messaging structures
19 *
20 * Selective Broadcast activations are induced by software action
21 * specifying a particular 8-descriptor "set" via a 6-bit index written
22 * to an MMR.
23 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
24 * each 6-bit index value. These descriptor sets are mapped in sequence
25 * starting with set 0 located at the address specified in the
26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
28 *
29 * We will use one set for sending BAU messages from each of the
30 * cpu's on the uvhub.
31 *
32 * TLB shootdown will use the first of the 8 descriptors of each set.
33 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
34 */
35
36#define MAX_CPUS_PER_UVHUB 128
37#define MAX_CPUS_PER_SOCKET 64
38#define ADP_SZ 64 /* hardware-provided max. */
39#define UV_CPUS_PER_AS 32 /* hardware-provided max. */
40#define ITEMS_PER_DESC 8
41/* the 'throttle' to prevent the hardware stay-busy bug */
42#define MAX_BAU_CONCURRENT 3
43#define UV_ACT_STATUS_MASK 0x3
44#define UV_ACT_STATUS_SIZE 2
45#define UV_DISTRIBUTION_SIZE 256
46#define UV_SW_ACK_NPENDING 8
47#define UV1_NET_ENDPOINT_INTD 0x38
48#define UV2_NET_ENDPOINT_INTD 0x28
49#define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51#define UV_DESC_PSHIFT 49
52#define UV_PAYLOADQ_GNODE_SHIFT 49
53#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54#define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55#define UV_BAU_TUNABLES_DIR "sgi_uv"
56#define UV_BAU_TUNABLES_FILE "bau_tunables"
57#define WHITESPACE " \t\n"
58#define cpubit_isset(cpu, bau_local_cpumask) \
59 test_bit((cpu), (bau_local_cpumask).bits)
60
61/* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */
62/*
63 * UV2: Bit 19 selects between
64 * (0): 10 microsecond timebase and
65 * (1): 80 microseconds
66 * we're using 560us, similar to UV1: 65 units of 10us
67 */
68#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
69#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
70
71#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
72 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
73 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
74/* assuming UV3 is the same */
75
76#define BAU_MISC_CONTROL_MULT_MASK 3
77
78#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
79/* [30:28] URGENCY_7 an index into a table of times */
80#define BAU_URGENCY_7_SHIFT 28
81#define BAU_URGENCY_7_MASK 7
82
83#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
84/* [45:40] BAU - BAU transaction timeout select - a multiplier */
85#define BAU_TRANS_SHIFT 40
86#define BAU_TRANS_MASK 0x3f
87
88/*
89 * shorten some awkward names
90 */
91#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
92#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
93#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
94#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
95#define PREFETCH_HINT_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT
96#define SB_STATUS_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
97#define write_gmmr uv_write_global_mmr64
98#define write_lmmr uv_write_local_mmr
99#define read_lmmr uv_read_local_mmr
100#define read_gmmr uv_read_global_mmr64
101
102/*
103 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
104 */
105#define DS_IDLE 0
106#define DS_ACTIVE 1
107#define DS_DESTINATION_TIMEOUT 2
108#define DS_SOURCE_TIMEOUT 3
109/*
110 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
111 * values 1 and 3 will not occur
112 * Decoded meaning ERROR BUSY AUX ERR
113 * ------------------------------- ---- ----- -------
114 * IDLE 0 0 0
115 * BUSY (active) 0 1 0
116 * SW Ack Timeout (destination) 1 0 0
117 * SW Ack INTD rejected (strong NACK) 1 0 1
118 * Source Side Time Out Detected 1 1 0
119 * Destination Side PUT Failed 1 1 1
120 */
121#define UV2H_DESC_IDLE 0
122#define UV2H_DESC_BUSY 2
123#define UV2H_DESC_DEST_TIMEOUT 4
124#define UV2H_DESC_DEST_STRONG_NACK 5
125#define UV2H_DESC_SOURCE_TIMEOUT 6
126#define UV2H_DESC_DEST_PUT_ERR 7
127
128/*
129 * delay for 'plugged' timeout retries, in microseconds
130 */
131#define PLUGGED_DELAY 10
132
133/*
134 * threshholds at which to use IPI to free resources
135 */
136/* after this # consecutive 'plugged' timeouts, use IPI to release resources */
137#define PLUGSB4RESET 100
138/* after this many consecutive timeouts, use IPI to release resources */
139#define TIMEOUTSB4RESET 1
140/* at this number uses of IPI to release resources, giveup the request */
141#define IPI_RESET_LIMIT 1
142/* after this # consecutive successes, bump up the throttle if it was lowered */
143#define COMPLETE_THRESHOLD 5
144/* after this # of giveups (fall back to kernel IPI's) disable the use of
145 the BAU for a period of time */
146#define GIVEUP_LIMIT 100
147
148#define UV_LB_SUBNODEID 0x10
149
150/* these two are the same for UV1 and UV2: */
151#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
152#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
153/* 4 bits of software ack period */
154#define UV2_ACK_MASK 0x7UL
155#define UV2_ACK_UNITS_SHFT 3
156#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
157
158/*
159 * number of entries in the destination side payload queue
160 */
161#define DEST_Q_SIZE 20
162/*
163 * number of destination side software ack resources
164 */
165#define DEST_NUM_RESOURCES 8
166/*
167 * completion statuses for sending a TLB flush message
168 */
169#define FLUSH_RETRY_PLUGGED 1
170#define FLUSH_RETRY_TIMEOUT 2
171#define FLUSH_GIVEUP 3
172#define FLUSH_COMPLETE 4
173
174/*
175 * tuning the action when the numalink network is extremely delayed
176 */
177#define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in
178 microseconds */
179#define CONGESTED_REPS 10 /* long delays averaged over
180 this many broadcasts */
181#define DISABLED_PERIOD 10 /* time for the bau to be
182 disabled, in seconds */
183/* see msg_type: */
184#define MSG_NOOP 0
185#define MSG_REGULAR 1
186#define MSG_RETRY 2
187
188/*
189 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
190 * If the 'multilevel' flag in the header portion of the descriptor
191 * has been set to 0, then endpoint multi-unicast mode is selected.
192 * The distribution specification (32 bytes) is interpreted as a 256-bit
193 * distribution vector. Adjacent bits correspond to consecutive even numbered
194 * nodeIDs. The result of adding the index of a given bit to the 15-bit
195 * 'base_dest_nasid' field of the header corresponds to the
196 * destination nodeID associated with that specified bit.
197 */
198struct pnmask {
199 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
200};
201
202/*
203 * mask of cpu's on a uvhub
204 * (during initialization we need to check that unsigned long has
205 * enough bits for max. cpu's per uvhub)
206 */
207struct bau_local_cpumask {
208 unsigned long bits;
209};
210
211/*
212 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
213 * only 12 bytes (96 bits) of the payload area are usable.
214 * An additional 3 bytes (bits 27:4) of the header address are carried
215 * to the next bytes of the destination payload queue.
216 * And an additional 2 bytes of the header Suppl_A field are also
217 * carried to the destination payload queue.
218 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
219 * of the destination payload queue, which is written by the hardware
220 * with the s/w ack resource bit vector.
221 * [ effective message contents (16 bytes (128 bits) maximum), not counting
222 * the s/w ack bit vector ]
223 */
224
225/*
226 * The payload is software-defined for INTD transactions
227 */
228struct bau_msg_payload {
229 unsigned long address; /* signifies a page or all
230 TLB's of the cpu */
231 /* 64 bits */
232 unsigned short sending_cpu; /* filled in by sender */
233 /* 16 bits */
234 unsigned short acknowledge_count; /* filled in by destination */
235 /* 16 bits */
236 unsigned int reserved1:32; /* not usable */
237};
238
239
240/*
241 * UV1 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
242 * see table 4.2.3.0.1 in broacast_assist spec.
243 */
244struct uv1_bau_msg_header {
245 unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
246 /* bits 5:0 */
247 unsigned int base_dest_nasid:15; /* nasid of the first bit */
248 /* bits 20:6 */ /* in uvhub map */
249 unsigned int command:8; /* message type */
250 /* bits 28:21 */
251 /* 0x38: SN3net EndPoint Message */
252 unsigned int rsvd_1:3; /* must be zero */
253 /* bits 31:29 */
254 /* int will align on 32 bits */
255 unsigned int rsvd_2:9; /* must be zero */
256 /* bits 40:32 */
257 /* Suppl_A is 56-41 */
258 unsigned int sequence:16; /* message sequence number */
259 /* bits 56:41 */ /* becomes bytes 16-17 of msg */
260 /* Address field (96:57) is
261 never used as an address
262 (these are address bits
263 42:3) */
264
265 unsigned int rsvd_3:1; /* must be zero */
266 /* bit 57 */
267 /* address bits 27:4 are payload */
268 /* these next 24 (58-81) bits become bytes 12-14 of msg */
269 /* bits 65:58 land in byte 12 */
270 unsigned int replied_to:1; /* sent as 0 by the source to
271 byte 12 */
272 /* bit 58 */
273 unsigned int msg_type:3; /* software type of the
274 message */
275 /* bits 61:59 */
276 unsigned int canceled:1; /* message canceled, resource
277 is to be freed*/
278 /* bit 62 */
279 unsigned int payload_1a:1; /* not currently used */
280 /* bit 63 */
281 unsigned int payload_1b:2; /* not currently used */
282 /* bits 65:64 */
283
284 /* bits 73:66 land in byte 13 */
285 unsigned int payload_1ca:6; /* not currently used */
286 /* bits 71:66 */
287 unsigned int payload_1c:2; /* not currently used */
288 /* bits 73:72 */
289
290 /* bits 81:74 land in byte 14 */
291 unsigned int payload_1d:6; /* not currently used */
292 /* bits 79:74 */
293 unsigned int payload_1e:2; /* not currently used */
294 /* bits 81:80 */
295
296 unsigned int rsvd_4:7; /* must be zero */
297 /* bits 88:82 */
298 unsigned int swack_flag:1; /* software acknowledge flag */
299 /* bit 89 */
300 /* INTD trasactions at
301 destination are to wait for
302 software acknowledge */
303 unsigned int rsvd_5:6; /* must be zero */
304 /* bits 95:90 */
305 unsigned int rsvd_6:5; /* must be zero */
306 /* bits 100:96 */
307 unsigned int int_both:1; /* if 1, interrupt both sockets
308 on the uvhub */
309 /* bit 101*/
310 unsigned int fairness:3; /* usually zero */
311 /* bits 104:102 */
312 unsigned int multilevel:1; /* multi-level multicast
313 format */
314 /* bit 105 */
315 /* 0 for TLB: endpoint multi-unicast messages */
316 unsigned int chaining:1; /* next descriptor is part of
317 this activation*/
318 /* bit 106 */
319 unsigned int rsvd_7:21; /* must be zero */
320 /* bits 127:107 */
321};
322
323/*
324 * UV2 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
325 * see figure 9-2 of harp_sys.pdf
326 * assuming UV3 is the same
327 */
328struct uv2_3_bau_msg_header {
329 unsigned int base_dest_nasid:15; /* nasid of the first bit */
330 /* bits 14:0 */ /* in uvhub map */
331 unsigned int dest_subnodeid:5; /* must be 0x10, for the LB */
332 /* bits 19:15 */
333 unsigned int rsvd_1:1; /* must be zero */
334 /* bit 20 */
335 /* Address bits 59:21 */
336 /* bits 25:2 of address (44:21) are payload */
337 /* these next 24 bits become bytes 12-14 of msg */
338 /* bits 28:21 land in byte 12 */
339 unsigned int replied_to:1; /* sent as 0 by the source to
340 byte 12 */
341 /* bit 21 */
342 unsigned int msg_type:3; /* software type of the
343 message */
344 /* bits 24:22 */
345 unsigned int canceled:1; /* message canceled, resource
346 is to be freed*/
347 /* bit 25 */
348 unsigned int payload_1:3; /* not currently used */
349 /* bits 28:26 */
350
351 /* bits 36:29 land in byte 13 */
352 unsigned int payload_2a:3; /* not currently used */
353 unsigned int payload_2b:5; /* not currently used */
354 /* bits 36:29 */
355
356 /* bits 44:37 land in byte 14 */
357 unsigned int payload_3:8; /* not currently used */
358 /* bits 44:37 */
359
360 unsigned int rsvd_2:7; /* reserved */
361 /* bits 51:45 */
362 unsigned int swack_flag:1; /* software acknowledge flag */
363 /* bit 52 */
364 unsigned int rsvd_3a:3; /* must be zero */
365 unsigned int rsvd_3b:8; /* must be zero */
366 unsigned int rsvd_3c:8; /* must be zero */
367 unsigned int rsvd_3d:3; /* must be zero */
368 /* bits 74:53 */
369 unsigned int fairness:3; /* usually zero */
370 /* bits 77:75 */
371
372 unsigned int sequence:16; /* message sequence number */
373 /* bits 93:78 Suppl_A */
374 unsigned int chaining:1; /* next descriptor is part of
375 this activation*/
376 /* bit 94 */
377 unsigned int multilevel:1; /* multi-level multicast
378 format */
379 /* bit 95 */
380 unsigned int rsvd_4:24; /* ordered / source node /
381 source subnode / aging
382 must be zero */
383 /* bits 119:96 */
384 unsigned int command:8; /* message type */
385 /* bits 127:120 */
386};
387
388/* Abstracted BAU functions */
389struct bau_operations {
390 unsigned long (*read_l_sw_ack)(void);
391 unsigned long (*read_g_sw_ack)(int pnode);
392 unsigned long (*bau_gpa_to_offset)(unsigned long vaddr);
393 void (*write_l_sw_ack)(unsigned long mmr);
394 void (*write_g_sw_ack)(int pnode, unsigned long mmr);
395 void (*write_payload_first)(int pnode, unsigned long mmr);
396 void (*write_payload_last)(int pnode, unsigned long mmr);
397};
398
399/*
400 * The activation descriptor:
401 * The format of the message to send, plus all accompanying control
402 * Should be 64 bytes
403 */
404struct bau_desc {
405 struct pnmask distribution;
406 /*
407 * message template, consisting of header and payload:
408 */
409 union bau_msg_header {
410 struct uv1_bau_msg_header uv1_hdr;
411 struct uv2_3_bau_msg_header uv2_3_hdr;
412 } header;
413
414 struct bau_msg_payload payload;
415};
416/* UV1:
417 * -payload-- ---------header------
418 * bytes 0-11 bits 41-56 bits 58-81
419 * A B (2) C (3)
420 *
421 * A/B/C are moved to:
422 * A C B
423 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
424 * ------------payload queue-----------
425 */
426/* UV2:
427 * -payload-- ---------header------
428 * bytes 0-11 bits 70-78 bits 21-44
429 * A B (2) C (3)
430 *
431 * A/B/C are moved to:
432 * A C B
433 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
434 * ------------payload queue-----------
435 */
436
437/*
438 * The payload queue on the destination side is an array of these.
439 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
440 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
441 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
442 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
443 * swack_vec and payload_2)
444 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
445 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
446 * operation."
447 */
448struct bau_pq_entry {
449 unsigned long address; /* signifies a page or all TLB's
450 of the cpu */
451 /* 64 bits, bytes 0-7 */
452 unsigned short sending_cpu; /* cpu that sent the message */
453 /* 16 bits, bytes 8-9 */
454 unsigned short acknowledge_count; /* filled in by destination */
455 /* 16 bits, bytes 10-11 */
456 /* these next 3 bytes come from bits 58-81 of the message header */
457 unsigned short replied_to:1; /* sent as 0 by the source */
458 unsigned short msg_type:3; /* software message type */
459 unsigned short canceled:1; /* sent as 0 by the source */
460 unsigned short unused1:3; /* not currently using */
461 /* byte 12 */
462 unsigned char unused2a; /* not currently using */
463 /* byte 13 */
464 unsigned char unused2; /* not currently using */
465 /* byte 14 */
466 unsigned char swack_vec; /* filled in by the hardware */
467 /* byte 15 (bits 127:120) */
468 unsigned short sequence; /* message sequence number */
469 /* bytes 16-17 */
470 unsigned char unused4[2]; /* not currently using bytes 18-19 */
471 /* bytes 18-19 */
472 int number_of_cpus; /* filled in at destination */
473 /* 32 bits, bytes 20-23 (aligned) */
474 unsigned char unused5[8]; /* not using */
475 /* bytes 24-31 */
476};
477
478struct msg_desc {
479 struct bau_pq_entry *msg;
480 int msg_slot;
481 struct bau_pq_entry *queue_first;
482 struct bau_pq_entry *queue_last;
483};
484
485struct reset_args {
486 int sender;
487};
488
489/*
490 * This structure is allocated per_cpu for UV TLB shootdown statistics.
491 */
492struct ptc_stats {
493 /* sender statistics */
494 unsigned long s_giveup; /* number of fall backs to
495 IPI-style flushes */
496 unsigned long s_requestor; /* number of shootdown
497 requests */
498 unsigned long s_stimeout; /* source side timeouts */
499 unsigned long s_dtimeout; /* destination side timeouts */
500 unsigned long s_strongnacks; /* number of strong nack's */
501 unsigned long s_time; /* time spent in sending side */
502 unsigned long s_retriesok; /* successful retries */
503 unsigned long s_ntargcpu; /* total number of cpu's
504 targeted */
505 unsigned long s_ntargself; /* times the sending cpu was
506 targeted */
507 unsigned long s_ntarglocals; /* targets of cpus on the local
508 blade */
509 unsigned long s_ntargremotes; /* targets of cpus on remote
510 blades */
511 unsigned long s_ntarglocaluvhub; /* targets of the local hub */
512 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
513 unsigned long s_ntarguvhub; /* total number of uvhubs
514 targeted */
515 unsigned long s_ntarguvhub16; /* number of times target
516 hubs >= 16*/
517 unsigned long s_ntarguvhub8; /* number of times target
518 hubs >= 8 */
519 unsigned long s_ntarguvhub4; /* number of times target
520 hubs >= 4 */
521 unsigned long s_ntarguvhub2; /* number of times target
522 hubs >= 2 */
523 unsigned long s_ntarguvhub1; /* number of times target
524 hubs == 1 */
525 unsigned long s_resets_plug; /* ipi-style resets from plug
526 state */
527 unsigned long s_resets_timeout; /* ipi-style resets from
528 timeouts */
529 unsigned long s_busy; /* status stayed busy past
530 s/w timer */
531 unsigned long s_throttles; /* waits in throttle */
532 unsigned long s_retry_messages; /* retry broadcasts */
533 unsigned long s_bau_reenabled; /* for bau enable/disable */
534 unsigned long s_bau_disabled; /* for bau enable/disable */
535 unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */
536 unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */
537 unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */
538 unsigned long s_overipilimit; /* over the ipi reset limit */
539 unsigned long s_giveuplimit; /* disables, over giveup limit*/
540 unsigned long s_enters; /* entries to the driver */
541 unsigned long s_ipifordisabled; /* fall back to IPI; disabled */
542 unsigned long s_plugged; /* plugged by h/w bug*/
543 unsigned long s_congested; /* giveup on long wait */
544 /* destination statistics */
545 unsigned long d_alltlb; /* times all tlb's on this
546 cpu were flushed */
547 unsigned long d_onetlb; /* times just one tlb on this
548 cpu was flushed */
549 unsigned long d_multmsg; /* interrupts with multiple
550 messages */
551 unsigned long d_nomsg; /* interrupts with no message */
552 unsigned long d_time; /* time spent on destination
553 side */
554 unsigned long d_requestee; /* number of messages
555 processed */
556 unsigned long d_retries; /* number of retry messages
557 processed */
558 unsigned long d_canceled; /* number of messages canceled
559 by retries */
560 unsigned long d_nocanceled; /* retries that found nothing
561 to cancel */
562 unsigned long d_resets; /* number of ipi-style requests
563 processed */
564 unsigned long d_rcanceled; /* number of messages canceled
565 by resets */
566};
567
568struct tunables {
569 int *tunp;
570 int deflt;
571};
572
573struct hub_and_pnode {
574 short uvhub;
575 short pnode;
576};
577
578struct socket_desc {
579 short num_cpus;
580 short cpu_number[MAX_CPUS_PER_SOCKET];
581};
582
583struct uvhub_desc {
584 unsigned short socket_mask;
585 short num_cpus;
586 short uvhub;
587 short pnode;
588 struct socket_desc socket[2];
589};
590
591/*
592 * one per-cpu; to locate the software tables
593 */
594struct bau_control {
595 struct bau_desc *descriptor_base;
596 struct bau_pq_entry *queue_first;
597 struct bau_pq_entry *queue_last;
598 struct bau_pq_entry *bau_msg_head;
599 struct bau_control *uvhub_master;
600 struct bau_control *socket_master;
601 struct ptc_stats *statp;
602 cpumask_t *cpumask;
603 unsigned long timeout_interval;
604 unsigned long set_bau_on_time;
605 atomic_t active_descriptor_count;
606 int plugged_tries;
607 int timeout_tries;
608 int ipi_attempts;
609 int conseccompletes;
610 bool nobau;
611 short baudisabled;
612 short cpu;
613 short osnode;
614 short uvhub_cpu;
615 short uvhub;
616 short uvhub_version;
617 short cpus_in_socket;
618 short cpus_in_uvhub;
619 short partition_base_pnode;
620 short busy; /* all were busy (war) */
621 unsigned short message_number;
622 unsigned short uvhub_quiesce;
623 short socket_acknowledge_count[DEST_Q_SIZE];
624 cycles_t send_message;
625 cycles_t period_end;
626 cycles_t period_time;
627 spinlock_t uvhub_lock;
628 spinlock_t queue_lock;
629 spinlock_t disable_lock;
630 /* tunables */
631 int max_concurr;
632 int max_concurr_const;
633 int plugged_delay;
634 int plugsb4reset;
635 int timeoutsb4reset;
636 int ipi_reset_limit;
637 int complete_threshold;
638 int cong_response_us;
639 int cong_reps;
640 cycles_t disabled_period;
641 int period_giveups;
642 int giveup_limit;
643 long period_requests;
644 struct hub_and_pnode *thp;
645};
646
647static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
648{
649 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
650}
651
652static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
653{
654 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
655}
656
657static inline void write_mmr_activation(unsigned long index)
658{
659 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
660}
661
662static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
663{
664 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
665}
666
667static inline void write_mmr_proc_payload_first(int pnode, unsigned long mmr_image)
668{
669 write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_FIRST, mmr_image);
670}
671
672static inline void write_mmr_proc_payload_last(int pnode, unsigned long mmr_image)
673{
674 write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_LAST, mmr_image);
675}
676
677static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
678{
679 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
680}
681
682static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
683{
684 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
685}
686
687static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
688{
689 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
690}
691
692static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
693{
694 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
695}
696
697static inline unsigned long read_mmr_misc_control(int pnode)
698{
699 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
700}
701
702static inline void write_mmr_sw_ack(unsigned long mr)
703{
704 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
705}
706
707static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
708{
709 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
710}
711
712static inline unsigned long read_mmr_sw_ack(void)
713{
714 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
715}
716
717static inline unsigned long read_gmmr_sw_ack(int pnode)
718{
719 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
720}
721
722static inline void write_mmr_proc_sw_ack(unsigned long mr)
723{
724 uv_write_local_mmr(UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
725}
726
727static inline void write_gmmr_proc_sw_ack(int pnode, unsigned long mr)
728{
729 write_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
730}
731
732static inline unsigned long read_mmr_proc_sw_ack(void)
733{
734 return read_lmmr(UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
735}
736
737static inline unsigned long read_gmmr_proc_sw_ack(int pnode)
738{
739 return read_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
740}
741
742static inline void write_mmr_data_config(int pnode, unsigned long mr)
743{
744 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
745}
746
747static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
748{
749 return constant_test_bit(uvhub, &dstp->bits[0]);
750}
751static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
752{
753 __set_bit(pnode, &dstp->bits[0]);
754}
755static inline void bau_uvhubs_clear(struct pnmask *dstp,
756 int nbits)
757{
758 bitmap_zero(&dstp->bits[0], nbits);
759}
760static inline int bau_uvhub_weight(struct pnmask *dstp)
761{
762 return bitmap_weight((unsigned long *)&dstp->bits[0],
763 UV_DISTRIBUTION_SIZE);
764}
765
766static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
767{
768 bitmap_zero(&dstp->bits, nbits);
769}
770
771extern void uv_bau_message_intr1(void);
772#ifdef CONFIG_TRACING
773#define trace_uv_bau_message_intr1 uv_bau_message_intr1
774#endif
775extern void uv_bau_timeout_intr1(void);
776
777struct atomic_short {
778 short counter;
779};
780
781/*
782 * atomic_read_short - read a short atomic variable
783 * @v: pointer of type atomic_short
784 *
785 * Atomically reads the value of @v.
786 */
787static inline int atomic_read_short(const struct atomic_short *v)
788{
789 return v->counter;
790}
791
792/*
793 * atom_asr - add and return a short int
794 * @i: short value to add
795 * @v: pointer of type atomic_short
796 *
797 * Atomically adds @i to @v and returns @i + @v
798 */
799static inline int atom_asr(short i, struct atomic_short *v)
800{
801 short __i = i;
802 asm volatile(LOCK_PREFIX "xaddw %0, %1"
803 : "+r" (i), "+m" (v->counter)
804 : : "memory");
805 return i + __i;
806}
807
808/*
809 * conditionally add 1 to *v, unless *v is >= u
810 * return 0 if we cannot add 1 to *v because it is >= u
811 * return 1 if we can add 1 to *v because it is < u
812 * the add is atomic
813 *
814 * This is close to atomic_add_unless(), but this allows the 'u' value
815 * to be lowered below the current 'v'. atomic_add_unless can only stop
816 * on equal.
817 */
818static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
819{
820 spin_lock(lock);
821 if (atomic_read(v) >= u) {
822 spin_unlock(lock);
823 return 0;
824 }
825 atomic_inc(v);
826 spin_unlock(lock);
827 return 1;
828}
829
830#endif /* _ASM_X86_UV_UV_BAU_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Broadcast Assist Unit definitions
7 *
8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef _ASM_X86_UV_UV_BAU_H
12#define _ASM_X86_UV_UV_BAU_H
13
14#include <linux/bitmap.h>
15#include <asm/idtentry.h>
16
17#define BITSPERBYTE 8
18
19/*
20 * Broadcast Assist Unit messaging structures
21 *
22 * Selective Broadcast activations are induced by software action
23 * specifying a particular 8-descriptor "set" via a 6-bit index written
24 * to an MMR.
25 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
26 * each 6-bit index value. These descriptor sets are mapped in sequence
27 * starting with set 0 located at the address specified in the
28 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
29 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
30 *
31 * We will use one set for sending BAU messages from each of the
32 * cpu's on the uvhub.
33 *
34 * TLB shootdown will use the first of the 8 descriptors of each set.
35 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
36 */
37
38#define MAX_CPUS_PER_UVHUB 128
39#define MAX_CPUS_PER_SOCKET 64
40#define ADP_SZ 64 /* hardware-provided max. */
41#define UV_CPUS_PER_AS 32 /* hardware-provided max. */
42#define ITEMS_PER_DESC 8
43/* the 'throttle' to prevent the hardware stay-busy bug */
44#define MAX_BAU_CONCURRENT 3
45#define UV_ACT_STATUS_MASK 0x3
46#define UV_ACT_STATUS_SIZE 2
47#define UV_DISTRIBUTION_SIZE 256
48#define UV_SW_ACK_NPENDING 8
49#define UV_NET_ENDPOINT_INTD 0x28
50#define UV_PAYLOADQ_GNODE_SHIFT 49
51#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
52#define UV_BAU_BASENAME "sgi_uv/bau_tunables"
53#define UV_BAU_TUNABLES_DIR "sgi_uv"
54#define UV_BAU_TUNABLES_FILE "bau_tunables"
55#define WHITESPACE " \t\n"
56#define cpubit_isset(cpu, bau_local_cpumask) \
57 test_bit((cpu), (bau_local_cpumask).bits)
58
59/* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */
60/*
61 * UV2: Bit 19 selects between
62 * (0): 10 microsecond timebase and
63 * (1): 80 microseconds
64 * we're using 560us
65 */
66#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
67/* assuming UV3 is the same */
68
69#define BAU_MISC_CONTROL_MULT_MASK 3
70
71#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
72/* [30:28] URGENCY_7 an index into a table of times */
73#define BAU_URGENCY_7_SHIFT 28
74#define BAU_URGENCY_7_MASK 7
75
76#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
77/* [45:40] BAU - BAU transaction timeout select - a multiplier */
78#define BAU_TRANS_SHIFT 40
79#define BAU_TRANS_MASK 0x3f
80
81/*
82 * shorten some awkward names
83 */
84#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
85#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
86#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
87#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
88#define PREFETCH_HINT_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT
89#define SB_STATUS_SHFT UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
90#define write_gmmr uv_write_global_mmr64
91#define write_lmmr uv_write_local_mmr
92#define read_lmmr uv_read_local_mmr
93#define read_gmmr uv_read_global_mmr64
94
95/*
96 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
97 */
98#define DS_IDLE 0
99#define DS_ACTIVE 1
100#define DS_DESTINATION_TIMEOUT 2
101#define DS_SOURCE_TIMEOUT 3
102/*
103 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
104 * values 1 and 3 will not occur
105 * Decoded meaning ERROR BUSY AUX ERR
106 * ------------------------------- ---- ----- -------
107 * IDLE 0 0 0
108 * BUSY (active) 0 1 0
109 * SW Ack Timeout (destination) 1 0 0
110 * SW Ack INTD rejected (strong NACK) 1 0 1
111 * Source Side Time Out Detected 1 1 0
112 * Destination Side PUT Failed 1 1 1
113 */
114#define UV2H_DESC_IDLE 0
115#define UV2H_DESC_BUSY 2
116#define UV2H_DESC_DEST_TIMEOUT 4
117#define UV2H_DESC_DEST_STRONG_NACK 5
118#define UV2H_DESC_SOURCE_TIMEOUT 6
119#define UV2H_DESC_DEST_PUT_ERR 7
120
121/*
122 * delay for 'plugged' timeout retries, in microseconds
123 */
124#define PLUGGED_DELAY 10
125
126/*
127 * threshholds at which to use IPI to free resources
128 */
129/* after this # consecutive 'plugged' timeouts, use IPI to release resources */
130#define PLUGSB4RESET 100
131/* after this many consecutive timeouts, use IPI to release resources */
132#define TIMEOUTSB4RESET 1
133/* at this number uses of IPI to release resources, giveup the request */
134#define IPI_RESET_LIMIT 1
135/* after this # consecutive successes, bump up the throttle if it was lowered */
136#define COMPLETE_THRESHOLD 5
137/* after this # of giveups (fall back to kernel IPI's) disable the use of
138 the BAU for a period of time */
139#define GIVEUP_LIMIT 100
140
141#define UV_LB_SUBNODEID 0x10
142
143#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
144#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
145/* 4 bits of software ack period */
146#define UV2_ACK_MASK 0x7UL
147#define UV2_ACK_UNITS_SHFT 3
148#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
149
150/*
151 * number of entries in the destination side payload queue
152 */
153#define DEST_Q_SIZE 20
154/*
155 * number of destination side software ack resources
156 */
157#define DEST_NUM_RESOURCES 8
158/*
159 * completion statuses for sending a TLB flush message
160 */
161#define FLUSH_RETRY_PLUGGED 1
162#define FLUSH_RETRY_TIMEOUT 2
163#define FLUSH_GIVEUP 3
164#define FLUSH_COMPLETE 4
165
166/*
167 * tuning the action when the numalink network is extremely delayed
168 */
169#define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in
170 microseconds */
171#define CONGESTED_REPS 10 /* long delays averaged over
172 this many broadcasts */
173#define DISABLED_PERIOD 10 /* time for the bau to be
174 disabled, in seconds */
175/* see msg_type: */
176#define MSG_NOOP 0
177#define MSG_REGULAR 1
178#define MSG_RETRY 2
179
180#define BAU_DESC_QUALIFIER 0x534749
181
182enum uv_bau_version {
183 UV_BAU_V2 = 2,
184 UV_BAU_V3,
185 UV_BAU_V4,
186};
187
188/*
189 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
190 * If the 'multilevel' flag in the header portion of the descriptor
191 * has been set to 0, then endpoint multi-unicast mode is selected.
192 * The distribution specification (32 bytes) is interpreted as a 256-bit
193 * distribution vector. Adjacent bits correspond to consecutive even numbered
194 * nodeIDs. The result of adding the index of a given bit to the 15-bit
195 * 'base_dest_nasid' field of the header corresponds to the
196 * destination nodeID associated with that specified bit.
197 */
198struct pnmask {
199 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
200};
201
202/*
203 * mask of cpu's on a uvhub
204 * (during initialization we need to check that unsigned long has
205 * enough bits for max. cpu's per uvhub)
206 */
207struct bau_local_cpumask {
208 unsigned long bits;
209};
210
211/*
212 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
213 * only 12 bytes (96 bits) of the payload area are usable.
214 * An additional 3 bytes (bits 27:4) of the header address are carried
215 * to the next bytes of the destination payload queue.
216 * And an additional 2 bytes of the header Suppl_A field are also
217 * carried to the destination payload queue.
218 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
219 * of the destination payload queue, which is written by the hardware
220 * with the s/w ack resource bit vector.
221 * [ effective message contents (16 bytes (128 bits) maximum), not counting
222 * the s/w ack bit vector ]
223 */
224
225/**
226 * struct uv2_3_bau_msg_payload - defines payload for INTD transactions
227 * @address: Signifies a page or all TLB's of the cpu
228 * @sending_cpu: CPU from which the message originates
229 * @acknowledge_count: CPUs on the destination Hub that received the interrupt
230 */
231struct uv2_3_bau_msg_payload {
232 u64 address;
233 u16 sending_cpu;
234 u16 acknowledge_count;
235};
236
237/**
238 * struct uv4_bau_msg_payload - defines payload for INTD transactions
239 * @address: Signifies a page or all TLB's of the cpu
240 * @sending_cpu: CPU from which the message originates
241 * @acknowledge_count: CPUs on the destination Hub that received the interrupt
242 * @qualifier: Set by source to verify origin of INTD broadcast
243 */
244struct uv4_bau_msg_payload {
245 u64 address;
246 u16 sending_cpu;
247 u16 acknowledge_count;
248 u32 reserved:8;
249 u32 qualifier:24;
250};
251
252/*
253 * UV2 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
254 * see figure 9-2 of harp_sys.pdf
255 * assuming UV3 is the same
256 */
257struct uv2_3_bau_msg_header {
258 unsigned int base_dest_nasid:15; /* nasid of the first bit */
259 /* bits 14:0 */ /* in uvhub map */
260 unsigned int dest_subnodeid:5; /* must be 0x10, for the LB */
261 /* bits 19:15 */
262 unsigned int rsvd_1:1; /* must be zero */
263 /* bit 20 */
264 /* Address bits 59:21 */
265 /* bits 25:2 of address (44:21) are payload */
266 /* these next 24 bits become bytes 12-14 of msg */
267 /* bits 28:21 land in byte 12 */
268 unsigned int replied_to:1; /* sent as 0 by the source to
269 byte 12 */
270 /* bit 21 */
271 unsigned int msg_type:3; /* software type of the
272 message */
273 /* bits 24:22 */
274 unsigned int canceled:1; /* message canceled, resource
275 is to be freed*/
276 /* bit 25 */
277 unsigned int payload_1:3; /* not currently used */
278 /* bits 28:26 */
279
280 /* bits 36:29 land in byte 13 */
281 unsigned int payload_2a:3; /* not currently used */
282 unsigned int payload_2b:5; /* not currently used */
283 /* bits 36:29 */
284
285 /* bits 44:37 land in byte 14 */
286 unsigned int payload_3:8; /* not currently used */
287 /* bits 44:37 */
288
289 unsigned int rsvd_2:7; /* reserved */
290 /* bits 51:45 */
291 unsigned int swack_flag:1; /* software acknowledge flag */
292 /* bit 52 */
293 unsigned int rsvd_3a:3; /* must be zero */
294 unsigned int rsvd_3b:8; /* must be zero */
295 unsigned int rsvd_3c:8; /* must be zero */
296 unsigned int rsvd_3d:3; /* must be zero */
297 /* bits 74:53 */
298 unsigned int fairness:3; /* usually zero */
299 /* bits 77:75 */
300
301 unsigned int sequence:16; /* message sequence number */
302 /* bits 93:78 Suppl_A */
303 unsigned int chaining:1; /* next descriptor is part of
304 this activation*/
305 /* bit 94 */
306 unsigned int multilevel:1; /* multi-level multicast
307 format */
308 /* bit 95 */
309 unsigned int rsvd_4:24; /* ordered / source node /
310 source subnode / aging
311 must be zero */
312 /* bits 119:96 */
313 unsigned int command:8; /* message type */
314 /* bits 127:120 */
315};
316
317/*
318 * The activation descriptor:
319 * The format of the message to send, plus all accompanying control
320 * Should be 64 bytes
321 */
322struct bau_desc {
323 struct pnmask distribution;
324 /*
325 * message template, consisting of header and payload:
326 */
327 union bau_msg_header {
328 struct uv2_3_bau_msg_header uv2_3_hdr;
329 } header;
330
331 union bau_payload_header {
332 struct uv2_3_bau_msg_payload uv2_3;
333 struct uv4_bau_msg_payload uv4;
334 } payload;
335};
336/* UV2:
337 * -payload-- ---------header------
338 * bytes 0-11 bits 70-78 bits 21-44
339 * A B (2) C (3)
340 *
341 * A/B/C are moved to:
342 * A C B
343 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
344 * ------------payload queue-----------
345 */
346
347/*
348 * The payload queue on the destination side is an array of these.
349 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
350 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
351 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
352 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
353 * swack_vec and payload_2)
354 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
355 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
356 * operation."
357 */
358struct bau_pq_entry {
359 unsigned long address; /* signifies a page or all TLB's
360 of the cpu */
361 /* 64 bits, bytes 0-7 */
362 unsigned short sending_cpu; /* cpu that sent the message */
363 /* 16 bits, bytes 8-9 */
364 unsigned short acknowledge_count; /* filled in by destination */
365 /* 16 bits, bytes 10-11 */
366 /* these next 3 bytes come from bits 58-81 of the message header */
367 unsigned short replied_to:1; /* sent as 0 by the source */
368 unsigned short msg_type:3; /* software message type */
369 unsigned short canceled:1; /* sent as 0 by the source */
370 unsigned short unused1:3; /* not currently using */
371 /* byte 12 */
372 unsigned char unused2a; /* not currently using */
373 /* byte 13 */
374 unsigned char unused2; /* not currently using */
375 /* byte 14 */
376 unsigned char swack_vec; /* filled in by the hardware */
377 /* byte 15 (bits 127:120) */
378 unsigned short sequence; /* message sequence number */
379 /* bytes 16-17 */
380 unsigned char unused4[2]; /* not currently using bytes 18-19 */
381 /* bytes 18-19 */
382 int number_of_cpus; /* filled in at destination */
383 /* 32 bits, bytes 20-23 (aligned) */
384 unsigned char unused5[8]; /* not using */
385 /* bytes 24-31 */
386};
387
388struct msg_desc {
389 struct bau_pq_entry *msg;
390 int msg_slot;
391 struct bau_pq_entry *queue_first;
392 struct bau_pq_entry *queue_last;
393};
394
395struct reset_args {
396 int sender;
397};
398
399/*
400 * This structure is allocated per_cpu for UV TLB shootdown statistics.
401 */
402struct ptc_stats {
403 /* sender statistics */
404 unsigned long s_giveup; /* number of fall backs to
405 IPI-style flushes */
406 unsigned long s_requestor; /* number of shootdown
407 requests */
408 unsigned long s_stimeout; /* source side timeouts */
409 unsigned long s_dtimeout; /* destination side timeouts */
410 unsigned long s_strongnacks; /* number of strong nack's */
411 unsigned long s_time; /* time spent in sending side */
412 unsigned long s_retriesok; /* successful retries */
413 unsigned long s_ntargcpu; /* total number of cpu's
414 targeted */
415 unsigned long s_ntargself; /* times the sending cpu was
416 targeted */
417 unsigned long s_ntarglocals; /* targets of cpus on the local
418 blade */
419 unsigned long s_ntargremotes; /* targets of cpus on remote
420 blades */
421 unsigned long s_ntarglocaluvhub; /* targets of the local hub */
422 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
423 unsigned long s_ntarguvhub; /* total number of uvhubs
424 targeted */
425 unsigned long s_ntarguvhub16; /* number of times target
426 hubs >= 16*/
427 unsigned long s_ntarguvhub8; /* number of times target
428 hubs >= 8 */
429 unsigned long s_ntarguvhub4; /* number of times target
430 hubs >= 4 */
431 unsigned long s_ntarguvhub2; /* number of times target
432 hubs >= 2 */
433 unsigned long s_ntarguvhub1; /* number of times target
434 hubs == 1 */
435 unsigned long s_resets_plug; /* ipi-style resets from plug
436 state */
437 unsigned long s_resets_timeout; /* ipi-style resets from
438 timeouts */
439 unsigned long s_busy; /* status stayed busy past
440 s/w timer */
441 unsigned long s_throttles; /* waits in throttle */
442 unsigned long s_retry_messages; /* retry broadcasts */
443 unsigned long s_bau_reenabled; /* for bau enable/disable */
444 unsigned long s_bau_disabled; /* for bau enable/disable */
445 unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */
446 unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */
447 unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */
448 unsigned long s_overipilimit; /* over the ipi reset limit */
449 unsigned long s_giveuplimit; /* disables, over giveup limit*/
450 unsigned long s_enters; /* entries to the driver */
451 unsigned long s_ipifordisabled; /* fall back to IPI; disabled */
452 unsigned long s_plugged; /* plugged by h/w bug*/
453 unsigned long s_congested; /* giveup on long wait */
454 /* destination statistics */
455 unsigned long d_alltlb; /* times all tlb's on this
456 cpu were flushed */
457 unsigned long d_onetlb; /* times just one tlb on this
458 cpu was flushed */
459 unsigned long d_multmsg; /* interrupts with multiple
460 messages */
461 unsigned long d_nomsg; /* interrupts with no message */
462 unsigned long d_time; /* time spent on destination
463 side */
464 unsigned long d_requestee; /* number of messages
465 processed */
466 unsigned long d_retries; /* number of retry messages
467 processed */
468 unsigned long d_canceled; /* number of messages canceled
469 by retries */
470 unsigned long d_nocanceled; /* retries that found nothing
471 to cancel */
472 unsigned long d_resets; /* number of ipi-style requests
473 processed */
474 unsigned long d_rcanceled; /* number of messages canceled
475 by resets */
476};
477
478struct tunables {
479 int *tunp;
480 int deflt;
481};
482
483struct hub_and_pnode {
484 short uvhub;
485 short pnode;
486};
487
488struct socket_desc {
489 short num_cpus;
490 short cpu_number[MAX_CPUS_PER_SOCKET];
491};
492
493struct uvhub_desc {
494 unsigned short socket_mask;
495 short num_cpus;
496 short uvhub;
497 short pnode;
498 struct socket_desc socket[2];
499};
500
501/**
502 * struct bau_control
503 * @status_mmr: location of status mmr, determined by uvhub_cpu
504 * @status_index: index of ERR|BUSY bits in status mmr, determined by uvhub_cpu
505 *
506 * Per-cpu control struct containing CPU topology information and BAU tuneables.
507 */
508struct bau_control {
509 struct bau_desc *descriptor_base;
510 struct bau_pq_entry *queue_first;
511 struct bau_pq_entry *queue_last;
512 struct bau_pq_entry *bau_msg_head;
513 struct bau_control *uvhub_master;
514 struct bau_control *socket_master;
515 struct ptc_stats *statp;
516 cpumask_t *cpumask;
517 unsigned long timeout_interval;
518 unsigned long set_bau_on_time;
519 atomic_t active_descriptor_count;
520 int plugged_tries;
521 int timeout_tries;
522 int ipi_attempts;
523 int conseccompletes;
524 u64 status_mmr;
525 int status_index;
526 bool nobau;
527 short baudisabled;
528 short cpu;
529 short osnode;
530 short uvhub_cpu;
531 short uvhub;
532 short uvhub_version;
533 short cpus_in_socket;
534 short cpus_in_uvhub;
535 short partition_base_pnode;
536 short busy; /* all were busy (war) */
537 unsigned short message_number;
538 unsigned short uvhub_quiesce;
539 short socket_acknowledge_count[DEST_Q_SIZE];
540 cycles_t send_message;
541 cycles_t period_end;
542 cycles_t period_time;
543 spinlock_t uvhub_lock;
544 spinlock_t queue_lock;
545 spinlock_t disable_lock;
546 /* tunables */
547 int max_concurr;
548 int max_concurr_const;
549 int plugged_delay;
550 int plugsb4reset;
551 int timeoutsb4reset;
552 int ipi_reset_limit;
553 int complete_threshold;
554 int cong_response_us;
555 int cong_reps;
556 cycles_t disabled_period;
557 int period_giveups;
558 int giveup_limit;
559 long period_requests;
560 struct hub_and_pnode *thp;
561};
562
563/* Abstracted BAU functions */
564struct bau_operations {
565 unsigned long (*read_l_sw_ack)(void);
566 unsigned long (*read_g_sw_ack)(int pnode);
567 unsigned long (*bau_gpa_to_offset)(unsigned long vaddr);
568 void (*write_l_sw_ack)(unsigned long mmr);
569 void (*write_g_sw_ack)(int pnode, unsigned long mmr);
570 void (*write_payload_first)(int pnode, unsigned long mmr);
571 void (*write_payload_last)(int pnode, unsigned long mmr);
572 int (*wait_completion)(struct bau_desc*,
573 struct bau_control*, long try);
574};
575
576static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
577{
578 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
579}
580
581static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
582{
583 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
584}
585
586static inline void write_mmr_activation(unsigned long index)
587{
588 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
589}
590
591static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
592{
593 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
594}
595
596static inline void write_mmr_proc_payload_first(int pnode, unsigned long mmr_image)
597{
598 write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_FIRST, mmr_image);
599}
600
601static inline void write_mmr_proc_payload_last(int pnode, unsigned long mmr_image)
602{
603 write_gmmr(pnode, UV4H_LB_PROC_INTD_QUEUE_LAST, mmr_image);
604}
605
606static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
607{
608 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
609}
610
611static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
612{
613 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
614}
615
616static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
617{
618 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
619}
620
621static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
622{
623 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
624}
625
626static inline unsigned long read_mmr_misc_control(int pnode)
627{
628 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
629}
630
631static inline void write_mmr_sw_ack(unsigned long mr)
632{
633 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
634}
635
636static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
637{
638 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
639}
640
641static inline unsigned long read_mmr_sw_ack(void)
642{
643 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
644}
645
646static inline unsigned long read_gmmr_sw_ack(int pnode)
647{
648 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
649}
650
651static inline void write_mmr_proc_sw_ack(unsigned long mr)
652{
653 uv_write_local_mmr(UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
654}
655
656static inline void write_gmmr_proc_sw_ack(int pnode, unsigned long mr)
657{
658 write_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR, mr);
659}
660
661static inline unsigned long read_mmr_proc_sw_ack(void)
662{
663 return read_lmmr(UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
664}
665
666static inline unsigned long read_gmmr_proc_sw_ack(int pnode)
667{
668 return read_gmmr(pnode, UV4H_LB_PROC_INTD_SOFT_ACK_PENDING);
669}
670
671static inline void write_mmr_data_config(int pnode, unsigned long mr)
672{
673 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
674}
675
676static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
677{
678 return constant_test_bit(uvhub, &dstp->bits[0]);
679}
680static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
681{
682 __set_bit(pnode, &dstp->bits[0]);
683}
684static inline void bau_uvhubs_clear(struct pnmask *dstp,
685 int nbits)
686{
687 bitmap_zero(&dstp->bits[0], nbits);
688}
689static inline int bau_uvhub_weight(struct pnmask *dstp)
690{
691 return bitmap_weight((unsigned long *)&dstp->bits[0],
692 UV_DISTRIBUTION_SIZE);
693}
694
695static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
696{
697 bitmap_zero(&dstp->bits, nbits);
698}
699
700struct atomic_short {
701 short counter;
702};
703
704/*
705 * atomic_read_short - read a short atomic variable
706 * @v: pointer of type atomic_short
707 *
708 * Atomically reads the value of @v.
709 */
710static inline int atomic_read_short(const struct atomic_short *v)
711{
712 return v->counter;
713}
714
715/*
716 * atom_asr - add and return a short int
717 * @i: short value to add
718 * @v: pointer of type atomic_short
719 *
720 * Atomically adds @i to @v and returns @i + @v
721 */
722static inline int atom_asr(short i, struct atomic_short *v)
723{
724 short __i = i;
725 asm volatile(LOCK_PREFIX "xaddw %0, %1"
726 : "+r" (i), "+m" (v->counter)
727 : : "memory");
728 return i + __i;
729}
730
731/*
732 * conditionally add 1 to *v, unless *v is >= u
733 * return 0 if we cannot add 1 to *v because it is >= u
734 * return 1 if we can add 1 to *v because it is < u
735 * the add is atomic
736 *
737 * This is close to atomic_add_unless(), but this allows the 'u' value
738 * to be lowered below the current 'v'. atomic_add_unless can only stop
739 * on equal.
740 */
741static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
742{
743 spin_lock(lock);
744 if (atomic_read(v) >= u) {
745 spin_unlock(lock);
746 return 0;
747 }
748 atomic_inc(v);
749 spin_unlock(lock);
750 return 1;
751}
752
753void uv_bau_message_interrupt(struct pt_regs *regs);
754
755#endif /* _ASM_X86_UV_UV_BAU_H */