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1/*
2 * Copyright (C) 2010 Google, Inc.
3 * Author: Erik Gilling <konkers@android.com>
4 *
5 * Copyright (C) 2011-2013 NVIDIA Corporation
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include "../dev.h"
19#include "../debug.h"
20#include "../cdma.h"
21#include "../channel.h"
22
23#define HOST1X_DEBUG_MAX_PAGE_OFFSET 102400
24
25enum {
26 HOST1X_OPCODE_SETCLASS = 0x00,
27 HOST1X_OPCODE_INCR = 0x01,
28 HOST1X_OPCODE_NONINCR = 0x02,
29 HOST1X_OPCODE_MASK = 0x03,
30 HOST1X_OPCODE_IMM = 0x04,
31 HOST1X_OPCODE_RESTART = 0x05,
32 HOST1X_OPCODE_GATHER = 0x06,
33 HOST1X_OPCODE_EXTEND = 0x0e,
34};
35
36enum {
37 HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK = 0x00,
38 HOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 0x01,
39};
40
41static unsigned int show_channel_command(struct output *o, u32 val)
42{
43 unsigned int mask, subop;
44
45 switch (val >> 28) {
46 case HOST1X_OPCODE_SETCLASS:
47 mask = val & 0x3f;
48 if (mask) {
49 host1x_debug_output(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [",
50 val >> 6 & 0x3ff,
51 val >> 16 & 0xfff, mask);
52 return hweight8(mask);
53 }
54
55 host1x_debug_output(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff);
56 return 0;
57
58 case HOST1X_OPCODE_INCR:
59 host1x_debug_output(o, "INCR(offset=%03x, [",
60 val >> 16 & 0xfff);
61 return val & 0xffff;
62
63 case HOST1X_OPCODE_NONINCR:
64 host1x_debug_output(o, "NONINCR(offset=%03x, [",
65 val >> 16 & 0xfff);
66 return val & 0xffff;
67
68 case HOST1X_OPCODE_MASK:
69 mask = val & 0xffff;
70 host1x_debug_output(o, "MASK(offset=%03x, mask=%03x, [",
71 val >> 16 & 0xfff, mask);
72 return hweight16(mask);
73
74 case HOST1X_OPCODE_IMM:
75 host1x_debug_output(o, "IMM(offset=%03x, data=%03x)\n",
76 val >> 16 & 0xfff, val & 0xffff);
77 return 0;
78
79 case HOST1X_OPCODE_RESTART:
80 host1x_debug_output(o, "RESTART(offset=%08x)\n", val << 4);
81 return 0;
82
83 case HOST1X_OPCODE_GATHER:
84 host1x_debug_output(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[",
85 val >> 16 & 0xfff, val >> 15 & 0x1,
86 val >> 14 & 0x1, val & 0x3fff);
87 return 1;
88
89 case HOST1X_OPCODE_EXTEND:
90 subop = val >> 24 & 0xf;
91 if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)
92 host1x_debug_output(o, "ACQUIRE_MLOCK(index=%d)\n",
93 val & 0xff);
94 else if (subop == HOST1X_OPCODE_EXTEND_RELEASE_MLOCK)
95 host1x_debug_output(o, "RELEASE_MLOCK(index=%d)\n",
96 val & 0xff);
97 else
98 host1x_debug_output(o, "EXTEND_UNKNOWN(%08x)\n", val);
99 return 0;
100
101 default:
102 return 0;
103 }
104}
105
106static void show_gather(struct output *o, phys_addr_t phys_addr,
107 unsigned int words, struct host1x_cdma *cdma,
108 phys_addr_t pin_addr, u32 *map_addr)
109{
110 /* Map dmaget cursor to corresponding mem handle */
111 u32 offset = phys_addr - pin_addr;
112 unsigned int data_count = 0, i;
113
114 /*
115 * Sometimes we're given different hardware address to the same
116 * page - in these cases the offset will get an invalid number and
117 * we just have to bail out.
118 */
119 if (offset > HOST1X_DEBUG_MAX_PAGE_OFFSET) {
120 host1x_debug_output(o, "[address mismatch]\n");
121 return;
122 }
123
124 for (i = 0; i < words; i++) {
125 u32 addr = phys_addr + i * 4;
126 u32 val = *(map_addr + offset / 4 + i);
127
128 if (!data_count) {
129 host1x_debug_output(o, "%08x: %08x:", addr, val);
130 data_count = show_channel_command(o, val);
131 } else {
132 host1x_debug_output(o, "%08x%s", val,
133 data_count > 0 ? ", " : "])\n");
134 data_count--;
135 }
136 }
137}
138
139static void show_channel_gathers(struct output *o, struct host1x_cdma *cdma)
140{
141 struct host1x_job *job;
142
143 list_for_each_entry(job, &cdma->sync_queue, list) {
144 unsigned int i;
145
146 host1x_debug_output(o, "\n%p: JOB, syncpt_id=%d, syncpt_val=%d, first_get=%08x, timeout=%d num_slots=%d, num_handles=%d\n",
147 job, job->syncpt_id, job->syncpt_end,
148 job->first_get, job->timeout,
149 job->num_slots, job->num_unpins);
150
151 for (i = 0; i < job->num_gathers; i++) {
152 struct host1x_job_gather *g = &job->gathers[i];
153 u32 *mapped;
154
155 if (job->gather_copy_mapped)
156 mapped = (u32 *)job->gather_copy_mapped;
157 else
158 mapped = host1x_bo_mmap(g->bo);
159
160 if (!mapped) {
161 host1x_debug_output(o, "[could not mmap]\n");
162 continue;
163 }
164
165 host1x_debug_output(o, " GATHER at %pad+%#x, %d words\n",
166 &g->base, g->offset, g->words);
167
168 show_gather(o, g->base + g->offset, g->words, cdma,
169 g->base, mapped);
170
171 if (!job->gather_copy_mapped)
172 host1x_bo_munmap(g->bo, mapped);
173 }
174 }
175}
176
177static void host1x_debug_show_channel_cdma(struct host1x *host,
178 struct host1x_channel *ch,
179 struct output *o)
180{
181 struct host1x_cdma *cdma = &ch->cdma;
182 u32 dmaput, dmaget, dmactrl;
183 u32 cbstat, cbread;
184 u32 val, base, baseval;
185
186 dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
187 dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
188 dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
189 cbread = host1x_sync_readl(host, HOST1X_SYNC_CBREAD(ch->id));
190 cbstat = host1x_sync_readl(host, HOST1X_SYNC_CBSTAT(ch->id));
191
192 host1x_debug_output(o, "%u-%s: ", ch->id, dev_name(ch->dev));
193
194 if (HOST1X_CHANNEL_DMACTRL_DMASTOP_V(dmactrl) ||
195 !ch->cdma.push_buffer.mapped) {
196 host1x_debug_output(o, "inactive\n\n");
197 return;
198 }
199
200 if (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) == HOST1X_CLASS_HOST1X &&
201 HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==
202 HOST1X_UCLASS_WAIT_SYNCPT)
203 host1x_debug_output(o, "waiting on syncpt %d val %d\n",
204 cbread >> 24, cbread & 0xffffff);
205 else if (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) ==
206 HOST1X_CLASS_HOST1X &&
207 HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==
208 HOST1X_UCLASS_WAIT_SYNCPT_BASE) {
209 base = (cbread >> 16) & 0xff;
210 baseval =
211 host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(base));
212 val = cbread & 0xffff;
213 host1x_debug_output(o, "waiting on syncpt %d val %d (base %d = %d; offset = %d)\n",
214 cbread >> 24, baseval + val, base,
215 baseval, val);
216 } else
217 host1x_debug_output(o, "active class %02x, offset %04x, val %08x\n",
218 HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat),
219 HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat),
220 cbread);
221
222 host1x_debug_output(o, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",
223 dmaput, dmaget, dmactrl);
224 host1x_debug_output(o, "CBREAD %08x, CBSTAT %08x\n", cbread, cbstat);
225
226 show_channel_gathers(o, cdma);
227 host1x_debug_output(o, "\n");
228}
229
230static void host1x_debug_show_channel_fifo(struct host1x *host,
231 struct host1x_channel *ch,
232 struct output *o)
233{
234 u32 val, rd_ptr, wr_ptr, start, end;
235 unsigned int data_count = 0;
236
237 host1x_debug_output(o, "%u: fifo:\n", ch->id);
238
239 val = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT);
240 host1x_debug_output(o, "FIFOSTAT %08x\n", val);
241 if (HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(val)) {
242 host1x_debug_output(o, "[empty]\n");
243 return;
244 }
245
246 host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);
247 host1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |
248 HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id),
249 HOST1X_SYNC_CFPEEK_CTRL);
250
251 val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_PTRS);
252 rd_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(val);
253 wr_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(val);
254
255 val = host1x_sync_readl(host, HOST1X_SYNC_CF_SETUP(ch->id));
256 start = HOST1X_SYNC_CF_SETUP_BASE_V(val);
257 end = HOST1X_SYNC_CF_SETUP_LIMIT_V(val);
258
259 do {
260 host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);
261 host1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |
262 HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id) |
263 HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(rd_ptr),
264 HOST1X_SYNC_CFPEEK_CTRL);
265 val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ);
266
267 if (!data_count) {
268 host1x_debug_output(o, "%08x:", val);
269 data_count = show_channel_command(o, val);
270 } else {
271 host1x_debug_output(o, "%08x%s", val,
272 data_count > 0 ? ", " : "])\n");
273 data_count--;
274 }
275
276 if (rd_ptr == end)
277 rd_ptr = start;
278 else
279 rd_ptr++;
280 } while (rd_ptr != wr_ptr);
281
282 if (data_count)
283 host1x_debug_output(o, ", ...])\n");
284 host1x_debug_output(o, "\n");
285
286 host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);
287}
288
289static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)
290{
291 unsigned int i;
292
293 host1x_debug_output(o, "---- mlocks ----\n");
294
295 for (i = 0; i < host1x_syncpt_nb_mlocks(host); i++) {
296 u32 owner =
297 host1x_sync_readl(host, HOST1X_SYNC_MLOCK_OWNER(i));
298 if (HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(owner))
299 host1x_debug_output(o, "%u: locked by channel %u\n",
300 i, HOST1X_SYNC_MLOCK_OWNER_CHID_V(owner));
301 else if (HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(owner))
302 host1x_debug_output(o, "%u: locked by cpu\n", i);
303 else
304 host1x_debug_output(o, "%u: unlocked\n", i);
305 }
306
307 host1x_debug_output(o, "\n");
308}
309
310static const struct host1x_debug_ops host1x_debug_ops = {
311 .show_channel_cdma = host1x_debug_show_channel_cdma,
312 .show_channel_fifo = host1x_debug_show_channel_fifo,
313 .show_mlocks = host1x_debug_show_mlocks,
314};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2010 Google, Inc.
4 * Author: Erik Gilling <konkers@android.com>
5 *
6 * Copyright (C) 2011-2013 NVIDIA Corporation
7 */
8
9#include "../dev.h"
10#include "../debug.h"
11#include "../cdma.h"
12#include "../channel.h"
13
14#define HOST1X_DEBUG_MAX_PAGE_OFFSET 102400
15
16enum {
17 HOST1X_OPCODE_SETCLASS = 0x00,
18 HOST1X_OPCODE_INCR = 0x01,
19 HOST1X_OPCODE_NONINCR = 0x02,
20 HOST1X_OPCODE_MASK = 0x03,
21 HOST1X_OPCODE_IMM = 0x04,
22 HOST1X_OPCODE_RESTART = 0x05,
23 HOST1X_OPCODE_GATHER = 0x06,
24 HOST1X_OPCODE_SETSTRMID = 0x07,
25 HOST1X_OPCODE_SETAPPID = 0x08,
26 HOST1X_OPCODE_SETPYLD = 0x09,
27 HOST1X_OPCODE_INCR_W = 0x0a,
28 HOST1X_OPCODE_NONINCR_W = 0x0b,
29 HOST1X_OPCODE_GATHER_W = 0x0c,
30 HOST1X_OPCODE_RESTART_W = 0x0d,
31 HOST1X_OPCODE_EXTEND = 0x0e,
32};
33
34enum {
35 HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK = 0x00,
36 HOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 0x01,
37};
38
39#define INVALID_PAYLOAD 0xffffffff
40
41static unsigned int show_channel_command(struct output *o, u32 val,
42 u32 *payload)
43{
44 unsigned int mask, subop, num, opcode;
45
46 opcode = val >> 28;
47
48 switch (opcode) {
49 case HOST1X_OPCODE_SETCLASS:
50 mask = val & 0x3f;
51 if (mask) {
52 host1x_debug_cont(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [",
53 val >> 6 & 0x3ff,
54 val >> 16 & 0xfff, mask);
55 return hweight8(mask);
56 }
57
58 host1x_debug_cont(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff);
59 return 0;
60
61 case HOST1X_OPCODE_INCR:
62 num = val & 0xffff;
63 host1x_debug_cont(o, "INCR(offset=%03x, [",
64 val >> 16 & 0xfff);
65 if (!num)
66 host1x_debug_cont(o, "])\n");
67
68 return num;
69
70 case HOST1X_OPCODE_NONINCR:
71 num = val & 0xffff;
72 host1x_debug_cont(o, "NONINCR(offset=%03x, [",
73 val >> 16 & 0xfff);
74 if (!num)
75 host1x_debug_cont(o, "])\n");
76
77 return num;
78
79 case HOST1X_OPCODE_MASK:
80 mask = val & 0xffff;
81 host1x_debug_cont(o, "MASK(offset=%03x, mask=%03x, [",
82 val >> 16 & 0xfff, mask);
83 if (!mask)
84 host1x_debug_cont(o, "])\n");
85
86 return hweight16(mask);
87
88 case HOST1X_OPCODE_IMM:
89 host1x_debug_cont(o, "IMM(offset=%03x, data=%03x)\n",
90 val >> 16 & 0xfff, val & 0xffff);
91 return 0;
92
93 case HOST1X_OPCODE_RESTART:
94 host1x_debug_cont(o, "RESTART(offset=%08x)\n", val << 4);
95 return 0;
96
97 case HOST1X_OPCODE_GATHER:
98 host1x_debug_cont(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[",
99 val >> 16 & 0xfff, val >> 15 & 0x1,
100 val >> 14 & 0x1, val & 0x3fff);
101 return 1;
102
103#if HOST1X_HW >= 6
104 case HOST1X_OPCODE_SETSTRMID:
105 host1x_debug_cont(o, "SETSTRMID(offset=%06x)\n",
106 val & 0x3fffff);
107 return 0;
108
109 case HOST1X_OPCODE_SETAPPID:
110 host1x_debug_cont(o, "SETAPPID(appid=%02x)\n", val & 0xff);
111 return 0;
112
113 case HOST1X_OPCODE_SETPYLD:
114 *payload = val & 0xffff;
115 host1x_debug_cont(o, "SETPYLD(data=%04x)\n", *payload);
116 return 0;
117
118 case HOST1X_OPCODE_INCR_W:
119 case HOST1X_OPCODE_NONINCR_W:
120 host1x_debug_cont(o, "%s(offset=%06x, ",
121 opcode == HOST1X_OPCODE_INCR_W ?
122 "INCR_W" : "NONINCR_W",
123 val & 0x3fffff);
124 if (*payload == 0) {
125 host1x_debug_cont(o, "[])\n");
126 return 0;
127 } else if (*payload == INVALID_PAYLOAD) {
128 host1x_debug_cont(o, "unknown)\n");
129 return 0;
130 } else {
131 host1x_debug_cont(o, "[");
132 return *payload;
133 }
134
135 case HOST1X_OPCODE_GATHER_W:
136 host1x_debug_cont(o, "GATHER_W(count=%04x, addr=[",
137 val & 0x3fff);
138 return 2;
139#endif
140
141 case HOST1X_OPCODE_EXTEND:
142 subop = val >> 24 & 0xf;
143 if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)
144 host1x_debug_cont(o, "ACQUIRE_MLOCK(index=%d)\n",
145 val & 0xff);
146 else if (subop == HOST1X_OPCODE_EXTEND_RELEASE_MLOCK)
147 host1x_debug_cont(o, "RELEASE_MLOCK(index=%d)\n",
148 val & 0xff);
149 else
150 host1x_debug_cont(o, "EXTEND_UNKNOWN(%08x)\n", val);
151 return 0;
152
153 default:
154 host1x_debug_cont(o, "UNKNOWN\n");
155 return 0;
156 }
157}
158
159static void show_gather(struct output *o, phys_addr_t phys_addr,
160 unsigned int words, struct host1x_cdma *cdma,
161 phys_addr_t pin_addr, u32 *map_addr)
162{
163 /* Map dmaget cursor to corresponding mem handle */
164 u32 offset = phys_addr - pin_addr;
165 unsigned int data_count = 0, i;
166 u32 payload = INVALID_PAYLOAD;
167
168 /*
169 * Sometimes we're given different hardware address to the same
170 * page - in these cases the offset will get an invalid number and
171 * we just have to bail out.
172 */
173 if (offset > HOST1X_DEBUG_MAX_PAGE_OFFSET) {
174 host1x_debug_output(o, "[address mismatch]\n");
175 return;
176 }
177
178 for (i = 0; i < words; i++) {
179 u32 addr = phys_addr + i * 4;
180 u32 val = *(map_addr + offset / 4 + i);
181
182 if (!data_count) {
183 host1x_debug_output(o, "%08x: %08x: ", addr, val);
184 data_count = show_channel_command(o, val, &payload);
185 } else {
186 host1x_debug_cont(o, "%08x%s", val,
187 data_count > 1 ? ", " : "])\n");
188 data_count--;
189 }
190 }
191}
192
193static void show_channel_gathers(struct output *o, struct host1x_cdma *cdma)
194{
195 struct host1x_job *job;
196
197 list_for_each_entry(job, &cdma->sync_queue, list) {
198 unsigned int i;
199
200 host1x_debug_output(o, "\n%p: JOB, syncpt_id=%d, syncpt_val=%d, first_get=%08x, timeout=%d num_slots=%d, num_handles=%d\n",
201 job, job->syncpt_id, job->syncpt_end,
202 job->first_get, job->timeout,
203 job->num_slots, job->num_unpins);
204
205 for (i = 0; i < job->num_gathers; i++) {
206 struct host1x_job_gather *g = &job->gathers[i];
207 u32 *mapped;
208
209 if (job->gather_copy_mapped)
210 mapped = (u32 *)job->gather_copy_mapped;
211 else
212 mapped = host1x_bo_mmap(g->bo);
213
214 if (!mapped) {
215 host1x_debug_output(o, "[could not mmap]\n");
216 continue;
217 }
218
219 host1x_debug_output(o, " GATHER at %pad+%#x, %d words\n",
220 &g->base, g->offset, g->words);
221
222 show_gather(o, g->base + g->offset, g->words, cdma,
223 g->base, mapped);
224
225 if (!job->gather_copy_mapped)
226 host1x_bo_munmap(g->bo, mapped);
227 }
228 }
229}
230
231#if HOST1X_HW >= 6
232#include "debug_hw_1x06.c"
233#else
234#include "debug_hw_1x01.c"
235#endif
236
237static const struct host1x_debug_ops host1x_debug_ops = {
238 .show_channel_cdma = host1x_debug_show_channel_cdma,
239 .show_channel_fifo = host1x_debug_show_channel_fifo,
240 .show_mlocks = host1x_debug_show_mlocks,
241};