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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_GPU_H__
19#define __MSM_GPU_H__
20
21#include <linux/clk.h>
22#include <linux/regulator/consumer.h>
23
24#include "msm_drv.h"
25#include "msm_fence.h"
26#include "msm_ringbuffer.h"
27
28struct msm_gem_submit;
29struct msm_gpu_perfcntr;
30
31/* So far, with hardware that I've seen to date, we can have:
32 * + zero, one, or two z180 2d cores
33 * + a3xx or a2xx 3d core, which share a common CP (the firmware
34 * for the CP seems to implement some different PM4 packet types
35 * but the basics of cmdstream submission are the same)
36 *
37 * Which means that the eventual complete "class" hierarchy, once
38 * support for all past and present hw is in place, becomes:
39 * + msm_gpu
40 * + adreno_gpu
41 * + a3xx_gpu
42 * + a2xx_gpu
43 * + z180_gpu
44 */
45struct msm_gpu_funcs {
46 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
47 int (*hw_init)(struct msm_gpu *gpu);
48 int (*pm_suspend)(struct msm_gpu *gpu);
49 int (*pm_resume)(struct msm_gpu *gpu);
50 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
51 struct msm_file_private *ctx);
52 void (*flush)(struct msm_gpu *gpu);
53 bool (*idle)(struct msm_gpu *gpu);
54 irqreturn_t (*irq)(struct msm_gpu *irq);
55 uint32_t (*last_fence)(struct msm_gpu *gpu);
56 void (*recover)(struct msm_gpu *gpu);
57 void (*destroy)(struct msm_gpu *gpu);
58#ifdef CONFIG_DEBUG_FS
59 /* show GPU status in debugfs: */
60 void (*show)(struct msm_gpu *gpu, struct seq_file *m);
61#endif
62};
63
64struct msm_gpu {
65 const char *name;
66 struct drm_device *dev;
67 const struct msm_gpu_funcs *funcs;
68
69 /* performance counters (hw & sw): */
70 spinlock_t perf_lock;
71 bool perfcntr_active;
72 struct {
73 bool active;
74 ktime_t time;
75 } last_sample;
76 uint32_t totaltime, activetime; /* sw counters */
77 uint32_t last_cntrs[5]; /* hw counters */
78 const struct msm_gpu_perfcntr *perfcntrs;
79 uint32_t num_perfcntrs;
80
81 /* ringbuffer: */
82 struct msm_ringbuffer *rb;
83 uint64_t rb_iova;
84
85 /* list of GEM active objects: */
86 struct list_head active_list;
87
88 /* fencing: */
89 struct msm_fence_context *fctx;
90
91 /* is gpu powered/active? */
92 int active_cnt;
93 bool inactive;
94
95 /* worker for handling active-list retiring: */
96 struct work_struct retire_work;
97
98 void __iomem *mmio;
99 int irq;
100
101 struct msm_gem_address_space *aspace;
102 int id;
103
104 /* Power Control: */
105 struct regulator *gpu_reg, *gpu_cx;
106 struct clk *ebi1_clk, *grp_clks[6];
107 uint32_t fast_rate, slow_rate, bus_freq;
108
109#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
110 struct msm_bus_scale_pdata *bus_scale_table;
111 uint32_t bsc;
112#endif
113
114 /* Hang and Inactivity Detection:
115 */
116#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
117#define DRM_MSM_INACTIVE_JIFFIES msecs_to_jiffies(DRM_MSM_INACTIVE_PERIOD)
118 struct timer_list inactive_timer;
119 struct work_struct inactive_work;
120#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
121#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
122 struct timer_list hangcheck_timer;
123 uint32_t hangcheck_fence;
124 struct work_struct recover_work;
125
126 struct list_head submit_list;
127};
128
129static inline bool msm_gpu_active(struct msm_gpu *gpu)
130{
131 return gpu->fctx->last_fence > gpu->funcs->last_fence(gpu);
132}
133
134/* Perf-Counters:
135 * The select_reg and select_val are just there for the benefit of the child
136 * class that actually enables the perf counter.. but msm_gpu base class
137 * will handle sampling/displaying the counters.
138 */
139
140struct msm_gpu_perfcntr {
141 uint32_t select_reg;
142 uint32_t sample_reg;
143 uint32_t select_val;
144 const char *name;
145};
146
147static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
148{
149 msm_writel(data, gpu->mmio + (reg << 2));
150}
151
152static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
153{
154 return msm_readl(gpu->mmio + (reg << 2));
155}
156
157static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
158{
159 uint32_t val = gpu_read(gpu, reg);
160
161 val &= ~mask;
162 gpu_write(gpu, reg, val | or);
163}
164
165static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
166{
167 u64 val;
168
169 /*
170 * Why not a readq here? Two reasons: 1) many of the LO registers are
171 * not quad word aligned and 2) the GPU hardware designers have a bit
172 * of a history of putting registers where they fit, especially in
173 * spins. The longer a GPU family goes the higher the chance that
174 * we'll get burned. We could do a series of validity checks if we
175 * wanted to, but really is a readq() that much better? Nah.
176 */
177
178 /*
179 * For some lo/hi registers (like perfcounters), the hi value is latched
180 * when the lo is read, so make sure to read the lo first to trigger
181 * that
182 */
183 val = (u64) msm_readl(gpu->mmio + (lo << 2));
184 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
185
186 return val;
187}
188
189static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
190{
191 /* Why not a writeq here? Read the screed above */
192 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
193 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
194}
195
196int msm_gpu_pm_suspend(struct msm_gpu *gpu);
197int msm_gpu_pm_resume(struct msm_gpu *gpu);
198
199void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
200void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
201int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
202 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
203
204void msm_gpu_retire(struct msm_gpu *gpu);
205void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
206 struct msm_file_private *ctx);
207
208int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
209 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
210 const char *name, const char *ioname, const char *irqname, int ringsz);
211void msm_gpu_cleanup(struct msm_gpu *gpu);
212
213struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
214void __init adreno_register(void);
215void __exit adreno_unregister(void);
216
217#endif /* __MSM_GPU_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#ifndef __MSM_GPU_H__
8#define __MSM_GPU_H__
9
10#include <linux/clk.h>
11#include <linux/interconnect.h>
12#include <linux/regulator/consumer.h>
13
14#include "msm_drv.h"
15#include "msm_fence.h"
16#include "msm_ringbuffer.h"
17
18struct msm_gem_submit;
19struct msm_gpu_perfcntr;
20struct msm_gpu_state;
21
22struct msm_gpu_config {
23 const char *ioname;
24 uint64_t va_start;
25 uint64_t va_end;
26 unsigned int nr_rings;
27};
28
29/* So far, with hardware that I've seen to date, we can have:
30 * + zero, one, or two z180 2d cores
31 * + a3xx or a2xx 3d core, which share a common CP (the firmware
32 * for the CP seems to implement some different PM4 packet types
33 * but the basics of cmdstream submission are the same)
34 *
35 * Which means that the eventual complete "class" hierarchy, once
36 * support for all past and present hw is in place, becomes:
37 * + msm_gpu
38 * + adreno_gpu
39 * + a3xx_gpu
40 * + a2xx_gpu
41 * + z180_gpu
42 */
43struct msm_gpu_funcs {
44 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
45 int (*hw_init)(struct msm_gpu *gpu);
46 int (*pm_suspend)(struct msm_gpu *gpu);
47 int (*pm_resume)(struct msm_gpu *gpu);
48 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
49 struct msm_file_private *ctx);
50 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
51 irqreturn_t (*irq)(struct msm_gpu *irq);
52 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
53 void (*recover)(struct msm_gpu *gpu);
54 void (*destroy)(struct msm_gpu *gpu);
55#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
56 /* show GPU status in debugfs: */
57 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
58 struct drm_printer *p);
59 /* for generation specific debugfs: */
60 int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
61#endif
62 unsigned long (*gpu_busy)(struct msm_gpu *gpu);
63 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
64 int (*gpu_state_put)(struct msm_gpu_state *state);
65 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
66 void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq);
67};
68
69struct msm_gpu {
70 const char *name;
71 struct drm_device *dev;
72 struct platform_device *pdev;
73 const struct msm_gpu_funcs *funcs;
74
75 /* performance counters (hw & sw): */
76 spinlock_t perf_lock;
77 bool perfcntr_active;
78 struct {
79 bool active;
80 ktime_t time;
81 } last_sample;
82 uint32_t totaltime, activetime; /* sw counters */
83 uint32_t last_cntrs[5]; /* hw counters */
84 const struct msm_gpu_perfcntr *perfcntrs;
85 uint32_t num_perfcntrs;
86
87 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
88 int nr_rings;
89
90 /* list of GEM active objects: */
91 struct list_head active_list;
92
93 /* does gpu need hw_init? */
94 bool needs_hw_init;
95
96 /* number of GPU hangs (for all contexts) */
97 int global_faults;
98
99 /* worker for handling active-list retiring: */
100 struct work_struct retire_work;
101
102 void __iomem *mmio;
103 int irq;
104
105 struct msm_gem_address_space *aspace;
106
107 /* Power Control: */
108 struct regulator *gpu_reg, *gpu_cx;
109 struct clk_bulk_data *grp_clks;
110 int nr_clocks;
111 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
112 uint32_t fast_rate;
113
114 struct icc_path *icc_path;
115
116 /* Hang and Inactivity Detection:
117 */
118#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
119
120#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
121#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD)
122 struct timer_list hangcheck_timer;
123 struct work_struct recover_work;
124
125 struct drm_gem_object *memptrs_bo;
126
127 struct {
128 struct devfreq *devfreq;
129 u64 busy_cycles;
130 ktime_t time;
131 } devfreq;
132
133 struct msm_gpu_state *crashstate;
134};
135
136/* It turns out that all targets use the same ringbuffer size */
137#define MSM_GPU_RINGBUFFER_SZ SZ_32K
138#define MSM_GPU_RINGBUFFER_BLKSIZE 32
139
140#define MSM_GPU_RB_CNTL_DEFAULT \
141 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
142 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
143
144static inline bool msm_gpu_active(struct msm_gpu *gpu)
145{
146 int i;
147
148 for (i = 0; i < gpu->nr_rings; i++) {
149 struct msm_ringbuffer *ring = gpu->rb[i];
150
151 if (ring->seqno > ring->memptrs->fence)
152 return true;
153 }
154
155 return false;
156}
157
158/* Perf-Counters:
159 * The select_reg and select_val are just there for the benefit of the child
160 * class that actually enables the perf counter.. but msm_gpu base class
161 * will handle sampling/displaying the counters.
162 */
163
164struct msm_gpu_perfcntr {
165 uint32_t select_reg;
166 uint32_t sample_reg;
167 uint32_t select_val;
168 const char *name;
169};
170
171struct msm_gpu_submitqueue {
172 int id;
173 u32 flags;
174 u32 prio;
175 int faults;
176 struct list_head node;
177 struct kref ref;
178};
179
180struct msm_gpu_state_bo {
181 u64 iova;
182 size_t size;
183 void *data;
184 bool encoded;
185};
186
187struct msm_gpu_state {
188 struct kref ref;
189 struct timespec64 time;
190
191 struct {
192 u64 iova;
193 u32 fence;
194 u32 seqno;
195 u32 rptr;
196 u32 wptr;
197 void *data;
198 int data_size;
199 bool encoded;
200 } ring[MSM_GPU_MAX_RINGS];
201
202 int nr_registers;
203 u32 *registers;
204
205 u32 rbbm_status;
206
207 char *comm;
208 char *cmd;
209
210 int nr_bos;
211 struct msm_gpu_state_bo *bos;
212};
213
214static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
215{
216 msm_writel(data, gpu->mmio + (reg << 2));
217}
218
219static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
220{
221 return msm_readl(gpu->mmio + (reg << 2));
222}
223
224static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
225{
226 uint32_t val = gpu_read(gpu, reg);
227
228 val &= ~mask;
229 gpu_write(gpu, reg, val | or);
230}
231
232static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
233{
234 u64 val;
235
236 /*
237 * Why not a readq here? Two reasons: 1) many of the LO registers are
238 * not quad word aligned and 2) the GPU hardware designers have a bit
239 * of a history of putting registers where they fit, especially in
240 * spins. The longer a GPU family goes the higher the chance that
241 * we'll get burned. We could do a series of validity checks if we
242 * wanted to, but really is a readq() that much better? Nah.
243 */
244
245 /*
246 * For some lo/hi registers (like perfcounters), the hi value is latched
247 * when the lo is read, so make sure to read the lo first to trigger
248 * that
249 */
250 val = (u64) msm_readl(gpu->mmio + (lo << 2));
251 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
252
253 return val;
254}
255
256static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
257{
258 /* Why not a writeq here? Read the screed above */
259 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
260 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
261}
262
263int msm_gpu_pm_suspend(struct msm_gpu *gpu);
264int msm_gpu_pm_resume(struct msm_gpu *gpu);
265void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
266
267int msm_gpu_hw_init(struct msm_gpu *gpu);
268
269void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
270void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
271int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
272 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
273
274void msm_gpu_retire(struct msm_gpu *gpu);
275void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
276 struct msm_file_private *ctx);
277
278int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
279 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
280 const char *name, struct msm_gpu_config *config);
281
282void msm_gpu_cleanup(struct msm_gpu *gpu);
283
284struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
285void __init adreno_register(void);
286void __exit adreno_unregister(void);
287
288static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
289{
290 if (queue)
291 kref_put(&queue->ref, msm_submitqueue_destroy);
292}
293
294static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
295{
296 struct msm_gpu_state *state = NULL;
297
298 mutex_lock(&gpu->dev->struct_mutex);
299
300 if (gpu->crashstate) {
301 kref_get(&gpu->crashstate->ref);
302 state = gpu->crashstate;
303 }
304
305 mutex_unlock(&gpu->dev->struct_mutex);
306
307 return state;
308}
309
310static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
311{
312 mutex_lock(&gpu->dev->struct_mutex);
313
314 if (gpu->crashstate) {
315 if (gpu->funcs->gpu_state_put(gpu->crashstate))
316 gpu->crashstate = NULL;
317 }
318
319 mutex_unlock(&gpu->dev->struct_mutex);
320}
321
322#endif /* __MSM_GPU_H__ */