1/*
   2 * Copyright 2015 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <linux/firmware.h>
  25#include <linux/slab.h>
  26#include <linux/module.h>
  27#include "drmP.h"
 
  28#include "amdgpu.h"
  29#include "amdgpu_atombios.h"
  30#include "amdgpu_ih.h"
  31#include "amdgpu_uvd.h"
  32#include "amdgpu_vce.h"
  33#include "atom.h"
  34#include "amdgpu_powerplay.h"
  35#include "si/sid.h"
 
  36#include "si_ih.h"
  37#include "gfx_v6_0.h"
  38#include "gmc_v6_0.h"
  39#include "si_dma.h"
  40#include "dce_v6_0.h"
  41#include "si.h"
  42#include "dce_virtual.h"
 
 
 
 
 
 
 
  43
  44static const u32 tahiti_golden_registers[] =
  45{
  46	0x17bc, 0x00000030, 0x00000011,
  47	0x2684, 0x00010000, 0x00018208,
  48	0x260c, 0xffffffff, 0x00000000,
  49	0x260d, 0xf00fffff, 0x00000400,
  50	0x260e, 0x0002021c, 0x00020200,
  51	0x031e, 0x00000080, 0x00000000,
  52	0x340c, 0x000000c0, 0x00800040,
  53	0x360c, 0x000000c0, 0x00800040,
  54	0x16ec, 0x000000f0, 0x00000070,
  55	0x16f0, 0x00200000, 0x50100000,
  56	0x1c0c, 0x31000311, 0x00000011,
  57	0x09df, 0x00000003, 0x000007ff,
  58	0x0903, 0x000007ff, 0x00000000,
  59	0x2285, 0xf000001f, 0x00000007,
  60	0x22c9, 0xffffffff, 0x00ffffff,
  61	0x22c4, 0x0000ff0f, 0x00000000,
  62	0xa293, 0x07ffffff, 0x4e000000,
  63	0xa0d4, 0x3f3f3fff, 0x2a00126a,
  64	0x000c, 0xffffffff, 0x0040,
  65	0x000d, 0x00000040, 0x00004040,
  66	0x2440, 0x07ffffff, 0x03000000,
  67	0x23a2, 0x01ff1f3f, 0x00000000,
  68	0x23a1, 0x01ff1f3f, 0x00000000,
  69	0x2418, 0x0000007f, 0x00000020,
  70	0x2542, 0x00010000, 0x00010000,
  71	0x2b05, 0x00000200, 0x000002fb,
  72	0x2b04, 0xffffffff, 0x0000543b,
  73	0x2b03, 0xffffffff, 0xa9210876,
  74	0x2234, 0xffffffff, 0x000fff40,
  75	0x2235, 0x0000001f, 0x00000010,
  76	0x0504, 0x20000000, 0x20fffed8,
  77	0x0570, 0x000c0fc0, 0x000c0400,
  78	0x052c, 0x0fffffff, 0xffffffff,
  79	0x052d, 0x0fffffff, 0x0fffffff,
  80	0x052e, 0x0fffffff, 0x0fffffff,
  81	0x052f, 0x0fffffff, 0x0fffffff
  82};
  83
  84static const u32 tahiti_golden_registers2[] =
  85{
  86	0x0319, 0x00000001, 0x00000001
  87};
  88
  89static const u32 tahiti_golden_rlc_registers[] =
  90{
  91	0x263e, 0xffffffff, 0x12011003,
  92	0x3109, 0xffffffff, 0x00601005,
  93	0x311f, 0xffffffff, 0x10104040,
  94	0x3122, 0xffffffff, 0x0100000a,
  95	0x30c5, 0xffffffff, 0x00000800,
  96	0x30c3, 0xffffffff, 0x800000f4,
  97	0x3d2a, 0x00000008, 0x00000000
  98};
  99
 100static const u32 pitcairn_golden_registers[] =
 101{
 102	0x17bc, 0x00000030, 0x00000011,
 103	0x2684, 0x00010000, 0x00018208,
 104	0x260c, 0xffffffff, 0x00000000,
 105	0x260d, 0xf00fffff, 0x00000400,
 106	0x260e, 0x0002021c, 0x00020200,
 107	0x031e, 0x00000080, 0x00000000,
 108	0x340c, 0x000300c0, 0x00800040,
 109	0x360c, 0x000300c0, 0x00800040,
 110	0x16ec, 0x000000f0, 0x00000070,
 111	0x16f0, 0x00200000, 0x50100000,
 112	0x1c0c, 0x31000311, 0x00000011,
 113	0x0ab9, 0x00073ffe, 0x000022a2,
 114	0x0903, 0x000007ff, 0x00000000,
 115	0x2285, 0xf000001f, 0x00000007,
 116	0x22c9, 0xffffffff, 0x00ffffff,
 117	0x22c4, 0x0000ff0f, 0x00000000,
 118	0xa293, 0x07ffffff, 0x4e000000,
 119	0xa0d4, 0x3f3f3fff, 0x2a00126a,
 120	0x000c, 0xffffffff, 0x0040,
 121	0x000d, 0x00000040, 0x00004040,
 122	0x2440, 0x07ffffff, 0x03000000,
 123	0x2418, 0x0000007f, 0x00000020,
 124	0x2542, 0x00010000, 0x00010000,
 125	0x2b05, 0x000003ff, 0x000000f7,
 126	0x2b04, 0xffffffff, 0x00000000,
 127	0x2b03, 0xffffffff, 0x32761054,
 128	0x2235, 0x0000001f, 0x00000010,
 129	0x0570, 0x000c0fc0, 0x000c0400,
 130	0x052c, 0x0fffffff, 0xffffffff,
 131	0x052d, 0x0fffffff, 0x0fffffff,
 132	0x052e, 0x0fffffff, 0x0fffffff,
 133	0x052f, 0x0fffffff, 0x0fffffff
 134};
 135
 136static const u32 pitcairn_golden_rlc_registers[] =
 137{
 138	0x263e, 0xffffffff, 0x12011003,
 139	0x3109, 0xffffffff, 0x00601004,
 140	0x311f, 0xffffffff, 0x10102020,
 141	0x3122, 0xffffffff, 0x01000020,
 142	0x30c5, 0xffffffff, 0x00000800,
 143	0x30c3, 0xffffffff, 0x800000a4
 144};
 145
 146static const u32 verde_pg_init[] =
 147{
 148	0x0d4f, 0xffffffff, 0x40000,
 149	0x0d4e, 0xffffffff, 0x200010ff,
 150	0x0d4f, 0xffffffff, 0x0,
 151	0x0d4f, 0xffffffff, 0x0,
 152	0x0d4f, 0xffffffff, 0x0,
 153	0x0d4f, 0xffffffff, 0x0,
 154	0x0d4f, 0xffffffff, 0x0,
 155	0x0d4f, 0xffffffff, 0x7007,
 156	0x0d4e, 0xffffffff, 0x300010ff,
 157	0x0d4f, 0xffffffff, 0x0,
 158	0x0d4f, 0xffffffff, 0x0,
 159	0x0d4f, 0xffffffff, 0x0,
 160	0x0d4f, 0xffffffff, 0x0,
 161	0x0d4f, 0xffffffff, 0x0,
 162	0x0d4f, 0xffffffff, 0x400000,
 163	0x0d4e, 0xffffffff, 0x100010ff,
 164	0x0d4f, 0xffffffff, 0x0,
 165	0x0d4f, 0xffffffff, 0x0,
 166	0x0d4f, 0xffffffff, 0x0,
 167	0x0d4f, 0xffffffff, 0x0,
 168	0x0d4f, 0xffffffff, 0x0,
 169	0x0d4f, 0xffffffff, 0x120200,
 170	0x0d4e, 0xffffffff, 0x500010ff,
 171	0x0d4f, 0xffffffff, 0x0,
 172	0x0d4f, 0xffffffff, 0x0,
 173	0x0d4f, 0xffffffff, 0x0,
 174	0x0d4f, 0xffffffff, 0x0,
 175	0x0d4f, 0xffffffff, 0x0,
 176	0x0d4f, 0xffffffff, 0x1e1e16,
 177	0x0d4e, 0xffffffff, 0x600010ff,
 178	0x0d4f, 0xffffffff, 0x0,
 179	0x0d4f, 0xffffffff, 0x0,
 180	0x0d4f, 0xffffffff, 0x0,
 181	0x0d4f, 0xffffffff, 0x0,
 182	0x0d4f, 0xffffffff, 0x0,
 183	0x0d4f, 0xffffffff, 0x171f1e,
 184	0x0d4e, 0xffffffff, 0x700010ff,
 185	0x0d4f, 0xffffffff, 0x0,
 186	0x0d4f, 0xffffffff, 0x0,
 187	0x0d4f, 0xffffffff, 0x0,
 188	0x0d4f, 0xffffffff, 0x0,
 189	0x0d4f, 0xffffffff, 0x0,
 190	0x0d4f, 0xffffffff, 0x0,
 191	0x0d4e, 0xffffffff, 0x9ff,
 192	0x0d40, 0xffffffff, 0x0,
 193	0x0d41, 0xffffffff, 0x10000800,
 194	0x0d41, 0xffffffff, 0xf,
 195	0x0d41, 0xffffffff, 0xf,
 196	0x0d40, 0xffffffff, 0x4,
 197	0x0d41, 0xffffffff, 0x1000051e,
 198	0x0d41, 0xffffffff, 0xffff,
 199	0x0d41, 0xffffffff, 0xffff,
 200	0x0d40, 0xffffffff, 0x8,
 201	0x0d41, 0xffffffff, 0x80500,
 202	0x0d40, 0xffffffff, 0x12,
 203	0x0d41, 0xffffffff, 0x9050c,
 204	0x0d40, 0xffffffff, 0x1d,
 205	0x0d41, 0xffffffff, 0xb052c,
 206	0x0d40, 0xffffffff, 0x2a,
 207	0x0d41, 0xffffffff, 0x1053e,
 208	0x0d40, 0xffffffff, 0x2d,
 209	0x0d41, 0xffffffff, 0x10546,
 210	0x0d40, 0xffffffff, 0x30,
 211	0x0d41, 0xffffffff, 0xa054e,
 212	0x0d40, 0xffffffff, 0x3c,
 213	0x0d41, 0xffffffff, 0x1055f,
 214	0x0d40, 0xffffffff, 0x3f,
 215	0x0d41, 0xffffffff, 0x10567,
 216	0x0d40, 0xffffffff, 0x42,
 217	0x0d41, 0xffffffff, 0x1056f,
 218	0x0d40, 0xffffffff, 0x45,
 219	0x0d41, 0xffffffff, 0x10572,
 220	0x0d40, 0xffffffff, 0x48,
 221	0x0d41, 0xffffffff, 0x20575,
 222	0x0d40, 0xffffffff, 0x4c,
 223	0x0d41, 0xffffffff, 0x190801,
 224	0x0d40, 0xffffffff, 0x67,
 225	0x0d41, 0xffffffff, 0x1082a,
 226	0x0d40, 0xffffffff, 0x6a,
 227	0x0d41, 0xffffffff, 0x1b082d,
 228	0x0d40, 0xffffffff, 0x87,
 229	0x0d41, 0xffffffff, 0x310851,
 230	0x0d40, 0xffffffff, 0xba,
 231	0x0d41, 0xffffffff, 0x891,
 232	0x0d40, 0xffffffff, 0xbc,
 233	0x0d41, 0xffffffff, 0x893,
 234	0x0d40, 0xffffffff, 0xbe,
 235	0x0d41, 0xffffffff, 0x20895,
 236	0x0d40, 0xffffffff, 0xc2,
 237	0x0d41, 0xffffffff, 0x20899,
 238	0x0d40, 0xffffffff, 0xc6,
 239	0x0d41, 0xffffffff, 0x2089d,
 240	0x0d40, 0xffffffff, 0xca,
 241	0x0d41, 0xffffffff, 0x8a1,
 242	0x0d40, 0xffffffff, 0xcc,
 243	0x0d41, 0xffffffff, 0x8a3,
 244	0x0d40, 0xffffffff, 0xce,
 245	0x0d41, 0xffffffff, 0x308a5,
 246	0x0d40, 0xffffffff, 0xd3,
 247	0x0d41, 0xffffffff, 0x6d08cd,
 248	0x0d40, 0xffffffff, 0x142,
 249	0x0d41, 0xffffffff, 0x2000095a,
 250	0x0d41, 0xffffffff, 0x1,
 251	0x0d40, 0xffffffff, 0x144,
 252	0x0d41, 0xffffffff, 0x301f095b,
 253	0x0d40, 0xffffffff, 0x165,
 254	0x0d41, 0xffffffff, 0xc094d,
 255	0x0d40, 0xffffffff, 0x173,
 256	0x0d41, 0xffffffff, 0xf096d,
 257	0x0d40, 0xffffffff, 0x184,
 258	0x0d41, 0xffffffff, 0x15097f,
 259	0x0d40, 0xffffffff, 0x19b,
 260	0x0d41, 0xffffffff, 0xc0998,
 261	0x0d40, 0xffffffff, 0x1a9,
 262	0x0d41, 0xffffffff, 0x409a7,
 263	0x0d40, 0xffffffff, 0x1af,
 264	0x0d41, 0xffffffff, 0xcdc,
 265	0x0d40, 0xffffffff, 0x1b1,
 266	0x0d41, 0xffffffff, 0x800,
 267	0x0d42, 0xffffffff, 0x6c9b2000,
 268	0x0d44, 0xfc00, 0x2000,
 269	0x0d51, 0xffffffff, 0xfc0,
 270	0x0a35, 0x00000100, 0x100
 271};
 272
 273static const u32 verde_golden_rlc_registers[] =
 274{
 275	0x263e, 0xffffffff, 0x02010002,
 276	0x3109, 0xffffffff, 0x033f1005,
 277	0x311f, 0xffffffff, 0x10808020,
 278	0x3122, 0xffffffff, 0x00800008,
 279	0x30c5, 0xffffffff, 0x00001000,
 280	0x30c3, 0xffffffff, 0x80010014
 281};
 282
 283static const u32 verde_golden_registers[] =
 284{
 285	0x17bc, 0x00000030, 0x00000011,
 286	0x2684, 0x00010000, 0x00018208,
 287	0x260c, 0xffffffff, 0x00000000,
 288	0x260d, 0xf00fffff, 0x00000400,
 289	0x260e, 0x0002021c, 0x00020200,
 290	0x031e, 0x00000080, 0x00000000,
 291	0x340c, 0x000300c0, 0x00800040,
 292	0x360c, 0x000300c0, 0x00800040,
 293	0x16ec, 0x000000f0, 0x00000070,
 294	0x16f0, 0x00200000, 0x50100000,
 295	0x1c0c, 0x31000311, 0x00000011,
 296	0x0ab9, 0x00073ffe, 0x000022a2,
 297	0x0903, 0x000007ff, 0x00000000,
 298	0x2285, 0xf000001f, 0x00000007,
 299	0x22c9, 0xffffffff, 0x00ffffff,
 300	0x22c4, 0x0000ff0f, 0x00000000,
 301	0xa293, 0x07ffffff, 0x4e000000,
 302	0xa0d4, 0x3f3f3fff, 0x0000124a,
 303	0x000c, 0xffffffff, 0x0040,
 304	0x000d, 0x00000040, 0x00004040,
 305	0x2440, 0x07ffffff, 0x03000000,
 306	0x23a2, 0x01ff1f3f, 0x00000000,
 307	0x23a1, 0x01ff1f3f, 0x00000000,
 308	0x2418, 0x0000007f, 0x00000020,
 309	0x2542, 0x00010000, 0x00010000,
 310	0x2b05, 0x000003ff, 0x00000003,
 311	0x2b04, 0xffffffff, 0x00000000,
 312	0x2b03, 0xffffffff, 0x00001032,
 313	0x2235, 0x0000001f, 0x00000010,
 314	0x0570, 0x000c0fc0, 0x000c0400,
 315	0x052c, 0x0fffffff, 0xffffffff,
 316	0x052d, 0x0fffffff, 0x0fffffff,
 317	0x052e, 0x0fffffff, 0x0fffffff,
 318	0x052f, 0x0fffffff, 0x0fffffff
 319};
 320
 321static const u32 oland_golden_registers[] =
 322{
 323	0x17bc, 0x00000030, 0x00000011,
 324	0x2684, 0x00010000, 0x00018208,
 325	0x260c, 0xffffffff, 0x00000000,
 326	0x260d, 0xf00fffff, 0x00000400,
 327	0x260e, 0x0002021c, 0x00020200,
 328	0x031e, 0x00000080, 0x00000000,
 329	0x340c, 0x000300c0, 0x00800040,
 330	0x360c, 0x000300c0, 0x00800040,
 331	0x16ec, 0x000000f0, 0x00000070,
 332	0x16f0, 0x00200000, 0x50100000,
 333	0x1c0c, 0x31000311, 0x00000011,
 334	0x0ab9, 0x00073ffe, 0x000022a2,
 335	0x0903, 0x000007ff, 0x00000000,
 336	0x2285, 0xf000001f, 0x00000007,
 337	0x22c9, 0xffffffff, 0x00ffffff,
 338	0x22c4, 0x0000ff0f, 0x00000000,
 339	0xa293, 0x07ffffff, 0x4e000000,
 340	0xa0d4, 0x3f3f3fff, 0x00000082,
 341	0x000c, 0xffffffff, 0x0040,
 342	0x000d, 0x00000040, 0x00004040,
 343	0x2440, 0x07ffffff, 0x03000000,
 344	0x2418, 0x0000007f, 0x00000020,
 345	0x2542, 0x00010000, 0x00010000,
 346	0x2b05, 0x000003ff, 0x000000f3,
 347	0x2b04, 0xffffffff, 0x00000000,
 348	0x2b03, 0xffffffff, 0x00003210,
 349	0x2235, 0x0000001f, 0x00000010,
 350	0x0570, 0x000c0fc0, 0x000c0400,
 351	0x052c, 0x0fffffff, 0xffffffff,
 352	0x052d, 0x0fffffff, 0x0fffffff,
 353	0x052e, 0x0fffffff, 0x0fffffff,
 354	0x052f, 0x0fffffff, 0x0fffffff
 
 355};
 356
 357static const u32 oland_golden_rlc_registers[] =
 358{
 359	0x263e, 0xffffffff, 0x02010002,
 360	0x3109, 0xffffffff, 0x00601005,
 361	0x311f, 0xffffffff, 0x10104040,
 362	0x3122, 0xffffffff, 0x0100000a,
 363	0x30c5, 0xffffffff, 0x00000800,
 364	0x30c3, 0xffffffff, 0x800000f4
 365};
 366
 367static const u32 hainan_golden_registers[] =
 368{
 369	0x17bc, 0x00000030, 0x00000011,
 370	0x2684, 0x00010000, 0x00018208,
 371	0x260c, 0xffffffff, 0x00000000,
 372	0x260d, 0xf00fffff, 0x00000400,
 373	0x260e, 0x0002021c, 0x00020200,
 374	0x031e, 0x00000080, 0x00000000,
 375	0x3430, 0xff000fff, 0x00000100,
 376	0x340c, 0x000300c0, 0x00800040,
 377	0x3630, 0xff000fff, 0x00000100,
 378	0x360c, 0x000300c0, 0x00800040,
 379	0x16ec, 0x000000f0, 0x00000070,
 380	0x16f0, 0x00200000, 0x50100000,
 381	0x1c0c, 0x31000311, 0x00000011,
 382	0x0ab9, 0x00073ffe, 0x000022a2,
 383	0x0903, 0x000007ff, 0x00000000,
 384	0x2285, 0xf000001f, 0x00000007,
 385	0x22c9, 0xffffffff, 0x00ffffff,
 386	0x22c4, 0x0000ff0f, 0x00000000,
 387	0xa293, 0x07ffffff, 0x4e000000,
 388	0xa0d4, 0x3f3f3fff, 0x00000000,
 389	0x000c, 0xffffffff, 0x0040,
 390	0x000d, 0x00000040, 0x00004040,
 391	0x2440, 0x03e00000, 0x03600000,
 392	0x2418, 0x0000007f, 0x00000020,
 393	0x2542, 0x00010000, 0x00010000,
 394	0x2b05, 0x000003ff, 0x000000f1,
 395	0x2b04, 0xffffffff, 0x00000000,
 396	0x2b03, 0xffffffff, 0x00003210,
 397	0x2235, 0x0000001f, 0x00000010,
 398	0x0570, 0x000c0fc0, 0x000c0400,
 399	0x052c, 0x0fffffff, 0xffffffff,
 400	0x052d, 0x0fffffff, 0x0fffffff,
 401	0x052e, 0x0fffffff, 0x0fffffff,
 402	0x052f, 0x0fffffff, 0x0fffffff
 403};
 404
 405static const u32 hainan_golden_registers2[] =
 406{
 407	0x263e, 0xffffffff, 0x2011003
 408};
 409
 410static const u32 tahiti_mgcg_cgcg_init[] =
 411{
 412	0x3100, 0xffffffff, 0xfffffffc,
 413	0x200b, 0xffffffff, 0xe0000000,
 414	0x2698, 0xffffffff, 0x00000100,
 415	0x24a9, 0xffffffff, 0x00000100,
 416	0x3059, 0xffffffff, 0x00000100,
 417	0x25dd, 0xffffffff, 0x00000100,
 418	0x2261, 0xffffffff, 0x06000100,
 419	0x2286, 0xffffffff, 0x00000100,
 420	0x24a8, 0xffffffff, 0x00000100,
 421	0x30e0, 0xffffffff, 0x00000100,
 422	0x22ca, 0xffffffff, 0x00000100,
 423	0x2451, 0xffffffff, 0x00000100,
 424	0x2362, 0xffffffff, 0x00000100,
 425	0x2363, 0xffffffff, 0x00000100,
 426	0x240c, 0xffffffff, 0x00000100,
 427	0x240d, 0xffffffff, 0x00000100,
 428	0x240e, 0xffffffff, 0x00000100,
 429	0x240f, 0xffffffff, 0x00000100,
 430	0x2b60, 0xffffffff, 0x00000100,
 431	0x2b15, 0xffffffff, 0x00000100,
 432	0x225f, 0xffffffff, 0x06000100,
 433	0x261a, 0xffffffff, 0x00000100,
 434	0x2544, 0xffffffff, 0x00000100,
 435	0x2bc1, 0xffffffff, 0x00000100,
 436	0x2b81, 0xffffffff, 0x00000100,
 437	0x2527, 0xffffffff, 0x00000100,
 438	0x200b, 0xffffffff, 0xe0000000,
 439	0x2458, 0xffffffff, 0x00010000,
 440	0x2459, 0xffffffff, 0x00030002,
 441	0x245a, 0xffffffff, 0x00040007,
 442	0x245b, 0xffffffff, 0x00060005,
 443	0x245c, 0xffffffff, 0x00090008,
 444	0x245d, 0xffffffff, 0x00020001,
 445	0x245e, 0xffffffff, 0x00040003,
 446	0x245f, 0xffffffff, 0x00000007,
 447	0x2460, 0xffffffff, 0x00060005,
 448	0x2461, 0xffffffff, 0x00090008,
 449	0x2462, 0xffffffff, 0x00030002,
 450	0x2463, 0xffffffff, 0x00050004,
 451	0x2464, 0xffffffff, 0x00000008,
 452	0x2465, 0xffffffff, 0x00070006,
 453	0x2466, 0xffffffff, 0x000a0009,
 454	0x2467, 0xffffffff, 0x00040003,
 455	0x2468, 0xffffffff, 0x00060005,
 456	0x2469, 0xffffffff, 0x00000009,
 457	0x246a, 0xffffffff, 0x00080007,
 458	0x246b, 0xffffffff, 0x000b000a,
 459	0x246c, 0xffffffff, 0x00050004,
 460	0x246d, 0xffffffff, 0x00070006,
 461	0x246e, 0xffffffff, 0x0008000b,
 462	0x246f, 0xffffffff, 0x000a0009,
 463	0x2470, 0xffffffff, 0x000d000c,
 464	0x2471, 0xffffffff, 0x00060005,
 465	0x2472, 0xffffffff, 0x00080007,
 466	0x2473, 0xffffffff, 0x0000000b,
 467	0x2474, 0xffffffff, 0x000a0009,
 468	0x2475, 0xffffffff, 0x000d000c,
 469	0x2476, 0xffffffff, 0x00070006,
 470	0x2477, 0xffffffff, 0x00090008,
 471	0x2478, 0xffffffff, 0x0000000c,
 472	0x2479, 0xffffffff, 0x000b000a,
 473	0x247a, 0xffffffff, 0x000e000d,
 474	0x247b, 0xffffffff, 0x00080007,
 475	0x247c, 0xffffffff, 0x000a0009,
 476	0x247d, 0xffffffff, 0x0000000d,
 477	0x247e, 0xffffffff, 0x000c000b,
 478	0x247f, 0xffffffff, 0x000f000e,
 479	0x2480, 0xffffffff, 0x00090008,
 480	0x2481, 0xffffffff, 0x000b000a,
 481	0x2482, 0xffffffff, 0x000c000f,
 482	0x2483, 0xffffffff, 0x000e000d,
 483	0x2484, 0xffffffff, 0x00110010,
 484	0x2485, 0xffffffff, 0x000a0009,
 485	0x2486, 0xffffffff, 0x000c000b,
 486	0x2487, 0xffffffff, 0x0000000f,
 487	0x2488, 0xffffffff, 0x000e000d,
 488	0x2489, 0xffffffff, 0x00110010,
 489	0x248a, 0xffffffff, 0x000b000a,
 490	0x248b, 0xffffffff, 0x000d000c,
 491	0x248c, 0xffffffff, 0x00000010,
 492	0x248d, 0xffffffff, 0x000f000e,
 493	0x248e, 0xffffffff, 0x00120011,
 494	0x248f, 0xffffffff, 0x000c000b,
 495	0x2490, 0xffffffff, 0x000e000d,
 496	0x2491, 0xffffffff, 0x00000011,
 497	0x2492, 0xffffffff, 0x0010000f,
 498	0x2493, 0xffffffff, 0x00130012,
 499	0x2494, 0xffffffff, 0x000d000c,
 500	0x2495, 0xffffffff, 0x000f000e,
 501	0x2496, 0xffffffff, 0x00100013,
 502	0x2497, 0xffffffff, 0x00120011,
 503	0x2498, 0xffffffff, 0x00150014,
 504	0x2499, 0xffffffff, 0x000e000d,
 505	0x249a, 0xffffffff, 0x0010000f,
 506	0x249b, 0xffffffff, 0x00000013,
 507	0x249c, 0xffffffff, 0x00120011,
 508	0x249d, 0xffffffff, 0x00150014,
 509	0x249e, 0xffffffff, 0x000f000e,
 510	0x249f, 0xffffffff, 0x00110010,
 511	0x24a0, 0xffffffff, 0x00000014,
 512	0x24a1, 0xffffffff, 0x00130012,
 513	0x24a2, 0xffffffff, 0x00160015,
 514	0x24a3, 0xffffffff, 0x0010000f,
 515	0x24a4, 0xffffffff, 0x00120011,
 516	0x24a5, 0xffffffff, 0x00000015,
 517	0x24a6, 0xffffffff, 0x00140013,
 518	0x24a7, 0xffffffff, 0x00170016,
 519	0x2454, 0xffffffff, 0x96940200,
 520	0x21c2, 0xffffffff, 0x00900100,
 521	0x311e, 0xffffffff, 0x00000080,
 522	0x3101, 0xffffffff, 0x0020003f,
 523	0x000c, 0xffffffff, 0x0000001c,
 524	0x000d, 0x000f0000, 0x000f0000,
 525	0x0583, 0xffffffff, 0x00000100,
 526	0x0409, 0xffffffff, 0x00000100,
 527	0x040b, 0x00000101, 0x00000000,
 528	0x082a, 0xffffffff, 0x00000104,
 529	0x0993, 0x000c0000, 0x000c0000,
 530	0x0992, 0x000c0000, 0x000c0000,
 531	0x1579, 0xff000fff, 0x00000100,
 532	0x157a, 0x00000001, 0x00000001,
 533	0x0bd4, 0x00000001, 0x00000001,
 534	0x0c33, 0xc0000fff, 0x00000104,
 535	0x3079, 0x00000001, 0x00000001,
 536	0x3430, 0xfffffff0, 0x00000100,
 537	0x3630, 0xfffffff0, 0x00000100
 538};
 539static const u32 pitcairn_mgcg_cgcg_init[] =
 540{
 541	0x3100, 0xffffffff, 0xfffffffc,
 542	0x200b, 0xffffffff, 0xe0000000,
 543	0x2698, 0xffffffff, 0x00000100,
 544	0x24a9, 0xffffffff, 0x00000100,
 545	0x3059, 0xffffffff, 0x00000100,
 546	0x25dd, 0xffffffff, 0x00000100,
 547	0x2261, 0xffffffff, 0x06000100,
 548	0x2286, 0xffffffff, 0x00000100,
 549	0x24a8, 0xffffffff, 0x00000100,
 550	0x30e0, 0xffffffff, 0x00000100,
 551	0x22ca, 0xffffffff, 0x00000100,
 552	0x2451, 0xffffffff, 0x00000100,
 553	0x2362, 0xffffffff, 0x00000100,
 554	0x2363, 0xffffffff, 0x00000100,
 555	0x240c, 0xffffffff, 0x00000100,
 556	0x240d, 0xffffffff, 0x00000100,
 557	0x240e, 0xffffffff, 0x00000100,
 558	0x240f, 0xffffffff, 0x00000100,
 559	0x2b60, 0xffffffff, 0x00000100,
 560	0x2b15, 0xffffffff, 0x00000100,
 561	0x225f, 0xffffffff, 0x06000100,
 562	0x261a, 0xffffffff, 0x00000100,
 563	0x2544, 0xffffffff, 0x00000100,
 564	0x2bc1, 0xffffffff, 0x00000100,
 565	0x2b81, 0xffffffff, 0x00000100,
 566	0x2527, 0xffffffff, 0x00000100,
 567	0x200b, 0xffffffff, 0xe0000000,
 568	0x2458, 0xffffffff, 0x00010000,
 569	0x2459, 0xffffffff, 0x00030002,
 570	0x245a, 0xffffffff, 0x00040007,
 571	0x245b, 0xffffffff, 0x00060005,
 572	0x245c, 0xffffffff, 0x00090008,
 573	0x245d, 0xffffffff, 0x00020001,
 574	0x245e, 0xffffffff, 0x00040003,
 575	0x245f, 0xffffffff, 0x00000007,
 576	0x2460, 0xffffffff, 0x00060005,
 577	0x2461, 0xffffffff, 0x00090008,
 578	0x2462, 0xffffffff, 0x00030002,
 579	0x2463, 0xffffffff, 0x00050004,
 580	0x2464, 0xffffffff, 0x00000008,
 581	0x2465, 0xffffffff, 0x00070006,
 582	0x2466, 0xffffffff, 0x000a0009,
 583	0x2467, 0xffffffff, 0x00040003,
 584	0x2468, 0xffffffff, 0x00060005,
 585	0x2469, 0xffffffff, 0x00000009,
 586	0x246a, 0xffffffff, 0x00080007,
 587	0x246b, 0xffffffff, 0x000b000a,
 588	0x246c, 0xffffffff, 0x00050004,
 589	0x246d, 0xffffffff, 0x00070006,
 590	0x246e, 0xffffffff, 0x0008000b,
 591	0x246f, 0xffffffff, 0x000a0009,
 592	0x2470, 0xffffffff, 0x000d000c,
 593	0x2480, 0xffffffff, 0x00090008,
 594	0x2481, 0xffffffff, 0x000b000a,
 595	0x2482, 0xffffffff, 0x000c000f,
 596	0x2483, 0xffffffff, 0x000e000d,
 597	0x2484, 0xffffffff, 0x00110010,
 598	0x2485, 0xffffffff, 0x000a0009,
 599	0x2486, 0xffffffff, 0x000c000b,
 600	0x2487, 0xffffffff, 0x0000000f,
 601	0x2488, 0xffffffff, 0x000e000d,
 602	0x2489, 0xffffffff, 0x00110010,
 603	0x248a, 0xffffffff, 0x000b000a,
 604	0x248b, 0xffffffff, 0x000d000c,
 605	0x248c, 0xffffffff, 0x00000010,
 606	0x248d, 0xffffffff, 0x000f000e,
 607	0x248e, 0xffffffff, 0x00120011,
 608	0x248f, 0xffffffff, 0x000c000b,
 609	0x2490, 0xffffffff, 0x000e000d,
 610	0x2491, 0xffffffff, 0x00000011,
 611	0x2492, 0xffffffff, 0x0010000f,
 612	0x2493, 0xffffffff, 0x00130012,
 613	0x2494, 0xffffffff, 0x000d000c,
 614	0x2495, 0xffffffff, 0x000f000e,
 615	0x2496, 0xffffffff, 0x00100013,
 616	0x2497, 0xffffffff, 0x00120011,
 617	0x2498, 0xffffffff, 0x00150014,
 618	0x2454, 0xffffffff, 0x96940200,
 619	0x21c2, 0xffffffff, 0x00900100,
 620	0x311e, 0xffffffff, 0x00000080,
 621	0x3101, 0xffffffff, 0x0020003f,
 622	0x000c, 0xffffffff, 0x0000001c,
 623	0x000d, 0x000f0000, 0x000f0000,
 624	0x0583, 0xffffffff, 0x00000100,
 625	0x0409, 0xffffffff, 0x00000100,
 626	0x040b, 0x00000101, 0x00000000,
 627	0x082a, 0xffffffff, 0x00000104,
 628	0x1579, 0xff000fff, 0x00000100,
 629	0x157a, 0x00000001, 0x00000001,
 630	0x0bd4, 0x00000001, 0x00000001,
 631	0x0c33, 0xc0000fff, 0x00000104,
 632	0x3079, 0x00000001, 0x00000001,
 633	0x3430, 0xfffffff0, 0x00000100,
 634	0x3630, 0xfffffff0, 0x00000100
 635};
 
 636static const u32 verde_mgcg_cgcg_init[] =
 637{
 638	0x3100, 0xffffffff, 0xfffffffc,
 639	0x200b, 0xffffffff, 0xe0000000,
 640	0x2698, 0xffffffff, 0x00000100,
 641	0x24a9, 0xffffffff, 0x00000100,
 642	0x3059, 0xffffffff, 0x00000100,
 643	0x25dd, 0xffffffff, 0x00000100,
 644	0x2261, 0xffffffff, 0x06000100,
 645	0x2286, 0xffffffff, 0x00000100,
 646	0x24a8, 0xffffffff, 0x00000100,
 647	0x30e0, 0xffffffff, 0x00000100,
 648	0x22ca, 0xffffffff, 0x00000100,
 649	0x2451, 0xffffffff, 0x00000100,
 650	0x2362, 0xffffffff, 0x00000100,
 651	0x2363, 0xffffffff, 0x00000100,
 652	0x240c, 0xffffffff, 0x00000100,
 653	0x240d, 0xffffffff, 0x00000100,
 654	0x240e, 0xffffffff, 0x00000100,
 655	0x240f, 0xffffffff, 0x00000100,
 656	0x2b60, 0xffffffff, 0x00000100,
 657	0x2b15, 0xffffffff, 0x00000100,
 658	0x225f, 0xffffffff, 0x06000100,
 659	0x261a, 0xffffffff, 0x00000100,
 660	0x2544, 0xffffffff, 0x00000100,
 661	0x2bc1, 0xffffffff, 0x00000100,
 662	0x2b81, 0xffffffff, 0x00000100,
 663	0x2527, 0xffffffff, 0x00000100,
 664	0x200b, 0xffffffff, 0xe0000000,
 665	0x2458, 0xffffffff, 0x00010000,
 666	0x2459, 0xffffffff, 0x00030002,
 667	0x245a, 0xffffffff, 0x00040007,
 668	0x245b, 0xffffffff, 0x00060005,
 669	0x245c, 0xffffffff, 0x00090008,
 670	0x245d, 0xffffffff, 0x00020001,
 671	0x245e, 0xffffffff, 0x00040003,
 672	0x245f, 0xffffffff, 0x00000007,
 673	0x2460, 0xffffffff, 0x00060005,
 674	0x2461, 0xffffffff, 0x00090008,
 675	0x2462, 0xffffffff, 0x00030002,
 676	0x2463, 0xffffffff, 0x00050004,
 677	0x2464, 0xffffffff, 0x00000008,
 678	0x2465, 0xffffffff, 0x00070006,
 679	0x2466, 0xffffffff, 0x000a0009,
 680	0x2467, 0xffffffff, 0x00040003,
 681	0x2468, 0xffffffff, 0x00060005,
 682	0x2469, 0xffffffff, 0x00000009,
 683	0x246a, 0xffffffff, 0x00080007,
 684	0x246b, 0xffffffff, 0x000b000a,
 685	0x246c, 0xffffffff, 0x00050004,
 686	0x246d, 0xffffffff, 0x00070006,
 687	0x246e, 0xffffffff, 0x0008000b,
 688	0x246f, 0xffffffff, 0x000a0009,
 689	0x2470, 0xffffffff, 0x000d000c,
 690	0x2480, 0xffffffff, 0x00090008,
 691	0x2481, 0xffffffff, 0x000b000a,
 692	0x2482, 0xffffffff, 0x000c000f,
 693	0x2483, 0xffffffff, 0x000e000d,
 694	0x2484, 0xffffffff, 0x00110010,
 695	0x2485, 0xffffffff, 0x000a0009,
 696	0x2486, 0xffffffff, 0x000c000b,
 697	0x2487, 0xffffffff, 0x0000000f,
 698	0x2488, 0xffffffff, 0x000e000d,
 699	0x2489, 0xffffffff, 0x00110010,
 700	0x248a, 0xffffffff, 0x000b000a,
 701	0x248b, 0xffffffff, 0x000d000c,
 702	0x248c, 0xffffffff, 0x00000010,
 703	0x248d, 0xffffffff, 0x000f000e,
 704	0x248e, 0xffffffff, 0x00120011,
 705	0x248f, 0xffffffff, 0x000c000b,
 706	0x2490, 0xffffffff, 0x000e000d,
 707	0x2491, 0xffffffff, 0x00000011,
 708	0x2492, 0xffffffff, 0x0010000f,
 709	0x2493, 0xffffffff, 0x00130012,
 710	0x2494, 0xffffffff, 0x000d000c,
 711	0x2495, 0xffffffff, 0x000f000e,
 712	0x2496, 0xffffffff, 0x00100013,
 713	0x2497, 0xffffffff, 0x00120011,
 714	0x2498, 0xffffffff, 0x00150014,
 715	0x2454, 0xffffffff, 0x96940200,
 716	0x21c2, 0xffffffff, 0x00900100,
 717	0x311e, 0xffffffff, 0x00000080,
 718	0x3101, 0xffffffff, 0x0020003f,
 719	0x000c, 0xffffffff, 0x0000001c,
 720	0x000d, 0x000f0000, 0x000f0000,
 721	0x0583, 0xffffffff, 0x00000100,
 722	0x0409, 0xffffffff, 0x00000100,
 723	0x040b, 0x00000101, 0x00000000,
 724	0x082a, 0xffffffff, 0x00000104,
 725	0x0993, 0x000c0000, 0x000c0000,
 726	0x0992, 0x000c0000, 0x000c0000,
 727	0x1579, 0xff000fff, 0x00000100,
 728	0x157a, 0x00000001, 0x00000001,
 729	0x0bd4, 0x00000001, 0x00000001,
 730	0x0c33, 0xc0000fff, 0x00000104,
 731	0x3079, 0x00000001, 0x00000001,
 732	0x3430, 0xfffffff0, 0x00000100,
 733	0x3630, 0xfffffff0, 0x00000100
 734};
 
 735static const u32 oland_mgcg_cgcg_init[] =
 736{
 737	0x3100, 0xffffffff, 0xfffffffc,
 738	0x200b, 0xffffffff, 0xe0000000,
 739	0x2698, 0xffffffff, 0x00000100,
 740	0x24a9, 0xffffffff, 0x00000100,
 741	0x3059, 0xffffffff, 0x00000100,
 742	0x25dd, 0xffffffff, 0x00000100,
 743	0x2261, 0xffffffff, 0x06000100,
 744	0x2286, 0xffffffff, 0x00000100,
 745	0x24a8, 0xffffffff, 0x00000100,
 746	0x30e0, 0xffffffff, 0x00000100,
 747	0x22ca, 0xffffffff, 0x00000100,
 748	0x2451, 0xffffffff, 0x00000100,
 749	0x2362, 0xffffffff, 0x00000100,
 750	0x2363, 0xffffffff, 0x00000100,
 751	0x240c, 0xffffffff, 0x00000100,
 752	0x240d, 0xffffffff, 0x00000100,
 753	0x240e, 0xffffffff, 0x00000100,
 754	0x240f, 0xffffffff, 0x00000100,
 755	0x2b60, 0xffffffff, 0x00000100,
 756	0x2b15, 0xffffffff, 0x00000100,
 757	0x225f, 0xffffffff, 0x06000100,
 758	0x261a, 0xffffffff, 0x00000100,
 759	0x2544, 0xffffffff, 0x00000100,
 760	0x2bc1, 0xffffffff, 0x00000100,
 761	0x2b81, 0xffffffff, 0x00000100,
 762	0x2527, 0xffffffff, 0x00000100,
 763	0x200b, 0xffffffff, 0xe0000000,
 764	0x2458, 0xffffffff, 0x00010000,
 765	0x2459, 0xffffffff, 0x00030002,
 766	0x245a, 0xffffffff, 0x00040007,
 767	0x245b, 0xffffffff, 0x00060005,
 768	0x245c, 0xffffffff, 0x00090008,
 769	0x245d, 0xffffffff, 0x00020001,
 770	0x245e, 0xffffffff, 0x00040003,
 771	0x245f, 0xffffffff, 0x00000007,
 772	0x2460, 0xffffffff, 0x00060005,
 773	0x2461, 0xffffffff, 0x00090008,
 774	0x2462, 0xffffffff, 0x00030002,
 775	0x2463, 0xffffffff, 0x00050004,
 776	0x2464, 0xffffffff, 0x00000008,
 777	0x2465, 0xffffffff, 0x00070006,
 778	0x2466, 0xffffffff, 0x000a0009,
 779	0x2467, 0xffffffff, 0x00040003,
 780	0x2468, 0xffffffff, 0x00060005,
 781	0x2469, 0xffffffff, 0x00000009,
 782	0x246a, 0xffffffff, 0x00080007,
 783	0x246b, 0xffffffff, 0x000b000a,
 784	0x246c, 0xffffffff, 0x00050004,
 785	0x246d, 0xffffffff, 0x00070006,
 786	0x246e, 0xffffffff, 0x0008000b,
 787	0x246f, 0xffffffff, 0x000a0009,
 788	0x2470, 0xffffffff, 0x000d000c,
 789	0x2471, 0xffffffff, 0x00060005,
 790	0x2472, 0xffffffff, 0x00080007,
 791	0x2473, 0xffffffff, 0x0000000b,
 792	0x2474, 0xffffffff, 0x000a0009,
 793	0x2475, 0xffffffff, 0x000d000c,
 794	0x2454, 0xffffffff, 0x96940200,
 795	0x21c2, 0xffffffff, 0x00900100,
 796	0x311e, 0xffffffff, 0x00000080,
 797	0x3101, 0xffffffff, 0x0020003f,
 798	0x000c, 0xffffffff, 0x0000001c,
 799	0x000d, 0x000f0000, 0x000f0000,
 800	0x0583, 0xffffffff, 0x00000100,
 801	0x0409, 0xffffffff, 0x00000100,
 802	0x040b, 0x00000101, 0x00000000,
 803	0x082a, 0xffffffff, 0x00000104,
 804	0x0993, 0x000c0000, 0x000c0000,
 805	0x0992, 0x000c0000, 0x000c0000,
 806	0x1579, 0xff000fff, 0x00000100,
 807	0x157a, 0x00000001, 0x00000001,
 808	0x0bd4, 0x00000001, 0x00000001,
 809	0x0c33, 0xc0000fff, 0x00000104,
 810	0x3079, 0x00000001, 0x00000001,
 811	0x3430, 0xfffffff0, 0x00000100,
 812	0x3630, 0xfffffff0, 0x00000100
 813};
 
 814static const u32 hainan_mgcg_cgcg_init[] =
 815{
 816	0x3100, 0xffffffff, 0xfffffffc,
 817	0x200b, 0xffffffff, 0xe0000000,
 818	0x2698, 0xffffffff, 0x00000100,
 819	0x24a9, 0xffffffff, 0x00000100,
 820	0x3059, 0xffffffff, 0x00000100,
 821	0x25dd, 0xffffffff, 0x00000100,
 822	0x2261, 0xffffffff, 0x06000100,
 823	0x2286, 0xffffffff, 0x00000100,
 824	0x24a8, 0xffffffff, 0x00000100,
 825	0x30e0, 0xffffffff, 0x00000100,
 826	0x22ca, 0xffffffff, 0x00000100,
 827	0x2451, 0xffffffff, 0x00000100,
 828	0x2362, 0xffffffff, 0x00000100,
 829	0x2363, 0xffffffff, 0x00000100,
 830	0x240c, 0xffffffff, 0x00000100,
 831	0x240d, 0xffffffff, 0x00000100,
 832	0x240e, 0xffffffff, 0x00000100,
 833	0x240f, 0xffffffff, 0x00000100,
 834	0x2b60, 0xffffffff, 0x00000100,
 835	0x2b15, 0xffffffff, 0x00000100,
 836	0x225f, 0xffffffff, 0x06000100,
 837	0x261a, 0xffffffff, 0x00000100,
 838	0x2544, 0xffffffff, 0x00000100,
 839	0x2bc1, 0xffffffff, 0x00000100,
 840	0x2b81, 0xffffffff, 0x00000100,
 841	0x2527, 0xffffffff, 0x00000100,
 842	0x200b, 0xffffffff, 0xe0000000,
 843	0x2458, 0xffffffff, 0x00010000,
 844	0x2459, 0xffffffff, 0x00030002,
 845	0x245a, 0xffffffff, 0x00040007,
 846	0x245b, 0xffffffff, 0x00060005,
 847	0x245c, 0xffffffff, 0x00090008,
 848	0x245d, 0xffffffff, 0x00020001,
 849	0x245e, 0xffffffff, 0x00040003,
 850	0x245f, 0xffffffff, 0x00000007,
 851	0x2460, 0xffffffff, 0x00060005,
 852	0x2461, 0xffffffff, 0x00090008,
 853	0x2462, 0xffffffff, 0x00030002,
 854	0x2463, 0xffffffff, 0x00050004,
 855	0x2464, 0xffffffff, 0x00000008,
 856	0x2465, 0xffffffff, 0x00070006,
 857	0x2466, 0xffffffff, 0x000a0009,
 858	0x2467, 0xffffffff, 0x00040003,
 859	0x2468, 0xffffffff, 0x00060005,
 860	0x2469, 0xffffffff, 0x00000009,
 861	0x246a, 0xffffffff, 0x00080007,
 862	0x246b, 0xffffffff, 0x000b000a,
 863	0x246c, 0xffffffff, 0x00050004,
 864	0x246d, 0xffffffff, 0x00070006,
 865	0x246e, 0xffffffff, 0x0008000b,
 866	0x246f, 0xffffffff, 0x000a0009,
 867	0x2470, 0xffffffff, 0x000d000c,
 868	0x2471, 0xffffffff, 0x00060005,
 869	0x2472, 0xffffffff, 0x00080007,
 870	0x2473, 0xffffffff, 0x0000000b,
 871	0x2474, 0xffffffff, 0x000a0009,
 872	0x2475, 0xffffffff, 0x000d000c,
 873	0x2454, 0xffffffff, 0x96940200,
 874	0x21c2, 0xffffffff, 0x00900100,
 875	0x311e, 0xffffffff, 0x00000080,
 876	0x3101, 0xffffffff, 0x0020003f,
 877	0x000c, 0xffffffff, 0x0000001c,
 878	0x000d, 0x000f0000, 0x000f0000,
 879	0x0583, 0xffffffff, 0x00000100,
 880	0x0409, 0xffffffff, 0x00000100,
 881	0x082a, 0xffffffff, 0x00000104,
 882	0x0993, 0x000c0000, 0x000c0000,
 883	0x0992, 0x000c0000, 0x000c0000,
 884	0x0bd4, 0x00000001, 0x00000001,
 885	0x0c33, 0xc0000fff, 0x00000104,
 886	0x3079, 0x00000001, 0x00000001,
 887	0x3430, 0xfffffff0, 0x00000100,
 888	0x3630, 0xfffffff0, 0x00000100
 889};
 890
 891static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 892{
 893	unsigned long flags;
 894	u32 r;
 895
 896	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 897	WREG32(AMDGPU_PCIE_INDEX, reg);
 898	(void)RREG32(AMDGPU_PCIE_INDEX);
 899	r = RREG32(AMDGPU_PCIE_DATA);
 900	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 901	return r;
 902}
 903
 904static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 905{
 906	unsigned long flags;
 907
 908	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 909	WREG32(AMDGPU_PCIE_INDEX, reg);
 910	(void)RREG32(AMDGPU_PCIE_INDEX);
 911	WREG32(AMDGPU_PCIE_DATA, v);
 912	(void)RREG32(AMDGPU_PCIE_DATA);
 913	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 914}
 915
 916static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
 917{
 918	unsigned long flags;
 919	u32 r;
 920
 921	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 922	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 923	(void)RREG32(PCIE_PORT_INDEX);
 924	r = RREG32(PCIE_PORT_DATA);
 925	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 926	return r;
 927}
 928
 929static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 930{
 931	unsigned long flags;
 932
 933	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 934	WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 935	(void)RREG32(PCIE_PORT_INDEX);
 936	WREG32(PCIE_PORT_DATA, (v));
 937	(void)RREG32(PCIE_PORT_DATA);
 938	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 939}
 940
 941static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
 942{
 943	unsigned long flags;
 944	u32 r;
 945
 946	spin_lock_irqsave(&adev->smc_idx_lock, flags);
 947	WREG32(SMC_IND_INDEX_0, (reg));
 948	r = RREG32(SMC_IND_DATA_0);
 949	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 950	return r;
 951}
 952
 953static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 954{
 955	unsigned long flags;
 956
 957	spin_lock_irqsave(&adev->smc_idx_lock, flags);
 958	WREG32(SMC_IND_INDEX_0, (reg));
 959	WREG32(SMC_IND_DATA_0, (v));
 960	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 961}
 962
 963static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
 964	{GRBM_STATUS, false},
 965	{GB_ADDR_CONFIG, false},
 966	{MC_ARB_RAMCFG, false},
 967	{GB_TILE_MODE0, false},
 968	{GB_TILE_MODE1, false},
 969	{GB_TILE_MODE2, false},
 970	{GB_TILE_MODE3, false},
 971	{GB_TILE_MODE4, false},
 972	{GB_TILE_MODE5, false},
 973	{GB_TILE_MODE6, false},
 974	{GB_TILE_MODE7, false},
 975	{GB_TILE_MODE8, false},
 976	{GB_TILE_MODE9, false},
 977	{GB_TILE_MODE10, false},
 978	{GB_TILE_MODE11, false},
 979	{GB_TILE_MODE12, false},
 980	{GB_TILE_MODE13, false},
 981	{GB_TILE_MODE14, false},
 982	{GB_TILE_MODE15, false},
 983	{GB_TILE_MODE16, false},
 984	{GB_TILE_MODE17, false},
 985	{GB_TILE_MODE18, false},
 986	{GB_TILE_MODE19, false},
 987	{GB_TILE_MODE20, false},
 988	{GB_TILE_MODE21, false},
 989	{GB_TILE_MODE22, false},
 990	{GB_TILE_MODE23, false},
 991	{GB_TILE_MODE24, false},
 992	{GB_TILE_MODE25, false},
 993	{GB_TILE_MODE26, false},
 994	{GB_TILE_MODE27, false},
 995	{GB_TILE_MODE28, false},
 996	{GB_TILE_MODE29, false},
 997	{GB_TILE_MODE30, false},
 998	{GB_TILE_MODE31, false},
 999	{CC_RB_BACKEND_DISABLE, false, true},
1000	{GC_USER_RB_BACKEND_DISABLE, false, true},
1001	{PA_SC_RASTER_CONFIG, false, true},
1002};
1003
1004static uint32_t si_read_indexed_register(struct amdgpu_device *adev,
1005					  u32 se_num, u32 sh_num,
1006					  u32 reg_offset)
1007{
1008	uint32_t val;
1009
1010	mutex_lock(&adev->grbm_idx_mutex);
1011	if (se_num != 0xffffffff || sh_num != 0xffffffff)
1012		amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1013
1014	val = RREG32(reg_offset);
1015
1016	if (se_num != 0xffffffff || sh_num != 0xffffffff)
1017		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1018	mutex_unlock(&adev->grbm_idx_mutex);
1019	return val;
1020}
1021
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1022static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1023			     u32 sh_num, u32 reg_offset, u32 *value)
1024{
1025	uint32_t i;
1026
1027	*value = 0;
1028	for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
 
 
1029		if (reg_offset != si_allowed_read_registers[i].reg_offset)
1030			continue;
1031
1032		if (!si_allowed_read_registers[i].untouched)
1033			*value = si_allowed_read_registers[i].grbm_indexed ?
1034				 si_read_indexed_register(adev, se_num,
1035							   sh_num, reg_offset) :
1036				 RREG32(reg_offset);
1037		return 0;
1038	}
1039	return -EINVAL;
1040}
1041
1042static bool si_read_disabled_bios(struct amdgpu_device *adev)
1043{
1044	u32 bus_cntl;
1045	u32 d1vga_control = 0;
1046	u32 d2vga_control = 0;
1047	u32 vga_render_control = 0;
1048	u32 rom_cntl;
1049	bool r;
1050
1051	bus_cntl = RREG32(R600_BUS_CNTL);
1052	if (adev->mode_info.num_crtc) {
1053		d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
1054		d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
1055		vga_render_control = RREG32(VGA_RENDER_CONTROL);
1056	}
1057	rom_cntl = RREG32(R600_ROM_CNTL);
1058
1059	/* enable the rom */
1060	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
1061	if (adev->mode_info.num_crtc) {
1062		/* Disable VGA mode */
1063		WREG32(AVIVO_D1VGA_CONTROL,
1064		       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1065					  AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1066		WREG32(AVIVO_D2VGA_CONTROL,
1067		       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1068					  AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1069		WREG32(VGA_RENDER_CONTROL,
1070		       (vga_render_control & C_000300_VGA_VSTATUS_CNTL));
1071	}
1072	WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
1073
1074	r = amdgpu_read_bios(adev);
1075
1076	/* restore regs */
1077	WREG32(R600_BUS_CNTL, bus_cntl);
1078	if (adev->mode_info.num_crtc) {
1079		WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
1080		WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
1081		WREG32(VGA_RENDER_CONTROL, vga_render_control);
1082	}
1083	WREG32(R600_ROM_CNTL, rom_cntl);
1084	return r;
1085}
1086
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1087//xxx: not implemented
1088static int si_asic_reset(struct amdgpu_device *adev)
1089{
1090	return 0;
1091}
1092
 
 
 
 
 
 
 
 
 
 
 
1093static void si_vga_set_state(struct amdgpu_device *adev, bool state)
1094{
1095	uint32_t temp;
1096
1097	temp = RREG32(CONFIG_CNTL);
1098	if (state == false) {
1099		temp &= ~(1<<0);
1100		temp |= (1<<1);
1101	} else {
1102		temp &= ~(1<<1);
1103	}
1104	WREG32(CONFIG_CNTL, temp);
1105}
1106
1107static u32 si_get_xclk(struct amdgpu_device *adev)
1108{
1109        u32 reference_clock = adev->clock.spll.reference_freq;
1110	u32 tmp;
1111
1112	tmp = RREG32(CG_CLKPIN_CNTL_2);
1113	if (tmp & MUX_TCLK_TO_XCLK)
1114		return TCLK;
1115
1116	tmp = RREG32(CG_CLKPIN_CNTL);
1117	if (tmp & XTALIN_DIVIDE)
1118		return reference_clock / 4;
1119
1120	return reference_clock;
1121}
1122
1123//xxx:not implemented
1124static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1125{
1126	return 0;
1127}
1128
1129static void si_detect_hw_virtualization(struct amdgpu_device *adev)
1130{
1131	if (is_virtual_machine()) /* passthrough mode */
1132		adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1133}
1134
1135static const struct amdgpu_asic_funcs si_asic_funcs =
1136{
1137	.read_disabled_bios = &si_read_disabled_bios,
1138	.detect_hw_virtualization = si_detect_hw_virtualization,
1139	.read_register = &si_read_register,
1140	.reset = &si_asic_reset,
 
1141	.set_vga_state = &si_vga_set_state,
1142	.get_xclk = &si_get_xclk,
1143	.set_uvd_clocks = &si_set_uvd_clocks,
1144	.set_vce_clocks = NULL,
 
 
 
 
 
 
 
 
 
1145};
1146
1147static uint32_t si_get_rev_id(struct amdgpu_device *adev)
1148{
1149	return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1150		>> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1151}
1152
1153static int si_common_early_init(void *handle)
1154{
1155	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1156
1157	adev->smc_rreg = &si_smc_rreg;
1158	adev->smc_wreg = &si_smc_wreg;
1159	adev->pcie_rreg = &si_pcie_rreg;
1160	adev->pcie_wreg = &si_pcie_wreg;
1161	adev->pciep_rreg = &si_pciep_rreg;
1162	adev->pciep_wreg = &si_pciep_wreg;
1163	adev->uvd_ctx_rreg = NULL;
1164	adev->uvd_ctx_wreg = NULL;
1165	adev->didt_rreg = NULL;
1166	adev->didt_wreg = NULL;
1167
1168	adev->asic_funcs = &si_asic_funcs;
1169
1170	adev->rev_id = si_get_rev_id(adev);
1171	adev->external_rev_id = 0xFF;
1172	switch (adev->asic_type) {
1173	case CHIP_TAHITI:
1174		adev->cg_flags =
1175			AMD_CG_SUPPORT_GFX_MGCG |
1176			AMD_CG_SUPPORT_GFX_MGLS |
1177			/*AMD_CG_SUPPORT_GFX_CGCG |*/
1178			AMD_CG_SUPPORT_GFX_CGLS |
1179			AMD_CG_SUPPORT_GFX_CGTS |
1180			AMD_CG_SUPPORT_GFX_CP_LS |
1181			AMD_CG_SUPPORT_MC_MGCG |
1182			AMD_CG_SUPPORT_SDMA_MGCG |
1183			AMD_CG_SUPPORT_BIF_LS |
1184			AMD_CG_SUPPORT_VCE_MGCG |
1185			AMD_CG_SUPPORT_UVD_MGCG |
1186			AMD_CG_SUPPORT_HDP_LS |
1187			AMD_CG_SUPPORT_HDP_MGCG;
1188			adev->pg_flags = 0;
1189		adev->external_rev_id = (adev->rev_id == 0) ? 1 :
1190					(adev->rev_id == 1) ? 5 : 6;
1191		break;
1192	case CHIP_PITCAIRN:
1193		adev->cg_flags =
1194			AMD_CG_SUPPORT_GFX_MGCG |
1195			AMD_CG_SUPPORT_GFX_MGLS |
1196			/*AMD_CG_SUPPORT_GFX_CGCG |*/
1197			AMD_CG_SUPPORT_GFX_CGLS |
1198			AMD_CG_SUPPORT_GFX_CGTS |
1199			AMD_CG_SUPPORT_GFX_CP_LS |
1200			AMD_CG_SUPPORT_GFX_RLC_LS |
1201			AMD_CG_SUPPORT_MC_LS |
1202			AMD_CG_SUPPORT_MC_MGCG |
1203			AMD_CG_SUPPORT_SDMA_MGCG |
1204			AMD_CG_SUPPORT_BIF_LS |
1205			AMD_CG_SUPPORT_VCE_MGCG |
1206			AMD_CG_SUPPORT_UVD_MGCG |
1207			AMD_CG_SUPPORT_HDP_LS |
1208			AMD_CG_SUPPORT_HDP_MGCG;
1209		adev->pg_flags = 0;
1210		adev->external_rev_id = adev->rev_id + 20;
1211		break;
1212
1213	case CHIP_VERDE:
1214		adev->cg_flags =
1215			AMD_CG_SUPPORT_GFX_MGCG |
1216			AMD_CG_SUPPORT_GFX_MGLS |
1217			AMD_CG_SUPPORT_GFX_CGLS |
1218			AMD_CG_SUPPORT_GFX_CGTS |
1219			AMD_CG_SUPPORT_GFX_CGTS_LS |
1220			AMD_CG_SUPPORT_GFX_CP_LS |
1221			AMD_CG_SUPPORT_MC_LS |
1222			AMD_CG_SUPPORT_MC_MGCG |
1223			AMD_CG_SUPPORT_SDMA_MGCG |
1224			AMD_CG_SUPPORT_SDMA_LS |
1225			AMD_CG_SUPPORT_BIF_LS |
1226			AMD_CG_SUPPORT_VCE_MGCG |
1227			AMD_CG_SUPPORT_UVD_MGCG |
1228			AMD_CG_SUPPORT_HDP_LS |
1229			AMD_CG_SUPPORT_HDP_MGCG;
1230		adev->pg_flags = 0;
1231		//???
1232		adev->external_rev_id = adev->rev_id + 40;
1233		break;
1234	case CHIP_OLAND:
1235		adev->cg_flags =
1236			AMD_CG_SUPPORT_GFX_MGCG |
1237			AMD_CG_SUPPORT_GFX_MGLS |
1238			/*AMD_CG_SUPPORT_GFX_CGCG |*/
1239			AMD_CG_SUPPORT_GFX_CGLS |
1240			AMD_CG_SUPPORT_GFX_CGTS |
1241			AMD_CG_SUPPORT_GFX_CP_LS |
1242			AMD_CG_SUPPORT_GFX_RLC_LS |
1243			AMD_CG_SUPPORT_MC_LS |
1244			AMD_CG_SUPPORT_MC_MGCG |
1245			AMD_CG_SUPPORT_SDMA_MGCG |
1246			AMD_CG_SUPPORT_BIF_LS |
1247			AMD_CG_SUPPORT_UVD_MGCG |
1248			AMD_CG_SUPPORT_HDP_LS |
1249			AMD_CG_SUPPORT_HDP_MGCG;
1250		adev->pg_flags = 0;
1251		adev->external_rev_id = 60;
1252		break;
1253	case CHIP_HAINAN:
1254		adev->cg_flags =
1255			AMD_CG_SUPPORT_GFX_MGCG |
1256			AMD_CG_SUPPORT_GFX_MGLS |
1257			/*AMD_CG_SUPPORT_GFX_CGCG |*/
1258			AMD_CG_SUPPORT_GFX_CGLS |
1259			AMD_CG_SUPPORT_GFX_CGTS |
1260			AMD_CG_SUPPORT_GFX_CP_LS |
1261			AMD_CG_SUPPORT_GFX_RLC_LS |
1262			AMD_CG_SUPPORT_MC_LS |
1263			AMD_CG_SUPPORT_MC_MGCG |
1264			AMD_CG_SUPPORT_SDMA_MGCG |
1265			AMD_CG_SUPPORT_BIF_LS |
1266			AMD_CG_SUPPORT_HDP_LS |
1267			AMD_CG_SUPPORT_HDP_MGCG;
1268		adev->pg_flags = 0;
1269		adev->external_rev_id = 70;
1270		break;
1271
1272	default:
1273		return -EINVAL;
1274	}
1275
1276	return 0;
1277}
1278
1279static int si_common_sw_init(void *handle)
1280{
1281	return 0;
1282}
1283
1284static int si_common_sw_fini(void *handle)
1285{
1286	return 0;
1287}
1288
1289
1290static void si_init_golden_registers(struct amdgpu_device *adev)
1291{
1292	switch (adev->asic_type) {
1293	case CHIP_TAHITI:
1294		amdgpu_program_register_sequence(adev,
1295						 tahiti_golden_registers,
1296						 (const u32)ARRAY_SIZE(tahiti_golden_registers));
1297		amdgpu_program_register_sequence(adev,
1298						 tahiti_golden_rlc_registers,
1299						 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1300		amdgpu_program_register_sequence(adev,
1301						 tahiti_mgcg_cgcg_init,
1302						 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1303		amdgpu_program_register_sequence(adev,
1304						 tahiti_golden_registers2,
1305						 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1306		break;
1307	case CHIP_PITCAIRN:
1308		amdgpu_program_register_sequence(adev,
1309						 pitcairn_golden_registers,
1310						 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1311		amdgpu_program_register_sequence(adev,
1312						 pitcairn_golden_rlc_registers,
1313						 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1314		amdgpu_program_register_sequence(adev,
1315						 pitcairn_mgcg_cgcg_init,
1316						 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
 
1317	case CHIP_VERDE:
1318		amdgpu_program_register_sequence(adev,
1319						 verde_golden_registers,
1320						 (const u32)ARRAY_SIZE(verde_golden_registers));
1321		amdgpu_program_register_sequence(adev,
1322						 verde_golden_rlc_registers,
1323						 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1324		amdgpu_program_register_sequence(adev,
1325						 verde_mgcg_cgcg_init,
1326						 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1327		amdgpu_program_register_sequence(adev,
1328						 verde_pg_init,
1329						 (const u32)ARRAY_SIZE(verde_pg_init));
1330		break;
1331	case CHIP_OLAND:
1332		amdgpu_program_register_sequence(adev,
1333						 oland_golden_registers,
1334						 (const u32)ARRAY_SIZE(oland_golden_registers));
1335		amdgpu_program_register_sequence(adev,
1336						 oland_golden_rlc_registers,
1337						 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1338		amdgpu_program_register_sequence(adev,
1339						 oland_mgcg_cgcg_init,
1340						 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
 
1341	case CHIP_HAINAN:
1342		amdgpu_program_register_sequence(adev,
1343						 hainan_golden_registers,
1344						 (const u32)ARRAY_SIZE(hainan_golden_registers));
1345		amdgpu_program_register_sequence(adev,
1346						 hainan_golden_registers2,
1347						 (const u32)ARRAY_SIZE(hainan_golden_registers2));
1348		amdgpu_program_register_sequence(adev,
1349						 hainan_mgcg_cgcg_init,
1350						 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1351		break;
1352
1353
1354	default:
1355		BUG();
1356	}
1357}
1358
1359static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1360{
1361	struct pci_dev *root = adev->pdev->bus->self;
1362	int bridge_pos, gpu_pos;
1363	u32 speed_cntl, mask, current_data_rate;
1364	int ret, i;
1365	u16 tmp16;
1366
1367	if (pci_is_root_bus(adev->pdev->bus))
1368		return;
1369
1370	if (amdgpu_pcie_gen2 == 0)
1371		return;
1372
1373	if (adev->flags & AMD_IS_APU)
1374		return;
1375
1376	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1377	if (ret != 0)
1378		return;
1379
1380	if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1381		return;
1382
1383	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1384	current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1385		LC_CURRENT_DATA_RATE_SHIFT;
1386	if (mask & DRM_PCIE_SPEED_80) {
1387		if (current_data_rate == 2) {
1388			DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1389			return;
1390		}
1391		DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1392	} else if (mask & DRM_PCIE_SPEED_50) {
1393		if (current_data_rate == 1) {
1394			DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1395			return;
1396		}
1397		DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1398	}
1399
1400	bridge_pos = pci_pcie_cap(root);
1401	if (!bridge_pos)
1402		return;
1403
1404	gpu_pos = pci_pcie_cap(adev->pdev);
1405	if (!gpu_pos)
1406		return;
1407
1408	if (mask & DRM_PCIE_SPEED_80) {
1409		if (current_data_rate != 2) {
1410			u16 bridge_cfg, gpu_cfg;
1411			u16 bridge_cfg2, gpu_cfg2;
1412			u32 max_lw, current_lw, tmp;
1413
1414			pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1415			pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1416
1417			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1418			pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1419
1420			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1421			pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1422
1423			tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1424			max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
1425			current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
1426
1427			if (current_lw < max_lw) {
1428				tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1429				if (tmp & LC_RENEGOTIATION_SUPPORT) {
1430					tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
1431					tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
1432					tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
1433					WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
1434				}
1435			}
1436
1437			for (i = 0; i < 10; i++) {
1438				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1439				if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1440					break;
1441
1442				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1443				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1444
1445				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1446				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1447
1448				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1449				tmp |= LC_SET_QUIESCE;
1450				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1451
1452				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1453				tmp |= LC_REDO_EQ;
1454				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1455
1456				mdelay(100);
1457
1458				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1459				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1460				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1461				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1462
1463				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1464				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1465				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1466				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1467
1468				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1469				tmp16 &= ~((1 << 4) | (7 << 9));
1470				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1471				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1472
1473				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1474				tmp16 &= ~((1 << 4) | (7 << 9));
1475				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1476				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1477
1478				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1479				tmp &= ~LC_SET_QUIESCE;
1480				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1481			}
1482		}
1483	}
1484
1485	speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
1486	speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
1487	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1488
1489	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1490	tmp16 &= ~0xf;
1491	if (mask & DRM_PCIE_SPEED_80)
1492		tmp16 |= 3;
1493	else if (mask & DRM_PCIE_SPEED_50)
1494		tmp16 |= 2;
1495	else
1496		tmp16 |= 1;
1497	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1498
1499	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1500	speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
1501	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1502
1503	for (i = 0; i < adev->usec_timeout; i++) {
1504		speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1505		if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
1506			break;
1507		udelay(1);
1508	}
1509}
1510
1511static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
1512{
1513	unsigned long flags;
1514	u32 r;
1515
1516	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1517	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1518	r = RREG32(EVERGREEN_PIF_PHY0_DATA);
1519	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1520	return r;
1521}
1522
1523static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1524{
1525	unsigned long flags;
1526
1527	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1528	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1529	WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
1530	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1531}
1532
1533static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
1534{
1535	unsigned long flags;
1536	u32 r;
1537
1538	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1539	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1540	r = RREG32(EVERGREEN_PIF_PHY1_DATA);
1541	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1542	return r;
1543}
1544
1545static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1546{
1547	unsigned long flags;
1548
1549	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1550	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1551	WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
1552	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1553}
1554static void si_program_aspm(struct amdgpu_device *adev)
1555{
1556	u32 data, orig;
1557	bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1558	bool disable_clkreq = false;
1559
1560	if (amdgpu_aspm == 0)
1561		return;
1562
1563	if (adev->flags & AMD_IS_APU)
1564		return;
1565	orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1566	data &= ~LC_XMIT_N_FTS_MASK;
1567	data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
1568	if (orig != data)
1569		WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
1570
1571	orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
1572	data |= LC_GO_TO_RECOVERY;
1573	if (orig != data)
1574		WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
1575
1576	orig = data = RREG32_PCIE(PCIE_P_CNTL);
1577	data |= P_IGNORE_EDB_ERR;
1578	if (orig != data)
1579		WREG32_PCIE(PCIE_P_CNTL, data);
1580
1581	orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1582	data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
1583	data |= LC_PMI_TO_L1_DIS;
1584	if (!disable_l0s)
1585		data |= LC_L0S_INACTIVITY(7);
1586
1587	if (!disable_l1) {
1588		data |= LC_L1_INACTIVITY(7);
1589		data &= ~LC_PMI_TO_L1_DIS;
1590		if (orig != data)
1591			WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1592
1593		if (!disable_plloff_in_l1) {
1594			bool clk_req_support;
1595
1596			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1597			data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1598			data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1599			if (orig != data)
1600				si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1601
1602			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1603			data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1604			data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1605			if (orig != data)
1606				si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1607
1608			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1609			data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1610			data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1611			if (orig != data)
1612				si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1613
1614			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1615			data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1616			data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1617			if (orig != data)
1618				si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1619
1620			if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
1621				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1622				data &= ~PLL_RAMP_UP_TIME_0_MASK;
1623				if (orig != data)
1624					si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1625
1626				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1627				data &= ~PLL_RAMP_UP_TIME_1_MASK;
1628				if (orig != data)
1629					si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1630
1631				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
1632				data &= ~PLL_RAMP_UP_TIME_2_MASK;
1633				if (orig != data)
1634					si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
1635
1636				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
1637				data &= ~PLL_RAMP_UP_TIME_3_MASK;
1638				if (orig != data)
1639					si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
1640
1641				orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1642				data &= ~PLL_RAMP_UP_TIME_0_MASK;
1643				if (orig != data)
1644					si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1645
1646				orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1647				data &= ~PLL_RAMP_UP_TIME_1_MASK;
1648				if (orig != data)
1649					si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1650
1651				orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
1652				data &= ~PLL_RAMP_UP_TIME_2_MASK;
1653				if (orig != data)
1654					si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
1655
1656				orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
1657				data &= ~PLL_RAMP_UP_TIME_3_MASK;
1658				if (orig != data)
1659					si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
1660			}
1661			orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1662			data &= ~LC_DYN_LANES_PWR_STATE_MASK;
1663			data |= LC_DYN_LANES_PWR_STATE(3);
1664			if (orig != data)
1665				WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
1666
1667			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
1668			data &= ~LS2_EXIT_TIME_MASK;
1669			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1670				data |= LS2_EXIT_TIME(5);
1671			if (orig != data)
1672				si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
1673
1674			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
1675			data &= ~LS2_EXIT_TIME_MASK;
1676			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1677				data |= LS2_EXIT_TIME(5);
1678			if (orig != data)
1679				si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
1680
1681			if (!disable_clkreq &&
1682			    !pci_is_root_bus(adev->pdev->bus)) {
1683				struct pci_dev *root = adev->pdev->bus->self;
1684				u32 lnkcap;
1685
1686				clk_req_support = false;
1687				pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1688				if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1689					clk_req_support = true;
1690			} else {
1691				clk_req_support = false;
1692			}
1693
1694			if (clk_req_support) {
1695				orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
1696				data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
1697				if (orig != data)
1698					WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
1699
1700				orig = data = RREG32(THM_CLK_CNTL);
1701				data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
1702				data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
1703				if (orig != data)
1704					WREG32(THM_CLK_CNTL, data);
1705
1706				orig = data = RREG32(MISC_CLK_CNTL);
1707				data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
1708				data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
1709				if (orig != data)
1710					WREG32(MISC_CLK_CNTL, data);
1711
1712				orig = data = RREG32(CG_CLKPIN_CNTL);
1713				data &= ~BCLK_AS_XCLK;
1714				if (orig != data)
1715					WREG32(CG_CLKPIN_CNTL, data);
1716
1717				orig = data = RREG32(CG_CLKPIN_CNTL_2);
1718				data &= ~FORCE_BIF_REFCLK_EN;
1719				if (orig != data)
1720					WREG32(CG_CLKPIN_CNTL_2, data);
1721
1722				orig = data = RREG32(MPLL_BYPASSCLK_SEL);
1723				data &= ~MPLL_CLKOUT_SEL_MASK;
1724				data |= MPLL_CLKOUT_SEL(4);
1725				if (orig != data)
1726					WREG32(MPLL_BYPASSCLK_SEL, data);
1727
1728				orig = data = RREG32(SPLL_CNTL_MODE);
1729				data &= ~SPLL_REFCLK_SEL_MASK;
1730				if (orig != data)
1731					WREG32(SPLL_CNTL_MODE, data);
1732			}
1733		}
1734	} else {
1735		if (orig != data)
1736			WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1737	}
1738
1739	orig = data = RREG32_PCIE(PCIE_CNTL2);
1740	data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
1741	if (orig != data)
1742		WREG32_PCIE(PCIE_CNTL2, data);
1743
1744	if (!disable_l0s) {
1745		data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1746		if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
1747			data = RREG32_PCIE(PCIE_LC_STATUS1);
1748			if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
1749				orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1750				data &= ~LC_L0S_INACTIVITY_MASK;
1751				if (orig != data)
1752					WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1753			}
1754		}
1755	}
1756}
1757
1758static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
1759{
1760	int readrq;
1761	u16 v;
1762
1763	readrq = pcie_get_readrq(adev->pdev);
1764	v = ffs(readrq) - 8;
1765	if ((v == 0) || (v == 6) || (v == 7))
1766		pcie_set_readrq(adev->pdev, 512);
1767}
1768
1769static int si_common_hw_init(void *handle)
1770{
1771	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1772
1773	si_fix_pci_max_read_req_size(adev);
1774	si_init_golden_registers(adev);
1775	si_pcie_gen3_enable(adev);
1776	si_program_aspm(adev);
1777
1778	return 0;
1779}
1780
1781static int si_common_hw_fini(void *handle)
1782{
1783	return 0;
1784}
1785
1786static int si_common_suspend(void *handle)
1787{
1788	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1789
1790	return si_common_hw_fini(adev);
1791}
1792
1793static int si_common_resume(void *handle)
1794{
1795	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1796
1797	return si_common_hw_init(adev);
1798}
1799
1800static bool si_common_is_idle(void *handle)
1801{
1802	return true;
1803}
1804
1805static int si_common_wait_for_idle(void *handle)
1806{
1807	return 0;
1808}
1809
1810static int si_common_soft_reset(void *handle)
1811{
1812	return 0;
1813}
1814
1815static int si_common_set_clockgating_state(void *handle,
1816					    enum amd_clockgating_state state)
1817{
1818	return 0;
1819}
1820
1821static int si_common_set_powergating_state(void *handle,
1822					    enum amd_powergating_state state)
1823{
1824	return 0;
1825}
1826
1827static const struct amd_ip_funcs si_common_ip_funcs = {
1828	.name = "si_common",
1829	.early_init = si_common_early_init,
1830	.late_init = NULL,
1831	.sw_init = si_common_sw_init,
1832	.sw_fini = si_common_sw_fini,
1833	.hw_init = si_common_hw_init,
1834	.hw_fini = si_common_hw_fini,
1835	.suspend = si_common_suspend,
1836	.resume = si_common_resume,
1837	.is_idle = si_common_is_idle,
1838	.wait_for_idle = si_common_wait_for_idle,
1839	.soft_reset = si_common_soft_reset,
1840	.set_clockgating_state = si_common_set_clockgating_state,
1841	.set_powergating_state = si_common_set_powergating_state,
1842};
1843
1844static const struct amdgpu_ip_block_version si_common_ip_block =
1845{
1846	.type = AMD_IP_BLOCK_TYPE_COMMON,
1847	.major = 1,
1848	.minor = 0,
1849	.rev = 0,
1850	.funcs = &si_common_ip_funcs,
1851};
1852
1853int si_set_ip_blocks(struct amdgpu_device *adev)
1854{
 
 
1855	switch (adev->asic_type) {
1856	case CHIP_VERDE:
1857	case CHIP_TAHITI:
1858	case CHIP_PITCAIRN:
1859		amdgpu_ip_block_add(adev, &si_common_ip_block);
1860		amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1861		amdgpu_ip_block_add(adev, &si_ih_ip_block);
1862		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
 
 
1863		if (adev->enable_virtual_display)
1864			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1865		else
1866			amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
1867		amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1868		amdgpu_ip_block_add(adev, &si_dma_ip_block);
1869		/* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1870		/* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1871		break;
1872	case CHIP_OLAND:
1873		amdgpu_ip_block_add(adev, &si_common_ip_block);
1874		amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1875		amdgpu_ip_block_add(adev, &si_ih_ip_block);
1876		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
 
 
1877		if (adev->enable_virtual_display)
1878			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1879		else
1880			amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
1881		amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1882		amdgpu_ip_block_add(adev, &si_dma_ip_block);
1883		/* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
1884		/* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
1885		break;
1886	case CHIP_HAINAN:
1887		amdgpu_ip_block_add(adev, &si_common_ip_block);
1888		amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
1889		amdgpu_ip_block_add(adev, &si_ih_ip_block);
1890		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
 
 
1891		if (adev->enable_virtual_display)
1892			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1893		amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
1894		amdgpu_ip_block_add(adev, &si_dma_ip_block);
1895		break;
1896	default:
1897		BUG();
1898	}
1899	return 0;
1900}
1901