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1#ifndef __ASMARM_ARCH_TIMER_H
2#define __ASMARM_ARCH_TIMER_H
3
4#include <asm/barrier.h>
5#include <asm/errno.h>
6#include <linux/clocksource.h>
7#include <linux/init.h>
8#include <linux/types.h>
9
10#include <clocksource/arm_arch_timer.h>
11
12#ifdef CONFIG_ARM_ARCH_TIMER
13int arch_timer_arch_init(void);
14
15/*
16 * These register accessors are marked inline so the compiler can
17 * nicely work out which register we want, and chuck away the rest of
18 * the code. At least it does so with a recent GCC (4.6.3).
19 */
20static __always_inline
21void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
22{
23 if (access == ARCH_TIMER_PHYS_ACCESS) {
24 switch (reg) {
25 case ARCH_TIMER_REG_CTRL:
26 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
27 break;
28 case ARCH_TIMER_REG_TVAL:
29 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
30 break;
31 }
32 } else if (access == ARCH_TIMER_VIRT_ACCESS) {
33 switch (reg) {
34 case ARCH_TIMER_REG_CTRL:
35 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
36 break;
37 case ARCH_TIMER_REG_TVAL:
38 asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
39 break;
40 }
41 }
42
43 isb();
44}
45
46static __always_inline
47u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
48{
49 u32 val = 0;
50
51 if (access == ARCH_TIMER_PHYS_ACCESS) {
52 switch (reg) {
53 case ARCH_TIMER_REG_CTRL:
54 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
55 break;
56 case ARCH_TIMER_REG_TVAL:
57 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
58 break;
59 }
60 } else if (access == ARCH_TIMER_VIRT_ACCESS) {
61 switch (reg) {
62 case ARCH_TIMER_REG_CTRL:
63 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
64 break;
65 case ARCH_TIMER_REG_TVAL:
66 asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
67 break;
68 }
69 }
70
71 return val;
72}
73
74static inline u32 arch_timer_get_cntfrq(void)
75{
76 u32 val;
77 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
78 return val;
79}
80
81static inline u64 arch_counter_get_cntpct(void)
82{
83 u64 cval;
84
85 isb();
86 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
87 return cval;
88}
89
90static inline u64 arch_counter_get_cntvct(void)
91{
92 u64 cval;
93
94 isb();
95 asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
96 return cval;
97}
98
99static inline u32 arch_timer_get_cntkctl(void)
100{
101 u32 cntkctl;
102 asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
103 return cntkctl;
104}
105
106static inline void arch_timer_set_cntkctl(u32 cntkctl)
107{
108 asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
109}
110
111#endif
112
113#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ASMARM_ARCH_TIMER_H
3#define __ASMARM_ARCH_TIMER_H
4
5#include <asm/barrier.h>
6#include <asm/errno.h>
7#include <asm/hwcap.h>
8#include <linux/clocksource.h>
9#include <linux/init.h>
10#include <linux/types.h>
11
12#include <clocksource/arm_arch_timer.h>
13
14#ifdef CONFIG_ARM_ARCH_TIMER
15/* 32bit ARM doesn't know anything about timer errata... */
16#define has_erratum_handler(h) (false)
17#define erratum_handler(h) (arch_timer_##h)
18
19int arch_timer_arch_init(void);
20
21/*
22 * These register accessors are marked inline so the compiler can
23 * nicely work out which register we want, and chuck away the rest of
24 * the code. At least it does so with a recent GCC (4.6.3).
25 */
26static __always_inline
27void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
28{
29 if (access == ARCH_TIMER_PHYS_ACCESS) {
30 switch (reg) {
31 case ARCH_TIMER_REG_CTRL:
32 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
33 break;
34 case ARCH_TIMER_REG_TVAL:
35 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
36 break;
37 }
38 } else if (access == ARCH_TIMER_VIRT_ACCESS) {
39 switch (reg) {
40 case ARCH_TIMER_REG_CTRL:
41 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
42 break;
43 case ARCH_TIMER_REG_TVAL:
44 asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
45 break;
46 }
47 }
48
49 isb();
50}
51
52static __always_inline
53u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
54{
55 u32 val = 0;
56
57 if (access == ARCH_TIMER_PHYS_ACCESS) {
58 switch (reg) {
59 case ARCH_TIMER_REG_CTRL:
60 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
61 break;
62 case ARCH_TIMER_REG_TVAL:
63 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
64 break;
65 }
66 } else if (access == ARCH_TIMER_VIRT_ACCESS) {
67 switch (reg) {
68 case ARCH_TIMER_REG_CTRL:
69 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
70 break;
71 case ARCH_TIMER_REG_TVAL:
72 asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
73 break;
74 }
75 }
76
77 return val;
78}
79
80static inline u32 arch_timer_get_cntfrq(void)
81{
82 u32 val;
83 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
84 return val;
85}
86
87static inline u64 __arch_counter_get_cntpct(void)
88{
89 u64 cval;
90
91 isb();
92 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
93 return cval;
94}
95
96static inline u64 __arch_counter_get_cntpct_stable(void)
97{
98 return __arch_counter_get_cntpct();
99}
100
101static inline u64 __arch_counter_get_cntvct(void)
102{
103 u64 cval;
104
105 isb();
106 asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
107 return cval;
108}
109
110static inline u64 __arch_counter_get_cntvct_stable(void)
111{
112 return __arch_counter_get_cntvct();
113}
114
115static inline u32 arch_timer_get_cntkctl(void)
116{
117 u32 cntkctl;
118 asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
119 return cntkctl;
120}
121
122static inline void arch_timer_set_cntkctl(u32 cntkctl)
123{
124 asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
125 isb();
126}
127
128static inline void arch_timer_set_evtstrm_feature(void)
129{
130 elf_hwcap |= HWCAP_EVTSTRM;
131}
132
133static inline bool arch_timer_have_evtstrm_feature(void)
134{
135 return elf_hwcap & HWCAP_EVTSTRM;
136}
137#endif
138
139#endif