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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/irq.h>
25#include <linux/log2.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/slab.h>
29#include <linux/dmi.h>
30#include <linux/dma-mapping.h>
31
32#include "xhci.h"
33#include "xhci-trace.h"
34#include "xhci-mtk.h"
35
36#define DRIVER_AUTHOR "Sarah Sharp"
37#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
38
39#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
40
41/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
42static int link_quirk;
43module_param(link_quirk, int, S_IRUGO | S_IWUSR);
44MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
45
46static unsigned int quirks;
47module_param(quirks, uint, S_IRUGO);
48MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
49
50/* TODO: copied from ehci-hcd.c - can this be refactored? */
51/*
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
57 *
58 * Returns negative errno, or zero on success
59 *
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
63 */
64int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
65{
66 u32 result;
67
68 do {
69 result = readl(ptr);
70 if (result == ~(u32)0) /* card removed */
71 return -ENODEV;
72 result &= mask;
73 if (result == done)
74 return 0;
75 udelay(1);
76 usec--;
77 } while (usec > 0);
78 return -ETIMEDOUT;
79}
80
81/*
82 * Disable interrupts and begin the xHCI halting process.
83 */
84void xhci_quiesce(struct xhci_hcd *xhci)
85{
86 u32 halted;
87 u32 cmd;
88 u32 mask;
89
90 mask = ~(XHCI_IRQS);
91 halted = readl(&xhci->op_regs->status) & STS_HALT;
92 if (!halted)
93 mask &= ~CMD_RUN;
94
95 cmd = readl(&xhci->op_regs->command);
96 cmd &= mask;
97 writel(cmd, &xhci->op_regs->command);
98}
99
100/*
101 * Force HC into halt state.
102 *
103 * Disable any IRQs and clear the run/stop bit.
104 * HC will complete any current and actively pipelined transactions, and
105 * should halt within 16 ms of the run/stop bit being cleared.
106 * Read HC Halted bit in the status register to see when the HC is finished.
107 */
108int xhci_halt(struct xhci_hcd *xhci)
109{
110 int ret;
111 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
112 xhci_quiesce(xhci);
113
114 ret = xhci_handshake(&xhci->op_regs->status,
115 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
116 if (ret) {
117 xhci_warn(xhci, "Host halt failed, %d\n", ret);
118 return ret;
119 }
120 xhci->xhc_state |= XHCI_STATE_HALTED;
121 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
122 return ret;
123}
124
125/*
126 * Set the run bit and wait for the host to be running.
127 */
128static int xhci_start(struct xhci_hcd *xhci)
129{
130 u32 temp;
131 int ret;
132
133 temp = readl(&xhci->op_regs->command);
134 temp |= (CMD_RUN);
135 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
136 temp);
137 writel(temp, &xhci->op_regs->command);
138
139 /*
140 * Wait for the HCHalted Status bit to be 0 to indicate the host is
141 * running.
142 */
143 ret = xhci_handshake(&xhci->op_regs->status,
144 STS_HALT, 0, XHCI_MAX_HALT_USEC);
145 if (ret == -ETIMEDOUT)
146 xhci_err(xhci, "Host took too long to start, "
147 "waited %u microseconds.\n",
148 XHCI_MAX_HALT_USEC);
149 if (!ret)
150 /* clear state flags. Including dying, halted or removing */
151 xhci->xhc_state = 0;
152
153 return ret;
154}
155
156/*
157 * Reset a halted HC.
158 *
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
162 */
163int xhci_reset(struct xhci_hcd *xhci)
164{
165 u32 command;
166 u32 state;
167 int ret, i;
168
169 state = readl(&xhci->op_regs->status);
170
171 if (state == ~(u32)0) {
172 xhci_warn(xhci, "Host not accessible, reset failed.\n");
173 return -ENODEV;
174 }
175
176 if ((state & STS_HALT) == 0) {
177 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
178 return 0;
179 }
180
181 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
182 command = readl(&xhci->op_regs->command);
183 command |= CMD_RESET;
184 writel(command, &xhci->op_regs->command);
185
186 /* Existing Intel xHCI controllers require a delay of 1 mS,
187 * after setting the CMD_RESET bit, and before accessing any
188 * HC registers. This allows the HC to complete the
189 * reset operation and be ready for HC register access.
190 * Without this delay, the subsequent HC register access,
191 * may result in a system hang very rarely.
192 */
193 if (xhci->quirks & XHCI_INTEL_HOST)
194 udelay(1000);
195
196 ret = xhci_handshake(&xhci->op_regs->command,
197 CMD_RESET, 0, 10 * 1000 * 1000);
198 if (ret)
199 return ret;
200
201 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
202 "Wait for controller to be ready for doorbell rings");
203 /*
204 * xHCI cannot write to any doorbells or operational registers other
205 * than status until the "Controller Not Ready" flag is cleared.
206 */
207 ret = xhci_handshake(&xhci->op_regs->status,
208 STS_CNR, 0, 10 * 1000 * 1000);
209
210 for (i = 0; i < 2; ++i) {
211 xhci->bus_state[i].port_c_suspend = 0;
212 xhci->bus_state[i].suspended_ports = 0;
213 xhci->bus_state[i].resuming_ports = 0;
214 }
215
216 return ret;
217}
218
219#ifdef CONFIG_PCI
220static int xhci_free_msi(struct xhci_hcd *xhci)
221{
222 int i;
223
224 if (!xhci->msix_entries)
225 return -EINVAL;
226
227 for (i = 0; i < xhci->msix_count; i++)
228 if (xhci->msix_entries[i].vector)
229 free_irq(xhci->msix_entries[i].vector,
230 xhci_to_hcd(xhci));
231 return 0;
232}
233
234/*
235 * Set up MSI
236 */
237static int xhci_setup_msi(struct xhci_hcd *xhci)
238{
239 int ret;
240 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
241
242 ret = pci_enable_msi(pdev);
243 if (ret) {
244 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
245 "failed to allocate MSI entry");
246 return ret;
247 }
248
249 ret = request_irq(pdev->irq, xhci_msi_irq,
250 0, "xhci_hcd", xhci_to_hcd(xhci));
251 if (ret) {
252 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
253 "disable MSI interrupt");
254 pci_disable_msi(pdev);
255 }
256
257 return ret;
258}
259
260/*
261 * Free IRQs
262 * free all IRQs request
263 */
264static void xhci_free_irq(struct xhci_hcd *xhci)
265{
266 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
267 int ret;
268
269 /* return if using legacy interrupt */
270 if (xhci_to_hcd(xhci)->irq > 0)
271 return;
272
273 ret = xhci_free_msi(xhci);
274 if (!ret)
275 return;
276 if (pdev->irq > 0)
277 free_irq(pdev->irq, xhci_to_hcd(xhci));
278
279 return;
280}
281
282/*
283 * Set up MSI-X
284 */
285static int xhci_setup_msix(struct xhci_hcd *xhci)
286{
287 int i, ret = 0;
288 struct usb_hcd *hcd = xhci_to_hcd(xhci);
289 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
290
291 /*
292 * calculate number of msi-x vectors supported.
293 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
294 * with max number of interrupters based on the xhci HCSPARAMS1.
295 * - num_online_cpus: maximum msi-x vectors per CPUs core.
296 * Add additional 1 vector to ensure always available interrupt.
297 */
298 xhci->msix_count = min(num_online_cpus() + 1,
299 HCS_MAX_INTRS(xhci->hcs_params1));
300
301 xhci->msix_entries =
302 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
303 GFP_KERNEL);
304 if (!xhci->msix_entries)
305 return -ENOMEM;
306
307 for (i = 0; i < xhci->msix_count; i++) {
308 xhci->msix_entries[i].entry = i;
309 xhci->msix_entries[i].vector = 0;
310 }
311
312 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
313 if (ret) {
314 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
315 "Failed to enable MSI-X");
316 goto free_entries;
317 }
318
319 for (i = 0; i < xhci->msix_count; i++) {
320 ret = request_irq(xhci->msix_entries[i].vector,
321 xhci_msi_irq,
322 0, "xhci_hcd", xhci_to_hcd(xhci));
323 if (ret)
324 goto disable_msix;
325 }
326
327 hcd->msix_enabled = 1;
328 return ret;
329
330disable_msix:
331 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
332 xhci_free_irq(xhci);
333 pci_disable_msix(pdev);
334free_entries:
335 kfree(xhci->msix_entries);
336 xhci->msix_entries = NULL;
337 return ret;
338}
339
340/* Free any IRQs and disable MSI-X */
341static void xhci_cleanup_msix(struct xhci_hcd *xhci)
342{
343 struct usb_hcd *hcd = xhci_to_hcd(xhci);
344 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
345
346 if (xhci->quirks & XHCI_PLAT)
347 return;
348
349 xhci_free_irq(xhci);
350
351 if (xhci->msix_entries) {
352 pci_disable_msix(pdev);
353 kfree(xhci->msix_entries);
354 xhci->msix_entries = NULL;
355 } else {
356 pci_disable_msi(pdev);
357 }
358
359 hcd->msix_enabled = 0;
360 return;
361}
362
363static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
364{
365 int i;
366
367 if (xhci->msix_entries) {
368 for (i = 0; i < xhci->msix_count; i++)
369 synchronize_irq(xhci->msix_entries[i].vector);
370 }
371}
372
373static int xhci_try_enable_msi(struct usb_hcd *hcd)
374{
375 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
376 struct pci_dev *pdev;
377 int ret;
378
379 /* The xhci platform device has set up IRQs through usb_add_hcd. */
380 if (xhci->quirks & XHCI_PLAT)
381 return 0;
382
383 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
384 /*
385 * Some Fresco Logic host controllers advertise MSI, but fail to
386 * generate interrupts. Don't even try to enable MSI.
387 */
388 if (xhci->quirks & XHCI_BROKEN_MSI)
389 goto legacy_irq;
390
391 /* unregister the legacy interrupt */
392 if (hcd->irq)
393 free_irq(hcd->irq, hcd);
394 hcd->irq = 0;
395
396 ret = xhci_setup_msix(xhci);
397 if (ret)
398 /* fall back to msi*/
399 ret = xhci_setup_msi(xhci);
400
401 if (!ret)
402 /* hcd->irq is 0, we have MSI */
403 return 0;
404
405 if (!pdev->irq) {
406 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
407 return -EINVAL;
408 }
409
410 legacy_irq:
411 if (!strlen(hcd->irq_descr))
412 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
413 hcd->driver->description, hcd->self.busnum);
414
415 /* fall back to legacy interrupt*/
416 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
417 hcd->irq_descr, hcd);
418 if (ret) {
419 xhci_err(xhci, "request interrupt %d failed\n",
420 pdev->irq);
421 return ret;
422 }
423 hcd->irq = pdev->irq;
424 return 0;
425}
426
427#else
428
429static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
430{
431 return 0;
432}
433
434static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
435{
436}
437
438static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
439{
440}
441
442#endif
443
444static void compliance_mode_recovery(unsigned long arg)
445{
446 struct xhci_hcd *xhci;
447 struct usb_hcd *hcd;
448 u32 temp;
449 int i;
450
451 xhci = (struct xhci_hcd *)arg;
452
453 for (i = 0; i < xhci->num_usb3_ports; i++) {
454 temp = readl(xhci->usb3_ports[i]);
455 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
456 /*
457 * Compliance Mode Detected. Letting USB Core
458 * handle the Warm Reset
459 */
460 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
461 "Compliance mode detected->port %d",
462 i + 1);
463 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
464 "Attempting compliance mode recovery");
465 hcd = xhci->shared_hcd;
466
467 if (hcd->state == HC_STATE_SUSPENDED)
468 usb_hcd_resume_root_hub(hcd);
469
470 usb_hcd_poll_rh_status(hcd);
471 }
472 }
473
474 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
475 mod_timer(&xhci->comp_mode_recovery_timer,
476 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
477}
478
479/*
480 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
481 * that causes ports behind that hardware to enter compliance mode sometimes.
482 * The quirk creates a timer that polls every 2 seconds the link state of
483 * each host controller's port and recovers it by issuing a Warm reset
484 * if Compliance mode is detected, otherwise the port will become "dead" (no
485 * device connections or disconnections will be detected anymore). Becasue no
486 * status event is generated when entering compliance mode (per xhci spec),
487 * this quirk is needed on systems that have the failing hardware installed.
488 */
489static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
490{
491 xhci->port_status_u0 = 0;
492 setup_timer(&xhci->comp_mode_recovery_timer,
493 compliance_mode_recovery, (unsigned long)xhci);
494 xhci->comp_mode_recovery_timer.expires = jiffies +
495 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
496
497 add_timer(&xhci->comp_mode_recovery_timer);
498 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
499 "Compliance mode recovery timer initialized");
500}
501
502/*
503 * This function identifies the systems that have installed the SN65LVPE502CP
504 * USB3.0 re-driver and that need the Compliance Mode Quirk.
505 * Systems:
506 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
507 */
508static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
509{
510 const char *dmi_product_name, *dmi_sys_vendor;
511
512 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
513 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
514 if (!dmi_product_name || !dmi_sys_vendor)
515 return false;
516
517 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
518 return false;
519
520 if (strstr(dmi_product_name, "Z420") ||
521 strstr(dmi_product_name, "Z620") ||
522 strstr(dmi_product_name, "Z820") ||
523 strstr(dmi_product_name, "Z1 Workstation"))
524 return true;
525
526 return false;
527}
528
529static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
530{
531 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
532}
533
534
535/*
536 * Initialize memory for HCD and xHC (one-time init).
537 *
538 * Program the PAGESIZE register, initialize the device context array, create
539 * device contexts (?), set up a command ring segment (or two?), create event
540 * ring (one for now).
541 */
542int xhci_init(struct usb_hcd *hcd)
543{
544 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
545 int retval = 0;
546
547 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
548 spin_lock_init(&xhci->lock);
549 if (xhci->hci_version == 0x95 && link_quirk) {
550 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
551 "QUIRK: Not clearing Link TRB chain bits.");
552 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
553 } else {
554 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
555 "xHCI doesn't need link TRB QUIRK");
556 }
557 retval = xhci_mem_init(xhci, GFP_KERNEL);
558 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
559
560 /* Initializing Compliance Mode Recovery Data If Needed */
561 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
562 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
563 compliance_mode_recovery_timer_init(xhci);
564 }
565
566 return retval;
567}
568
569/*-------------------------------------------------------------------------*/
570
571
572static int xhci_run_finished(struct xhci_hcd *xhci)
573{
574 if (xhci_start(xhci)) {
575 xhci_halt(xhci);
576 return -ENODEV;
577 }
578 xhci->shared_hcd->state = HC_STATE_RUNNING;
579 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
580
581 if (xhci->quirks & XHCI_NEC_HOST)
582 xhci_ring_cmd_db(xhci);
583
584 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
585 "Finished xhci_run for USB3 roothub");
586 return 0;
587}
588
589/*
590 * Start the HC after it was halted.
591 *
592 * This function is called by the USB core when the HC driver is added.
593 * Its opposite is xhci_stop().
594 *
595 * xhci_init() must be called once before this function can be called.
596 * Reset the HC, enable device slot contexts, program DCBAAP, and
597 * set command ring pointer and event ring pointer.
598 *
599 * Setup MSI-X vectors and enable interrupts.
600 */
601int xhci_run(struct usb_hcd *hcd)
602{
603 u32 temp;
604 u64 temp_64;
605 int ret;
606 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
607
608 /* Start the xHCI host controller running only after the USB 2.0 roothub
609 * is setup.
610 */
611
612 hcd->uses_new_polling = 1;
613 if (!usb_hcd_is_primary_hcd(hcd))
614 return xhci_run_finished(xhci);
615
616 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
617
618 ret = xhci_try_enable_msi(hcd);
619 if (ret)
620 return ret;
621
622 xhci_dbg(xhci, "Command ring memory map follows:\n");
623 xhci_debug_ring(xhci, xhci->cmd_ring);
624 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
625 xhci_dbg_cmd_ptrs(xhci);
626
627 xhci_dbg(xhci, "ERST memory map follows:\n");
628 xhci_dbg_erst(xhci, &xhci->erst);
629 xhci_dbg(xhci, "Event ring:\n");
630 xhci_debug_ring(xhci, xhci->event_ring);
631 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
632 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
633 temp_64 &= ~ERST_PTR_MASK;
634 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
635 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
636
637 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
638 "// Set the interrupt modulation register");
639 temp = readl(&xhci->ir_set->irq_control);
640 temp &= ~ER_IRQ_INTERVAL_MASK;
641 /*
642 * the increment interval is 8 times as much as that defined
643 * in xHCI spec on MTK's controller
644 */
645 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
646 writel(temp, &xhci->ir_set->irq_control);
647
648 /* Set the HCD state before we enable the irqs */
649 temp = readl(&xhci->op_regs->command);
650 temp |= (CMD_EIE);
651 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
652 "// Enable interrupts, cmd = 0x%x.", temp);
653 writel(temp, &xhci->op_regs->command);
654
655 temp = readl(&xhci->ir_set->irq_pending);
656 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
657 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
658 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
659 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
660 xhci_print_ir_set(xhci, 0);
661
662 if (xhci->quirks & XHCI_NEC_HOST) {
663 struct xhci_command *command;
664 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
665 if (!command)
666 return -ENOMEM;
667 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
668 TRB_TYPE(TRB_NEC_GET_FW));
669 }
670 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
671 "Finished xhci_run for USB2 roothub");
672 return 0;
673}
674EXPORT_SYMBOL_GPL(xhci_run);
675
676/*
677 * Stop xHCI driver.
678 *
679 * This function is called by the USB core when the HC driver is removed.
680 * Its opposite is xhci_run().
681 *
682 * Disable device contexts, disable IRQs, and quiesce the HC.
683 * Reset the HC, finish any completed transactions, and cleanup memory.
684 */
685void xhci_stop(struct usb_hcd *hcd)
686{
687 u32 temp;
688 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
689
690 mutex_lock(&xhci->mutex);
691
692 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
693 spin_lock_irq(&xhci->lock);
694
695 xhci->xhc_state |= XHCI_STATE_HALTED;
696 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
697 xhci_halt(xhci);
698 xhci_reset(xhci);
699 spin_unlock_irq(&xhci->lock);
700 }
701
702 if (!usb_hcd_is_primary_hcd(hcd)) {
703 mutex_unlock(&xhci->mutex);
704 return;
705 }
706
707 xhci_cleanup_msix(xhci);
708
709 /* Deleting Compliance Mode Recovery Timer */
710 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
711 (!(xhci_all_ports_seen_u0(xhci)))) {
712 del_timer_sync(&xhci->comp_mode_recovery_timer);
713 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
714 "%s: compliance mode recovery timer deleted",
715 __func__);
716 }
717
718 if (xhci->quirks & XHCI_AMD_PLL_FIX)
719 usb_amd_dev_put();
720
721 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
722 "// Disabling event ring interrupts");
723 temp = readl(&xhci->op_regs->status);
724 writel(temp & ~STS_EINT, &xhci->op_regs->status);
725 temp = readl(&xhci->ir_set->irq_pending);
726 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
727 xhci_print_ir_set(xhci, 0);
728
729 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
730 xhci_mem_cleanup(xhci);
731 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
732 "xhci_stop completed - status = %x",
733 readl(&xhci->op_regs->status));
734 mutex_unlock(&xhci->mutex);
735}
736
737/*
738 * Shutdown HC (not bus-specific)
739 *
740 * This is called when the machine is rebooting or halting. We assume that the
741 * machine will be powered off, and the HC's internal state will be reset.
742 * Don't bother to free memory.
743 *
744 * This will only ever be called with the main usb_hcd (the USB3 roothub).
745 */
746void xhci_shutdown(struct usb_hcd *hcd)
747{
748 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
749
750 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
751 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
752
753 spin_lock_irq(&xhci->lock);
754 xhci_halt(xhci);
755 /* Workaround for spurious wakeups at shutdown with HSW */
756 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
757 xhci_reset(xhci);
758 spin_unlock_irq(&xhci->lock);
759
760 xhci_cleanup_msix(xhci);
761
762 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
763 "xhci_shutdown completed - status = %x",
764 readl(&xhci->op_regs->status));
765
766 /* Yet another workaround for spurious wakeups at shutdown with HSW */
767 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
768 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
769}
770
771#ifdef CONFIG_PM
772static void xhci_save_registers(struct xhci_hcd *xhci)
773{
774 xhci->s3.command = readl(&xhci->op_regs->command);
775 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
776 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
777 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
778 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
779 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
780 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
781 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
782 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
783}
784
785static void xhci_restore_registers(struct xhci_hcd *xhci)
786{
787 writel(xhci->s3.command, &xhci->op_regs->command);
788 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
789 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
790 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
791 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
792 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
793 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
794 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
795 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
796}
797
798static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
799{
800 u64 val_64;
801
802 /* step 2: initialize command ring buffer */
803 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
804 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
805 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
806 xhci->cmd_ring->dequeue) &
807 (u64) ~CMD_RING_RSVD_BITS) |
808 xhci->cmd_ring->cycle_state;
809 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
810 "// Setting command ring address to 0x%llx",
811 (long unsigned long) val_64);
812 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
813}
814
815/*
816 * The whole command ring must be cleared to zero when we suspend the host.
817 *
818 * The host doesn't save the command ring pointer in the suspend well, so we
819 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
820 * aligned, because of the reserved bits in the command ring dequeue pointer
821 * register. Therefore, we can't just set the dequeue pointer back in the
822 * middle of the ring (TRBs are 16-byte aligned).
823 */
824static void xhci_clear_command_ring(struct xhci_hcd *xhci)
825{
826 struct xhci_ring *ring;
827 struct xhci_segment *seg;
828
829 ring = xhci->cmd_ring;
830 seg = ring->deq_seg;
831 do {
832 memset(seg->trbs, 0,
833 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
834 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
835 cpu_to_le32(~TRB_CYCLE);
836 seg = seg->next;
837 } while (seg != ring->deq_seg);
838
839 /* Reset the software enqueue and dequeue pointers */
840 ring->deq_seg = ring->first_seg;
841 ring->dequeue = ring->first_seg->trbs;
842 ring->enq_seg = ring->deq_seg;
843 ring->enqueue = ring->dequeue;
844
845 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
846 /*
847 * Ring is now zeroed, so the HW should look for change of ownership
848 * when the cycle bit is set to 1.
849 */
850 ring->cycle_state = 1;
851
852 /*
853 * Reset the hardware dequeue pointer.
854 * Yes, this will need to be re-written after resume, but we're paranoid
855 * and want to make sure the hardware doesn't access bogus memory
856 * because, say, the BIOS or an SMI started the host without changing
857 * the command ring pointers.
858 */
859 xhci_set_cmd_ring_deq(xhci);
860}
861
862static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
863{
864 int port_index;
865 __le32 __iomem **port_array;
866 unsigned long flags;
867 u32 t1, t2;
868
869 spin_lock_irqsave(&xhci->lock, flags);
870
871 /* disble usb3 ports Wake bits*/
872 port_index = xhci->num_usb3_ports;
873 port_array = xhci->usb3_ports;
874 while (port_index--) {
875 t1 = readl(port_array[port_index]);
876 t1 = xhci_port_state_to_neutral(t1);
877 t2 = t1 & ~PORT_WAKE_BITS;
878 if (t1 != t2)
879 writel(t2, port_array[port_index]);
880 }
881
882 /* disble usb2 ports Wake bits*/
883 port_index = xhci->num_usb2_ports;
884 port_array = xhci->usb2_ports;
885 while (port_index--) {
886 t1 = readl(port_array[port_index]);
887 t1 = xhci_port_state_to_neutral(t1);
888 t2 = t1 & ~PORT_WAKE_BITS;
889 if (t1 != t2)
890 writel(t2, port_array[port_index]);
891 }
892
893 spin_unlock_irqrestore(&xhci->lock, flags);
894}
895
896/*
897 * Stop HC (not bus-specific)
898 *
899 * This is called when the machine transition into S3/S4 mode.
900 *
901 */
902int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
903{
904 int rc = 0;
905 unsigned int delay = XHCI_MAX_HALT_USEC;
906 struct usb_hcd *hcd = xhci_to_hcd(xhci);
907 u32 command;
908
909 if (!hcd->state)
910 return 0;
911
912 if (hcd->state != HC_STATE_SUSPENDED ||
913 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
914 return -EINVAL;
915
916 /* Clear root port wake on bits if wakeup not allowed. */
917 if (!do_wakeup)
918 xhci_disable_port_wake_on_bits(xhci);
919
920 /* Don't poll the roothubs on bus suspend. */
921 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
922 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
923 del_timer_sync(&hcd->rh_timer);
924 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
925 del_timer_sync(&xhci->shared_hcd->rh_timer);
926
927 spin_lock_irq(&xhci->lock);
928 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
929 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
930 /* step 1: stop endpoint */
931 /* skipped assuming that port suspend has done */
932
933 /* step 2: clear Run/Stop bit */
934 command = readl(&xhci->op_regs->command);
935 command &= ~CMD_RUN;
936 writel(command, &xhci->op_regs->command);
937
938 /* Some chips from Fresco Logic need an extraordinary delay */
939 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
940
941 if (xhci_handshake(&xhci->op_regs->status,
942 STS_HALT, STS_HALT, delay)) {
943 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
944 spin_unlock_irq(&xhci->lock);
945 return -ETIMEDOUT;
946 }
947 xhci_clear_command_ring(xhci);
948
949 /* step 3: save registers */
950 xhci_save_registers(xhci);
951
952 /* step 4: set CSS flag */
953 command = readl(&xhci->op_regs->command);
954 command |= CMD_CSS;
955 writel(command, &xhci->op_regs->command);
956 if (xhci_handshake(&xhci->op_regs->status,
957 STS_SAVE, 0, 10 * 1000)) {
958 xhci_warn(xhci, "WARN: xHC save state timeout\n");
959 spin_unlock_irq(&xhci->lock);
960 return -ETIMEDOUT;
961 }
962 spin_unlock_irq(&xhci->lock);
963
964 /*
965 * Deleting Compliance Mode Recovery Timer because the xHCI Host
966 * is about to be suspended.
967 */
968 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
969 (!(xhci_all_ports_seen_u0(xhci)))) {
970 del_timer_sync(&xhci->comp_mode_recovery_timer);
971 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
972 "%s: compliance mode recovery timer deleted",
973 __func__);
974 }
975
976 /* step 5: remove core well power */
977 /* synchronize irq when using MSI-X */
978 xhci_msix_sync_irqs(xhci);
979
980 return rc;
981}
982EXPORT_SYMBOL_GPL(xhci_suspend);
983
984/*
985 * start xHC (not bus-specific)
986 *
987 * This is called when the machine transition from S3/S4 mode.
988 *
989 */
990int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
991{
992 u32 command, temp = 0, status;
993 struct usb_hcd *hcd = xhci_to_hcd(xhci);
994 struct usb_hcd *secondary_hcd;
995 int retval = 0;
996 bool comp_timer_running = false;
997
998 if (!hcd->state)
999 return 0;
1000
1001 /* Wait a bit if either of the roothubs need to settle from the
1002 * transition into bus suspend.
1003 */
1004 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1005 time_before(jiffies,
1006 xhci->bus_state[1].next_statechange))
1007 msleep(100);
1008
1009 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1010 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1011
1012 spin_lock_irq(&xhci->lock);
1013 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1014 hibernated = true;
1015
1016 if (!hibernated) {
1017 /* step 1: restore register */
1018 xhci_restore_registers(xhci);
1019 /* step 2: initialize command ring buffer */
1020 xhci_set_cmd_ring_deq(xhci);
1021 /* step 3: restore state and start state*/
1022 /* step 3: set CRS flag */
1023 command = readl(&xhci->op_regs->command);
1024 command |= CMD_CRS;
1025 writel(command, &xhci->op_regs->command);
1026 if (xhci_handshake(&xhci->op_regs->status,
1027 STS_RESTORE, 0, 10 * 1000)) {
1028 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1029 spin_unlock_irq(&xhci->lock);
1030 return -ETIMEDOUT;
1031 }
1032 temp = readl(&xhci->op_regs->status);
1033 }
1034
1035 /* If restore operation fails, re-initialize the HC during resume */
1036 if ((temp & STS_SRE) || hibernated) {
1037
1038 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1039 !(xhci_all_ports_seen_u0(xhci))) {
1040 del_timer_sync(&xhci->comp_mode_recovery_timer);
1041 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1042 "Compliance Mode Recovery Timer deleted!");
1043 }
1044
1045 /* Let the USB core know _both_ roothubs lost power. */
1046 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1047 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1048
1049 xhci_dbg(xhci, "Stop HCD\n");
1050 xhci_halt(xhci);
1051 xhci_reset(xhci);
1052 spin_unlock_irq(&xhci->lock);
1053 xhci_cleanup_msix(xhci);
1054
1055 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1056 temp = readl(&xhci->op_regs->status);
1057 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1058 temp = readl(&xhci->ir_set->irq_pending);
1059 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1060 xhci_print_ir_set(xhci, 0);
1061
1062 xhci_dbg(xhci, "cleaning up memory\n");
1063 xhci_mem_cleanup(xhci);
1064 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1065 readl(&xhci->op_regs->status));
1066
1067 /* USB core calls the PCI reinit and start functions twice:
1068 * first with the primary HCD, and then with the secondary HCD.
1069 * If we don't do the same, the host will never be started.
1070 */
1071 if (!usb_hcd_is_primary_hcd(hcd))
1072 secondary_hcd = hcd;
1073 else
1074 secondary_hcd = xhci->shared_hcd;
1075
1076 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1077 retval = xhci_init(hcd->primary_hcd);
1078 if (retval)
1079 return retval;
1080 comp_timer_running = true;
1081
1082 xhci_dbg(xhci, "Start the primary HCD\n");
1083 retval = xhci_run(hcd->primary_hcd);
1084 if (!retval) {
1085 xhci_dbg(xhci, "Start the secondary HCD\n");
1086 retval = xhci_run(secondary_hcd);
1087 }
1088 hcd->state = HC_STATE_SUSPENDED;
1089 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1090 goto done;
1091 }
1092
1093 /* step 4: set Run/Stop bit */
1094 command = readl(&xhci->op_regs->command);
1095 command |= CMD_RUN;
1096 writel(command, &xhci->op_regs->command);
1097 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1098 0, 250 * 1000);
1099
1100 /* step 5: walk topology and initialize portsc,
1101 * portpmsc and portli
1102 */
1103 /* this is done in bus_resume */
1104
1105 /* step 6: restart each of the previously
1106 * Running endpoints by ringing their doorbells
1107 */
1108
1109 spin_unlock_irq(&xhci->lock);
1110
1111 done:
1112 if (retval == 0) {
1113 /* Resume root hubs only when have pending events. */
1114 status = readl(&xhci->op_regs->status);
1115 if (status & STS_EINT) {
1116 usb_hcd_resume_root_hub(xhci->shared_hcd);
1117 usb_hcd_resume_root_hub(hcd);
1118 }
1119 }
1120
1121 /*
1122 * If system is subject to the Quirk, Compliance Mode Timer needs to
1123 * be re-initialized Always after a system resume. Ports are subject
1124 * to suffer the Compliance Mode issue again. It doesn't matter if
1125 * ports have entered previously to U0 before system's suspension.
1126 */
1127 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1128 compliance_mode_recovery_timer_init(xhci);
1129
1130 /* Re-enable port polling. */
1131 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1132 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1133 usb_hcd_poll_rh_status(xhci->shared_hcd);
1134 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1135 usb_hcd_poll_rh_status(hcd);
1136
1137 return retval;
1138}
1139EXPORT_SYMBOL_GPL(xhci_resume);
1140#endif /* CONFIG_PM */
1141
1142/*-------------------------------------------------------------------------*/
1143
1144/**
1145 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1146 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1147 * value to right shift 1 for the bitmask.
1148 *
1149 * Index = (epnum * 2) + direction - 1,
1150 * where direction = 0 for OUT, 1 for IN.
1151 * For control endpoints, the IN index is used (OUT index is unused), so
1152 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1153 */
1154unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1155{
1156 unsigned int index;
1157 if (usb_endpoint_xfer_control(desc))
1158 index = (unsigned int) (usb_endpoint_num(desc)*2);
1159 else
1160 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1161 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1162 return index;
1163}
1164
1165/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1166 * address from the XHCI endpoint index.
1167 */
1168unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1169{
1170 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1171 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1172 return direction | number;
1173}
1174
1175/* Find the flag for this endpoint (for use in the control context). Use the
1176 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1177 * bit 1, etc.
1178 */
1179unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1180{
1181 return 1 << (xhci_get_endpoint_index(desc) + 1);
1182}
1183
1184/* Find the flag for this endpoint (for use in the control context). Use the
1185 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1186 * bit 1, etc.
1187 */
1188unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1189{
1190 return 1 << (ep_index + 1);
1191}
1192
1193/* Compute the last valid endpoint context index. Basically, this is the
1194 * endpoint index plus one. For slot contexts with more than valid endpoint,
1195 * we find the most significant bit set in the added contexts flags.
1196 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1197 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1198 */
1199unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1200{
1201 return fls(added_ctxs) - 1;
1202}
1203
1204/* Returns 1 if the arguments are OK;
1205 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1206 */
1207static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1208 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1209 const char *func) {
1210 struct xhci_hcd *xhci;
1211 struct xhci_virt_device *virt_dev;
1212
1213 if (!hcd || (check_ep && !ep) || !udev) {
1214 pr_debug("xHCI %s called with invalid args\n", func);
1215 return -EINVAL;
1216 }
1217 if (!udev->parent) {
1218 pr_debug("xHCI %s called for root hub\n", func);
1219 return 0;
1220 }
1221
1222 xhci = hcd_to_xhci(hcd);
1223 if (check_virt_dev) {
1224 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1225 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1226 func);
1227 return -EINVAL;
1228 }
1229
1230 virt_dev = xhci->devs[udev->slot_id];
1231 if (virt_dev->udev != udev) {
1232 xhci_dbg(xhci, "xHCI %s called with udev and "
1233 "virt_dev does not match\n", func);
1234 return -EINVAL;
1235 }
1236 }
1237
1238 if (xhci->xhc_state & XHCI_STATE_HALTED)
1239 return -ENODEV;
1240
1241 return 1;
1242}
1243
1244static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1245 struct usb_device *udev, struct xhci_command *command,
1246 bool ctx_change, bool must_succeed);
1247
1248/*
1249 * Full speed devices may have a max packet size greater than 8 bytes, but the
1250 * USB core doesn't know that until it reads the first 8 bytes of the
1251 * descriptor. If the usb_device's max packet size changes after that point,
1252 * we need to issue an evaluate context command and wait on it.
1253 */
1254static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1255 unsigned int ep_index, struct urb *urb)
1256{
1257 struct xhci_container_ctx *out_ctx;
1258 struct xhci_input_control_ctx *ctrl_ctx;
1259 struct xhci_ep_ctx *ep_ctx;
1260 struct xhci_command *command;
1261 int max_packet_size;
1262 int hw_max_packet_size;
1263 int ret = 0;
1264
1265 out_ctx = xhci->devs[slot_id]->out_ctx;
1266 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1267 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1268 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1269 if (hw_max_packet_size != max_packet_size) {
1270 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1271 "Max Packet Size for ep 0 changed.");
1272 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1273 "Max packet size in usb_device = %d",
1274 max_packet_size);
1275 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1276 "Max packet size in xHCI HW = %d",
1277 hw_max_packet_size);
1278 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1279 "Issuing evaluate context command.");
1280
1281 /* Set up the input context flags for the command */
1282 /* FIXME: This won't work if a non-default control endpoint
1283 * changes max packet sizes.
1284 */
1285
1286 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1287 if (!command)
1288 return -ENOMEM;
1289
1290 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1291 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1292 if (!ctrl_ctx) {
1293 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1294 __func__);
1295 ret = -ENOMEM;
1296 goto command_cleanup;
1297 }
1298 /* Set up the modified control endpoint 0 */
1299 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1300 xhci->devs[slot_id]->out_ctx, ep_index);
1301
1302 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1303 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1304 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1305
1306 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1307 ctrl_ctx->drop_flags = 0;
1308
1309 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1310 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1311 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1312 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1313
1314 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1315 true, false);
1316
1317 /* Clean up the input context for later use by bandwidth
1318 * functions.
1319 */
1320 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1321command_cleanup:
1322 kfree(command->completion);
1323 kfree(command);
1324 }
1325 return ret;
1326}
1327
1328/*
1329 * non-error returns are a promise to giveback() the urb later
1330 * we drop ownership so next owner (or urb unlink) can get it
1331 */
1332int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1333{
1334 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1335 struct xhci_td *buffer;
1336 unsigned long flags;
1337 int ret = 0;
1338 unsigned int slot_id, ep_index;
1339 struct urb_priv *urb_priv;
1340 int size, i;
1341
1342 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1343 true, true, __func__) <= 0)
1344 return -EINVAL;
1345
1346 slot_id = urb->dev->slot_id;
1347 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1348
1349 if (!HCD_HW_ACCESSIBLE(hcd)) {
1350 if (!in_interrupt())
1351 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1352 ret = -ESHUTDOWN;
1353 goto exit;
1354 }
1355
1356 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1357 size = urb->number_of_packets;
1358 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1359 urb->transfer_buffer_length > 0 &&
1360 urb->transfer_flags & URB_ZERO_PACKET &&
1361 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1362 size = 2;
1363 else
1364 size = 1;
1365
1366 urb_priv = kzalloc(sizeof(struct urb_priv) +
1367 size * sizeof(struct xhci_td *), mem_flags);
1368 if (!urb_priv)
1369 return -ENOMEM;
1370
1371 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1372 if (!buffer) {
1373 kfree(urb_priv);
1374 return -ENOMEM;
1375 }
1376
1377 for (i = 0; i < size; i++) {
1378 urb_priv->td[i] = buffer;
1379 buffer++;
1380 }
1381
1382 urb_priv->length = size;
1383 urb_priv->td_cnt = 0;
1384 urb->hcpriv = urb_priv;
1385
1386 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1387 /* Check to see if the max packet size for the default control
1388 * endpoint changed during FS device enumeration
1389 */
1390 if (urb->dev->speed == USB_SPEED_FULL) {
1391 ret = xhci_check_maxpacket(xhci, slot_id,
1392 ep_index, urb);
1393 if (ret < 0) {
1394 xhci_urb_free_priv(urb_priv);
1395 urb->hcpriv = NULL;
1396 return ret;
1397 }
1398 }
1399
1400 /* We have a spinlock and interrupts disabled, so we must pass
1401 * atomic context to this function, which may allocate memory.
1402 */
1403 spin_lock_irqsave(&xhci->lock, flags);
1404 if (xhci->xhc_state & XHCI_STATE_DYING)
1405 goto dying;
1406 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1407 slot_id, ep_index);
1408 if (ret)
1409 goto free_priv;
1410 spin_unlock_irqrestore(&xhci->lock, flags);
1411 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1412 spin_lock_irqsave(&xhci->lock, flags);
1413 if (xhci->xhc_state & XHCI_STATE_DYING)
1414 goto dying;
1415 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1416 EP_GETTING_STREAMS) {
1417 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1418 "is transitioning to using streams.\n");
1419 ret = -EINVAL;
1420 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1421 EP_GETTING_NO_STREAMS) {
1422 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1423 "is transitioning to "
1424 "not having streams.\n");
1425 ret = -EINVAL;
1426 } else {
1427 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1428 slot_id, ep_index);
1429 }
1430 if (ret)
1431 goto free_priv;
1432 spin_unlock_irqrestore(&xhci->lock, flags);
1433 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1434 spin_lock_irqsave(&xhci->lock, flags);
1435 if (xhci->xhc_state & XHCI_STATE_DYING)
1436 goto dying;
1437 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1438 slot_id, ep_index);
1439 if (ret)
1440 goto free_priv;
1441 spin_unlock_irqrestore(&xhci->lock, flags);
1442 } else {
1443 spin_lock_irqsave(&xhci->lock, flags);
1444 if (xhci->xhc_state & XHCI_STATE_DYING)
1445 goto dying;
1446 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1447 slot_id, ep_index);
1448 if (ret)
1449 goto free_priv;
1450 spin_unlock_irqrestore(&xhci->lock, flags);
1451 }
1452exit:
1453 return ret;
1454dying:
1455 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1456 "non-responsive xHCI host.\n",
1457 urb->ep->desc.bEndpointAddress, urb);
1458 ret = -ESHUTDOWN;
1459free_priv:
1460 xhci_urb_free_priv(urb_priv);
1461 urb->hcpriv = NULL;
1462 spin_unlock_irqrestore(&xhci->lock, flags);
1463 return ret;
1464}
1465
1466/*
1467 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1468 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1469 * should pick up where it left off in the TD, unless a Set Transfer Ring
1470 * Dequeue Pointer is issued.
1471 *
1472 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1473 * the ring. Since the ring is a contiguous structure, they can't be physically
1474 * removed. Instead, there are two options:
1475 *
1476 * 1) If the HC is in the middle of processing the URB to be canceled, we
1477 * simply move the ring's dequeue pointer past those TRBs using the Set
1478 * Transfer Ring Dequeue Pointer command. This will be the common case,
1479 * when drivers timeout on the last submitted URB and attempt to cancel.
1480 *
1481 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1482 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1483 * HC will need to invalidate the any TRBs it has cached after the stop
1484 * endpoint command, as noted in the xHCI 0.95 errata.
1485 *
1486 * 3) The TD may have completed by the time the Stop Endpoint Command
1487 * completes, so software needs to handle that case too.
1488 *
1489 * This function should protect against the TD enqueueing code ringing the
1490 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1491 * It also needs to account for multiple cancellations on happening at the same
1492 * time for the same endpoint.
1493 *
1494 * Note that this function can be called in any context, or so says
1495 * usb_hcd_unlink_urb()
1496 */
1497int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1498{
1499 unsigned long flags;
1500 int ret, i;
1501 u32 temp;
1502 struct xhci_hcd *xhci;
1503 struct urb_priv *urb_priv;
1504 struct xhci_td *td;
1505 unsigned int ep_index;
1506 struct xhci_ring *ep_ring;
1507 struct xhci_virt_ep *ep;
1508 struct xhci_command *command;
1509
1510 xhci = hcd_to_xhci(hcd);
1511 spin_lock_irqsave(&xhci->lock, flags);
1512 /* Make sure the URB hasn't completed or been unlinked already */
1513 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1514 if (ret || !urb->hcpriv)
1515 goto done;
1516 temp = readl(&xhci->op_regs->status);
1517 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1518 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1519 "HW died, freeing TD.");
1520 urb_priv = urb->hcpriv;
1521 for (i = urb_priv->td_cnt;
1522 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1523 i++) {
1524 td = urb_priv->td[i];
1525 if (!list_empty(&td->td_list))
1526 list_del_init(&td->td_list);
1527 if (!list_empty(&td->cancelled_td_list))
1528 list_del_init(&td->cancelled_td_list);
1529 }
1530
1531 usb_hcd_unlink_urb_from_ep(hcd, urb);
1532 spin_unlock_irqrestore(&xhci->lock, flags);
1533 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1534 xhci_urb_free_priv(urb_priv);
1535 return ret;
1536 }
1537
1538 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1539 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1540 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1541 if (!ep_ring) {
1542 ret = -EINVAL;
1543 goto done;
1544 }
1545
1546 urb_priv = urb->hcpriv;
1547 i = urb_priv->td_cnt;
1548 if (i < urb_priv->length)
1549 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1550 "Cancel URB %p, dev %s, ep 0x%x, "
1551 "starting at offset 0x%llx",
1552 urb, urb->dev->devpath,
1553 urb->ep->desc.bEndpointAddress,
1554 (unsigned long long) xhci_trb_virt_to_dma(
1555 urb_priv->td[i]->start_seg,
1556 urb_priv->td[i]->first_trb));
1557
1558 for (; i < urb_priv->length; i++) {
1559 td = urb_priv->td[i];
1560 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1561 }
1562
1563 /* Queue a stop endpoint command, but only if this is
1564 * the first cancellation to be handled.
1565 */
1566 if (!(ep->ep_state & EP_HALT_PENDING)) {
1567 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1568 if (!command) {
1569 ret = -ENOMEM;
1570 goto done;
1571 }
1572 ep->ep_state |= EP_HALT_PENDING;
1573 ep->stop_cmds_pending++;
1574 ep->stop_cmd_timer.expires = jiffies +
1575 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1576 add_timer(&ep->stop_cmd_timer);
1577 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1578 ep_index, 0);
1579 xhci_ring_cmd_db(xhci);
1580 }
1581done:
1582 spin_unlock_irqrestore(&xhci->lock, flags);
1583 return ret;
1584}
1585
1586/* Drop an endpoint from a new bandwidth configuration for this device.
1587 * Only one call to this function is allowed per endpoint before
1588 * check_bandwidth() or reset_bandwidth() must be called.
1589 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1590 * add the endpoint to the schedule with possibly new parameters denoted by a
1591 * different endpoint descriptor in usb_host_endpoint.
1592 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1593 * not allowed.
1594 *
1595 * The USB core will not allow URBs to be queued to an endpoint that is being
1596 * disabled, so there's no need for mutual exclusion to protect
1597 * the xhci->devs[slot_id] structure.
1598 */
1599int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1600 struct usb_host_endpoint *ep)
1601{
1602 struct xhci_hcd *xhci;
1603 struct xhci_container_ctx *in_ctx, *out_ctx;
1604 struct xhci_input_control_ctx *ctrl_ctx;
1605 unsigned int ep_index;
1606 struct xhci_ep_ctx *ep_ctx;
1607 u32 drop_flag;
1608 u32 new_add_flags, new_drop_flags;
1609 int ret;
1610
1611 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1612 if (ret <= 0)
1613 return ret;
1614 xhci = hcd_to_xhci(hcd);
1615 if (xhci->xhc_state & XHCI_STATE_DYING)
1616 return -ENODEV;
1617
1618 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1619 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1620 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1621 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1622 __func__, drop_flag);
1623 return 0;
1624 }
1625
1626 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1627 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1628 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1629 if (!ctrl_ctx) {
1630 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1631 __func__);
1632 return 0;
1633 }
1634
1635 ep_index = xhci_get_endpoint_index(&ep->desc);
1636 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1637 /* If the HC already knows the endpoint is disabled,
1638 * or the HCD has noted it is disabled, ignore this request
1639 */
1640 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1641 le32_to_cpu(ctrl_ctx->drop_flags) &
1642 xhci_get_endpoint_flag(&ep->desc)) {
1643 /* Do not warn when called after a usb_device_reset */
1644 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1645 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1646 __func__, ep);
1647 return 0;
1648 }
1649
1650 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1651 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1652
1653 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1654 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1655
1656 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1657
1658 if (xhci->quirks & XHCI_MTK_HOST)
1659 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1660
1661 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1662 (unsigned int) ep->desc.bEndpointAddress,
1663 udev->slot_id,
1664 (unsigned int) new_drop_flags,
1665 (unsigned int) new_add_flags);
1666 return 0;
1667}
1668
1669/* Add an endpoint to a new possible bandwidth configuration for this device.
1670 * Only one call to this function is allowed per endpoint before
1671 * check_bandwidth() or reset_bandwidth() must be called.
1672 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1673 * add the endpoint to the schedule with possibly new parameters denoted by a
1674 * different endpoint descriptor in usb_host_endpoint.
1675 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1676 * not allowed.
1677 *
1678 * The USB core will not allow URBs to be queued to an endpoint until the
1679 * configuration or alt setting is installed in the device, so there's no need
1680 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1681 */
1682int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1683 struct usb_host_endpoint *ep)
1684{
1685 struct xhci_hcd *xhci;
1686 struct xhci_container_ctx *in_ctx;
1687 unsigned int ep_index;
1688 struct xhci_input_control_ctx *ctrl_ctx;
1689 u32 added_ctxs;
1690 u32 new_add_flags, new_drop_flags;
1691 struct xhci_virt_device *virt_dev;
1692 int ret = 0;
1693
1694 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1695 if (ret <= 0) {
1696 /* So we won't queue a reset ep command for a root hub */
1697 ep->hcpriv = NULL;
1698 return ret;
1699 }
1700 xhci = hcd_to_xhci(hcd);
1701 if (xhci->xhc_state & XHCI_STATE_DYING)
1702 return -ENODEV;
1703
1704 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1705 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1706 /* FIXME when we have to issue an evaluate endpoint command to
1707 * deal with ep0 max packet size changing once we get the
1708 * descriptors
1709 */
1710 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1711 __func__, added_ctxs);
1712 return 0;
1713 }
1714
1715 virt_dev = xhci->devs[udev->slot_id];
1716 in_ctx = virt_dev->in_ctx;
1717 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1718 if (!ctrl_ctx) {
1719 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1720 __func__);
1721 return 0;
1722 }
1723
1724 ep_index = xhci_get_endpoint_index(&ep->desc);
1725 /* If this endpoint is already in use, and the upper layers are trying
1726 * to add it again without dropping it, reject the addition.
1727 */
1728 if (virt_dev->eps[ep_index].ring &&
1729 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1730 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1731 "without dropping it.\n",
1732 (unsigned int) ep->desc.bEndpointAddress);
1733 return -EINVAL;
1734 }
1735
1736 /* If the HCD has already noted the endpoint is enabled,
1737 * ignore this request.
1738 */
1739 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1740 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1741 __func__, ep);
1742 return 0;
1743 }
1744
1745 /*
1746 * Configuration and alternate setting changes must be done in
1747 * process context, not interrupt context (or so documenation
1748 * for usb_set_interface() and usb_set_configuration() claim).
1749 */
1750 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1751 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1752 __func__, ep->desc.bEndpointAddress);
1753 return -ENOMEM;
1754 }
1755
1756 if (xhci->quirks & XHCI_MTK_HOST) {
1757 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1758 if (ret < 0) {
1759 xhci_free_or_cache_endpoint_ring(xhci,
1760 virt_dev, ep_index);
1761 return ret;
1762 }
1763 }
1764
1765 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1766 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1767
1768 /* If xhci_endpoint_disable() was called for this endpoint, but the
1769 * xHC hasn't been notified yet through the check_bandwidth() call,
1770 * this re-adds a new state for the endpoint from the new endpoint
1771 * descriptors. We must drop and re-add this endpoint, so we leave the
1772 * drop flags alone.
1773 */
1774 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1775
1776 /* Store the usb_device pointer for later use */
1777 ep->hcpriv = udev;
1778
1779 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1780 (unsigned int) ep->desc.bEndpointAddress,
1781 udev->slot_id,
1782 (unsigned int) new_drop_flags,
1783 (unsigned int) new_add_flags);
1784 return 0;
1785}
1786
1787static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1788{
1789 struct xhci_input_control_ctx *ctrl_ctx;
1790 struct xhci_ep_ctx *ep_ctx;
1791 struct xhci_slot_ctx *slot_ctx;
1792 int i;
1793
1794 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1795 if (!ctrl_ctx) {
1796 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1797 __func__);
1798 return;
1799 }
1800
1801 /* When a device's add flag and drop flag are zero, any subsequent
1802 * configure endpoint command will leave that endpoint's state
1803 * untouched. Make sure we don't leave any old state in the input
1804 * endpoint contexts.
1805 */
1806 ctrl_ctx->drop_flags = 0;
1807 ctrl_ctx->add_flags = 0;
1808 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1809 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1810 /* Endpoint 0 is always valid */
1811 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1812 for (i = 1; i < 31; ++i) {
1813 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1814 ep_ctx->ep_info = 0;
1815 ep_ctx->ep_info2 = 0;
1816 ep_ctx->deq = 0;
1817 ep_ctx->tx_info = 0;
1818 }
1819}
1820
1821static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1822 struct usb_device *udev, u32 *cmd_status)
1823{
1824 int ret;
1825
1826 switch (*cmd_status) {
1827 case COMP_CMD_ABORT:
1828 case COMP_CMD_STOP:
1829 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1830 ret = -ETIME;
1831 break;
1832 case COMP_ENOMEM:
1833 dev_warn(&udev->dev,
1834 "Not enough host controller resources for new device state.\n");
1835 ret = -ENOMEM;
1836 /* FIXME: can we allocate more resources for the HC? */
1837 break;
1838 case COMP_BW_ERR:
1839 case COMP_2ND_BW_ERR:
1840 dev_warn(&udev->dev,
1841 "Not enough bandwidth for new device state.\n");
1842 ret = -ENOSPC;
1843 /* FIXME: can we go back to the old state? */
1844 break;
1845 case COMP_TRB_ERR:
1846 /* the HCD set up something wrong */
1847 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1848 "add flag = 1, "
1849 "and endpoint is not disabled.\n");
1850 ret = -EINVAL;
1851 break;
1852 case COMP_DEV_ERR:
1853 dev_warn(&udev->dev,
1854 "ERROR: Incompatible device for endpoint configure command.\n");
1855 ret = -ENODEV;
1856 break;
1857 case COMP_SUCCESS:
1858 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1859 "Successful Endpoint Configure command");
1860 ret = 0;
1861 break;
1862 default:
1863 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1864 *cmd_status);
1865 ret = -EINVAL;
1866 break;
1867 }
1868 return ret;
1869}
1870
1871static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1872 struct usb_device *udev, u32 *cmd_status)
1873{
1874 int ret;
1875 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1876
1877 switch (*cmd_status) {
1878 case COMP_CMD_ABORT:
1879 case COMP_CMD_STOP:
1880 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1881 ret = -ETIME;
1882 break;
1883 case COMP_EINVAL:
1884 dev_warn(&udev->dev,
1885 "WARN: xHCI driver setup invalid evaluate context command.\n");
1886 ret = -EINVAL;
1887 break;
1888 case COMP_EBADSLT:
1889 dev_warn(&udev->dev,
1890 "WARN: slot not enabled for evaluate context command.\n");
1891 ret = -EINVAL;
1892 break;
1893 case COMP_CTX_STATE:
1894 dev_warn(&udev->dev,
1895 "WARN: invalid context state for evaluate context command.\n");
1896 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1897 ret = -EINVAL;
1898 break;
1899 case COMP_DEV_ERR:
1900 dev_warn(&udev->dev,
1901 "ERROR: Incompatible device for evaluate context command.\n");
1902 ret = -ENODEV;
1903 break;
1904 case COMP_MEL_ERR:
1905 /* Max Exit Latency too large error */
1906 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1907 ret = -EINVAL;
1908 break;
1909 case COMP_SUCCESS:
1910 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1911 "Successful evaluate context command");
1912 ret = 0;
1913 break;
1914 default:
1915 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1916 *cmd_status);
1917 ret = -EINVAL;
1918 break;
1919 }
1920 return ret;
1921}
1922
1923static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1924 struct xhci_input_control_ctx *ctrl_ctx)
1925{
1926 u32 valid_add_flags;
1927 u32 valid_drop_flags;
1928
1929 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1930 * (bit 1). The default control endpoint is added during the Address
1931 * Device command and is never removed until the slot is disabled.
1932 */
1933 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1934 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1935
1936 /* Use hweight32 to count the number of ones in the add flags, or
1937 * number of endpoints added. Don't count endpoints that are changed
1938 * (both added and dropped).
1939 */
1940 return hweight32(valid_add_flags) -
1941 hweight32(valid_add_flags & valid_drop_flags);
1942}
1943
1944static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1945 struct xhci_input_control_ctx *ctrl_ctx)
1946{
1947 u32 valid_add_flags;
1948 u32 valid_drop_flags;
1949
1950 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1951 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1952
1953 return hweight32(valid_drop_flags) -
1954 hweight32(valid_add_flags & valid_drop_flags);
1955}
1956
1957/*
1958 * We need to reserve the new number of endpoints before the configure endpoint
1959 * command completes. We can't subtract the dropped endpoints from the number
1960 * of active endpoints until the command completes because we can oversubscribe
1961 * the host in this case:
1962 *
1963 * - the first configure endpoint command drops more endpoints than it adds
1964 * - a second configure endpoint command that adds more endpoints is queued
1965 * - the first configure endpoint command fails, so the config is unchanged
1966 * - the second command may succeed, even though there isn't enough resources
1967 *
1968 * Must be called with xhci->lock held.
1969 */
1970static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1971 struct xhci_input_control_ctx *ctrl_ctx)
1972{
1973 u32 added_eps;
1974
1975 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1976 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1977 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1978 "Not enough ep ctxs: "
1979 "%u active, need to add %u, limit is %u.",
1980 xhci->num_active_eps, added_eps,
1981 xhci->limit_active_eps);
1982 return -ENOMEM;
1983 }
1984 xhci->num_active_eps += added_eps;
1985 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1986 "Adding %u ep ctxs, %u now active.", added_eps,
1987 xhci->num_active_eps);
1988 return 0;
1989}
1990
1991/*
1992 * The configure endpoint was failed by the xHC for some other reason, so we
1993 * need to revert the resources that failed configuration would have used.
1994 *
1995 * Must be called with xhci->lock held.
1996 */
1997static void xhci_free_host_resources(struct xhci_hcd *xhci,
1998 struct xhci_input_control_ctx *ctrl_ctx)
1999{
2000 u32 num_failed_eps;
2001
2002 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2003 xhci->num_active_eps -= num_failed_eps;
2004 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2005 "Removing %u failed ep ctxs, %u now active.",
2006 num_failed_eps,
2007 xhci->num_active_eps);
2008}
2009
2010/*
2011 * Now that the command has completed, clean up the active endpoint count by
2012 * subtracting out the endpoints that were dropped (but not changed).
2013 *
2014 * Must be called with xhci->lock held.
2015 */
2016static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2017 struct xhci_input_control_ctx *ctrl_ctx)
2018{
2019 u32 num_dropped_eps;
2020
2021 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2022 xhci->num_active_eps -= num_dropped_eps;
2023 if (num_dropped_eps)
2024 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2025 "Removing %u dropped ep ctxs, %u now active.",
2026 num_dropped_eps,
2027 xhci->num_active_eps);
2028}
2029
2030static unsigned int xhci_get_block_size(struct usb_device *udev)
2031{
2032 switch (udev->speed) {
2033 case USB_SPEED_LOW:
2034 case USB_SPEED_FULL:
2035 return FS_BLOCK;
2036 case USB_SPEED_HIGH:
2037 return HS_BLOCK;
2038 case USB_SPEED_SUPER:
2039 case USB_SPEED_SUPER_PLUS:
2040 return SS_BLOCK;
2041 case USB_SPEED_UNKNOWN:
2042 case USB_SPEED_WIRELESS:
2043 default:
2044 /* Should never happen */
2045 return 1;
2046 }
2047}
2048
2049static unsigned int
2050xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2051{
2052 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2053 return LS_OVERHEAD;
2054 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2055 return FS_OVERHEAD;
2056 return HS_OVERHEAD;
2057}
2058
2059/* If we are changing a LS/FS device under a HS hub,
2060 * make sure (if we are activating a new TT) that the HS bus has enough
2061 * bandwidth for this new TT.
2062 */
2063static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2064 struct xhci_virt_device *virt_dev,
2065 int old_active_eps)
2066{
2067 struct xhci_interval_bw_table *bw_table;
2068 struct xhci_tt_bw_info *tt_info;
2069
2070 /* Find the bandwidth table for the root port this TT is attached to. */
2071 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2072 tt_info = virt_dev->tt_info;
2073 /* If this TT already had active endpoints, the bandwidth for this TT
2074 * has already been added. Removing all periodic endpoints (and thus
2075 * making the TT enactive) will only decrease the bandwidth used.
2076 */
2077 if (old_active_eps)
2078 return 0;
2079 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2080 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2081 return -ENOMEM;
2082 return 0;
2083 }
2084 /* Not sure why we would have no new active endpoints...
2085 *
2086 * Maybe because of an Evaluate Context change for a hub update or a
2087 * control endpoint 0 max packet size change?
2088 * FIXME: skip the bandwidth calculation in that case.
2089 */
2090 return 0;
2091}
2092
2093static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2094 struct xhci_virt_device *virt_dev)
2095{
2096 unsigned int bw_reserved;
2097
2098 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2099 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2100 return -ENOMEM;
2101
2102 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2103 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2104 return -ENOMEM;
2105
2106 return 0;
2107}
2108
2109/*
2110 * This algorithm is a very conservative estimate of the worst-case scheduling
2111 * scenario for any one interval. The hardware dynamically schedules the
2112 * packets, so we can't tell which microframe could be the limiting factor in
2113 * the bandwidth scheduling. This only takes into account periodic endpoints.
2114 *
2115 * Obviously, we can't solve an NP complete problem to find the minimum worst
2116 * case scenario. Instead, we come up with an estimate that is no less than
2117 * the worst case bandwidth used for any one microframe, but may be an
2118 * over-estimate.
2119 *
2120 * We walk the requirements for each endpoint by interval, starting with the
2121 * smallest interval, and place packets in the schedule where there is only one
2122 * possible way to schedule packets for that interval. In order to simplify
2123 * this algorithm, we record the largest max packet size for each interval, and
2124 * assume all packets will be that size.
2125 *
2126 * For interval 0, we obviously must schedule all packets for each interval.
2127 * The bandwidth for interval 0 is just the amount of data to be transmitted
2128 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2129 * the number of packets).
2130 *
2131 * For interval 1, we have two possible microframes to schedule those packets
2132 * in. For this algorithm, if we can schedule the same number of packets for
2133 * each possible scheduling opportunity (each microframe), we will do so. The
2134 * remaining number of packets will be saved to be transmitted in the gaps in
2135 * the next interval's scheduling sequence.
2136 *
2137 * As we move those remaining packets to be scheduled with interval 2 packets,
2138 * we have to double the number of remaining packets to transmit. This is
2139 * because the intervals are actually powers of 2, and we would be transmitting
2140 * the previous interval's packets twice in this interval. We also have to be
2141 * sure that when we look at the largest max packet size for this interval, we
2142 * also look at the largest max packet size for the remaining packets and take
2143 * the greater of the two.
2144 *
2145 * The algorithm continues to evenly distribute packets in each scheduling
2146 * opportunity, and push the remaining packets out, until we get to the last
2147 * interval. Then those packets and their associated overhead are just added
2148 * to the bandwidth used.
2149 */
2150static int xhci_check_bw_table(struct xhci_hcd *xhci,
2151 struct xhci_virt_device *virt_dev,
2152 int old_active_eps)
2153{
2154 unsigned int bw_reserved;
2155 unsigned int max_bandwidth;
2156 unsigned int bw_used;
2157 unsigned int block_size;
2158 struct xhci_interval_bw_table *bw_table;
2159 unsigned int packet_size = 0;
2160 unsigned int overhead = 0;
2161 unsigned int packets_transmitted = 0;
2162 unsigned int packets_remaining = 0;
2163 unsigned int i;
2164
2165 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2166 return xhci_check_ss_bw(xhci, virt_dev);
2167
2168 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2169 max_bandwidth = HS_BW_LIMIT;
2170 /* Convert percent of bus BW reserved to blocks reserved */
2171 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2172 } else {
2173 max_bandwidth = FS_BW_LIMIT;
2174 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2175 }
2176
2177 bw_table = virt_dev->bw_table;
2178 /* We need to translate the max packet size and max ESIT payloads into
2179 * the units the hardware uses.
2180 */
2181 block_size = xhci_get_block_size(virt_dev->udev);
2182
2183 /* If we are manipulating a LS/FS device under a HS hub, double check
2184 * that the HS bus has enough bandwidth if we are activing a new TT.
2185 */
2186 if (virt_dev->tt_info) {
2187 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2188 "Recalculating BW for rootport %u",
2189 virt_dev->real_port);
2190 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2191 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2192 "newly activated TT.\n");
2193 return -ENOMEM;
2194 }
2195 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2196 "Recalculating BW for TT slot %u port %u",
2197 virt_dev->tt_info->slot_id,
2198 virt_dev->tt_info->ttport);
2199 } else {
2200 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2201 "Recalculating BW for rootport %u",
2202 virt_dev->real_port);
2203 }
2204
2205 /* Add in how much bandwidth will be used for interval zero, or the
2206 * rounded max ESIT payload + number of packets * largest overhead.
2207 */
2208 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2209 bw_table->interval_bw[0].num_packets *
2210 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2211
2212 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2213 unsigned int bw_added;
2214 unsigned int largest_mps;
2215 unsigned int interval_overhead;
2216
2217 /*
2218 * How many packets could we transmit in this interval?
2219 * If packets didn't fit in the previous interval, we will need
2220 * to transmit that many packets twice within this interval.
2221 */
2222 packets_remaining = 2 * packets_remaining +
2223 bw_table->interval_bw[i].num_packets;
2224
2225 /* Find the largest max packet size of this or the previous
2226 * interval.
2227 */
2228 if (list_empty(&bw_table->interval_bw[i].endpoints))
2229 largest_mps = 0;
2230 else {
2231 struct xhci_virt_ep *virt_ep;
2232 struct list_head *ep_entry;
2233
2234 ep_entry = bw_table->interval_bw[i].endpoints.next;
2235 virt_ep = list_entry(ep_entry,
2236 struct xhci_virt_ep, bw_endpoint_list);
2237 /* Convert to blocks, rounding up */
2238 largest_mps = DIV_ROUND_UP(
2239 virt_ep->bw_info.max_packet_size,
2240 block_size);
2241 }
2242 if (largest_mps > packet_size)
2243 packet_size = largest_mps;
2244
2245 /* Use the larger overhead of this or the previous interval. */
2246 interval_overhead = xhci_get_largest_overhead(
2247 &bw_table->interval_bw[i]);
2248 if (interval_overhead > overhead)
2249 overhead = interval_overhead;
2250
2251 /* How many packets can we evenly distribute across
2252 * (1 << (i + 1)) possible scheduling opportunities?
2253 */
2254 packets_transmitted = packets_remaining >> (i + 1);
2255
2256 /* Add in the bandwidth used for those scheduled packets */
2257 bw_added = packets_transmitted * (overhead + packet_size);
2258
2259 /* How many packets do we have remaining to transmit? */
2260 packets_remaining = packets_remaining % (1 << (i + 1));
2261
2262 /* What largest max packet size should those packets have? */
2263 /* If we've transmitted all packets, don't carry over the
2264 * largest packet size.
2265 */
2266 if (packets_remaining == 0) {
2267 packet_size = 0;
2268 overhead = 0;
2269 } else if (packets_transmitted > 0) {
2270 /* Otherwise if we do have remaining packets, and we've
2271 * scheduled some packets in this interval, take the
2272 * largest max packet size from endpoints with this
2273 * interval.
2274 */
2275 packet_size = largest_mps;
2276 overhead = interval_overhead;
2277 }
2278 /* Otherwise carry over packet_size and overhead from the last
2279 * time we had a remainder.
2280 */
2281 bw_used += bw_added;
2282 if (bw_used > max_bandwidth) {
2283 xhci_warn(xhci, "Not enough bandwidth. "
2284 "Proposed: %u, Max: %u\n",
2285 bw_used, max_bandwidth);
2286 return -ENOMEM;
2287 }
2288 }
2289 /*
2290 * Ok, we know we have some packets left over after even-handedly
2291 * scheduling interval 15. We don't know which microframes they will
2292 * fit into, so we over-schedule and say they will be scheduled every
2293 * microframe.
2294 */
2295 if (packets_remaining > 0)
2296 bw_used += overhead + packet_size;
2297
2298 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2299 unsigned int port_index = virt_dev->real_port - 1;
2300
2301 /* OK, we're manipulating a HS device attached to a
2302 * root port bandwidth domain. Include the number of active TTs
2303 * in the bandwidth used.
2304 */
2305 bw_used += TT_HS_OVERHEAD *
2306 xhci->rh_bw[port_index].num_active_tts;
2307 }
2308
2309 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2310 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2311 "Available: %u " "percent",
2312 bw_used, max_bandwidth, bw_reserved,
2313 (max_bandwidth - bw_used - bw_reserved) * 100 /
2314 max_bandwidth);
2315
2316 bw_used += bw_reserved;
2317 if (bw_used > max_bandwidth) {
2318 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2319 bw_used, max_bandwidth);
2320 return -ENOMEM;
2321 }
2322
2323 bw_table->bw_used = bw_used;
2324 return 0;
2325}
2326
2327static bool xhci_is_async_ep(unsigned int ep_type)
2328{
2329 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2330 ep_type != ISOC_IN_EP &&
2331 ep_type != INT_IN_EP);
2332}
2333
2334static bool xhci_is_sync_in_ep(unsigned int ep_type)
2335{
2336 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2337}
2338
2339static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2340{
2341 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2342
2343 if (ep_bw->ep_interval == 0)
2344 return SS_OVERHEAD_BURST +
2345 (ep_bw->mult * ep_bw->num_packets *
2346 (SS_OVERHEAD + mps));
2347 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2348 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2349 1 << ep_bw->ep_interval);
2350
2351}
2352
2353void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2354 struct xhci_bw_info *ep_bw,
2355 struct xhci_interval_bw_table *bw_table,
2356 struct usb_device *udev,
2357 struct xhci_virt_ep *virt_ep,
2358 struct xhci_tt_bw_info *tt_info)
2359{
2360 struct xhci_interval_bw *interval_bw;
2361 int normalized_interval;
2362
2363 if (xhci_is_async_ep(ep_bw->type))
2364 return;
2365
2366 if (udev->speed >= USB_SPEED_SUPER) {
2367 if (xhci_is_sync_in_ep(ep_bw->type))
2368 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2369 xhci_get_ss_bw_consumed(ep_bw);
2370 else
2371 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2372 xhci_get_ss_bw_consumed(ep_bw);
2373 return;
2374 }
2375
2376 /* SuperSpeed endpoints never get added to intervals in the table, so
2377 * this check is only valid for HS/FS/LS devices.
2378 */
2379 if (list_empty(&virt_ep->bw_endpoint_list))
2380 return;
2381 /* For LS/FS devices, we need to translate the interval expressed in
2382 * microframes to frames.
2383 */
2384 if (udev->speed == USB_SPEED_HIGH)
2385 normalized_interval = ep_bw->ep_interval;
2386 else
2387 normalized_interval = ep_bw->ep_interval - 3;
2388
2389 if (normalized_interval == 0)
2390 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2391 interval_bw = &bw_table->interval_bw[normalized_interval];
2392 interval_bw->num_packets -= ep_bw->num_packets;
2393 switch (udev->speed) {
2394 case USB_SPEED_LOW:
2395 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2396 break;
2397 case USB_SPEED_FULL:
2398 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2399 break;
2400 case USB_SPEED_HIGH:
2401 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2402 break;
2403 case USB_SPEED_SUPER:
2404 case USB_SPEED_SUPER_PLUS:
2405 case USB_SPEED_UNKNOWN:
2406 case USB_SPEED_WIRELESS:
2407 /* Should never happen because only LS/FS/HS endpoints will get
2408 * added to the endpoint list.
2409 */
2410 return;
2411 }
2412 if (tt_info)
2413 tt_info->active_eps -= 1;
2414 list_del_init(&virt_ep->bw_endpoint_list);
2415}
2416
2417static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2418 struct xhci_bw_info *ep_bw,
2419 struct xhci_interval_bw_table *bw_table,
2420 struct usb_device *udev,
2421 struct xhci_virt_ep *virt_ep,
2422 struct xhci_tt_bw_info *tt_info)
2423{
2424 struct xhci_interval_bw *interval_bw;
2425 struct xhci_virt_ep *smaller_ep;
2426 int normalized_interval;
2427
2428 if (xhci_is_async_ep(ep_bw->type))
2429 return;
2430
2431 if (udev->speed == USB_SPEED_SUPER) {
2432 if (xhci_is_sync_in_ep(ep_bw->type))
2433 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2434 xhci_get_ss_bw_consumed(ep_bw);
2435 else
2436 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2437 xhci_get_ss_bw_consumed(ep_bw);
2438 return;
2439 }
2440
2441 /* For LS/FS devices, we need to translate the interval expressed in
2442 * microframes to frames.
2443 */
2444 if (udev->speed == USB_SPEED_HIGH)
2445 normalized_interval = ep_bw->ep_interval;
2446 else
2447 normalized_interval = ep_bw->ep_interval - 3;
2448
2449 if (normalized_interval == 0)
2450 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2451 interval_bw = &bw_table->interval_bw[normalized_interval];
2452 interval_bw->num_packets += ep_bw->num_packets;
2453 switch (udev->speed) {
2454 case USB_SPEED_LOW:
2455 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2456 break;
2457 case USB_SPEED_FULL:
2458 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2459 break;
2460 case USB_SPEED_HIGH:
2461 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2462 break;
2463 case USB_SPEED_SUPER:
2464 case USB_SPEED_SUPER_PLUS:
2465 case USB_SPEED_UNKNOWN:
2466 case USB_SPEED_WIRELESS:
2467 /* Should never happen because only LS/FS/HS endpoints will get
2468 * added to the endpoint list.
2469 */
2470 return;
2471 }
2472
2473 if (tt_info)
2474 tt_info->active_eps += 1;
2475 /* Insert the endpoint into the list, largest max packet size first. */
2476 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2477 bw_endpoint_list) {
2478 if (ep_bw->max_packet_size >=
2479 smaller_ep->bw_info.max_packet_size) {
2480 /* Add the new ep before the smaller endpoint */
2481 list_add_tail(&virt_ep->bw_endpoint_list,
2482 &smaller_ep->bw_endpoint_list);
2483 return;
2484 }
2485 }
2486 /* Add the new endpoint at the end of the list. */
2487 list_add_tail(&virt_ep->bw_endpoint_list,
2488 &interval_bw->endpoints);
2489}
2490
2491void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2492 struct xhci_virt_device *virt_dev,
2493 int old_active_eps)
2494{
2495 struct xhci_root_port_bw_info *rh_bw_info;
2496 if (!virt_dev->tt_info)
2497 return;
2498
2499 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2500 if (old_active_eps == 0 &&
2501 virt_dev->tt_info->active_eps != 0) {
2502 rh_bw_info->num_active_tts += 1;
2503 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2504 } else if (old_active_eps != 0 &&
2505 virt_dev->tt_info->active_eps == 0) {
2506 rh_bw_info->num_active_tts -= 1;
2507 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2508 }
2509}
2510
2511static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2512 struct xhci_virt_device *virt_dev,
2513 struct xhci_container_ctx *in_ctx)
2514{
2515 struct xhci_bw_info ep_bw_info[31];
2516 int i;
2517 struct xhci_input_control_ctx *ctrl_ctx;
2518 int old_active_eps = 0;
2519
2520 if (virt_dev->tt_info)
2521 old_active_eps = virt_dev->tt_info->active_eps;
2522
2523 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2524 if (!ctrl_ctx) {
2525 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2526 __func__);
2527 return -ENOMEM;
2528 }
2529
2530 for (i = 0; i < 31; i++) {
2531 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2532 continue;
2533
2534 /* Make a copy of the BW info in case we need to revert this */
2535 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2536 sizeof(ep_bw_info[i]));
2537 /* Drop the endpoint from the interval table if the endpoint is
2538 * being dropped or changed.
2539 */
2540 if (EP_IS_DROPPED(ctrl_ctx, i))
2541 xhci_drop_ep_from_interval_table(xhci,
2542 &virt_dev->eps[i].bw_info,
2543 virt_dev->bw_table,
2544 virt_dev->udev,
2545 &virt_dev->eps[i],
2546 virt_dev->tt_info);
2547 }
2548 /* Overwrite the information stored in the endpoints' bw_info */
2549 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2550 for (i = 0; i < 31; i++) {
2551 /* Add any changed or added endpoints to the interval table */
2552 if (EP_IS_ADDED(ctrl_ctx, i))
2553 xhci_add_ep_to_interval_table(xhci,
2554 &virt_dev->eps[i].bw_info,
2555 virt_dev->bw_table,
2556 virt_dev->udev,
2557 &virt_dev->eps[i],
2558 virt_dev->tt_info);
2559 }
2560
2561 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2562 /* Ok, this fits in the bandwidth we have.
2563 * Update the number of active TTs.
2564 */
2565 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2566 return 0;
2567 }
2568
2569 /* We don't have enough bandwidth for this, revert the stored info. */
2570 for (i = 0; i < 31; i++) {
2571 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2572 continue;
2573
2574 /* Drop the new copies of any added or changed endpoints from
2575 * the interval table.
2576 */
2577 if (EP_IS_ADDED(ctrl_ctx, i)) {
2578 xhci_drop_ep_from_interval_table(xhci,
2579 &virt_dev->eps[i].bw_info,
2580 virt_dev->bw_table,
2581 virt_dev->udev,
2582 &virt_dev->eps[i],
2583 virt_dev->tt_info);
2584 }
2585 /* Revert the endpoint back to its old information */
2586 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2587 sizeof(ep_bw_info[i]));
2588 /* Add any changed or dropped endpoints back into the table */
2589 if (EP_IS_DROPPED(ctrl_ctx, i))
2590 xhci_add_ep_to_interval_table(xhci,
2591 &virt_dev->eps[i].bw_info,
2592 virt_dev->bw_table,
2593 virt_dev->udev,
2594 &virt_dev->eps[i],
2595 virt_dev->tt_info);
2596 }
2597 return -ENOMEM;
2598}
2599
2600
2601/* Issue a configure endpoint command or evaluate context command
2602 * and wait for it to finish.
2603 */
2604static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2605 struct usb_device *udev,
2606 struct xhci_command *command,
2607 bool ctx_change, bool must_succeed)
2608{
2609 int ret;
2610 unsigned long flags;
2611 struct xhci_input_control_ctx *ctrl_ctx;
2612 struct xhci_virt_device *virt_dev;
2613
2614 if (!command)
2615 return -EINVAL;
2616
2617 spin_lock_irqsave(&xhci->lock, flags);
2618 virt_dev = xhci->devs[udev->slot_id];
2619
2620 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2621 if (!ctrl_ctx) {
2622 spin_unlock_irqrestore(&xhci->lock, flags);
2623 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2624 __func__);
2625 return -ENOMEM;
2626 }
2627
2628 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2629 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2630 spin_unlock_irqrestore(&xhci->lock, flags);
2631 xhci_warn(xhci, "Not enough host resources, "
2632 "active endpoint contexts = %u\n",
2633 xhci->num_active_eps);
2634 return -ENOMEM;
2635 }
2636 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2637 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2638 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2639 xhci_free_host_resources(xhci, ctrl_ctx);
2640 spin_unlock_irqrestore(&xhci->lock, flags);
2641 xhci_warn(xhci, "Not enough bandwidth\n");
2642 return -ENOMEM;
2643 }
2644
2645 if (!ctx_change)
2646 ret = xhci_queue_configure_endpoint(xhci, command,
2647 command->in_ctx->dma,
2648 udev->slot_id, must_succeed);
2649 else
2650 ret = xhci_queue_evaluate_context(xhci, command,
2651 command->in_ctx->dma,
2652 udev->slot_id, must_succeed);
2653 if (ret < 0) {
2654 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2655 xhci_free_host_resources(xhci, ctrl_ctx);
2656 spin_unlock_irqrestore(&xhci->lock, flags);
2657 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2658 "FIXME allocate a new ring segment");
2659 return -ENOMEM;
2660 }
2661 xhci_ring_cmd_db(xhci);
2662 spin_unlock_irqrestore(&xhci->lock, flags);
2663
2664 /* Wait for the configure endpoint command to complete */
2665 wait_for_completion(command->completion);
2666
2667 if (!ctx_change)
2668 ret = xhci_configure_endpoint_result(xhci, udev,
2669 &command->status);
2670 else
2671 ret = xhci_evaluate_context_result(xhci, udev,
2672 &command->status);
2673
2674 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2675 spin_lock_irqsave(&xhci->lock, flags);
2676 /* If the command failed, remove the reserved resources.
2677 * Otherwise, clean up the estimate to include dropped eps.
2678 */
2679 if (ret)
2680 xhci_free_host_resources(xhci, ctrl_ctx);
2681 else
2682 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2683 spin_unlock_irqrestore(&xhci->lock, flags);
2684 }
2685 return ret;
2686}
2687
2688static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2689 struct xhci_virt_device *vdev, int i)
2690{
2691 struct xhci_virt_ep *ep = &vdev->eps[i];
2692
2693 if (ep->ep_state & EP_HAS_STREAMS) {
2694 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2695 xhci_get_endpoint_address(i));
2696 xhci_free_stream_info(xhci, ep->stream_info);
2697 ep->stream_info = NULL;
2698 ep->ep_state &= ~EP_HAS_STREAMS;
2699 }
2700}
2701
2702/* Called after one or more calls to xhci_add_endpoint() or
2703 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2704 * to call xhci_reset_bandwidth().
2705 *
2706 * Since we are in the middle of changing either configuration or
2707 * installing a new alt setting, the USB core won't allow URBs to be
2708 * enqueued for any endpoint on the old config or interface. Nothing
2709 * else should be touching the xhci->devs[slot_id] structure, so we
2710 * don't need to take the xhci->lock for manipulating that.
2711 */
2712int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2713{
2714 int i;
2715 int ret = 0;
2716 struct xhci_hcd *xhci;
2717 struct xhci_virt_device *virt_dev;
2718 struct xhci_input_control_ctx *ctrl_ctx;
2719 struct xhci_slot_ctx *slot_ctx;
2720 struct xhci_command *command;
2721
2722 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2723 if (ret <= 0)
2724 return ret;
2725 xhci = hcd_to_xhci(hcd);
2726 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2727 (xhci->xhc_state & XHCI_STATE_REMOVING))
2728 return -ENODEV;
2729
2730 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2731 virt_dev = xhci->devs[udev->slot_id];
2732
2733 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2734 if (!command)
2735 return -ENOMEM;
2736
2737 command->in_ctx = virt_dev->in_ctx;
2738
2739 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2740 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2741 if (!ctrl_ctx) {
2742 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2743 __func__);
2744 ret = -ENOMEM;
2745 goto command_cleanup;
2746 }
2747 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2748 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2749 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2750
2751 /* Don't issue the command if there's no endpoints to update. */
2752 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2753 ctrl_ctx->drop_flags == 0) {
2754 ret = 0;
2755 goto command_cleanup;
2756 }
2757 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2758 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2759 for (i = 31; i >= 1; i--) {
2760 __le32 le32 = cpu_to_le32(BIT(i));
2761
2762 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2763 || (ctrl_ctx->add_flags & le32) || i == 1) {
2764 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2765 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2766 break;
2767 }
2768 }
2769 xhci_dbg(xhci, "New Input Control Context:\n");
2770 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2771 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2772
2773 ret = xhci_configure_endpoint(xhci, udev, command,
2774 false, false);
2775 if (ret)
2776 /* Callee should call reset_bandwidth() */
2777 goto command_cleanup;
2778
2779 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2780 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2781 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2782
2783 /* Free any rings that were dropped, but not changed. */
2784 for (i = 1; i < 31; ++i) {
2785 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2786 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2787 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2788 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2789 }
2790 }
2791 xhci_zero_in_ctx(xhci, virt_dev);
2792 /*
2793 * Install any rings for completely new endpoints or changed endpoints,
2794 * and free or cache any old rings from changed endpoints.
2795 */
2796 for (i = 1; i < 31; ++i) {
2797 if (!virt_dev->eps[i].new_ring)
2798 continue;
2799 /* Only cache or free the old ring if it exists.
2800 * It may not if this is the first add of an endpoint.
2801 */
2802 if (virt_dev->eps[i].ring) {
2803 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2804 }
2805 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2806 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2807 virt_dev->eps[i].new_ring = NULL;
2808 }
2809command_cleanup:
2810 kfree(command->completion);
2811 kfree(command);
2812
2813 return ret;
2814}
2815
2816void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2817{
2818 struct xhci_hcd *xhci;
2819 struct xhci_virt_device *virt_dev;
2820 int i, ret;
2821
2822 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2823 if (ret <= 0)
2824 return;
2825 xhci = hcd_to_xhci(hcd);
2826
2827 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2828 virt_dev = xhci->devs[udev->slot_id];
2829 /* Free any rings allocated for added endpoints */
2830 for (i = 0; i < 31; ++i) {
2831 if (virt_dev->eps[i].new_ring) {
2832 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2833 virt_dev->eps[i].new_ring = NULL;
2834 }
2835 }
2836 xhci_zero_in_ctx(xhci, virt_dev);
2837}
2838
2839static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2840 struct xhci_container_ctx *in_ctx,
2841 struct xhci_container_ctx *out_ctx,
2842 struct xhci_input_control_ctx *ctrl_ctx,
2843 u32 add_flags, u32 drop_flags)
2844{
2845 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2846 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2847 xhci_slot_copy(xhci, in_ctx, out_ctx);
2848 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2849
2850 xhci_dbg(xhci, "Input Context:\n");
2851 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2852}
2853
2854static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2855 unsigned int slot_id, unsigned int ep_index,
2856 struct xhci_dequeue_state *deq_state)
2857{
2858 struct xhci_input_control_ctx *ctrl_ctx;
2859 struct xhci_container_ctx *in_ctx;
2860 struct xhci_ep_ctx *ep_ctx;
2861 u32 added_ctxs;
2862 dma_addr_t addr;
2863
2864 in_ctx = xhci->devs[slot_id]->in_ctx;
2865 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2866 if (!ctrl_ctx) {
2867 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2868 __func__);
2869 return;
2870 }
2871
2872 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2873 xhci->devs[slot_id]->out_ctx, ep_index);
2874 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2875 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2876 deq_state->new_deq_ptr);
2877 if (addr == 0) {
2878 xhci_warn(xhci, "WARN Cannot submit config ep after "
2879 "reset ep command\n");
2880 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2881 deq_state->new_deq_seg,
2882 deq_state->new_deq_ptr);
2883 return;
2884 }
2885 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2886
2887 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2888 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2889 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2890 added_ctxs, added_ctxs);
2891}
2892
2893void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2894 unsigned int ep_index, struct xhci_td *td)
2895{
2896 struct xhci_dequeue_state deq_state;
2897 struct xhci_virt_ep *ep;
2898 struct usb_device *udev = td->urb->dev;
2899
2900 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2901 "Cleaning up stalled endpoint ring");
2902 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2903 /* We need to move the HW's dequeue pointer past this TD,
2904 * or it will attempt to resend it on the next doorbell ring.
2905 */
2906 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2907 ep_index, ep->stopped_stream, td, &deq_state);
2908
2909 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2910 return;
2911
2912 /* HW with the reset endpoint quirk will use the saved dequeue state to
2913 * issue a configure endpoint command later.
2914 */
2915 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2916 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2917 "Queueing new dequeue state");
2918 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2919 ep_index, ep->stopped_stream, &deq_state);
2920 } else {
2921 /* Better hope no one uses the input context between now and the
2922 * reset endpoint completion!
2923 * XXX: No idea how this hardware will react when stream rings
2924 * are enabled.
2925 */
2926 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2927 "Setting up input context for "
2928 "configure endpoint command");
2929 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2930 ep_index, &deq_state);
2931 }
2932}
2933
2934/* Called when clearing halted device. The core should have sent the control
2935 * message to clear the device halt condition. The host side of the halt should
2936 * already be cleared with a reset endpoint command issued when the STALL tx
2937 * event was received.
2938 *
2939 * Context: in_interrupt
2940 */
2941
2942void xhci_endpoint_reset(struct usb_hcd *hcd,
2943 struct usb_host_endpoint *ep)
2944{
2945 struct xhci_hcd *xhci;
2946
2947 xhci = hcd_to_xhci(hcd);
2948
2949 /*
2950 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2951 * The Reset Endpoint Command may only be issued to endpoints in the
2952 * Halted state. If software wishes reset the Data Toggle or Sequence
2953 * Number of an endpoint that isn't in the Halted state, then software
2954 * may issue a Configure Endpoint Command with the Drop and Add bits set
2955 * for the target endpoint. that is in the Stopped state.
2956 */
2957
2958 /* For now just print debug to follow the situation */
2959 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
2960 ep->desc.bEndpointAddress);
2961}
2962
2963static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2964 struct usb_device *udev, struct usb_host_endpoint *ep,
2965 unsigned int slot_id)
2966{
2967 int ret;
2968 unsigned int ep_index;
2969 unsigned int ep_state;
2970
2971 if (!ep)
2972 return -EINVAL;
2973 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2974 if (ret <= 0)
2975 return -EINVAL;
2976 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
2977 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2978 " descriptor for ep 0x%x does not support streams\n",
2979 ep->desc.bEndpointAddress);
2980 return -EINVAL;
2981 }
2982
2983 ep_index = xhci_get_endpoint_index(&ep->desc);
2984 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2985 if (ep_state & EP_HAS_STREAMS ||
2986 ep_state & EP_GETTING_STREAMS) {
2987 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2988 "already has streams set up.\n",
2989 ep->desc.bEndpointAddress);
2990 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2991 "dynamic stream context array reallocation.\n");
2992 return -EINVAL;
2993 }
2994 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2995 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2996 "endpoint 0x%x; URBs are pending.\n",
2997 ep->desc.bEndpointAddress);
2998 return -EINVAL;
2999 }
3000 return 0;
3001}
3002
3003static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3004 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3005{
3006 unsigned int max_streams;
3007
3008 /* The stream context array size must be a power of two */
3009 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3010 /*
3011 * Find out how many primary stream array entries the host controller
3012 * supports. Later we may use secondary stream arrays (similar to 2nd
3013 * level page entries), but that's an optional feature for xHCI host
3014 * controllers. xHCs must support at least 4 stream IDs.
3015 */
3016 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3017 if (*num_stream_ctxs > max_streams) {
3018 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3019 max_streams);
3020 *num_stream_ctxs = max_streams;
3021 *num_streams = max_streams;
3022 }
3023}
3024
3025/* Returns an error code if one of the endpoint already has streams.
3026 * This does not change any data structures, it only checks and gathers
3027 * information.
3028 */
3029static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3030 struct usb_device *udev,
3031 struct usb_host_endpoint **eps, unsigned int num_eps,
3032 unsigned int *num_streams, u32 *changed_ep_bitmask)
3033{
3034 unsigned int max_streams;
3035 unsigned int endpoint_flag;
3036 int i;
3037 int ret;
3038
3039 for (i = 0; i < num_eps; i++) {
3040 ret = xhci_check_streams_endpoint(xhci, udev,
3041 eps[i], udev->slot_id);
3042 if (ret < 0)
3043 return ret;
3044
3045 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3046 if (max_streams < (*num_streams - 1)) {
3047 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3048 eps[i]->desc.bEndpointAddress,
3049 max_streams);
3050 *num_streams = max_streams+1;
3051 }
3052
3053 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3054 if (*changed_ep_bitmask & endpoint_flag)
3055 return -EINVAL;
3056 *changed_ep_bitmask |= endpoint_flag;
3057 }
3058 return 0;
3059}
3060
3061static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3062 struct usb_device *udev,
3063 struct usb_host_endpoint **eps, unsigned int num_eps)
3064{
3065 u32 changed_ep_bitmask = 0;
3066 unsigned int slot_id;
3067 unsigned int ep_index;
3068 unsigned int ep_state;
3069 int i;
3070
3071 slot_id = udev->slot_id;
3072 if (!xhci->devs[slot_id])
3073 return 0;
3074
3075 for (i = 0; i < num_eps; i++) {
3076 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3077 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3078 /* Are streams already being freed for the endpoint? */
3079 if (ep_state & EP_GETTING_NO_STREAMS) {
3080 xhci_warn(xhci, "WARN Can't disable streams for "
3081 "endpoint 0x%x, "
3082 "streams are being disabled already\n",
3083 eps[i]->desc.bEndpointAddress);
3084 return 0;
3085 }
3086 /* Are there actually any streams to free? */
3087 if (!(ep_state & EP_HAS_STREAMS) &&
3088 !(ep_state & EP_GETTING_STREAMS)) {
3089 xhci_warn(xhci, "WARN Can't disable streams for "
3090 "endpoint 0x%x, "
3091 "streams are already disabled!\n",
3092 eps[i]->desc.bEndpointAddress);
3093 xhci_warn(xhci, "WARN xhci_free_streams() called "
3094 "with non-streams endpoint\n");
3095 return 0;
3096 }
3097 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3098 }
3099 return changed_ep_bitmask;
3100}
3101
3102/*
3103 * The USB device drivers use this function (through the HCD interface in USB
3104 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3105 * coordinate mass storage command queueing across multiple endpoints (basically
3106 * a stream ID == a task ID).
3107 *
3108 * Setting up streams involves allocating the same size stream context array
3109 * for each endpoint and issuing a configure endpoint command for all endpoints.
3110 *
3111 * Don't allow the call to succeed if one endpoint only supports one stream
3112 * (which means it doesn't support streams at all).
3113 *
3114 * Drivers may get less stream IDs than they asked for, if the host controller
3115 * hardware or endpoints claim they can't support the number of requested
3116 * stream IDs.
3117 */
3118int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3119 struct usb_host_endpoint **eps, unsigned int num_eps,
3120 unsigned int num_streams, gfp_t mem_flags)
3121{
3122 int i, ret;
3123 struct xhci_hcd *xhci;
3124 struct xhci_virt_device *vdev;
3125 struct xhci_command *config_cmd;
3126 struct xhci_input_control_ctx *ctrl_ctx;
3127 unsigned int ep_index;
3128 unsigned int num_stream_ctxs;
3129 unsigned int max_packet;
3130 unsigned long flags;
3131 u32 changed_ep_bitmask = 0;
3132
3133 if (!eps)
3134 return -EINVAL;
3135
3136 /* Add one to the number of streams requested to account for
3137 * stream 0 that is reserved for xHCI usage.
3138 */
3139 num_streams += 1;
3140 xhci = hcd_to_xhci(hcd);
3141 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3142 num_streams);
3143
3144 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3145 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3146 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3147 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3148 return -ENOSYS;
3149 }
3150
3151 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3152 if (!config_cmd) {
3153 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3154 return -ENOMEM;
3155 }
3156 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3157 if (!ctrl_ctx) {
3158 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3159 __func__);
3160 xhci_free_command(xhci, config_cmd);
3161 return -ENOMEM;
3162 }
3163
3164 /* Check to make sure all endpoints are not already configured for
3165 * streams. While we're at it, find the maximum number of streams that
3166 * all the endpoints will support and check for duplicate endpoints.
3167 */
3168 spin_lock_irqsave(&xhci->lock, flags);
3169 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3170 num_eps, &num_streams, &changed_ep_bitmask);
3171 if (ret < 0) {
3172 xhci_free_command(xhci, config_cmd);
3173 spin_unlock_irqrestore(&xhci->lock, flags);
3174 return ret;
3175 }
3176 if (num_streams <= 1) {
3177 xhci_warn(xhci, "WARN: endpoints can't handle "
3178 "more than one stream.\n");
3179 xhci_free_command(xhci, config_cmd);
3180 spin_unlock_irqrestore(&xhci->lock, flags);
3181 return -EINVAL;
3182 }
3183 vdev = xhci->devs[udev->slot_id];
3184 /* Mark each endpoint as being in transition, so
3185 * xhci_urb_enqueue() will reject all URBs.
3186 */
3187 for (i = 0; i < num_eps; i++) {
3188 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3189 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3190 }
3191 spin_unlock_irqrestore(&xhci->lock, flags);
3192
3193 /* Setup internal data structures and allocate HW data structures for
3194 * streams (but don't install the HW structures in the input context
3195 * until we're sure all memory allocation succeeded).
3196 */
3197 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3198 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3199 num_stream_ctxs, num_streams);
3200
3201 for (i = 0; i < num_eps; i++) {
3202 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3203 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3204 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3205 num_stream_ctxs,
3206 num_streams,
3207 max_packet, mem_flags);
3208 if (!vdev->eps[ep_index].stream_info)
3209 goto cleanup;
3210 /* Set maxPstreams in endpoint context and update deq ptr to
3211 * point to stream context array. FIXME
3212 */
3213 }
3214
3215 /* Set up the input context for a configure endpoint command. */
3216 for (i = 0; i < num_eps; i++) {
3217 struct xhci_ep_ctx *ep_ctx;
3218
3219 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3220 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3221
3222 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3223 vdev->out_ctx, ep_index);
3224 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3225 vdev->eps[ep_index].stream_info);
3226 }
3227 /* Tell the HW to drop its old copy of the endpoint context info
3228 * and add the updated copy from the input context.
3229 */
3230 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3231 vdev->out_ctx, ctrl_ctx,
3232 changed_ep_bitmask, changed_ep_bitmask);
3233
3234 /* Issue and wait for the configure endpoint command */
3235 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3236 false, false);
3237
3238 /* xHC rejected the configure endpoint command for some reason, so we
3239 * leave the old ring intact and free our internal streams data
3240 * structure.
3241 */
3242 if (ret < 0)
3243 goto cleanup;
3244
3245 spin_lock_irqsave(&xhci->lock, flags);
3246 for (i = 0; i < num_eps; i++) {
3247 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3248 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3249 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3250 udev->slot_id, ep_index);
3251 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3252 }
3253 xhci_free_command(xhci, config_cmd);
3254 spin_unlock_irqrestore(&xhci->lock, flags);
3255
3256 /* Subtract 1 for stream 0, which drivers can't use */
3257 return num_streams - 1;
3258
3259cleanup:
3260 /* If it didn't work, free the streams! */
3261 for (i = 0; i < num_eps; i++) {
3262 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3263 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3264 vdev->eps[ep_index].stream_info = NULL;
3265 /* FIXME Unset maxPstreams in endpoint context and
3266 * update deq ptr to point to normal string ring.
3267 */
3268 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3269 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3270 xhci_endpoint_zero(xhci, vdev, eps[i]);
3271 }
3272 xhci_free_command(xhci, config_cmd);
3273 return -ENOMEM;
3274}
3275
3276/* Transition the endpoint from using streams to being a "normal" endpoint
3277 * without streams.
3278 *
3279 * Modify the endpoint context state, submit a configure endpoint command,
3280 * and free all endpoint rings for streams if that completes successfully.
3281 */
3282int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3283 struct usb_host_endpoint **eps, unsigned int num_eps,
3284 gfp_t mem_flags)
3285{
3286 int i, ret;
3287 struct xhci_hcd *xhci;
3288 struct xhci_virt_device *vdev;
3289 struct xhci_command *command;
3290 struct xhci_input_control_ctx *ctrl_ctx;
3291 unsigned int ep_index;
3292 unsigned long flags;
3293 u32 changed_ep_bitmask;
3294
3295 xhci = hcd_to_xhci(hcd);
3296 vdev = xhci->devs[udev->slot_id];
3297
3298 /* Set up a configure endpoint command to remove the streams rings */
3299 spin_lock_irqsave(&xhci->lock, flags);
3300 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3301 udev, eps, num_eps);
3302 if (changed_ep_bitmask == 0) {
3303 spin_unlock_irqrestore(&xhci->lock, flags);
3304 return -EINVAL;
3305 }
3306
3307 /* Use the xhci_command structure from the first endpoint. We may have
3308 * allocated too many, but the driver may call xhci_free_streams() for
3309 * each endpoint it grouped into one call to xhci_alloc_streams().
3310 */
3311 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3312 command = vdev->eps[ep_index].stream_info->free_streams_command;
3313 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3314 if (!ctrl_ctx) {
3315 spin_unlock_irqrestore(&xhci->lock, flags);
3316 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3317 __func__);
3318 return -EINVAL;
3319 }
3320
3321 for (i = 0; i < num_eps; i++) {
3322 struct xhci_ep_ctx *ep_ctx;
3323
3324 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3325 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3326 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3327 EP_GETTING_NO_STREAMS;
3328
3329 xhci_endpoint_copy(xhci, command->in_ctx,
3330 vdev->out_ctx, ep_index);
3331 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3332 &vdev->eps[ep_index]);
3333 }
3334 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3335 vdev->out_ctx, ctrl_ctx,
3336 changed_ep_bitmask, changed_ep_bitmask);
3337 spin_unlock_irqrestore(&xhci->lock, flags);
3338
3339 /* Issue and wait for the configure endpoint command,
3340 * which must succeed.
3341 */
3342 ret = xhci_configure_endpoint(xhci, udev, command,
3343 false, true);
3344
3345 /* xHC rejected the configure endpoint command for some reason, so we
3346 * leave the streams rings intact.
3347 */
3348 if (ret < 0)
3349 return ret;
3350
3351 spin_lock_irqsave(&xhci->lock, flags);
3352 for (i = 0; i < num_eps; i++) {
3353 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3354 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3355 vdev->eps[ep_index].stream_info = NULL;
3356 /* FIXME Unset maxPstreams in endpoint context and
3357 * update deq ptr to point to normal string ring.
3358 */
3359 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3360 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3361 }
3362 spin_unlock_irqrestore(&xhci->lock, flags);
3363
3364 return 0;
3365}
3366
3367/*
3368 * Deletes endpoint resources for endpoints that were active before a Reset
3369 * Device command, or a Disable Slot command. The Reset Device command leaves
3370 * the control endpoint intact, whereas the Disable Slot command deletes it.
3371 *
3372 * Must be called with xhci->lock held.
3373 */
3374void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3375 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3376{
3377 int i;
3378 unsigned int num_dropped_eps = 0;
3379 unsigned int drop_flags = 0;
3380
3381 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3382 if (virt_dev->eps[i].ring) {
3383 drop_flags |= 1 << i;
3384 num_dropped_eps++;
3385 }
3386 }
3387 xhci->num_active_eps -= num_dropped_eps;
3388 if (num_dropped_eps)
3389 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3390 "Dropped %u ep ctxs, flags = 0x%x, "
3391 "%u now active.",
3392 num_dropped_eps, drop_flags,
3393 xhci->num_active_eps);
3394}
3395
3396/*
3397 * This submits a Reset Device Command, which will set the device state to 0,
3398 * set the device address to 0, and disable all the endpoints except the default
3399 * control endpoint. The USB core should come back and call
3400 * xhci_address_device(), and then re-set up the configuration. If this is
3401 * called because of a usb_reset_and_verify_device(), then the old alternate
3402 * settings will be re-installed through the normal bandwidth allocation
3403 * functions.
3404 *
3405 * Wait for the Reset Device command to finish. Remove all structures
3406 * associated with the endpoints that were disabled. Clear the input device
3407 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3408 *
3409 * If the virt_dev to be reset does not exist or does not match the udev,
3410 * it means the device is lost, possibly due to the xHC restore error and
3411 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3412 * re-allocate the device.
3413 */
3414int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3415{
3416 int ret, i;
3417 unsigned long flags;
3418 struct xhci_hcd *xhci;
3419 unsigned int slot_id;
3420 struct xhci_virt_device *virt_dev;
3421 struct xhci_command *reset_device_cmd;
3422 int last_freed_endpoint;
3423 struct xhci_slot_ctx *slot_ctx;
3424 int old_active_eps = 0;
3425
3426 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3427 if (ret <= 0)
3428 return ret;
3429 xhci = hcd_to_xhci(hcd);
3430 slot_id = udev->slot_id;
3431 virt_dev = xhci->devs[slot_id];
3432 if (!virt_dev) {
3433 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3434 "not exist. Re-allocate the device\n", slot_id);
3435 ret = xhci_alloc_dev(hcd, udev);
3436 if (ret == 1)
3437 return 0;
3438 else
3439 return -EINVAL;
3440 }
3441
3442 if (virt_dev->tt_info)
3443 old_active_eps = virt_dev->tt_info->active_eps;
3444
3445 if (virt_dev->udev != udev) {
3446 /* If the virt_dev and the udev does not match, this virt_dev
3447 * may belong to another udev.
3448 * Re-allocate the device.
3449 */
3450 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3451 "not match the udev. Re-allocate the device\n",
3452 slot_id);
3453 ret = xhci_alloc_dev(hcd, udev);
3454 if (ret == 1)
3455 return 0;
3456 else
3457 return -EINVAL;
3458 }
3459
3460 /* If device is not setup, there is no point in resetting it */
3461 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3462 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3463 SLOT_STATE_DISABLED)
3464 return 0;
3465
3466 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3467 /* Allocate the command structure that holds the struct completion.
3468 * Assume we're in process context, since the normal device reset
3469 * process has to wait for the device anyway. Storage devices are
3470 * reset as part of error handling, so use GFP_NOIO instead of
3471 * GFP_KERNEL.
3472 */
3473 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3474 if (!reset_device_cmd) {
3475 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3476 return -ENOMEM;
3477 }
3478
3479 /* Attempt to submit the Reset Device command to the command ring */
3480 spin_lock_irqsave(&xhci->lock, flags);
3481
3482 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3483 if (ret) {
3484 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3485 spin_unlock_irqrestore(&xhci->lock, flags);
3486 goto command_cleanup;
3487 }
3488 xhci_ring_cmd_db(xhci);
3489 spin_unlock_irqrestore(&xhci->lock, flags);
3490
3491 /* Wait for the Reset Device command to finish */
3492 wait_for_completion(reset_device_cmd->completion);
3493
3494 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3495 * unless we tried to reset a slot ID that wasn't enabled,
3496 * or the device wasn't in the addressed or configured state.
3497 */
3498 ret = reset_device_cmd->status;
3499 switch (ret) {
3500 case COMP_CMD_ABORT:
3501 case COMP_CMD_STOP:
3502 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3503 ret = -ETIME;
3504 goto command_cleanup;
3505 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3506 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3507 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3508 slot_id,
3509 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3510 xhci_dbg(xhci, "Not freeing device rings.\n");
3511 /* Don't treat this as an error. May change my mind later. */
3512 ret = 0;
3513 goto command_cleanup;
3514 case COMP_SUCCESS:
3515 xhci_dbg(xhci, "Successful reset device command.\n");
3516 break;
3517 default:
3518 if (xhci_is_vendor_info_code(xhci, ret))
3519 break;
3520 xhci_warn(xhci, "Unknown completion code %u for "
3521 "reset device command.\n", ret);
3522 ret = -EINVAL;
3523 goto command_cleanup;
3524 }
3525
3526 /* Free up host controller endpoint resources */
3527 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3528 spin_lock_irqsave(&xhci->lock, flags);
3529 /* Don't delete the default control endpoint resources */
3530 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3531 spin_unlock_irqrestore(&xhci->lock, flags);
3532 }
3533
3534 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3535 last_freed_endpoint = 1;
3536 for (i = 1; i < 31; ++i) {
3537 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3538
3539 if (ep->ep_state & EP_HAS_STREAMS) {
3540 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3541 xhci_get_endpoint_address(i));
3542 xhci_free_stream_info(xhci, ep->stream_info);
3543 ep->stream_info = NULL;
3544 ep->ep_state &= ~EP_HAS_STREAMS;
3545 }
3546
3547 if (ep->ring) {
3548 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3549 last_freed_endpoint = i;
3550 }
3551 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3552 xhci_drop_ep_from_interval_table(xhci,
3553 &virt_dev->eps[i].bw_info,
3554 virt_dev->bw_table,
3555 udev,
3556 &virt_dev->eps[i],
3557 virt_dev->tt_info);
3558 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3559 }
3560 /* If necessary, update the number of active TTs on this root port */
3561 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3562
3563 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3564 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3565 ret = 0;
3566
3567command_cleanup:
3568 xhci_free_command(xhci, reset_device_cmd);
3569 return ret;
3570}
3571
3572/*
3573 * At this point, the struct usb_device is about to go away, the device has
3574 * disconnected, and all traffic has been stopped and the endpoints have been
3575 * disabled. Free any HC data structures associated with that device.
3576 */
3577void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3578{
3579 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3580 struct xhci_virt_device *virt_dev;
3581 unsigned long flags;
3582 u32 state;
3583 int i, ret;
3584 struct xhci_command *command;
3585
3586 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3587 if (!command)
3588 return;
3589
3590#ifndef CONFIG_USB_DEFAULT_PERSIST
3591 /*
3592 * We called pm_runtime_get_noresume when the device was attached.
3593 * Decrement the counter here to allow controller to runtime suspend
3594 * if no devices remain.
3595 */
3596 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3597 pm_runtime_put_noidle(hcd->self.controller);
3598#endif
3599
3600 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3601 /* If the host is halted due to driver unload, we still need to free the
3602 * device.
3603 */
3604 if (ret <= 0 && ret != -ENODEV) {
3605 kfree(command);
3606 return;
3607 }
3608
3609 virt_dev = xhci->devs[udev->slot_id];
3610
3611 /* Stop any wayward timer functions (which may grab the lock) */
3612 for (i = 0; i < 31; ++i) {
3613 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3614 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3615 }
3616
3617 spin_lock_irqsave(&xhci->lock, flags);
3618 /* Don't disable the slot if the host controller is dead. */
3619 state = readl(&xhci->op_regs->status);
3620 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3621 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3622 xhci_free_virt_device(xhci, udev->slot_id);
3623 spin_unlock_irqrestore(&xhci->lock, flags);
3624 kfree(command);
3625 return;
3626 }
3627
3628 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3629 udev->slot_id)) {
3630 spin_unlock_irqrestore(&xhci->lock, flags);
3631 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3632 return;
3633 }
3634 xhci_ring_cmd_db(xhci);
3635 spin_unlock_irqrestore(&xhci->lock, flags);
3636
3637 /*
3638 * Event command completion handler will free any data structures
3639 * associated with the slot. XXX Can free sleep?
3640 */
3641}
3642
3643/*
3644 * Checks if we have enough host controller resources for the default control
3645 * endpoint.
3646 *
3647 * Must be called with xhci->lock held.
3648 */
3649static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3650{
3651 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3652 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3653 "Not enough ep ctxs: "
3654 "%u active, need to add 1, limit is %u.",
3655 xhci->num_active_eps, xhci->limit_active_eps);
3656 return -ENOMEM;
3657 }
3658 xhci->num_active_eps += 1;
3659 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3660 "Adding 1 ep ctx, %u now active.",
3661 xhci->num_active_eps);
3662 return 0;
3663}
3664
3665
3666/*
3667 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3668 * timed out, or allocating memory failed. Returns 1 on success.
3669 */
3670int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3671{
3672 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3673 unsigned long flags;
3674 int ret, slot_id;
3675 struct xhci_command *command;
3676
3677 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3678 if (!command)
3679 return 0;
3680
3681 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3682 mutex_lock(&xhci->mutex);
3683 spin_lock_irqsave(&xhci->lock, flags);
3684 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3685 if (ret) {
3686 spin_unlock_irqrestore(&xhci->lock, flags);
3687 mutex_unlock(&xhci->mutex);
3688 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3689 xhci_free_command(xhci, command);
3690 return 0;
3691 }
3692 xhci_ring_cmd_db(xhci);
3693 spin_unlock_irqrestore(&xhci->lock, flags);
3694
3695 wait_for_completion(command->completion);
3696 slot_id = command->slot_id;
3697 mutex_unlock(&xhci->mutex);
3698
3699 if (!slot_id || command->status != COMP_SUCCESS) {
3700 xhci_err(xhci, "Error while assigning device slot ID\n");
3701 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3702 HCS_MAX_SLOTS(
3703 readl(&xhci->cap_regs->hcs_params1)));
3704 xhci_free_command(xhci, command);
3705 return 0;
3706 }
3707
3708 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3709 spin_lock_irqsave(&xhci->lock, flags);
3710 ret = xhci_reserve_host_control_ep_resources(xhci);
3711 if (ret) {
3712 spin_unlock_irqrestore(&xhci->lock, flags);
3713 xhci_warn(xhci, "Not enough host resources, "
3714 "active endpoint contexts = %u\n",
3715 xhci->num_active_eps);
3716 goto disable_slot;
3717 }
3718 spin_unlock_irqrestore(&xhci->lock, flags);
3719 }
3720 /* Use GFP_NOIO, since this function can be called from
3721 * xhci_discover_or_reset_device(), which may be called as part of
3722 * mass storage driver error handling.
3723 */
3724 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3725 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3726 goto disable_slot;
3727 }
3728 udev->slot_id = slot_id;
3729
3730#ifndef CONFIG_USB_DEFAULT_PERSIST
3731 /*
3732 * If resetting upon resume, we can't put the controller into runtime
3733 * suspend if there is a device attached.
3734 */
3735 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3736 pm_runtime_get_noresume(hcd->self.controller);
3737#endif
3738
3739
3740 xhci_free_command(xhci, command);
3741 /* Is this a LS or FS device under a HS hub? */
3742 /* Hub or peripherial? */
3743 return 1;
3744
3745disable_slot:
3746 /* Disable slot, if we can do it without mem alloc */
3747 spin_lock_irqsave(&xhci->lock, flags);
3748 kfree(command->completion);
3749 command->completion = NULL;
3750 command->status = 0;
3751 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3752 udev->slot_id))
3753 xhci_ring_cmd_db(xhci);
3754 spin_unlock_irqrestore(&xhci->lock, flags);
3755 return 0;
3756}
3757
3758/*
3759 * Issue an Address Device command and optionally send a corresponding
3760 * SetAddress request to the device.
3761 */
3762static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3763 enum xhci_setup_dev setup)
3764{
3765 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3766 unsigned long flags;
3767 struct xhci_virt_device *virt_dev;
3768 int ret = 0;
3769 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3770 struct xhci_slot_ctx *slot_ctx;
3771 struct xhci_input_control_ctx *ctrl_ctx;
3772 u64 temp_64;
3773 struct xhci_command *command = NULL;
3774
3775 mutex_lock(&xhci->mutex);
3776
3777 if (xhci->xhc_state) { /* dying, removing or halted */
3778 ret = -ESHUTDOWN;
3779 goto out;
3780 }
3781
3782 if (!udev->slot_id) {
3783 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3784 "Bad Slot ID %d", udev->slot_id);
3785 ret = -EINVAL;
3786 goto out;
3787 }
3788
3789 virt_dev = xhci->devs[udev->slot_id];
3790
3791 if (WARN_ON(!virt_dev)) {
3792 /*
3793 * In plug/unplug torture test with an NEC controller,
3794 * a zero-dereference was observed once due to virt_dev = 0.
3795 * Print useful debug rather than crash if it is observed again!
3796 */
3797 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3798 udev->slot_id);
3799 ret = -EINVAL;
3800 goto out;
3801 }
3802
3803 if (setup == SETUP_CONTEXT_ONLY) {
3804 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3805 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3806 SLOT_STATE_DEFAULT) {
3807 xhci_dbg(xhci, "Slot already in default state\n");
3808 goto out;
3809 }
3810 }
3811
3812 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3813 if (!command) {
3814 ret = -ENOMEM;
3815 goto out;
3816 }
3817
3818 command->in_ctx = virt_dev->in_ctx;
3819
3820 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3821 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3822 if (!ctrl_ctx) {
3823 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3824 __func__);
3825 ret = -EINVAL;
3826 goto out;
3827 }
3828 /*
3829 * If this is the first Set Address since device plug-in or
3830 * virt_device realloaction after a resume with an xHCI power loss,
3831 * then set up the slot context.
3832 */
3833 if (!slot_ctx->dev_info)
3834 xhci_setup_addressable_virt_dev(xhci, udev);
3835 /* Otherwise, update the control endpoint ring enqueue pointer. */
3836 else
3837 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3838 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3839 ctrl_ctx->drop_flags = 0;
3840
3841 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3842 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3843 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3844 le32_to_cpu(slot_ctx->dev_info) >> 27);
3845
3846 spin_lock_irqsave(&xhci->lock, flags);
3847 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3848 udev->slot_id, setup);
3849 if (ret) {
3850 spin_unlock_irqrestore(&xhci->lock, flags);
3851 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3852 "FIXME: allocate a command ring segment");
3853 goto out;
3854 }
3855 xhci_ring_cmd_db(xhci);
3856 spin_unlock_irqrestore(&xhci->lock, flags);
3857
3858 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3859 wait_for_completion(command->completion);
3860
3861 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3862 * the SetAddress() "recovery interval" required by USB and aborting the
3863 * command on a timeout.
3864 */
3865 switch (command->status) {
3866 case COMP_CMD_ABORT:
3867 case COMP_CMD_STOP:
3868 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3869 ret = -ETIME;
3870 break;
3871 case COMP_CTX_STATE:
3872 case COMP_EBADSLT:
3873 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3874 act, udev->slot_id);
3875 ret = -EINVAL;
3876 break;
3877 case COMP_TX_ERR:
3878 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3879 ret = -EPROTO;
3880 break;
3881 case COMP_DEV_ERR:
3882 dev_warn(&udev->dev,
3883 "ERROR: Incompatible device for setup %s command\n", act);
3884 ret = -ENODEV;
3885 break;
3886 case COMP_SUCCESS:
3887 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3888 "Successful setup %s command", act);
3889 break;
3890 default:
3891 xhci_err(xhci,
3892 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3893 act, command->status);
3894 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3895 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3896 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3897 ret = -EINVAL;
3898 break;
3899 }
3900 if (ret)
3901 goto out;
3902 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3903 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3904 "Op regs DCBAA ptr = %#016llx", temp_64);
3905 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3906 "Slot ID %d dcbaa entry @%p = %#016llx",
3907 udev->slot_id,
3908 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3909 (unsigned long long)
3910 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3911 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3912 "Output Context DMA address = %#08llx",
3913 (unsigned long long)virt_dev->out_ctx->dma);
3914 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3915 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3916 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3917 le32_to_cpu(slot_ctx->dev_info) >> 27);
3918 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3919 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3920 /*
3921 * USB core uses address 1 for the roothubs, so we add one to the
3922 * address given back to us by the HC.
3923 */
3924 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3925 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3926 le32_to_cpu(slot_ctx->dev_info) >> 27);
3927 /* Zero the input context control for later use */
3928 ctrl_ctx->add_flags = 0;
3929 ctrl_ctx->drop_flags = 0;
3930
3931 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3932 "Internal device address = %d",
3933 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3934out:
3935 mutex_unlock(&xhci->mutex);
3936 if (command) {
3937 kfree(command->completion);
3938 kfree(command);
3939 }
3940 return ret;
3941}
3942
3943int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3944{
3945 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3946}
3947
3948int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3949{
3950 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3951}
3952
3953/*
3954 * Transfer the port index into real index in the HW port status
3955 * registers. Caculate offset between the port's PORTSC register
3956 * and port status base. Divide the number of per port register
3957 * to get the real index. The raw port number bases 1.
3958 */
3959int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3960{
3961 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3962 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3963 __le32 __iomem *addr;
3964 int raw_port;
3965
3966 if (hcd->speed < HCD_USB3)
3967 addr = xhci->usb2_ports[port1 - 1];
3968 else
3969 addr = xhci->usb3_ports[port1 - 1];
3970
3971 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
3972 return raw_port;
3973}
3974
3975/*
3976 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3977 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3978 */
3979static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
3980 struct usb_device *udev, u16 max_exit_latency)
3981{
3982 struct xhci_virt_device *virt_dev;
3983 struct xhci_command *command;
3984 struct xhci_input_control_ctx *ctrl_ctx;
3985 struct xhci_slot_ctx *slot_ctx;
3986 unsigned long flags;
3987 int ret;
3988
3989 spin_lock_irqsave(&xhci->lock, flags);
3990
3991 virt_dev = xhci->devs[udev->slot_id];
3992
3993 /*
3994 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
3995 * xHC was re-initialized. Exit latency will be set later after
3996 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
3997 */
3998
3999 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4000 spin_unlock_irqrestore(&xhci->lock, flags);
4001 return 0;
4002 }
4003
4004 /* Attempt to issue an Evaluate Context command to change the MEL. */
4005 command = xhci->lpm_command;
4006 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4007 if (!ctrl_ctx) {
4008 spin_unlock_irqrestore(&xhci->lock, flags);
4009 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4010 __func__);
4011 return -ENOMEM;
4012 }
4013
4014 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4015 spin_unlock_irqrestore(&xhci->lock, flags);
4016
4017 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4018 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4019 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4020 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4021 slot_ctx->dev_state = 0;
4022
4023 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4024 "Set up evaluate context for LPM MEL change.");
4025 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4026 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4027
4028 /* Issue and wait for the evaluate context command. */
4029 ret = xhci_configure_endpoint(xhci, udev, command,
4030 true, true);
4031 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4032 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4033
4034 if (!ret) {
4035 spin_lock_irqsave(&xhci->lock, flags);
4036 virt_dev->current_mel = max_exit_latency;
4037 spin_unlock_irqrestore(&xhci->lock, flags);
4038 }
4039 return ret;
4040}
4041
4042#ifdef CONFIG_PM
4043
4044/* BESL to HIRD Encoding array for USB2 LPM */
4045static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4046 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4047
4048/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4049static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4050 struct usb_device *udev)
4051{
4052 int u2del, besl, besl_host;
4053 int besl_device = 0;
4054 u32 field;
4055
4056 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4057 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4058
4059 if (field & USB_BESL_SUPPORT) {
4060 for (besl_host = 0; besl_host < 16; besl_host++) {
4061 if (xhci_besl_encoding[besl_host] >= u2del)
4062 break;
4063 }
4064 /* Use baseline BESL value as default */
4065 if (field & USB_BESL_BASELINE_VALID)
4066 besl_device = USB_GET_BESL_BASELINE(field);
4067 else if (field & USB_BESL_DEEP_VALID)
4068 besl_device = USB_GET_BESL_DEEP(field);
4069 } else {
4070 if (u2del <= 50)
4071 besl_host = 0;
4072 else
4073 besl_host = (u2del - 51) / 75 + 1;
4074 }
4075
4076 besl = besl_host + besl_device;
4077 if (besl > 15)
4078 besl = 15;
4079
4080 return besl;
4081}
4082
4083/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4084static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4085{
4086 u32 field;
4087 int l1;
4088 int besld = 0;
4089 int hirdm = 0;
4090
4091 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4092
4093 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4094 l1 = udev->l1_params.timeout / 256;
4095
4096 /* device has preferred BESLD */
4097 if (field & USB_BESL_DEEP_VALID) {
4098 besld = USB_GET_BESL_DEEP(field);
4099 hirdm = 1;
4100 }
4101
4102 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4103}
4104
4105int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4106 struct usb_device *udev, int enable)
4107{
4108 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4109 __le32 __iomem **port_array;
4110 __le32 __iomem *pm_addr, *hlpm_addr;
4111 u32 pm_val, hlpm_val, field;
4112 unsigned int port_num;
4113 unsigned long flags;
4114 int hird, exit_latency;
4115 int ret;
4116
4117 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4118 !udev->lpm_capable)
4119 return -EPERM;
4120
4121 if (!udev->parent || udev->parent->parent ||
4122 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4123 return -EPERM;
4124
4125 if (udev->usb2_hw_lpm_capable != 1)
4126 return -EPERM;
4127
4128 spin_lock_irqsave(&xhci->lock, flags);
4129
4130 port_array = xhci->usb2_ports;
4131 port_num = udev->portnum - 1;
4132 pm_addr = port_array[port_num] + PORTPMSC;
4133 pm_val = readl(pm_addr);
4134 hlpm_addr = port_array[port_num] + PORTHLPMC;
4135 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4136
4137 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4138 enable ? "enable" : "disable", port_num + 1);
4139
4140 if (enable) {
4141 /* Host supports BESL timeout instead of HIRD */
4142 if (udev->usb2_hw_lpm_besl_capable) {
4143 /* if device doesn't have a preferred BESL value use a
4144 * default one which works with mixed HIRD and BESL
4145 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4146 */
4147 if ((field & USB_BESL_SUPPORT) &&
4148 (field & USB_BESL_BASELINE_VALID))
4149 hird = USB_GET_BESL_BASELINE(field);
4150 else
4151 hird = udev->l1_params.besl;
4152
4153 exit_latency = xhci_besl_encoding[hird];
4154 spin_unlock_irqrestore(&xhci->lock, flags);
4155
4156 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4157 * input context for link powermanagement evaluate
4158 * context commands. It is protected by hcd->bandwidth
4159 * mutex and is shared by all devices. We need to set
4160 * the max ext latency in USB 2 BESL LPM as well, so
4161 * use the same mutex and xhci_change_max_exit_latency()
4162 */
4163 mutex_lock(hcd->bandwidth_mutex);
4164 ret = xhci_change_max_exit_latency(xhci, udev,
4165 exit_latency);
4166 mutex_unlock(hcd->bandwidth_mutex);
4167
4168 if (ret < 0)
4169 return ret;
4170 spin_lock_irqsave(&xhci->lock, flags);
4171
4172 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4173 writel(hlpm_val, hlpm_addr);
4174 /* flush write */
4175 readl(hlpm_addr);
4176 } else {
4177 hird = xhci_calculate_hird_besl(xhci, udev);
4178 }
4179
4180 pm_val &= ~PORT_HIRD_MASK;
4181 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4182 writel(pm_val, pm_addr);
4183 pm_val = readl(pm_addr);
4184 pm_val |= PORT_HLE;
4185 writel(pm_val, pm_addr);
4186 /* flush write */
4187 readl(pm_addr);
4188 } else {
4189 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4190 writel(pm_val, pm_addr);
4191 /* flush write */
4192 readl(pm_addr);
4193 if (udev->usb2_hw_lpm_besl_capable) {
4194 spin_unlock_irqrestore(&xhci->lock, flags);
4195 mutex_lock(hcd->bandwidth_mutex);
4196 xhci_change_max_exit_latency(xhci, udev, 0);
4197 mutex_unlock(hcd->bandwidth_mutex);
4198 return 0;
4199 }
4200 }
4201
4202 spin_unlock_irqrestore(&xhci->lock, flags);
4203 return 0;
4204}
4205
4206/* check if a usb2 port supports a given extened capability protocol
4207 * only USB2 ports extended protocol capability values are cached.
4208 * Return 1 if capability is supported
4209 */
4210static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4211 unsigned capability)
4212{
4213 u32 port_offset, port_count;
4214 int i;
4215
4216 for (i = 0; i < xhci->num_ext_caps; i++) {
4217 if (xhci->ext_caps[i] & capability) {
4218 /* port offsets starts at 1 */
4219 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4220 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4221 if (port >= port_offset &&
4222 port < port_offset + port_count)
4223 return 1;
4224 }
4225 }
4226 return 0;
4227}
4228
4229int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4230{
4231 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4232 int portnum = udev->portnum - 1;
4233
4234 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4235 !udev->lpm_capable)
4236 return 0;
4237
4238 /* we only support lpm for non-hub device connected to root hub yet */
4239 if (!udev->parent || udev->parent->parent ||
4240 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4241 return 0;
4242
4243 if (xhci->hw_lpm_support == 1 &&
4244 xhci_check_usb2_port_capability(
4245 xhci, portnum, XHCI_HLC)) {
4246 udev->usb2_hw_lpm_capable = 1;
4247 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4248 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4249 if (xhci_check_usb2_port_capability(xhci, portnum,
4250 XHCI_BLC))
4251 udev->usb2_hw_lpm_besl_capable = 1;
4252 }
4253
4254 return 0;
4255}
4256
4257/*---------------------- USB 3.0 Link PM functions ------------------------*/
4258
4259/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4260static unsigned long long xhci_service_interval_to_ns(
4261 struct usb_endpoint_descriptor *desc)
4262{
4263 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4264}
4265
4266static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4267 enum usb3_link_state state)
4268{
4269 unsigned long long sel;
4270 unsigned long long pel;
4271 unsigned int max_sel_pel;
4272 char *state_name;
4273
4274 switch (state) {
4275 case USB3_LPM_U1:
4276 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4277 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4278 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4279 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4280 state_name = "U1";
4281 break;
4282 case USB3_LPM_U2:
4283 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4284 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4285 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4286 state_name = "U2";
4287 break;
4288 default:
4289 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4290 __func__);
4291 return USB3_LPM_DISABLED;
4292 }
4293
4294 if (sel <= max_sel_pel && pel <= max_sel_pel)
4295 return USB3_LPM_DEVICE_INITIATED;
4296
4297 if (sel > max_sel_pel)
4298 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4299 "due to long SEL %llu ms\n",
4300 state_name, sel);
4301 else
4302 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4303 "due to long PEL %llu ms\n",
4304 state_name, pel);
4305 return USB3_LPM_DISABLED;
4306}
4307
4308/* The U1 timeout should be the maximum of the following values:
4309 * - For control endpoints, U1 system exit latency (SEL) * 3
4310 * - For bulk endpoints, U1 SEL * 5
4311 * - For interrupt endpoints:
4312 * - Notification EPs, U1 SEL * 3
4313 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4314 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4315 */
4316static unsigned long long xhci_calculate_intel_u1_timeout(
4317 struct usb_device *udev,
4318 struct usb_endpoint_descriptor *desc)
4319{
4320 unsigned long long timeout_ns;
4321 int ep_type;
4322 int intr_type;
4323
4324 ep_type = usb_endpoint_type(desc);
4325 switch (ep_type) {
4326 case USB_ENDPOINT_XFER_CONTROL:
4327 timeout_ns = udev->u1_params.sel * 3;
4328 break;
4329 case USB_ENDPOINT_XFER_BULK:
4330 timeout_ns = udev->u1_params.sel * 5;
4331 break;
4332 case USB_ENDPOINT_XFER_INT:
4333 intr_type = usb_endpoint_interrupt_type(desc);
4334 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4335 timeout_ns = udev->u1_params.sel * 3;
4336 break;
4337 }
4338 /* Otherwise the calculation is the same as isoc eps */
4339 case USB_ENDPOINT_XFER_ISOC:
4340 timeout_ns = xhci_service_interval_to_ns(desc);
4341 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4342 if (timeout_ns < udev->u1_params.sel * 2)
4343 timeout_ns = udev->u1_params.sel * 2;
4344 break;
4345 default:
4346 return 0;
4347 }
4348
4349 return timeout_ns;
4350}
4351
4352/* Returns the hub-encoded U1 timeout value. */
4353static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4354 struct usb_device *udev,
4355 struct usb_endpoint_descriptor *desc)
4356{
4357 unsigned long long timeout_ns;
4358
4359 if (xhci->quirks & XHCI_INTEL_HOST)
4360 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4361 else
4362 timeout_ns = udev->u1_params.sel;
4363
4364 /* The U1 timeout is encoded in 1us intervals.
4365 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4366 */
4367 if (timeout_ns == USB3_LPM_DISABLED)
4368 timeout_ns = 1;
4369 else
4370 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4371
4372 /* If the necessary timeout value is bigger than what we can set in the
4373 * USB 3.0 hub, we have to disable hub-initiated U1.
4374 */
4375 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4376 return timeout_ns;
4377 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4378 "due to long timeout %llu ms\n", timeout_ns);
4379 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4380}
4381
4382/* The U2 timeout should be the maximum of:
4383 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4384 * - largest bInterval of any active periodic endpoint (to avoid going
4385 * into lower power link states between intervals).
4386 * - the U2 Exit Latency of the device
4387 */
4388static unsigned long long xhci_calculate_intel_u2_timeout(
4389 struct usb_device *udev,
4390 struct usb_endpoint_descriptor *desc)
4391{
4392 unsigned long long timeout_ns;
4393 unsigned long long u2_del_ns;
4394
4395 timeout_ns = 10 * 1000 * 1000;
4396
4397 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4398 (xhci_service_interval_to_ns(desc) > timeout_ns))
4399 timeout_ns = xhci_service_interval_to_ns(desc);
4400
4401 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4402 if (u2_del_ns > timeout_ns)
4403 timeout_ns = u2_del_ns;
4404
4405 return timeout_ns;
4406}
4407
4408/* Returns the hub-encoded U2 timeout value. */
4409static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4410 struct usb_device *udev,
4411 struct usb_endpoint_descriptor *desc)
4412{
4413 unsigned long long timeout_ns;
4414
4415 if (xhci->quirks & XHCI_INTEL_HOST)
4416 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4417 else
4418 timeout_ns = udev->u2_params.sel;
4419
4420 /* The U2 timeout is encoded in 256us intervals */
4421 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4422 /* If the necessary timeout value is bigger than what we can set in the
4423 * USB 3.0 hub, we have to disable hub-initiated U2.
4424 */
4425 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4426 return timeout_ns;
4427 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4428 "due to long timeout %llu ms\n", timeout_ns);
4429 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4430}
4431
4432static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4433 struct usb_device *udev,
4434 struct usb_endpoint_descriptor *desc,
4435 enum usb3_link_state state,
4436 u16 *timeout)
4437{
4438 if (state == USB3_LPM_U1)
4439 return xhci_calculate_u1_timeout(xhci, udev, desc);
4440 else if (state == USB3_LPM_U2)
4441 return xhci_calculate_u2_timeout(xhci, udev, desc);
4442
4443 return USB3_LPM_DISABLED;
4444}
4445
4446static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4447 struct usb_device *udev,
4448 struct usb_endpoint_descriptor *desc,
4449 enum usb3_link_state state,
4450 u16 *timeout)
4451{
4452 u16 alt_timeout;
4453
4454 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4455 desc, state, timeout);
4456
4457 /* If we found we can't enable hub-initiated LPM, or
4458 * the U1 or U2 exit latency was too high to allow
4459 * device-initiated LPM as well, just stop searching.
4460 */
4461 if (alt_timeout == USB3_LPM_DISABLED ||
4462 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4463 *timeout = alt_timeout;
4464 return -E2BIG;
4465 }
4466 if (alt_timeout > *timeout)
4467 *timeout = alt_timeout;
4468 return 0;
4469}
4470
4471static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4472 struct usb_device *udev,
4473 struct usb_host_interface *alt,
4474 enum usb3_link_state state,
4475 u16 *timeout)
4476{
4477 int j;
4478
4479 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4480 if (xhci_update_timeout_for_endpoint(xhci, udev,
4481 &alt->endpoint[j].desc, state, timeout))
4482 return -E2BIG;
4483 continue;
4484 }
4485 return 0;
4486}
4487
4488static int xhci_check_intel_tier_policy(struct usb_device *udev,
4489 enum usb3_link_state state)
4490{
4491 struct usb_device *parent;
4492 unsigned int num_hubs;
4493
4494 if (state == USB3_LPM_U2)
4495 return 0;
4496
4497 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4498 for (parent = udev->parent, num_hubs = 0; parent->parent;
4499 parent = parent->parent)
4500 num_hubs++;
4501
4502 if (num_hubs < 2)
4503 return 0;
4504
4505 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4506 " below second-tier hub.\n");
4507 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4508 "to decrease power consumption.\n");
4509 return -E2BIG;
4510}
4511
4512static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4513 struct usb_device *udev,
4514 enum usb3_link_state state)
4515{
4516 if (xhci->quirks & XHCI_INTEL_HOST)
4517 return xhci_check_intel_tier_policy(udev, state);
4518 else
4519 return 0;
4520}
4521
4522/* Returns the U1 or U2 timeout that should be enabled.
4523 * If the tier check or timeout setting functions return with a non-zero exit
4524 * code, that means the timeout value has been finalized and we shouldn't look
4525 * at any more endpoints.
4526 */
4527static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4528 struct usb_device *udev, enum usb3_link_state state)
4529{
4530 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4531 struct usb_host_config *config;
4532 char *state_name;
4533 int i;
4534 u16 timeout = USB3_LPM_DISABLED;
4535
4536 if (state == USB3_LPM_U1)
4537 state_name = "U1";
4538 else if (state == USB3_LPM_U2)
4539 state_name = "U2";
4540 else {
4541 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4542 state);
4543 return timeout;
4544 }
4545
4546 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4547 return timeout;
4548
4549 /* Gather some information about the currently installed configuration
4550 * and alternate interface settings.
4551 */
4552 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4553 state, &timeout))
4554 return timeout;
4555
4556 config = udev->actconfig;
4557 if (!config)
4558 return timeout;
4559
4560 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4561 struct usb_driver *driver;
4562 struct usb_interface *intf = config->interface[i];
4563
4564 if (!intf)
4565 continue;
4566
4567 /* Check if any currently bound drivers want hub-initiated LPM
4568 * disabled.
4569 */
4570 if (intf->dev.driver) {
4571 driver = to_usb_driver(intf->dev.driver);
4572 if (driver && driver->disable_hub_initiated_lpm) {
4573 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4574 "at request of driver %s\n",
4575 state_name, driver->name);
4576 return xhci_get_timeout_no_hub_lpm(udev, state);
4577 }
4578 }
4579
4580 /* Not sure how this could happen... */
4581 if (!intf->cur_altsetting)
4582 continue;
4583
4584 if (xhci_update_timeout_for_interface(xhci, udev,
4585 intf->cur_altsetting,
4586 state, &timeout))
4587 return timeout;
4588 }
4589 return timeout;
4590}
4591
4592static int calculate_max_exit_latency(struct usb_device *udev,
4593 enum usb3_link_state state_changed,
4594 u16 hub_encoded_timeout)
4595{
4596 unsigned long long u1_mel_us = 0;
4597 unsigned long long u2_mel_us = 0;
4598 unsigned long long mel_us = 0;
4599 bool disabling_u1;
4600 bool disabling_u2;
4601 bool enabling_u1;
4602 bool enabling_u2;
4603
4604 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4605 hub_encoded_timeout == USB3_LPM_DISABLED);
4606 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4607 hub_encoded_timeout == USB3_LPM_DISABLED);
4608
4609 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4610 hub_encoded_timeout != USB3_LPM_DISABLED);
4611 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4612 hub_encoded_timeout != USB3_LPM_DISABLED);
4613
4614 /* If U1 was already enabled and we're not disabling it,
4615 * or we're going to enable U1, account for the U1 max exit latency.
4616 */
4617 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4618 enabling_u1)
4619 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4620 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4621 enabling_u2)
4622 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4623
4624 if (u1_mel_us > u2_mel_us)
4625 mel_us = u1_mel_us;
4626 else
4627 mel_us = u2_mel_us;
4628 /* xHCI host controller max exit latency field is only 16 bits wide. */
4629 if (mel_us > MAX_EXIT) {
4630 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4631 "is too big.\n", mel_us);
4632 return -E2BIG;
4633 }
4634 return mel_us;
4635}
4636
4637/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4638int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4639 struct usb_device *udev, enum usb3_link_state state)
4640{
4641 struct xhci_hcd *xhci;
4642 u16 hub_encoded_timeout;
4643 int mel;
4644 int ret;
4645
4646 xhci = hcd_to_xhci(hcd);
4647 /* The LPM timeout values are pretty host-controller specific, so don't
4648 * enable hub-initiated timeouts unless the vendor has provided
4649 * information about their timeout algorithm.
4650 */
4651 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4652 !xhci->devs[udev->slot_id])
4653 return USB3_LPM_DISABLED;
4654
4655 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4656 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4657 if (mel < 0) {
4658 /* Max Exit Latency is too big, disable LPM. */
4659 hub_encoded_timeout = USB3_LPM_DISABLED;
4660 mel = 0;
4661 }
4662
4663 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4664 if (ret)
4665 return ret;
4666 return hub_encoded_timeout;
4667}
4668
4669int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4670 struct usb_device *udev, enum usb3_link_state state)
4671{
4672 struct xhci_hcd *xhci;
4673 u16 mel;
4674
4675 xhci = hcd_to_xhci(hcd);
4676 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4677 !xhci->devs[udev->slot_id])
4678 return 0;
4679
4680 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4681 return xhci_change_max_exit_latency(xhci, udev, mel);
4682}
4683#else /* CONFIG_PM */
4684
4685int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4686 struct usb_device *udev, int enable)
4687{
4688 return 0;
4689}
4690
4691int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4692{
4693 return 0;
4694}
4695
4696int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4697 struct usb_device *udev, enum usb3_link_state state)
4698{
4699 return USB3_LPM_DISABLED;
4700}
4701
4702int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4703 struct usb_device *udev, enum usb3_link_state state)
4704{
4705 return 0;
4706}
4707#endif /* CONFIG_PM */
4708
4709/*-------------------------------------------------------------------------*/
4710
4711/* Once a hub descriptor is fetched for a device, we need to update the xHC's
4712 * internal data structures for the device.
4713 */
4714int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4715 struct usb_tt *tt, gfp_t mem_flags)
4716{
4717 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4718 struct xhci_virt_device *vdev;
4719 struct xhci_command *config_cmd;
4720 struct xhci_input_control_ctx *ctrl_ctx;
4721 struct xhci_slot_ctx *slot_ctx;
4722 unsigned long flags;
4723 unsigned think_time;
4724 int ret;
4725
4726 /* Ignore root hubs */
4727 if (!hdev->parent)
4728 return 0;
4729
4730 vdev = xhci->devs[hdev->slot_id];
4731 if (!vdev) {
4732 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4733 return -EINVAL;
4734 }
4735 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4736 if (!config_cmd) {
4737 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4738 return -ENOMEM;
4739 }
4740 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4741 if (!ctrl_ctx) {
4742 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4743 __func__);
4744 xhci_free_command(xhci, config_cmd);
4745 return -ENOMEM;
4746 }
4747
4748 spin_lock_irqsave(&xhci->lock, flags);
4749 if (hdev->speed == USB_SPEED_HIGH &&
4750 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4751 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4752 xhci_free_command(xhci, config_cmd);
4753 spin_unlock_irqrestore(&xhci->lock, flags);
4754 return -ENOMEM;
4755 }
4756
4757 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4758 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4759 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4760 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4761 /*
4762 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4763 * but it may be already set to 1 when setup an xHCI virtual
4764 * device, so clear it anyway.
4765 */
4766 if (tt->multi)
4767 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4768 else if (hdev->speed == USB_SPEED_FULL)
4769 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4770
4771 if (xhci->hci_version > 0x95) {
4772 xhci_dbg(xhci, "xHCI version %x needs hub "
4773 "TT think time and number of ports\n",
4774 (unsigned int) xhci->hci_version);
4775 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4776 /* Set TT think time - convert from ns to FS bit times.
4777 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4778 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4779 *
4780 * xHCI 1.0: this field shall be 0 if the device is not a
4781 * High-spped hub.
4782 */
4783 think_time = tt->think_time;
4784 if (think_time != 0)
4785 think_time = (think_time / 666) - 1;
4786 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4787 slot_ctx->tt_info |=
4788 cpu_to_le32(TT_THINK_TIME(think_time));
4789 } else {
4790 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4791 "TT think time or number of ports\n",
4792 (unsigned int) xhci->hci_version);
4793 }
4794 slot_ctx->dev_state = 0;
4795 spin_unlock_irqrestore(&xhci->lock, flags);
4796
4797 xhci_dbg(xhci, "Set up %s for hub device.\n",
4798 (xhci->hci_version > 0x95) ?
4799 "configure endpoint" : "evaluate context");
4800 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4801 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4802
4803 /* Issue and wait for the configure endpoint or
4804 * evaluate context command.
4805 */
4806 if (xhci->hci_version > 0x95)
4807 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4808 false, false);
4809 else
4810 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4811 true, false);
4812
4813 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4814 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4815
4816 xhci_free_command(xhci, config_cmd);
4817 return ret;
4818}
4819
4820int xhci_get_frame(struct usb_hcd *hcd)
4821{
4822 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4823 /* EHCI mods by the periodic size. Why? */
4824 return readl(&xhci->run_regs->microframe_index) >> 3;
4825}
4826
4827int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4828{
4829 struct xhci_hcd *xhci;
4830 struct device *dev = hcd->self.controller;
4831 int retval;
4832
4833 /* Accept arbitrarily long scatter-gather lists */
4834 hcd->self.sg_tablesize = ~0;
4835
4836 /* support to build packet from discontinuous buffers */
4837 hcd->self.no_sg_constraint = 1;
4838
4839 /* XHCI controllers don't stop the ep queue on short packets :| */
4840 hcd->self.no_stop_on_short = 1;
4841
4842 xhci = hcd_to_xhci(hcd);
4843
4844 if (usb_hcd_is_primary_hcd(hcd)) {
4845 xhci->main_hcd = hcd;
4846 /* Mark the first roothub as being USB 2.0.
4847 * The xHCI driver will register the USB 3.0 roothub.
4848 */
4849 hcd->speed = HCD_USB2;
4850 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4851 /*
4852 * USB 2.0 roothub under xHCI has an integrated TT,
4853 * (rate matching hub) as opposed to having an OHCI/UHCI
4854 * companion controller.
4855 */
4856 hcd->has_tt = 1;
4857 } else {
4858 if (xhci->sbrn == 0x31) {
4859 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4860 hcd->speed = HCD_USB31;
4861 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4862 }
4863 /* xHCI private pointer was set in xhci_pci_probe for the second
4864 * registered roothub.
4865 */
4866 return 0;
4867 }
4868
4869 mutex_init(&xhci->mutex);
4870 xhci->cap_regs = hcd->regs;
4871 xhci->op_regs = hcd->regs +
4872 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4873 xhci->run_regs = hcd->regs +
4874 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4875 /* Cache read-only capability registers */
4876 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4877 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4878 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4879 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4880 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4881 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4882 if (xhci->hci_version > 0x100)
4883 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4884 xhci_print_registers(xhci);
4885
4886 xhci->quirks |= quirks;
4887
4888 get_quirks(dev, xhci);
4889
4890 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4891 * success event after a short transfer. This quirk will ignore such
4892 * spurious event.
4893 */
4894 if (xhci->hci_version > 0x96)
4895 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4896
4897 /* Make sure the HC is halted. */
4898 retval = xhci_halt(xhci);
4899 if (retval)
4900 return retval;
4901
4902 xhci_dbg(xhci, "Resetting HCD\n");
4903 /* Reset the internal HC memory state and registers. */
4904 retval = xhci_reset(xhci);
4905 if (retval)
4906 return retval;
4907 xhci_dbg(xhci, "Reset complete\n");
4908
4909 /*
4910 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4911 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4912 * address memory pointers actually. So, this driver clears the AC64
4913 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4914 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4915 */
4916 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
4917 xhci->hcc_params &= ~BIT(0);
4918
4919 /* Set dma_mask and coherent_dma_mask to 64-bits,
4920 * if xHC supports 64-bit addressing */
4921 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4922 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4923 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4924 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4925 } else {
4926 /*
4927 * This is to avoid error in cases where a 32-bit USB
4928 * controller is used on a 64-bit capable system.
4929 */
4930 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4931 if (retval)
4932 return retval;
4933 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4934 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4935 }
4936
4937 xhci_dbg(xhci, "Calling HCD init\n");
4938 /* Initialize HCD and host controller data structures. */
4939 retval = xhci_init(hcd);
4940 if (retval)
4941 return retval;
4942 xhci_dbg(xhci, "Called HCD init\n");
4943
4944 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4945 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4946
4947 return 0;
4948}
4949EXPORT_SYMBOL_GPL(xhci_gen_setup);
4950
4951static const struct hc_driver xhci_hc_driver = {
4952 .description = "xhci-hcd",
4953 .product_desc = "xHCI Host Controller",
4954 .hcd_priv_size = sizeof(struct xhci_hcd),
4955
4956 /*
4957 * generic hardware linkage
4958 */
4959 .irq = xhci_irq,
4960 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4961
4962 /*
4963 * basic lifecycle operations
4964 */
4965 .reset = NULL, /* set in xhci_init_driver() */
4966 .start = xhci_run,
4967 .stop = xhci_stop,
4968 .shutdown = xhci_shutdown,
4969
4970 /*
4971 * managing i/o requests and associated device resources
4972 */
4973 .urb_enqueue = xhci_urb_enqueue,
4974 .urb_dequeue = xhci_urb_dequeue,
4975 .alloc_dev = xhci_alloc_dev,
4976 .free_dev = xhci_free_dev,
4977 .alloc_streams = xhci_alloc_streams,
4978 .free_streams = xhci_free_streams,
4979 .add_endpoint = xhci_add_endpoint,
4980 .drop_endpoint = xhci_drop_endpoint,
4981 .endpoint_reset = xhci_endpoint_reset,
4982 .check_bandwidth = xhci_check_bandwidth,
4983 .reset_bandwidth = xhci_reset_bandwidth,
4984 .address_device = xhci_address_device,
4985 .enable_device = xhci_enable_device,
4986 .update_hub_device = xhci_update_hub_device,
4987 .reset_device = xhci_discover_or_reset_device,
4988
4989 /*
4990 * scheduling support
4991 */
4992 .get_frame_number = xhci_get_frame,
4993
4994 /*
4995 * root hub support
4996 */
4997 .hub_control = xhci_hub_control,
4998 .hub_status_data = xhci_hub_status_data,
4999 .bus_suspend = xhci_bus_suspend,
5000 .bus_resume = xhci_bus_resume,
5001
5002 /*
5003 * call back when device connected and addressed
5004 */
5005 .update_device = xhci_update_device,
5006 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5007 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5008 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5009 .find_raw_port_number = xhci_find_raw_port_number,
5010};
5011
5012void xhci_init_driver(struct hc_driver *drv,
5013 const struct xhci_driver_overrides *over)
5014{
5015 BUG_ON(!over);
5016
5017 /* Copy the generic table to drv then apply the overrides */
5018 *drv = xhci_hc_driver;
5019
5020 if (over) {
5021 drv->hcd_priv_size += over->extra_priv_size;
5022 if (over->reset)
5023 drv->reset = over->reset;
5024 if (over->start)
5025 drv->start = over->start;
5026 }
5027}
5028EXPORT_SYMBOL_GPL(xhci_init_driver);
5029
5030MODULE_DESCRIPTION(DRIVER_DESC);
5031MODULE_AUTHOR(DRIVER_AUTHOR);
5032MODULE_LICENSE("GPL");
5033
5034static int __init xhci_hcd_init(void)
5035{
5036 /*
5037 * Check the compiler generated sizes of structures that must be laid
5038 * out in specific ways for hardware access.
5039 */
5040 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5041 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5042 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5043 /* xhci_device_control has eight fields, and also
5044 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5045 */
5046 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5047 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5048 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5049 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5050 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5051 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5052 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5053
5054 if (usb_disabled())
5055 return -ENODEV;
5056
5057 return 0;
5058}
5059
5060/*
5061 * If an init function is provided, an exit function must also be provided
5062 * to allow module unload.
5063 */
5064static void __exit xhci_hcd_fini(void) { }
5065
5066module_init(xhci_hcd_init);
5067module_exit(xhci_hcd_fini);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/pci.h>
12#include <linux/iopoll.h>
13#include <linux/irq.h>
14#include <linux/log2.h>
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/slab.h>
18#include <linux/dmi.h>
19#include <linux/dma-mapping.h>
20
21#include "xhci.h"
22#include "xhci-trace.h"
23#include "xhci-mtk.h"
24#include "xhci-debugfs.h"
25#include "xhci-dbgcap.h"
26
27#define DRIVER_AUTHOR "Sarah Sharp"
28#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29
30#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31
32/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33static int link_quirk;
34module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36
37static unsigned long long quirks;
38module_param(quirks, ullong, S_IRUGO);
39MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40
41static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42{
43 struct xhci_segment *seg = ring->first_seg;
44
45 if (!td || !td->start_seg)
46 return false;
47 do {
48 if (seg == td->start_seg)
49 return true;
50 seg = seg->next;
51 } while (seg && seg != ring->first_seg);
52
53 return false;
54}
55
56/*
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
62 *
63 * Returns negative errno, or zero on success
64 *
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 */
69int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
70{
71 u32 result;
72 int ret;
73
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
76 result == U32_MAX,
77 1, usec);
78 if (result == U32_MAX) /* card removed */
79 return -ENODEV;
80
81 return ret;
82}
83
84/*
85 * Disable interrupts and begin the xHCI halting process.
86 */
87void xhci_quiesce(struct xhci_hcd *xhci)
88{
89 u32 halted;
90 u32 cmd;
91 u32 mask;
92
93 mask = ~(XHCI_IRQS);
94 halted = readl(&xhci->op_regs->status) & STS_HALT;
95 if (!halted)
96 mask &= ~CMD_RUN;
97
98 cmd = readl(&xhci->op_regs->command);
99 cmd &= mask;
100 writel(cmd, &xhci->op_regs->command);
101}
102
103/*
104 * Force HC into halt state.
105 *
106 * Disable any IRQs and clear the run/stop bit.
107 * HC will complete any current and actively pipelined transactions, and
108 * should halt within 16 ms of the run/stop bit being cleared.
109 * Read HC Halted bit in the status register to see when the HC is finished.
110 */
111int xhci_halt(struct xhci_hcd *xhci)
112{
113 int ret;
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
115 xhci_quiesce(xhci);
116
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
119 if (ret) {
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
121 return ret;
122 }
123 xhci->xhc_state |= XHCI_STATE_HALTED;
124 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
125 return ret;
126}
127
128/*
129 * Set the run bit and wait for the host to be running.
130 */
131int xhci_start(struct xhci_hcd *xhci)
132{
133 u32 temp;
134 int ret;
135
136 temp = readl(&xhci->op_regs->command);
137 temp |= (CMD_RUN);
138 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
139 temp);
140 writel(temp, &xhci->op_regs->command);
141
142 /*
143 * Wait for the HCHalted Status bit to be 0 to indicate the host is
144 * running.
145 */
146 ret = xhci_handshake(&xhci->op_regs->status,
147 STS_HALT, 0, XHCI_MAX_HALT_USEC);
148 if (ret == -ETIMEDOUT)
149 xhci_err(xhci, "Host took too long to start, "
150 "waited %u microseconds.\n",
151 XHCI_MAX_HALT_USEC);
152 if (!ret)
153 /* clear state flags. Including dying, halted or removing */
154 xhci->xhc_state = 0;
155
156 return ret;
157}
158
159/*
160 * Reset a halted HC.
161 *
162 * This resets pipelines, timers, counters, state machines, etc.
163 * Transactions will be terminated immediately, and operational registers
164 * will be set to their defaults.
165 */
166int xhci_reset(struct xhci_hcd *xhci)
167{
168 u32 command;
169 u32 state;
170 int ret;
171
172 state = readl(&xhci->op_regs->status);
173
174 if (state == ~(u32)0) {
175 xhci_warn(xhci, "Host not accessible, reset failed.\n");
176 return -ENODEV;
177 }
178
179 if ((state & STS_HALT) == 0) {
180 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
181 return 0;
182 }
183
184 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
185 command = readl(&xhci->op_regs->command);
186 command |= CMD_RESET;
187 writel(command, &xhci->op_regs->command);
188
189 /* Existing Intel xHCI controllers require a delay of 1 mS,
190 * after setting the CMD_RESET bit, and before accessing any
191 * HC registers. This allows the HC to complete the
192 * reset operation and be ready for HC register access.
193 * Without this delay, the subsequent HC register access,
194 * may result in a system hang very rarely.
195 */
196 if (xhci->quirks & XHCI_INTEL_HOST)
197 udelay(1000);
198
199 ret = xhci_handshake(&xhci->op_regs->command,
200 CMD_RESET, 0, 10 * 1000 * 1000);
201 if (ret)
202 return ret;
203
204 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
205 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
206
207 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
208 "Wait for controller to be ready for doorbell rings");
209 /*
210 * xHCI cannot write to any doorbells or operational registers other
211 * than status until the "Controller Not Ready" flag is cleared.
212 */
213 ret = xhci_handshake(&xhci->op_regs->status,
214 STS_CNR, 0, 10 * 1000 * 1000);
215
216 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
217 xhci->usb2_rhub.bus_state.suspended_ports = 0;
218 xhci->usb2_rhub.bus_state.resuming_ports = 0;
219 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
220 xhci->usb3_rhub.bus_state.suspended_ports = 0;
221 xhci->usb3_rhub.bus_state.resuming_ports = 0;
222
223 return ret;
224}
225
226static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
227{
228 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
229 int err, i;
230 u64 val;
231
232 /*
233 * Some Renesas controllers get into a weird state if they are
234 * reset while programmed with 64bit addresses (they will preserve
235 * the top half of the address in internal, non visible
236 * registers). You end up with half the address coming from the
237 * kernel, and the other half coming from the firmware. Also,
238 * changing the programming leads to extra accesses even if the
239 * controller is supposed to be halted. The controller ends up with
240 * a fatal fault, and is then ripe for being properly reset.
241 *
242 * Special care is taken to only apply this if the device is behind
243 * an iommu. Doing anything when there is no iommu is definitely
244 * unsafe...
245 */
246 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
247 return;
248
249 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
250
251 /* Clear HSEIE so that faults do not get signaled */
252 val = readl(&xhci->op_regs->command);
253 val &= ~CMD_HSEIE;
254 writel(val, &xhci->op_regs->command);
255
256 /* Clear HSE (aka FATAL) */
257 val = readl(&xhci->op_regs->status);
258 val |= STS_FATAL;
259 writel(val, &xhci->op_regs->status);
260
261 /* Now zero the registers, and brace for impact */
262 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
263 if (upper_32_bits(val))
264 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
265 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
268
269 for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
270 struct xhci_intr_reg __iomem *ir;
271
272 ir = &xhci->run_regs->ir_set[i];
273 val = xhci_read_64(xhci, &ir->erst_base);
274 if (upper_32_bits(val))
275 xhci_write_64(xhci, 0, &ir->erst_base);
276 val= xhci_read_64(xhci, &ir->erst_dequeue);
277 if (upper_32_bits(val))
278 xhci_write_64(xhci, 0, &ir->erst_dequeue);
279 }
280
281 /* Wait for the fault to appear. It will be cleared on reset */
282 err = xhci_handshake(&xhci->op_regs->status,
283 STS_FATAL, STS_FATAL,
284 XHCI_MAX_HALT_USEC);
285 if (!err)
286 xhci_info(xhci, "Fault detected\n");
287}
288
289#ifdef CONFIG_USB_PCI
290/*
291 * Set up MSI
292 */
293static int xhci_setup_msi(struct xhci_hcd *xhci)
294{
295 int ret;
296 /*
297 * TODO:Check with MSI Soc for sysdev
298 */
299 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
300
301 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
302 if (ret < 0) {
303 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
304 "failed to allocate MSI entry");
305 return ret;
306 }
307
308 ret = request_irq(pdev->irq, xhci_msi_irq,
309 0, "xhci_hcd", xhci_to_hcd(xhci));
310 if (ret) {
311 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
312 "disable MSI interrupt");
313 pci_free_irq_vectors(pdev);
314 }
315
316 return ret;
317}
318
319/*
320 * Set up MSI-X
321 */
322static int xhci_setup_msix(struct xhci_hcd *xhci)
323{
324 int i, ret = 0;
325 struct usb_hcd *hcd = xhci_to_hcd(xhci);
326 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
327
328 /*
329 * calculate number of msi-x vectors supported.
330 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
331 * with max number of interrupters based on the xhci HCSPARAMS1.
332 * - num_online_cpus: maximum msi-x vectors per CPUs core.
333 * Add additional 1 vector to ensure always available interrupt.
334 */
335 xhci->msix_count = min(num_online_cpus() + 1,
336 HCS_MAX_INTRS(xhci->hcs_params1));
337
338 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
339 PCI_IRQ_MSIX);
340 if (ret < 0) {
341 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
342 "Failed to enable MSI-X");
343 return ret;
344 }
345
346 for (i = 0; i < xhci->msix_count; i++) {
347 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
348 "xhci_hcd", xhci_to_hcd(xhci));
349 if (ret)
350 goto disable_msix;
351 }
352
353 hcd->msix_enabled = 1;
354 return ret;
355
356disable_msix:
357 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
358 while (--i >= 0)
359 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
360 pci_free_irq_vectors(pdev);
361 return ret;
362}
363
364/* Free any IRQs and disable MSI-X */
365static void xhci_cleanup_msix(struct xhci_hcd *xhci)
366{
367 struct usb_hcd *hcd = xhci_to_hcd(xhci);
368 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
369
370 if (xhci->quirks & XHCI_PLAT)
371 return;
372
373 /* return if using legacy interrupt */
374 if (hcd->irq > 0)
375 return;
376
377 if (hcd->msix_enabled) {
378 int i;
379
380 for (i = 0; i < xhci->msix_count; i++)
381 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
382 } else {
383 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
384 }
385
386 pci_free_irq_vectors(pdev);
387 hcd->msix_enabled = 0;
388}
389
390static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
391{
392 struct usb_hcd *hcd = xhci_to_hcd(xhci);
393
394 if (hcd->msix_enabled) {
395 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
396 int i;
397
398 for (i = 0; i < xhci->msix_count; i++)
399 synchronize_irq(pci_irq_vector(pdev, i));
400 }
401}
402
403static int xhci_try_enable_msi(struct usb_hcd *hcd)
404{
405 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
406 struct pci_dev *pdev;
407 int ret;
408
409 /* The xhci platform device has set up IRQs through usb_add_hcd. */
410 if (xhci->quirks & XHCI_PLAT)
411 return 0;
412
413 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
414 /*
415 * Some Fresco Logic host controllers advertise MSI, but fail to
416 * generate interrupts. Don't even try to enable MSI.
417 */
418 if (xhci->quirks & XHCI_BROKEN_MSI)
419 goto legacy_irq;
420
421 /* unregister the legacy interrupt */
422 if (hcd->irq)
423 free_irq(hcd->irq, hcd);
424 hcd->irq = 0;
425
426 ret = xhci_setup_msix(xhci);
427 if (ret)
428 /* fall back to msi*/
429 ret = xhci_setup_msi(xhci);
430
431 if (!ret) {
432 hcd->msi_enabled = 1;
433 return 0;
434 }
435
436 if (!pdev->irq) {
437 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
438 return -EINVAL;
439 }
440
441 legacy_irq:
442 if (!strlen(hcd->irq_descr))
443 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
444 hcd->driver->description, hcd->self.busnum);
445
446 /* fall back to legacy interrupt*/
447 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
448 hcd->irq_descr, hcd);
449 if (ret) {
450 xhci_err(xhci, "request interrupt %d failed\n",
451 pdev->irq);
452 return ret;
453 }
454 hcd->irq = pdev->irq;
455 return 0;
456}
457
458#else
459
460static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
461{
462 return 0;
463}
464
465static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
466{
467}
468
469static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
470{
471}
472
473#endif
474
475static void compliance_mode_recovery(struct timer_list *t)
476{
477 struct xhci_hcd *xhci;
478 struct usb_hcd *hcd;
479 struct xhci_hub *rhub;
480 u32 temp;
481 int i;
482
483 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
484 rhub = &xhci->usb3_rhub;
485
486 for (i = 0; i < rhub->num_ports; i++) {
487 temp = readl(rhub->ports[i]->addr);
488 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
489 /*
490 * Compliance Mode Detected. Letting USB Core
491 * handle the Warm Reset
492 */
493 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
494 "Compliance mode detected->port %d",
495 i + 1);
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Attempting compliance mode recovery");
498 hcd = xhci->shared_hcd;
499
500 if (hcd->state == HC_STATE_SUSPENDED)
501 usb_hcd_resume_root_hub(hcd);
502
503 usb_hcd_poll_rh_status(hcd);
504 }
505 }
506
507 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
508 mod_timer(&xhci->comp_mode_recovery_timer,
509 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
510}
511
512/*
513 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
514 * that causes ports behind that hardware to enter compliance mode sometimes.
515 * The quirk creates a timer that polls every 2 seconds the link state of
516 * each host controller's port and recovers it by issuing a Warm reset
517 * if Compliance mode is detected, otherwise the port will become "dead" (no
518 * device connections or disconnections will be detected anymore). Becasue no
519 * status event is generated when entering compliance mode (per xhci spec),
520 * this quirk is needed on systems that have the failing hardware installed.
521 */
522static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
523{
524 xhci->port_status_u0 = 0;
525 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
526 0);
527 xhci->comp_mode_recovery_timer.expires = jiffies +
528 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
529
530 add_timer(&xhci->comp_mode_recovery_timer);
531 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
532 "Compliance mode recovery timer initialized");
533}
534
535/*
536 * This function identifies the systems that have installed the SN65LVPE502CP
537 * USB3.0 re-driver and that need the Compliance Mode Quirk.
538 * Systems:
539 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
540 */
541static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
542{
543 const char *dmi_product_name, *dmi_sys_vendor;
544
545 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
546 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
547 if (!dmi_product_name || !dmi_sys_vendor)
548 return false;
549
550 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
551 return false;
552
553 if (strstr(dmi_product_name, "Z420") ||
554 strstr(dmi_product_name, "Z620") ||
555 strstr(dmi_product_name, "Z820") ||
556 strstr(dmi_product_name, "Z1 Workstation"))
557 return true;
558
559 return false;
560}
561
562static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
563{
564 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
565}
566
567
568/*
569 * Initialize memory for HCD and xHC (one-time init).
570 *
571 * Program the PAGESIZE register, initialize the device context array, create
572 * device contexts (?), set up a command ring segment (or two?), create event
573 * ring (one for now).
574 */
575static int xhci_init(struct usb_hcd *hcd)
576{
577 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
578 int retval = 0;
579
580 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
581 spin_lock_init(&xhci->lock);
582 if (xhci->hci_version == 0x95 && link_quirk) {
583 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
584 "QUIRK: Not clearing Link TRB chain bits.");
585 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
586 } else {
587 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
588 "xHCI doesn't need link TRB QUIRK");
589 }
590 retval = xhci_mem_init(xhci, GFP_KERNEL);
591 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
592
593 /* Initializing Compliance Mode Recovery Data If Needed */
594 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
595 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
596 compliance_mode_recovery_timer_init(xhci);
597 }
598
599 return retval;
600}
601
602/*-------------------------------------------------------------------------*/
603
604
605static int xhci_run_finished(struct xhci_hcd *xhci)
606{
607 if (xhci_start(xhci)) {
608 xhci_halt(xhci);
609 return -ENODEV;
610 }
611 xhci->shared_hcd->state = HC_STATE_RUNNING;
612 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
613
614 if (xhci->quirks & XHCI_NEC_HOST)
615 xhci_ring_cmd_db(xhci);
616
617 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
618 "Finished xhci_run for USB3 roothub");
619 return 0;
620}
621
622/*
623 * Start the HC after it was halted.
624 *
625 * This function is called by the USB core when the HC driver is added.
626 * Its opposite is xhci_stop().
627 *
628 * xhci_init() must be called once before this function can be called.
629 * Reset the HC, enable device slot contexts, program DCBAAP, and
630 * set command ring pointer and event ring pointer.
631 *
632 * Setup MSI-X vectors and enable interrupts.
633 */
634int xhci_run(struct usb_hcd *hcd)
635{
636 u32 temp;
637 u64 temp_64;
638 int ret;
639 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
640
641 /* Start the xHCI host controller running only after the USB 2.0 roothub
642 * is setup.
643 */
644
645 hcd->uses_new_polling = 1;
646 if (!usb_hcd_is_primary_hcd(hcd))
647 return xhci_run_finished(xhci);
648
649 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
650
651 ret = xhci_try_enable_msi(hcd);
652 if (ret)
653 return ret;
654
655 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
656 temp_64 &= ~ERST_PTR_MASK;
657 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
658 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
659
660 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
661 "// Set the interrupt modulation register");
662 temp = readl(&xhci->ir_set->irq_control);
663 temp &= ~ER_IRQ_INTERVAL_MASK;
664 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
665 writel(temp, &xhci->ir_set->irq_control);
666
667 /* Set the HCD state before we enable the irqs */
668 temp = readl(&xhci->op_regs->command);
669 temp |= (CMD_EIE);
670 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
671 "// Enable interrupts, cmd = 0x%x.", temp);
672 writel(temp, &xhci->op_regs->command);
673
674 temp = readl(&xhci->ir_set->irq_pending);
675 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
676 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
677 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
678 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
679
680 if (xhci->quirks & XHCI_NEC_HOST) {
681 struct xhci_command *command;
682
683 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
684 if (!command)
685 return -ENOMEM;
686
687 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
688 TRB_TYPE(TRB_NEC_GET_FW));
689 if (ret)
690 xhci_free_command(xhci, command);
691 }
692 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
693 "Finished xhci_run for USB2 roothub");
694
695 xhci_dbc_init(xhci);
696
697 xhci_debugfs_init(xhci);
698
699 return 0;
700}
701EXPORT_SYMBOL_GPL(xhci_run);
702
703/*
704 * Stop xHCI driver.
705 *
706 * This function is called by the USB core when the HC driver is removed.
707 * Its opposite is xhci_run().
708 *
709 * Disable device contexts, disable IRQs, and quiesce the HC.
710 * Reset the HC, finish any completed transactions, and cleanup memory.
711 */
712static void xhci_stop(struct usb_hcd *hcd)
713{
714 u32 temp;
715 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
716
717 mutex_lock(&xhci->mutex);
718
719 /* Only halt host and free memory after both hcds are removed */
720 if (!usb_hcd_is_primary_hcd(hcd)) {
721 mutex_unlock(&xhci->mutex);
722 return;
723 }
724
725 xhci_dbc_exit(xhci);
726
727 spin_lock_irq(&xhci->lock);
728 xhci->xhc_state |= XHCI_STATE_HALTED;
729 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
730 xhci_halt(xhci);
731 xhci_reset(xhci);
732 spin_unlock_irq(&xhci->lock);
733
734 xhci_cleanup_msix(xhci);
735
736 /* Deleting Compliance Mode Recovery Timer */
737 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
738 (!(xhci_all_ports_seen_u0(xhci)))) {
739 del_timer_sync(&xhci->comp_mode_recovery_timer);
740 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
741 "%s: compliance mode recovery timer deleted",
742 __func__);
743 }
744
745 if (xhci->quirks & XHCI_AMD_PLL_FIX)
746 usb_amd_dev_put();
747
748 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
749 "// Disabling event ring interrupts");
750 temp = readl(&xhci->op_regs->status);
751 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
752 temp = readl(&xhci->ir_set->irq_pending);
753 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
754
755 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
756 xhci_mem_cleanup(xhci);
757 xhci_debugfs_exit(xhci);
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "xhci_stop completed - status = %x",
760 readl(&xhci->op_regs->status));
761 mutex_unlock(&xhci->mutex);
762}
763
764/*
765 * Shutdown HC (not bus-specific)
766 *
767 * This is called when the machine is rebooting or halting. We assume that the
768 * machine will be powered off, and the HC's internal state will be reset.
769 * Don't bother to free memory.
770 *
771 * This will only ever be called with the main usb_hcd (the USB3 roothub).
772 */
773static void xhci_shutdown(struct usb_hcd *hcd)
774{
775 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
776
777 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
778 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
779
780 spin_lock_irq(&xhci->lock);
781 xhci_halt(xhci);
782 /* Workaround for spurious wakeups at shutdown with HSW */
783 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
784 xhci_reset(xhci);
785 spin_unlock_irq(&xhci->lock);
786
787 xhci_cleanup_msix(xhci);
788
789 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
790 "xhci_shutdown completed - status = %x",
791 readl(&xhci->op_regs->status));
792
793 /* Yet another workaround for spurious wakeups at shutdown with HSW */
794 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
795 pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot);
796}
797
798#ifdef CONFIG_PM
799static void xhci_save_registers(struct xhci_hcd *xhci)
800{
801 xhci->s3.command = readl(&xhci->op_regs->command);
802 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
803 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
804 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
805 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
806 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
807 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
808 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
809 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
810}
811
812static void xhci_restore_registers(struct xhci_hcd *xhci)
813{
814 writel(xhci->s3.command, &xhci->op_regs->command);
815 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
816 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
817 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
818 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
819 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
820 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
821 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
822 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
823}
824
825static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
826{
827 u64 val_64;
828
829 /* step 2: initialize command ring buffer */
830 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
831 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
832 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
833 xhci->cmd_ring->dequeue) &
834 (u64) ~CMD_RING_RSVD_BITS) |
835 xhci->cmd_ring->cycle_state;
836 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
837 "// Setting command ring address to 0x%llx",
838 (long unsigned long) val_64);
839 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
840}
841
842/*
843 * The whole command ring must be cleared to zero when we suspend the host.
844 *
845 * The host doesn't save the command ring pointer in the suspend well, so we
846 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
847 * aligned, because of the reserved bits in the command ring dequeue pointer
848 * register. Therefore, we can't just set the dequeue pointer back in the
849 * middle of the ring (TRBs are 16-byte aligned).
850 */
851static void xhci_clear_command_ring(struct xhci_hcd *xhci)
852{
853 struct xhci_ring *ring;
854 struct xhci_segment *seg;
855
856 ring = xhci->cmd_ring;
857 seg = ring->deq_seg;
858 do {
859 memset(seg->trbs, 0,
860 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
861 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
862 cpu_to_le32(~TRB_CYCLE);
863 seg = seg->next;
864 } while (seg != ring->deq_seg);
865
866 /* Reset the software enqueue and dequeue pointers */
867 ring->deq_seg = ring->first_seg;
868 ring->dequeue = ring->first_seg->trbs;
869 ring->enq_seg = ring->deq_seg;
870 ring->enqueue = ring->dequeue;
871
872 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
873 /*
874 * Ring is now zeroed, so the HW should look for change of ownership
875 * when the cycle bit is set to 1.
876 */
877 ring->cycle_state = 1;
878
879 /*
880 * Reset the hardware dequeue pointer.
881 * Yes, this will need to be re-written after resume, but we're paranoid
882 * and want to make sure the hardware doesn't access bogus memory
883 * because, say, the BIOS or an SMI started the host without changing
884 * the command ring pointers.
885 */
886 xhci_set_cmd_ring_deq(xhci);
887}
888
889static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
890{
891 struct xhci_port **ports;
892 int port_index;
893 unsigned long flags;
894 u32 t1, t2, portsc;
895
896 spin_lock_irqsave(&xhci->lock, flags);
897
898 /* disable usb3 ports Wake bits */
899 port_index = xhci->usb3_rhub.num_ports;
900 ports = xhci->usb3_rhub.ports;
901 while (port_index--) {
902 t1 = readl(ports[port_index]->addr);
903 portsc = t1;
904 t1 = xhci_port_state_to_neutral(t1);
905 t2 = t1 & ~PORT_WAKE_BITS;
906 if (t1 != t2) {
907 writel(t2, ports[port_index]->addr);
908 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
909 xhci->usb3_rhub.hcd->self.busnum,
910 port_index + 1, portsc, t2);
911 }
912 }
913
914 /* disable usb2 ports Wake bits */
915 port_index = xhci->usb2_rhub.num_ports;
916 ports = xhci->usb2_rhub.ports;
917 while (port_index--) {
918 t1 = readl(ports[port_index]->addr);
919 portsc = t1;
920 t1 = xhci_port_state_to_neutral(t1);
921 t2 = t1 & ~PORT_WAKE_BITS;
922 if (t1 != t2) {
923 writel(t2, ports[port_index]->addr);
924 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
925 xhci->usb2_rhub.hcd->self.busnum,
926 port_index + 1, portsc, t2);
927 }
928 }
929 spin_unlock_irqrestore(&xhci->lock, flags);
930}
931
932static bool xhci_pending_portevent(struct xhci_hcd *xhci)
933{
934 struct xhci_port **ports;
935 int port_index;
936 u32 status;
937 u32 portsc;
938
939 status = readl(&xhci->op_regs->status);
940 if (status & STS_EINT)
941 return true;
942 /*
943 * Checking STS_EINT is not enough as there is a lag between a change
944 * bit being set and the Port Status Change Event that it generated
945 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
946 */
947
948 port_index = xhci->usb2_rhub.num_ports;
949 ports = xhci->usb2_rhub.ports;
950 while (port_index--) {
951 portsc = readl(ports[port_index]->addr);
952 if (portsc & PORT_CHANGE_MASK ||
953 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
954 return true;
955 }
956 port_index = xhci->usb3_rhub.num_ports;
957 ports = xhci->usb3_rhub.ports;
958 while (port_index--) {
959 portsc = readl(ports[port_index]->addr);
960 if (portsc & PORT_CHANGE_MASK ||
961 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
962 return true;
963 }
964 return false;
965}
966
967/*
968 * Stop HC (not bus-specific)
969 *
970 * This is called when the machine transition into S3/S4 mode.
971 *
972 */
973int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
974{
975 int rc = 0;
976 unsigned int delay = XHCI_MAX_HALT_USEC;
977 struct usb_hcd *hcd = xhci_to_hcd(xhci);
978 u32 command;
979 u32 res;
980
981 if (!hcd->state)
982 return 0;
983
984 if (hcd->state != HC_STATE_SUSPENDED ||
985 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
986 return -EINVAL;
987
988 xhci_dbc_suspend(xhci);
989
990 /* Clear root port wake on bits if wakeup not allowed. */
991 if (!do_wakeup)
992 xhci_disable_port_wake_on_bits(xhci);
993
994 /* Don't poll the roothubs on bus suspend. */
995 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
996 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
997 del_timer_sync(&hcd->rh_timer);
998 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
999 del_timer_sync(&xhci->shared_hcd->rh_timer);
1000
1001 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1002 usleep_range(1000, 1500);
1003
1004 spin_lock_irq(&xhci->lock);
1005 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1006 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1007 /* step 1: stop endpoint */
1008 /* skipped assuming that port suspend has done */
1009
1010 /* step 2: clear Run/Stop bit */
1011 command = readl(&xhci->op_regs->command);
1012 command &= ~CMD_RUN;
1013 writel(command, &xhci->op_regs->command);
1014
1015 /* Some chips from Fresco Logic need an extraordinary delay */
1016 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1017
1018 if (xhci_handshake(&xhci->op_regs->status,
1019 STS_HALT, STS_HALT, delay)) {
1020 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1021 spin_unlock_irq(&xhci->lock);
1022 return -ETIMEDOUT;
1023 }
1024 xhci_clear_command_ring(xhci);
1025
1026 /* step 3: save registers */
1027 xhci_save_registers(xhci);
1028
1029 /* step 4: set CSS flag */
1030 command = readl(&xhci->op_regs->command);
1031 command |= CMD_CSS;
1032 writel(command, &xhci->op_regs->command);
1033 xhci->broken_suspend = 0;
1034 if (xhci_handshake(&xhci->op_regs->status,
1035 STS_SAVE, 0, 20 * 1000)) {
1036 /*
1037 * AMD SNPS xHC 3.0 occasionally does not clear the
1038 * SSS bit of USBSTS and when driver tries to poll
1039 * to see if the xHC clears BIT(8) which never happens
1040 * and driver assumes that controller is not responding
1041 * and times out. To workaround this, its good to check
1042 * if SRE and HCE bits are not set (as per xhci
1043 * Section 5.4.2) and bypass the timeout.
1044 */
1045 res = readl(&xhci->op_regs->status);
1046 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1047 (((res & STS_SRE) == 0) &&
1048 ((res & STS_HCE) == 0))) {
1049 xhci->broken_suspend = 1;
1050 } else {
1051 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1052 spin_unlock_irq(&xhci->lock);
1053 return -ETIMEDOUT;
1054 }
1055 }
1056 spin_unlock_irq(&xhci->lock);
1057
1058 /*
1059 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1060 * is about to be suspended.
1061 */
1062 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1063 (!(xhci_all_ports_seen_u0(xhci)))) {
1064 del_timer_sync(&xhci->comp_mode_recovery_timer);
1065 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1066 "%s: compliance mode recovery timer deleted",
1067 __func__);
1068 }
1069
1070 /* step 5: remove core well power */
1071 /* synchronize irq when using MSI-X */
1072 xhci_msix_sync_irqs(xhci);
1073
1074 return rc;
1075}
1076EXPORT_SYMBOL_GPL(xhci_suspend);
1077
1078/*
1079 * start xHC (not bus-specific)
1080 *
1081 * This is called when the machine transition from S3/S4 mode.
1082 *
1083 */
1084int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1085{
1086 u32 command, temp = 0;
1087 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1088 struct usb_hcd *secondary_hcd;
1089 int retval = 0;
1090 bool comp_timer_running = false;
1091
1092 if (!hcd->state)
1093 return 0;
1094
1095 /* Wait a bit if either of the roothubs need to settle from the
1096 * transition into bus suspend.
1097 */
1098
1099 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1100 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1101 msleep(100);
1102
1103 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1104 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1105
1106 spin_lock_irq(&xhci->lock);
1107 if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
1108 hibernated = true;
1109
1110 if (!hibernated) {
1111 /*
1112 * Some controllers might lose power during suspend, so wait
1113 * for controller not ready bit to clear, just as in xHC init.
1114 */
1115 retval = xhci_handshake(&xhci->op_regs->status,
1116 STS_CNR, 0, 10 * 1000 * 1000);
1117 if (retval) {
1118 xhci_warn(xhci, "Controller not ready at resume %d\n",
1119 retval);
1120 spin_unlock_irq(&xhci->lock);
1121 return retval;
1122 }
1123 /* step 1: restore register */
1124 xhci_restore_registers(xhci);
1125 /* step 2: initialize command ring buffer */
1126 xhci_set_cmd_ring_deq(xhci);
1127 /* step 3: restore state and start state*/
1128 /* step 3: set CRS flag */
1129 command = readl(&xhci->op_regs->command);
1130 command |= CMD_CRS;
1131 writel(command, &xhci->op_regs->command);
1132 /*
1133 * Some controllers take up to 55+ ms to complete the controller
1134 * restore so setting the timeout to 100ms. Xhci specification
1135 * doesn't mention any timeout value.
1136 */
1137 if (xhci_handshake(&xhci->op_regs->status,
1138 STS_RESTORE, 0, 100 * 1000)) {
1139 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1140 spin_unlock_irq(&xhci->lock);
1141 return -ETIMEDOUT;
1142 }
1143 temp = readl(&xhci->op_regs->status);
1144 }
1145
1146 /* If restore operation fails, re-initialize the HC during resume */
1147 if ((temp & STS_SRE) || hibernated) {
1148
1149 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1150 !(xhci_all_ports_seen_u0(xhci))) {
1151 del_timer_sync(&xhci->comp_mode_recovery_timer);
1152 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1153 "Compliance Mode Recovery Timer deleted!");
1154 }
1155
1156 /* Let the USB core know _both_ roothubs lost power. */
1157 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1158 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1159
1160 xhci_dbg(xhci, "Stop HCD\n");
1161 xhci_halt(xhci);
1162 xhci_zero_64b_regs(xhci);
1163 xhci_reset(xhci);
1164 spin_unlock_irq(&xhci->lock);
1165 xhci_cleanup_msix(xhci);
1166
1167 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1168 temp = readl(&xhci->op_regs->status);
1169 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1170 temp = readl(&xhci->ir_set->irq_pending);
1171 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1172
1173 xhci_dbg(xhci, "cleaning up memory\n");
1174 xhci_mem_cleanup(xhci);
1175 xhci_debugfs_exit(xhci);
1176 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1177 readl(&xhci->op_regs->status));
1178
1179 /* USB core calls the PCI reinit and start functions twice:
1180 * first with the primary HCD, and then with the secondary HCD.
1181 * If we don't do the same, the host will never be started.
1182 */
1183 if (!usb_hcd_is_primary_hcd(hcd))
1184 secondary_hcd = hcd;
1185 else
1186 secondary_hcd = xhci->shared_hcd;
1187
1188 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1189 retval = xhci_init(hcd->primary_hcd);
1190 if (retval)
1191 return retval;
1192 comp_timer_running = true;
1193
1194 xhci_dbg(xhci, "Start the primary HCD\n");
1195 retval = xhci_run(hcd->primary_hcd);
1196 if (!retval) {
1197 xhci_dbg(xhci, "Start the secondary HCD\n");
1198 retval = xhci_run(secondary_hcd);
1199 }
1200 hcd->state = HC_STATE_SUSPENDED;
1201 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1202 goto done;
1203 }
1204
1205 /* step 4: set Run/Stop bit */
1206 command = readl(&xhci->op_regs->command);
1207 command |= CMD_RUN;
1208 writel(command, &xhci->op_regs->command);
1209 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1210 0, 250 * 1000);
1211
1212 /* step 5: walk topology and initialize portsc,
1213 * portpmsc and portli
1214 */
1215 /* this is done in bus_resume */
1216
1217 /* step 6: restart each of the previously
1218 * Running endpoints by ringing their doorbells
1219 */
1220
1221 spin_unlock_irq(&xhci->lock);
1222
1223 xhci_dbc_resume(xhci);
1224
1225 done:
1226 if (retval == 0) {
1227 /* Resume root hubs only when have pending events. */
1228 if (xhci_pending_portevent(xhci)) {
1229 usb_hcd_resume_root_hub(xhci->shared_hcd);
1230 usb_hcd_resume_root_hub(hcd);
1231 }
1232 }
1233
1234 /*
1235 * If system is subject to the Quirk, Compliance Mode Timer needs to
1236 * be re-initialized Always after a system resume. Ports are subject
1237 * to suffer the Compliance Mode issue again. It doesn't matter if
1238 * ports have entered previously to U0 before system's suspension.
1239 */
1240 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1241 compliance_mode_recovery_timer_init(xhci);
1242
1243 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1244 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1245
1246 /* Re-enable port polling. */
1247 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1248 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1249 usb_hcd_poll_rh_status(xhci->shared_hcd);
1250 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1251 usb_hcd_poll_rh_status(hcd);
1252
1253 return retval;
1254}
1255EXPORT_SYMBOL_GPL(xhci_resume);
1256#endif /* CONFIG_PM */
1257
1258/*-------------------------------------------------------------------------*/
1259
1260/*
1261 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1262 * we'll copy the actual data into the TRB address register. This is limited to
1263 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1264 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1265 */
1266static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1267 gfp_t mem_flags)
1268{
1269 if (xhci_urb_suitable_for_idt(urb))
1270 return 0;
1271
1272 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1273}
1274
1275/**
1276 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1277 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1278 * value to right shift 1 for the bitmask.
1279 *
1280 * Index = (epnum * 2) + direction - 1,
1281 * where direction = 0 for OUT, 1 for IN.
1282 * For control endpoints, the IN index is used (OUT index is unused), so
1283 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1284 */
1285unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1286{
1287 unsigned int index;
1288 if (usb_endpoint_xfer_control(desc))
1289 index = (unsigned int) (usb_endpoint_num(desc)*2);
1290 else
1291 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1292 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1293 return index;
1294}
1295
1296/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1297 * address from the XHCI endpoint index.
1298 */
1299unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1300{
1301 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1302 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1303 return direction | number;
1304}
1305
1306/* Find the flag for this endpoint (for use in the control context). Use the
1307 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1308 * bit 1, etc.
1309 */
1310static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1311{
1312 return 1 << (xhci_get_endpoint_index(desc) + 1);
1313}
1314
1315/* Find the flag for this endpoint (for use in the control context). Use the
1316 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1317 * bit 1, etc.
1318 */
1319static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1320{
1321 return 1 << (ep_index + 1);
1322}
1323
1324/* Compute the last valid endpoint context index. Basically, this is the
1325 * endpoint index plus one. For slot contexts with more than valid endpoint,
1326 * we find the most significant bit set in the added contexts flags.
1327 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1328 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1329 */
1330unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1331{
1332 return fls(added_ctxs) - 1;
1333}
1334
1335/* Returns 1 if the arguments are OK;
1336 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1337 */
1338static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1339 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1340 const char *func) {
1341 struct xhci_hcd *xhci;
1342 struct xhci_virt_device *virt_dev;
1343
1344 if (!hcd || (check_ep && !ep) || !udev) {
1345 pr_debug("xHCI %s called with invalid args\n", func);
1346 return -EINVAL;
1347 }
1348 if (!udev->parent) {
1349 pr_debug("xHCI %s called for root hub\n", func);
1350 return 0;
1351 }
1352
1353 xhci = hcd_to_xhci(hcd);
1354 if (check_virt_dev) {
1355 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1356 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1357 func);
1358 return -EINVAL;
1359 }
1360
1361 virt_dev = xhci->devs[udev->slot_id];
1362 if (virt_dev->udev != udev) {
1363 xhci_dbg(xhci, "xHCI %s called with udev and "
1364 "virt_dev does not match\n", func);
1365 return -EINVAL;
1366 }
1367 }
1368
1369 if (xhci->xhc_state & XHCI_STATE_HALTED)
1370 return -ENODEV;
1371
1372 return 1;
1373}
1374
1375static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1376 struct usb_device *udev, struct xhci_command *command,
1377 bool ctx_change, bool must_succeed);
1378
1379/*
1380 * Full speed devices may have a max packet size greater than 8 bytes, but the
1381 * USB core doesn't know that until it reads the first 8 bytes of the
1382 * descriptor. If the usb_device's max packet size changes after that point,
1383 * we need to issue an evaluate context command and wait on it.
1384 */
1385static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1386 unsigned int ep_index, struct urb *urb)
1387{
1388 struct xhci_container_ctx *out_ctx;
1389 struct xhci_input_control_ctx *ctrl_ctx;
1390 struct xhci_ep_ctx *ep_ctx;
1391 struct xhci_command *command;
1392 int max_packet_size;
1393 int hw_max_packet_size;
1394 int ret = 0;
1395
1396 out_ctx = xhci->devs[slot_id]->out_ctx;
1397 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1398 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1399 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1400 if (hw_max_packet_size != max_packet_size) {
1401 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1402 "Max Packet Size for ep 0 changed.");
1403 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1404 "Max packet size in usb_device = %d",
1405 max_packet_size);
1406 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1407 "Max packet size in xHCI HW = %d",
1408 hw_max_packet_size);
1409 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1410 "Issuing evaluate context command.");
1411
1412 /* Set up the input context flags for the command */
1413 /* FIXME: This won't work if a non-default control endpoint
1414 * changes max packet sizes.
1415 */
1416
1417 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1418 if (!command)
1419 return -ENOMEM;
1420
1421 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1422 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1423 if (!ctrl_ctx) {
1424 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1425 __func__);
1426 ret = -ENOMEM;
1427 goto command_cleanup;
1428 }
1429 /* Set up the modified control endpoint 0 */
1430 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1431 xhci->devs[slot_id]->out_ctx, ep_index);
1432
1433 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1434 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1435 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1436
1437 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1438 ctrl_ctx->drop_flags = 0;
1439
1440 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1441 true, false);
1442
1443 /* Clean up the input context for later use by bandwidth
1444 * functions.
1445 */
1446 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1447command_cleanup:
1448 kfree(command->completion);
1449 kfree(command);
1450 }
1451 return ret;
1452}
1453
1454/*
1455 * non-error returns are a promise to giveback() the urb later
1456 * we drop ownership so next owner (or urb unlink) can get it
1457 */
1458static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1459{
1460 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1461 unsigned long flags;
1462 int ret = 0;
1463 unsigned int slot_id, ep_index;
1464 unsigned int *ep_state;
1465 struct urb_priv *urb_priv;
1466 int num_tds;
1467
1468 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1469 true, true, __func__) <= 0)
1470 return -EINVAL;
1471
1472 slot_id = urb->dev->slot_id;
1473 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1474 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1475
1476 if (!HCD_HW_ACCESSIBLE(hcd)) {
1477 if (!in_interrupt())
1478 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1479 return -ESHUTDOWN;
1480 }
1481 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1482 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1483 return -ENODEV;
1484 }
1485
1486 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1487 num_tds = urb->number_of_packets;
1488 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1489 urb->transfer_buffer_length > 0 &&
1490 urb->transfer_flags & URB_ZERO_PACKET &&
1491 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1492 num_tds = 2;
1493 else
1494 num_tds = 1;
1495
1496 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1497 if (!urb_priv)
1498 return -ENOMEM;
1499
1500 urb_priv->num_tds = num_tds;
1501 urb_priv->num_tds_done = 0;
1502 urb->hcpriv = urb_priv;
1503
1504 trace_xhci_urb_enqueue(urb);
1505
1506 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1507 /* Check to see if the max packet size for the default control
1508 * endpoint changed during FS device enumeration
1509 */
1510 if (urb->dev->speed == USB_SPEED_FULL) {
1511 ret = xhci_check_maxpacket(xhci, slot_id,
1512 ep_index, urb);
1513 if (ret < 0) {
1514 xhci_urb_free_priv(urb_priv);
1515 urb->hcpriv = NULL;
1516 return ret;
1517 }
1518 }
1519 }
1520
1521 spin_lock_irqsave(&xhci->lock, flags);
1522
1523 if (xhci->xhc_state & XHCI_STATE_DYING) {
1524 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1525 urb->ep->desc.bEndpointAddress, urb);
1526 ret = -ESHUTDOWN;
1527 goto free_priv;
1528 }
1529 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1530 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1531 *ep_state);
1532 ret = -EINVAL;
1533 goto free_priv;
1534 }
1535 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1536 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1537 ret = -EINVAL;
1538 goto free_priv;
1539 }
1540
1541 switch (usb_endpoint_type(&urb->ep->desc)) {
1542
1543 case USB_ENDPOINT_XFER_CONTROL:
1544 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1545 slot_id, ep_index);
1546 break;
1547 case USB_ENDPOINT_XFER_BULK:
1548 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1549 slot_id, ep_index);
1550 break;
1551 case USB_ENDPOINT_XFER_INT:
1552 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1553 slot_id, ep_index);
1554 break;
1555 case USB_ENDPOINT_XFER_ISOC:
1556 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1557 slot_id, ep_index);
1558 }
1559
1560 if (ret) {
1561free_priv:
1562 xhci_urb_free_priv(urb_priv);
1563 urb->hcpriv = NULL;
1564 }
1565 spin_unlock_irqrestore(&xhci->lock, flags);
1566 return ret;
1567}
1568
1569/*
1570 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1571 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1572 * should pick up where it left off in the TD, unless a Set Transfer Ring
1573 * Dequeue Pointer is issued.
1574 *
1575 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1576 * the ring. Since the ring is a contiguous structure, they can't be physically
1577 * removed. Instead, there are two options:
1578 *
1579 * 1) If the HC is in the middle of processing the URB to be canceled, we
1580 * simply move the ring's dequeue pointer past those TRBs using the Set
1581 * Transfer Ring Dequeue Pointer command. This will be the common case,
1582 * when drivers timeout on the last submitted URB and attempt to cancel.
1583 *
1584 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1585 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1586 * HC will need to invalidate the any TRBs it has cached after the stop
1587 * endpoint command, as noted in the xHCI 0.95 errata.
1588 *
1589 * 3) The TD may have completed by the time the Stop Endpoint Command
1590 * completes, so software needs to handle that case too.
1591 *
1592 * This function should protect against the TD enqueueing code ringing the
1593 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1594 * It also needs to account for multiple cancellations on happening at the same
1595 * time for the same endpoint.
1596 *
1597 * Note that this function can be called in any context, or so says
1598 * usb_hcd_unlink_urb()
1599 */
1600static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1601{
1602 unsigned long flags;
1603 int ret, i;
1604 u32 temp;
1605 struct xhci_hcd *xhci;
1606 struct urb_priv *urb_priv;
1607 struct xhci_td *td;
1608 unsigned int ep_index;
1609 struct xhci_ring *ep_ring;
1610 struct xhci_virt_ep *ep;
1611 struct xhci_command *command;
1612 struct xhci_virt_device *vdev;
1613
1614 xhci = hcd_to_xhci(hcd);
1615 spin_lock_irqsave(&xhci->lock, flags);
1616
1617 trace_xhci_urb_dequeue(urb);
1618
1619 /* Make sure the URB hasn't completed or been unlinked already */
1620 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1621 if (ret)
1622 goto done;
1623
1624 /* give back URB now if we can't queue it for cancel */
1625 vdev = xhci->devs[urb->dev->slot_id];
1626 urb_priv = urb->hcpriv;
1627 if (!vdev || !urb_priv)
1628 goto err_giveback;
1629
1630 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1631 ep = &vdev->eps[ep_index];
1632 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1633 if (!ep || !ep_ring)
1634 goto err_giveback;
1635
1636 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1637 temp = readl(&xhci->op_regs->status);
1638 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1639 xhci_hc_died(xhci);
1640 goto done;
1641 }
1642
1643 /*
1644 * check ring is not re-allocated since URB was enqueued. If it is, then
1645 * make sure none of the ring related pointers in this URB private data
1646 * are touched, such as td_list, otherwise we overwrite freed data
1647 */
1648 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1649 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1650 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1651 td = &urb_priv->td[i];
1652 if (!list_empty(&td->cancelled_td_list))
1653 list_del_init(&td->cancelled_td_list);
1654 }
1655 goto err_giveback;
1656 }
1657
1658 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1659 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1660 "HC halted, freeing TD manually.");
1661 for (i = urb_priv->num_tds_done;
1662 i < urb_priv->num_tds;
1663 i++) {
1664 td = &urb_priv->td[i];
1665 if (!list_empty(&td->td_list))
1666 list_del_init(&td->td_list);
1667 if (!list_empty(&td->cancelled_td_list))
1668 list_del_init(&td->cancelled_td_list);
1669 }
1670 goto err_giveback;
1671 }
1672
1673 i = urb_priv->num_tds_done;
1674 if (i < urb_priv->num_tds)
1675 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1676 "Cancel URB %p, dev %s, ep 0x%x, "
1677 "starting at offset 0x%llx",
1678 urb, urb->dev->devpath,
1679 urb->ep->desc.bEndpointAddress,
1680 (unsigned long long) xhci_trb_virt_to_dma(
1681 urb_priv->td[i].start_seg,
1682 urb_priv->td[i].first_trb));
1683
1684 for (; i < urb_priv->num_tds; i++) {
1685 td = &urb_priv->td[i];
1686 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1687 }
1688
1689 /* Queue a stop endpoint command, but only if this is
1690 * the first cancellation to be handled.
1691 */
1692 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1693 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1694 if (!command) {
1695 ret = -ENOMEM;
1696 goto done;
1697 }
1698 ep->ep_state |= EP_STOP_CMD_PENDING;
1699 ep->stop_cmd_timer.expires = jiffies +
1700 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1701 add_timer(&ep->stop_cmd_timer);
1702 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1703 ep_index, 0);
1704 xhci_ring_cmd_db(xhci);
1705 }
1706done:
1707 spin_unlock_irqrestore(&xhci->lock, flags);
1708 return ret;
1709
1710err_giveback:
1711 if (urb_priv)
1712 xhci_urb_free_priv(urb_priv);
1713 usb_hcd_unlink_urb_from_ep(hcd, urb);
1714 spin_unlock_irqrestore(&xhci->lock, flags);
1715 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1716 return ret;
1717}
1718
1719/* Drop an endpoint from a new bandwidth configuration for this device.
1720 * Only one call to this function is allowed per endpoint before
1721 * check_bandwidth() or reset_bandwidth() must be called.
1722 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1723 * add the endpoint to the schedule with possibly new parameters denoted by a
1724 * different endpoint descriptor in usb_host_endpoint.
1725 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1726 * not allowed.
1727 *
1728 * The USB core will not allow URBs to be queued to an endpoint that is being
1729 * disabled, so there's no need for mutual exclusion to protect
1730 * the xhci->devs[slot_id] structure.
1731 */
1732static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1733 struct usb_host_endpoint *ep)
1734{
1735 struct xhci_hcd *xhci;
1736 struct xhci_container_ctx *in_ctx, *out_ctx;
1737 struct xhci_input_control_ctx *ctrl_ctx;
1738 unsigned int ep_index;
1739 struct xhci_ep_ctx *ep_ctx;
1740 u32 drop_flag;
1741 u32 new_add_flags, new_drop_flags;
1742 int ret;
1743
1744 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1745 if (ret <= 0)
1746 return ret;
1747 xhci = hcd_to_xhci(hcd);
1748 if (xhci->xhc_state & XHCI_STATE_DYING)
1749 return -ENODEV;
1750
1751 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1752 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1753 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1754 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1755 __func__, drop_flag);
1756 return 0;
1757 }
1758
1759 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1760 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1761 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1762 if (!ctrl_ctx) {
1763 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1764 __func__);
1765 return 0;
1766 }
1767
1768 ep_index = xhci_get_endpoint_index(&ep->desc);
1769 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1770 /* If the HC already knows the endpoint is disabled,
1771 * or the HCD has noted it is disabled, ignore this request
1772 */
1773 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1774 le32_to_cpu(ctrl_ctx->drop_flags) &
1775 xhci_get_endpoint_flag(&ep->desc)) {
1776 /* Do not warn when called after a usb_device_reset */
1777 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1778 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1779 __func__, ep);
1780 return 0;
1781 }
1782
1783 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1784 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1785
1786 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1787 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1788
1789 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1790
1791 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1792
1793 if (xhci->quirks & XHCI_MTK_HOST)
1794 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1795
1796 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1797 (unsigned int) ep->desc.bEndpointAddress,
1798 udev->slot_id,
1799 (unsigned int) new_drop_flags,
1800 (unsigned int) new_add_flags);
1801 return 0;
1802}
1803
1804/* Add an endpoint to a new possible bandwidth configuration for this device.
1805 * Only one call to this function is allowed per endpoint before
1806 * check_bandwidth() or reset_bandwidth() must be called.
1807 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1808 * add the endpoint to the schedule with possibly new parameters denoted by a
1809 * different endpoint descriptor in usb_host_endpoint.
1810 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1811 * not allowed.
1812 *
1813 * The USB core will not allow URBs to be queued to an endpoint until the
1814 * configuration or alt setting is installed in the device, so there's no need
1815 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1816 */
1817static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1818 struct usb_host_endpoint *ep)
1819{
1820 struct xhci_hcd *xhci;
1821 struct xhci_container_ctx *in_ctx;
1822 unsigned int ep_index;
1823 struct xhci_input_control_ctx *ctrl_ctx;
1824 struct xhci_ep_ctx *ep_ctx;
1825 u32 added_ctxs;
1826 u32 new_add_flags, new_drop_flags;
1827 struct xhci_virt_device *virt_dev;
1828 int ret = 0;
1829
1830 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1831 if (ret <= 0) {
1832 /* So we won't queue a reset ep command for a root hub */
1833 ep->hcpriv = NULL;
1834 return ret;
1835 }
1836 xhci = hcd_to_xhci(hcd);
1837 if (xhci->xhc_state & XHCI_STATE_DYING)
1838 return -ENODEV;
1839
1840 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1841 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1842 /* FIXME when we have to issue an evaluate endpoint command to
1843 * deal with ep0 max packet size changing once we get the
1844 * descriptors
1845 */
1846 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1847 __func__, added_ctxs);
1848 return 0;
1849 }
1850
1851 virt_dev = xhci->devs[udev->slot_id];
1852 in_ctx = virt_dev->in_ctx;
1853 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1854 if (!ctrl_ctx) {
1855 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1856 __func__);
1857 return 0;
1858 }
1859
1860 ep_index = xhci_get_endpoint_index(&ep->desc);
1861 /* If this endpoint is already in use, and the upper layers are trying
1862 * to add it again without dropping it, reject the addition.
1863 */
1864 if (virt_dev->eps[ep_index].ring &&
1865 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1866 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1867 "without dropping it.\n",
1868 (unsigned int) ep->desc.bEndpointAddress);
1869 return -EINVAL;
1870 }
1871
1872 /* If the HCD has already noted the endpoint is enabled,
1873 * ignore this request.
1874 */
1875 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1876 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1877 __func__, ep);
1878 return 0;
1879 }
1880
1881 /*
1882 * Configuration and alternate setting changes must be done in
1883 * process context, not interrupt context (or so documenation
1884 * for usb_set_interface() and usb_set_configuration() claim).
1885 */
1886 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1887 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1888 __func__, ep->desc.bEndpointAddress);
1889 return -ENOMEM;
1890 }
1891
1892 if (xhci->quirks & XHCI_MTK_HOST) {
1893 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1894 if (ret < 0) {
1895 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1896 virt_dev->eps[ep_index].new_ring = NULL;
1897 return ret;
1898 }
1899 }
1900
1901 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1902 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1903
1904 /* If xhci_endpoint_disable() was called for this endpoint, but the
1905 * xHC hasn't been notified yet through the check_bandwidth() call,
1906 * this re-adds a new state for the endpoint from the new endpoint
1907 * descriptors. We must drop and re-add this endpoint, so we leave the
1908 * drop flags alone.
1909 */
1910 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1911
1912 /* Store the usb_device pointer for later use */
1913 ep->hcpriv = udev;
1914
1915 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1916 trace_xhci_add_endpoint(ep_ctx);
1917
1918 xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index);
1919
1920 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1921 (unsigned int) ep->desc.bEndpointAddress,
1922 udev->slot_id,
1923 (unsigned int) new_drop_flags,
1924 (unsigned int) new_add_flags);
1925 return 0;
1926}
1927
1928static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1929{
1930 struct xhci_input_control_ctx *ctrl_ctx;
1931 struct xhci_ep_ctx *ep_ctx;
1932 struct xhci_slot_ctx *slot_ctx;
1933 int i;
1934
1935 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1936 if (!ctrl_ctx) {
1937 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1938 __func__);
1939 return;
1940 }
1941
1942 /* When a device's add flag and drop flag are zero, any subsequent
1943 * configure endpoint command will leave that endpoint's state
1944 * untouched. Make sure we don't leave any old state in the input
1945 * endpoint contexts.
1946 */
1947 ctrl_ctx->drop_flags = 0;
1948 ctrl_ctx->add_flags = 0;
1949 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1950 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1951 /* Endpoint 0 is always valid */
1952 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1953 for (i = 1; i < 31; i++) {
1954 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1955 ep_ctx->ep_info = 0;
1956 ep_ctx->ep_info2 = 0;
1957 ep_ctx->deq = 0;
1958 ep_ctx->tx_info = 0;
1959 }
1960}
1961
1962static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1963 struct usb_device *udev, u32 *cmd_status)
1964{
1965 int ret;
1966
1967 switch (*cmd_status) {
1968 case COMP_COMMAND_ABORTED:
1969 case COMP_COMMAND_RING_STOPPED:
1970 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1971 ret = -ETIME;
1972 break;
1973 case COMP_RESOURCE_ERROR:
1974 dev_warn(&udev->dev,
1975 "Not enough host controller resources for new device state.\n");
1976 ret = -ENOMEM;
1977 /* FIXME: can we allocate more resources for the HC? */
1978 break;
1979 case COMP_BANDWIDTH_ERROR:
1980 case COMP_SECONDARY_BANDWIDTH_ERROR:
1981 dev_warn(&udev->dev,
1982 "Not enough bandwidth for new device state.\n");
1983 ret = -ENOSPC;
1984 /* FIXME: can we go back to the old state? */
1985 break;
1986 case COMP_TRB_ERROR:
1987 /* the HCD set up something wrong */
1988 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1989 "add flag = 1, "
1990 "and endpoint is not disabled.\n");
1991 ret = -EINVAL;
1992 break;
1993 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1994 dev_warn(&udev->dev,
1995 "ERROR: Incompatible device for endpoint configure command.\n");
1996 ret = -ENODEV;
1997 break;
1998 case COMP_SUCCESS:
1999 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2000 "Successful Endpoint Configure command");
2001 ret = 0;
2002 break;
2003 default:
2004 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2005 *cmd_status);
2006 ret = -EINVAL;
2007 break;
2008 }
2009 return ret;
2010}
2011
2012static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2013 struct usb_device *udev, u32 *cmd_status)
2014{
2015 int ret;
2016
2017 switch (*cmd_status) {
2018 case COMP_COMMAND_ABORTED:
2019 case COMP_COMMAND_RING_STOPPED:
2020 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2021 ret = -ETIME;
2022 break;
2023 case COMP_PARAMETER_ERROR:
2024 dev_warn(&udev->dev,
2025 "WARN: xHCI driver setup invalid evaluate context command.\n");
2026 ret = -EINVAL;
2027 break;
2028 case COMP_SLOT_NOT_ENABLED_ERROR:
2029 dev_warn(&udev->dev,
2030 "WARN: slot not enabled for evaluate context command.\n");
2031 ret = -EINVAL;
2032 break;
2033 case COMP_CONTEXT_STATE_ERROR:
2034 dev_warn(&udev->dev,
2035 "WARN: invalid context state for evaluate context command.\n");
2036 ret = -EINVAL;
2037 break;
2038 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2039 dev_warn(&udev->dev,
2040 "ERROR: Incompatible device for evaluate context command.\n");
2041 ret = -ENODEV;
2042 break;
2043 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2044 /* Max Exit Latency too large error */
2045 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2046 ret = -EINVAL;
2047 break;
2048 case COMP_SUCCESS:
2049 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2050 "Successful evaluate context command");
2051 ret = 0;
2052 break;
2053 default:
2054 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2055 *cmd_status);
2056 ret = -EINVAL;
2057 break;
2058 }
2059 return ret;
2060}
2061
2062static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2063 struct xhci_input_control_ctx *ctrl_ctx)
2064{
2065 u32 valid_add_flags;
2066 u32 valid_drop_flags;
2067
2068 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2069 * (bit 1). The default control endpoint is added during the Address
2070 * Device command and is never removed until the slot is disabled.
2071 */
2072 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2073 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2074
2075 /* Use hweight32 to count the number of ones in the add flags, or
2076 * number of endpoints added. Don't count endpoints that are changed
2077 * (both added and dropped).
2078 */
2079 return hweight32(valid_add_flags) -
2080 hweight32(valid_add_flags & valid_drop_flags);
2081}
2082
2083static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2084 struct xhci_input_control_ctx *ctrl_ctx)
2085{
2086 u32 valid_add_flags;
2087 u32 valid_drop_flags;
2088
2089 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2090 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2091
2092 return hweight32(valid_drop_flags) -
2093 hweight32(valid_add_flags & valid_drop_flags);
2094}
2095
2096/*
2097 * We need to reserve the new number of endpoints before the configure endpoint
2098 * command completes. We can't subtract the dropped endpoints from the number
2099 * of active endpoints until the command completes because we can oversubscribe
2100 * the host in this case:
2101 *
2102 * - the first configure endpoint command drops more endpoints than it adds
2103 * - a second configure endpoint command that adds more endpoints is queued
2104 * - the first configure endpoint command fails, so the config is unchanged
2105 * - the second command may succeed, even though there isn't enough resources
2106 *
2107 * Must be called with xhci->lock held.
2108 */
2109static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2110 struct xhci_input_control_ctx *ctrl_ctx)
2111{
2112 u32 added_eps;
2113
2114 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2115 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2116 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2117 "Not enough ep ctxs: "
2118 "%u active, need to add %u, limit is %u.",
2119 xhci->num_active_eps, added_eps,
2120 xhci->limit_active_eps);
2121 return -ENOMEM;
2122 }
2123 xhci->num_active_eps += added_eps;
2124 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2125 "Adding %u ep ctxs, %u now active.", added_eps,
2126 xhci->num_active_eps);
2127 return 0;
2128}
2129
2130/*
2131 * The configure endpoint was failed by the xHC for some other reason, so we
2132 * need to revert the resources that failed configuration would have used.
2133 *
2134 * Must be called with xhci->lock held.
2135 */
2136static void xhci_free_host_resources(struct xhci_hcd *xhci,
2137 struct xhci_input_control_ctx *ctrl_ctx)
2138{
2139 u32 num_failed_eps;
2140
2141 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2142 xhci->num_active_eps -= num_failed_eps;
2143 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2144 "Removing %u failed ep ctxs, %u now active.",
2145 num_failed_eps,
2146 xhci->num_active_eps);
2147}
2148
2149/*
2150 * Now that the command has completed, clean up the active endpoint count by
2151 * subtracting out the endpoints that were dropped (but not changed).
2152 *
2153 * Must be called with xhci->lock held.
2154 */
2155static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2156 struct xhci_input_control_ctx *ctrl_ctx)
2157{
2158 u32 num_dropped_eps;
2159
2160 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2161 xhci->num_active_eps -= num_dropped_eps;
2162 if (num_dropped_eps)
2163 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2164 "Removing %u dropped ep ctxs, %u now active.",
2165 num_dropped_eps,
2166 xhci->num_active_eps);
2167}
2168
2169static unsigned int xhci_get_block_size(struct usb_device *udev)
2170{
2171 switch (udev->speed) {
2172 case USB_SPEED_LOW:
2173 case USB_SPEED_FULL:
2174 return FS_BLOCK;
2175 case USB_SPEED_HIGH:
2176 return HS_BLOCK;
2177 case USB_SPEED_SUPER:
2178 case USB_SPEED_SUPER_PLUS:
2179 return SS_BLOCK;
2180 case USB_SPEED_UNKNOWN:
2181 case USB_SPEED_WIRELESS:
2182 default:
2183 /* Should never happen */
2184 return 1;
2185 }
2186}
2187
2188static unsigned int
2189xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2190{
2191 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2192 return LS_OVERHEAD;
2193 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2194 return FS_OVERHEAD;
2195 return HS_OVERHEAD;
2196}
2197
2198/* If we are changing a LS/FS device under a HS hub,
2199 * make sure (if we are activating a new TT) that the HS bus has enough
2200 * bandwidth for this new TT.
2201 */
2202static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2203 struct xhci_virt_device *virt_dev,
2204 int old_active_eps)
2205{
2206 struct xhci_interval_bw_table *bw_table;
2207 struct xhci_tt_bw_info *tt_info;
2208
2209 /* Find the bandwidth table for the root port this TT is attached to. */
2210 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2211 tt_info = virt_dev->tt_info;
2212 /* If this TT already had active endpoints, the bandwidth for this TT
2213 * has already been added. Removing all periodic endpoints (and thus
2214 * making the TT enactive) will only decrease the bandwidth used.
2215 */
2216 if (old_active_eps)
2217 return 0;
2218 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2219 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2220 return -ENOMEM;
2221 return 0;
2222 }
2223 /* Not sure why we would have no new active endpoints...
2224 *
2225 * Maybe because of an Evaluate Context change for a hub update or a
2226 * control endpoint 0 max packet size change?
2227 * FIXME: skip the bandwidth calculation in that case.
2228 */
2229 return 0;
2230}
2231
2232static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2233 struct xhci_virt_device *virt_dev)
2234{
2235 unsigned int bw_reserved;
2236
2237 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2238 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2239 return -ENOMEM;
2240
2241 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2242 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2243 return -ENOMEM;
2244
2245 return 0;
2246}
2247
2248/*
2249 * This algorithm is a very conservative estimate of the worst-case scheduling
2250 * scenario for any one interval. The hardware dynamically schedules the
2251 * packets, so we can't tell which microframe could be the limiting factor in
2252 * the bandwidth scheduling. This only takes into account periodic endpoints.
2253 *
2254 * Obviously, we can't solve an NP complete problem to find the minimum worst
2255 * case scenario. Instead, we come up with an estimate that is no less than
2256 * the worst case bandwidth used for any one microframe, but may be an
2257 * over-estimate.
2258 *
2259 * We walk the requirements for each endpoint by interval, starting with the
2260 * smallest interval, and place packets in the schedule where there is only one
2261 * possible way to schedule packets for that interval. In order to simplify
2262 * this algorithm, we record the largest max packet size for each interval, and
2263 * assume all packets will be that size.
2264 *
2265 * For interval 0, we obviously must schedule all packets for each interval.
2266 * The bandwidth for interval 0 is just the amount of data to be transmitted
2267 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2268 * the number of packets).
2269 *
2270 * For interval 1, we have two possible microframes to schedule those packets
2271 * in. For this algorithm, if we can schedule the same number of packets for
2272 * each possible scheduling opportunity (each microframe), we will do so. The
2273 * remaining number of packets will be saved to be transmitted in the gaps in
2274 * the next interval's scheduling sequence.
2275 *
2276 * As we move those remaining packets to be scheduled with interval 2 packets,
2277 * we have to double the number of remaining packets to transmit. This is
2278 * because the intervals are actually powers of 2, and we would be transmitting
2279 * the previous interval's packets twice in this interval. We also have to be
2280 * sure that when we look at the largest max packet size for this interval, we
2281 * also look at the largest max packet size for the remaining packets and take
2282 * the greater of the two.
2283 *
2284 * The algorithm continues to evenly distribute packets in each scheduling
2285 * opportunity, and push the remaining packets out, until we get to the last
2286 * interval. Then those packets and their associated overhead are just added
2287 * to the bandwidth used.
2288 */
2289static int xhci_check_bw_table(struct xhci_hcd *xhci,
2290 struct xhci_virt_device *virt_dev,
2291 int old_active_eps)
2292{
2293 unsigned int bw_reserved;
2294 unsigned int max_bandwidth;
2295 unsigned int bw_used;
2296 unsigned int block_size;
2297 struct xhci_interval_bw_table *bw_table;
2298 unsigned int packet_size = 0;
2299 unsigned int overhead = 0;
2300 unsigned int packets_transmitted = 0;
2301 unsigned int packets_remaining = 0;
2302 unsigned int i;
2303
2304 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2305 return xhci_check_ss_bw(xhci, virt_dev);
2306
2307 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2308 max_bandwidth = HS_BW_LIMIT;
2309 /* Convert percent of bus BW reserved to blocks reserved */
2310 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2311 } else {
2312 max_bandwidth = FS_BW_LIMIT;
2313 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2314 }
2315
2316 bw_table = virt_dev->bw_table;
2317 /* We need to translate the max packet size and max ESIT payloads into
2318 * the units the hardware uses.
2319 */
2320 block_size = xhci_get_block_size(virt_dev->udev);
2321
2322 /* If we are manipulating a LS/FS device under a HS hub, double check
2323 * that the HS bus has enough bandwidth if we are activing a new TT.
2324 */
2325 if (virt_dev->tt_info) {
2326 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2327 "Recalculating BW for rootport %u",
2328 virt_dev->real_port);
2329 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2330 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2331 "newly activated TT.\n");
2332 return -ENOMEM;
2333 }
2334 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2335 "Recalculating BW for TT slot %u port %u",
2336 virt_dev->tt_info->slot_id,
2337 virt_dev->tt_info->ttport);
2338 } else {
2339 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2340 "Recalculating BW for rootport %u",
2341 virt_dev->real_port);
2342 }
2343
2344 /* Add in how much bandwidth will be used for interval zero, or the
2345 * rounded max ESIT payload + number of packets * largest overhead.
2346 */
2347 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2348 bw_table->interval_bw[0].num_packets *
2349 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2350
2351 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2352 unsigned int bw_added;
2353 unsigned int largest_mps;
2354 unsigned int interval_overhead;
2355
2356 /*
2357 * How many packets could we transmit in this interval?
2358 * If packets didn't fit in the previous interval, we will need
2359 * to transmit that many packets twice within this interval.
2360 */
2361 packets_remaining = 2 * packets_remaining +
2362 bw_table->interval_bw[i].num_packets;
2363
2364 /* Find the largest max packet size of this or the previous
2365 * interval.
2366 */
2367 if (list_empty(&bw_table->interval_bw[i].endpoints))
2368 largest_mps = 0;
2369 else {
2370 struct xhci_virt_ep *virt_ep;
2371 struct list_head *ep_entry;
2372
2373 ep_entry = bw_table->interval_bw[i].endpoints.next;
2374 virt_ep = list_entry(ep_entry,
2375 struct xhci_virt_ep, bw_endpoint_list);
2376 /* Convert to blocks, rounding up */
2377 largest_mps = DIV_ROUND_UP(
2378 virt_ep->bw_info.max_packet_size,
2379 block_size);
2380 }
2381 if (largest_mps > packet_size)
2382 packet_size = largest_mps;
2383
2384 /* Use the larger overhead of this or the previous interval. */
2385 interval_overhead = xhci_get_largest_overhead(
2386 &bw_table->interval_bw[i]);
2387 if (interval_overhead > overhead)
2388 overhead = interval_overhead;
2389
2390 /* How many packets can we evenly distribute across
2391 * (1 << (i + 1)) possible scheduling opportunities?
2392 */
2393 packets_transmitted = packets_remaining >> (i + 1);
2394
2395 /* Add in the bandwidth used for those scheduled packets */
2396 bw_added = packets_transmitted * (overhead + packet_size);
2397
2398 /* How many packets do we have remaining to transmit? */
2399 packets_remaining = packets_remaining % (1 << (i + 1));
2400
2401 /* What largest max packet size should those packets have? */
2402 /* If we've transmitted all packets, don't carry over the
2403 * largest packet size.
2404 */
2405 if (packets_remaining == 0) {
2406 packet_size = 0;
2407 overhead = 0;
2408 } else if (packets_transmitted > 0) {
2409 /* Otherwise if we do have remaining packets, and we've
2410 * scheduled some packets in this interval, take the
2411 * largest max packet size from endpoints with this
2412 * interval.
2413 */
2414 packet_size = largest_mps;
2415 overhead = interval_overhead;
2416 }
2417 /* Otherwise carry over packet_size and overhead from the last
2418 * time we had a remainder.
2419 */
2420 bw_used += bw_added;
2421 if (bw_used > max_bandwidth) {
2422 xhci_warn(xhci, "Not enough bandwidth. "
2423 "Proposed: %u, Max: %u\n",
2424 bw_used, max_bandwidth);
2425 return -ENOMEM;
2426 }
2427 }
2428 /*
2429 * Ok, we know we have some packets left over after even-handedly
2430 * scheduling interval 15. We don't know which microframes they will
2431 * fit into, so we over-schedule and say they will be scheduled every
2432 * microframe.
2433 */
2434 if (packets_remaining > 0)
2435 bw_used += overhead + packet_size;
2436
2437 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2438 unsigned int port_index = virt_dev->real_port - 1;
2439
2440 /* OK, we're manipulating a HS device attached to a
2441 * root port bandwidth domain. Include the number of active TTs
2442 * in the bandwidth used.
2443 */
2444 bw_used += TT_HS_OVERHEAD *
2445 xhci->rh_bw[port_index].num_active_tts;
2446 }
2447
2448 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2449 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2450 "Available: %u " "percent",
2451 bw_used, max_bandwidth, bw_reserved,
2452 (max_bandwidth - bw_used - bw_reserved) * 100 /
2453 max_bandwidth);
2454
2455 bw_used += bw_reserved;
2456 if (bw_used > max_bandwidth) {
2457 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2458 bw_used, max_bandwidth);
2459 return -ENOMEM;
2460 }
2461
2462 bw_table->bw_used = bw_used;
2463 return 0;
2464}
2465
2466static bool xhci_is_async_ep(unsigned int ep_type)
2467{
2468 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2469 ep_type != ISOC_IN_EP &&
2470 ep_type != INT_IN_EP);
2471}
2472
2473static bool xhci_is_sync_in_ep(unsigned int ep_type)
2474{
2475 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2476}
2477
2478static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2479{
2480 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2481
2482 if (ep_bw->ep_interval == 0)
2483 return SS_OVERHEAD_BURST +
2484 (ep_bw->mult * ep_bw->num_packets *
2485 (SS_OVERHEAD + mps));
2486 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2487 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2488 1 << ep_bw->ep_interval);
2489
2490}
2491
2492static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2493 struct xhci_bw_info *ep_bw,
2494 struct xhci_interval_bw_table *bw_table,
2495 struct usb_device *udev,
2496 struct xhci_virt_ep *virt_ep,
2497 struct xhci_tt_bw_info *tt_info)
2498{
2499 struct xhci_interval_bw *interval_bw;
2500 int normalized_interval;
2501
2502 if (xhci_is_async_ep(ep_bw->type))
2503 return;
2504
2505 if (udev->speed >= USB_SPEED_SUPER) {
2506 if (xhci_is_sync_in_ep(ep_bw->type))
2507 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2508 xhci_get_ss_bw_consumed(ep_bw);
2509 else
2510 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2511 xhci_get_ss_bw_consumed(ep_bw);
2512 return;
2513 }
2514
2515 /* SuperSpeed endpoints never get added to intervals in the table, so
2516 * this check is only valid for HS/FS/LS devices.
2517 */
2518 if (list_empty(&virt_ep->bw_endpoint_list))
2519 return;
2520 /* For LS/FS devices, we need to translate the interval expressed in
2521 * microframes to frames.
2522 */
2523 if (udev->speed == USB_SPEED_HIGH)
2524 normalized_interval = ep_bw->ep_interval;
2525 else
2526 normalized_interval = ep_bw->ep_interval - 3;
2527
2528 if (normalized_interval == 0)
2529 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2530 interval_bw = &bw_table->interval_bw[normalized_interval];
2531 interval_bw->num_packets -= ep_bw->num_packets;
2532 switch (udev->speed) {
2533 case USB_SPEED_LOW:
2534 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2535 break;
2536 case USB_SPEED_FULL:
2537 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2538 break;
2539 case USB_SPEED_HIGH:
2540 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2541 break;
2542 case USB_SPEED_SUPER:
2543 case USB_SPEED_SUPER_PLUS:
2544 case USB_SPEED_UNKNOWN:
2545 case USB_SPEED_WIRELESS:
2546 /* Should never happen because only LS/FS/HS endpoints will get
2547 * added to the endpoint list.
2548 */
2549 return;
2550 }
2551 if (tt_info)
2552 tt_info->active_eps -= 1;
2553 list_del_init(&virt_ep->bw_endpoint_list);
2554}
2555
2556static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2557 struct xhci_bw_info *ep_bw,
2558 struct xhci_interval_bw_table *bw_table,
2559 struct usb_device *udev,
2560 struct xhci_virt_ep *virt_ep,
2561 struct xhci_tt_bw_info *tt_info)
2562{
2563 struct xhci_interval_bw *interval_bw;
2564 struct xhci_virt_ep *smaller_ep;
2565 int normalized_interval;
2566
2567 if (xhci_is_async_ep(ep_bw->type))
2568 return;
2569
2570 if (udev->speed == USB_SPEED_SUPER) {
2571 if (xhci_is_sync_in_ep(ep_bw->type))
2572 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2573 xhci_get_ss_bw_consumed(ep_bw);
2574 else
2575 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2576 xhci_get_ss_bw_consumed(ep_bw);
2577 return;
2578 }
2579
2580 /* For LS/FS devices, we need to translate the interval expressed in
2581 * microframes to frames.
2582 */
2583 if (udev->speed == USB_SPEED_HIGH)
2584 normalized_interval = ep_bw->ep_interval;
2585 else
2586 normalized_interval = ep_bw->ep_interval - 3;
2587
2588 if (normalized_interval == 0)
2589 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2590 interval_bw = &bw_table->interval_bw[normalized_interval];
2591 interval_bw->num_packets += ep_bw->num_packets;
2592 switch (udev->speed) {
2593 case USB_SPEED_LOW:
2594 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2595 break;
2596 case USB_SPEED_FULL:
2597 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2598 break;
2599 case USB_SPEED_HIGH:
2600 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2601 break;
2602 case USB_SPEED_SUPER:
2603 case USB_SPEED_SUPER_PLUS:
2604 case USB_SPEED_UNKNOWN:
2605 case USB_SPEED_WIRELESS:
2606 /* Should never happen because only LS/FS/HS endpoints will get
2607 * added to the endpoint list.
2608 */
2609 return;
2610 }
2611
2612 if (tt_info)
2613 tt_info->active_eps += 1;
2614 /* Insert the endpoint into the list, largest max packet size first. */
2615 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2616 bw_endpoint_list) {
2617 if (ep_bw->max_packet_size >=
2618 smaller_ep->bw_info.max_packet_size) {
2619 /* Add the new ep before the smaller endpoint */
2620 list_add_tail(&virt_ep->bw_endpoint_list,
2621 &smaller_ep->bw_endpoint_list);
2622 return;
2623 }
2624 }
2625 /* Add the new endpoint at the end of the list. */
2626 list_add_tail(&virt_ep->bw_endpoint_list,
2627 &interval_bw->endpoints);
2628}
2629
2630void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2631 struct xhci_virt_device *virt_dev,
2632 int old_active_eps)
2633{
2634 struct xhci_root_port_bw_info *rh_bw_info;
2635 if (!virt_dev->tt_info)
2636 return;
2637
2638 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2639 if (old_active_eps == 0 &&
2640 virt_dev->tt_info->active_eps != 0) {
2641 rh_bw_info->num_active_tts += 1;
2642 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2643 } else if (old_active_eps != 0 &&
2644 virt_dev->tt_info->active_eps == 0) {
2645 rh_bw_info->num_active_tts -= 1;
2646 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2647 }
2648}
2649
2650static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2651 struct xhci_virt_device *virt_dev,
2652 struct xhci_container_ctx *in_ctx)
2653{
2654 struct xhci_bw_info ep_bw_info[31];
2655 int i;
2656 struct xhci_input_control_ctx *ctrl_ctx;
2657 int old_active_eps = 0;
2658
2659 if (virt_dev->tt_info)
2660 old_active_eps = virt_dev->tt_info->active_eps;
2661
2662 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2663 if (!ctrl_ctx) {
2664 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2665 __func__);
2666 return -ENOMEM;
2667 }
2668
2669 for (i = 0; i < 31; i++) {
2670 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2671 continue;
2672
2673 /* Make a copy of the BW info in case we need to revert this */
2674 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2675 sizeof(ep_bw_info[i]));
2676 /* Drop the endpoint from the interval table if the endpoint is
2677 * being dropped or changed.
2678 */
2679 if (EP_IS_DROPPED(ctrl_ctx, i))
2680 xhci_drop_ep_from_interval_table(xhci,
2681 &virt_dev->eps[i].bw_info,
2682 virt_dev->bw_table,
2683 virt_dev->udev,
2684 &virt_dev->eps[i],
2685 virt_dev->tt_info);
2686 }
2687 /* Overwrite the information stored in the endpoints' bw_info */
2688 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2689 for (i = 0; i < 31; i++) {
2690 /* Add any changed or added endpoints to the interval table */
2691 if (EP_IS_ADDED(ctrl_ctx, i))
2692 xhci_add_ep_to_interval_table(xhci,
2693 &virt_dev->eps[i].bw_info,
2694 virt_dev->bw_table,
2695 virt_dev->udev,
2696 &virt_dev->eps[i],
2697 virt_dev->tt_info);
2698 }
2699
2700 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2701 /* Ok, this fits in the bandwidth we have.
2702 * Update the number of active TTs.
2703 */
2704 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2705 return 0;
2706 }
2707
2708 /* We don't have enough bandwidth for this, revert the stored info. */
2709 for (i = 0; i < 31; i++) {
2710 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2711 continue;
2712
2713 /* Drop the new copies of any added or changed endpoints from
2714 * the interval table.
2715 */
2716 if (EP_IS_ADDED(ctrl_ctx, i)) {
2717 xhci_drop_ep_from_interval_table(xhci,
2718 &virt_dev->eps[i].bw_info,
2719 virt_dev->bw_table,
2720 virt_dev->udev,
2721 &virt_dev->eps[i],
2722 virt_dev->tt_info);
2723 }
2724 /* Revert the endpoint back to its old information */
2725 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2726 sizeof(ep_bw_info[i]));
2727 /* Add any changed or dropped endpoints back into the table */
2728 if (EP_IS_DROPPED(ctrl_ctx, i))
2729 xhci_add_ep_to_interval_table(xhci,
2730 &virt_dev->eps[i].bw_info,
2731 virt_dev->bw_table,
2732 virt_dev->udev,
2733 &virt_dev->eps[i],
2734 virt_dev->tt_info);
2735 }
2736 return -ENOMEM;
2737}
2738
2739
2740/* Issue a configure endpoint command or evaluate context command
2741 * and wait for it to finish.
2742 */
2743static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2744 struct usb_device *udev,
2745 struct xhci_command *command,
2746 bool ctx_change, bool must_succeed)
2747{
2748 int ret;
2749 unsigned long flags;
2750 struct xhci_input_control_ctx *ctrl_ctx;
2751 struct xhci_virt_device *virt_dev;
2752 struct xhci_slot_ctx *slot_ctx;
2753
2754 if (!command)
2755 return -EINVAL;
2756
2757 spin_lock_irqsave(&xhci->lock, flags);
2758
2759 if (xhci->xhc_state & XHCI_STATE_DYING) {
2760 spin_unlock_irqrestore(&xhci->lock, flags);
2761 return -ESHUTDOWN;
2762 }
2763
2764 virt_dev = xhci->devs[udev->slot_id];
2765
2766 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2767 if (!ctrl_ctx) {
2768 spin_unlock_irqrestore(&xhci->lock, flags);
2769 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2770 __func__);
2771 return -ENOMEM;
2772 }
2773
2774 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2775 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2776 spin_unlock_irqrestore(&xhci->lock, flags);
2777 xhci_warn(xhci, "Not enough host resources, "
2778 "active endpoint contexts = %u\n",
2779 xhci->num_active_eps);
2780 return -ENOMEM;
2781 }
2782 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2783 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2784 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2785 xhci_free_host_resources(xhci, ctrl_ctx);
2786 spin_unlock_irqrestore(&xhci->lock, flags);
2787 xhci_warn(xhci, "Not enough bandwidth\n");
2788 return -ENOMEM;
2789 }
2790
2791 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2792
2793 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2794 trace_xhci_configure_endpoint(slot_ctx);
2795
2796 if (!ctx_change)
2797 ret = xhci_queue_configure_endpoint(xhci, command,
2798 command->in_ctx->dma,
2799 udev->slot_id, must_succeed);
2800 else
2801 ret = xhci_queue_evaluate_context(xhci, command,
2802 command->in_ctx->dma,
2803 udev->slot_id, must_succeed);
2804 if (ret < 0) {
2805 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2806 xhci_free_host_resources(xhci, ctrl_ctx);
2807 spin_unlock_irqrestore(&xhci->lock, flags);
2808 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2809 "FIXME allocate a new ring segment");
2810 return -ENOMEM;
2811 }
2812 xhci_ring_cmd_db(xhci);
2813 spin_unlock_irqrestore(&xhci->lock, flags);
2814
2815 /* Wait for the configure endpoint command to complete */
2816 wait_for_completion(command->completion);
2817
2818 if (!ctx_change)
2819 ret = xhci_configure_endpoint_result(xhci, udev,
2820 &command->status);
2821 else
2822 ret = xhci_evaluate_context_result(xhci, udev,
2823 &command->status);
2824
2825 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2826 spin_lock_irqsave(&xhci->lock, flags);
2827 /* If the command failed, remove the reserved resources.
2828 * Otherwise, clean up the estimate to include dropped eps.
2829 */
2830 if (ret)
2831 xhci_free_host_resources(xhci, ctrl_ctx);
2832 else
2833 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2834 spin_unlock_irqrestore(&xhci->lock, flags);
2835 }
2836 return ret;
2837}
2838
2839static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2840 struct xhci_virt_device *vdev, int i)
2841{
2842 struct xhci_virt_ep *ep = &vdev->eps[i];
2843
2844 if (ep->ep_state & EP_HAS_STREAMS) {
2845 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2846 xhci_get_endpoint_address(i));
2847 xhci_free_stream_info(xhci, ep->stream_info);
2848 ep->stream_info = NULL;
2849 ep->ep_state &= ~EP_HAS_STREAMS;
2850 }
2851}
2852
2853/* Called after one or more calls to xhci_add_endpoint() or
2854 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2855 * to call xhci_reset_bandwidth().
2856 *
2857 * Since we are in the middle of changing either configuration or
2858 * installing a new alt setting, the USB core won't allow URBs to be
2859 * enqueued for any endpoint on the old config or interface. Nothing
2860 * else should be touching the xhci->devs[slot_id] structure, so we
2861 * don't need to take the xhci->lock for manipulating that.
2862 */
2863static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2864{
2865 int i;
2866 int ret = 0;
2867 struct xhci_hcd *xhci;
2868 struct xhci_virt_device *virt_dev;
2869 struct xhci_input_control_ctx *ctrl_ctx;
2870 struct xhci_slot_ctx *slot_ctx;
2871 struct xhci_command *command;
2872
2873 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2874 if (ret <= 0)
2875 return ret;
2876 xhci = hcd_to_xhci(hcd);
2877 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2878 (xhci->xhc_state & XHCI_STATE_REMOVING))
2879 return -ENODEV;
2880
2881 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2882 virt_dev = xhci->devs[udev->slot_id];
2883
2884 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2885 if (!command)
2886 return -ENOMEM;
2887
2888 command->in_ctx = virt_dev->in_ctx;
2889
2890 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2891 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2892 if (!ctrl_ctx) {
2893 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2894 __func__);
2895 ret = -ENOMEM;
2896 goto command_cleanup;
2897 }
2898 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2899 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2900 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2901
2902 /* Don't issue the command if there's no endpoints to update. */
2903 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2904 ctrl_ctx->drop_flags == 0) {
2905 ret = 0;
2906 goto command_cleanup;
2907 }
2908 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2909 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2910 for (i = 31; i >= 1; i--) {
2911 __le32 le32 = cpu_to_le32(BIT(i));
2912
2913 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2914 || (ctrl_ctx->add_flags & le32) || i == 1) {
2915 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2916 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2917 break;
2918 }
2919 }
2920
2921 ret = xhci_configure_endpoint(xhci, udev, command,
2922 false, false);
2923 if (ret)
2924 /* Callee should call reset_bandwidth() */
2925 goto command_cleanup;
2926
2927 /* Free any rings that were dropped, but not changed. */
2928 for (i = 1; i < 31; i++) {
2929 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2930 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2931 xhci_free_endpoint_ring(xhci, virt_dev, i);
2932 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2933 }
2934 }
2935 xhci_zero_in_ctx(xhci, virt_dev);
2936 /*
2937 * Install any rings for completely new endpoints or changed endpoints,
2938 * and free any old rings from changed endpoints.
2939 */
2940 for (i = 1; i < 31; i++) {
2941 if (!virt_dev->eps[i].new_ring)
2942 continue;
2943 /* Only free the old ring if it exists.
2944 * It may not if this is the first add of an endpoint.
2945 */
2946 if (virt_dev->eps[i].ring) {
2947 xhci_free_endpoint_ring(xhci, virt_dev, i);
2948 }
2949 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2950 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2951 virt_dev->eps[i].new_ring = NULL;
2952 }
2953command_cleanup:
2954 kfree(command->completion);
2955 kfree(command);
2956
2957 return ret;
2958}
2959
2960static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2961{
2962 struct xhci_hcd *xhci;
2963 struct xhci_virt_device *virt_dev;
2964 int i, ret;
2965
2966 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2967 if (ret <= 0)
2968 return;
2969 xhci = hcd_to_xhci(hcd);
2970
2971 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2972 virt_dev = xhci->devs[udev->slot_id];
2973 /* Free any rings allocated for added endpoints */
2974 for (i = 0; i < 31; i++) {
2975 if (virt_dev->eps[i].new_ring) {
2976 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
2977 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2978 virt_dev->eps[i].new_ring = NULL;
2979 }
2980 }
2981 xhci_zero_in_ctx(xhci, virt_dev);
2982}
2983
2984static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2985 struct xhci_container_ctx *in_ctx,
2986 struct xhci_container_ctx *out_ctx,
2987 struct xhci_input_control_ctx *ctrl_ctx,
2988 u32 add_flags, u32 drop_flags)
2989{
2990 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2991 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2992 xhci_slot_copy(xhci, in_ctx, out_ctx);
2993 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2994}
2995
2996static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2997 unsigned int slot_id, unsigned int ep_index,
2998 struct xhci_dequeue_state *deq_state)
2999{
3000 struct xhci_input_control_ctx *ctrl_ctx;
3001 struct xhci_container_ctx *in_ctx;
3002 struct xhci_ep_ctx *ep_ctx;
3003 u32 added_ctxs;
3004 dma_addr_t addr;
3005
3006 in_ctx = xhci->devs[slot_id]->in_ctx;
3007 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
3008 if (!ctrl_ctx) {
3009 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3010 __func__);
3011 return;
3012 }
3013
3014 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
3015 xhci->devs[slot_id]->out_ctx, ep_index);
3016 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
3017 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3018 deq_state->new_deq_ptr);
3019 if (addr == 0) {
3020 xhci_warn(xhci, "WARN Cannot submit config ep after "
3021 "reset ep command\n");
3022 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
3023 deq_state->new_deq_seg,
3024 deq_state->new_deq_ptr);
3025 return;
3026 }
3027 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
3028
3029 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
3030 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
3031 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
3032 added_ctxs, added_ctxs);
3033}
3034
3035void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
3036 unsigned int stream_id, struct xhci_td *td)
3037{
3038 struct xhci_dequeue_state deq_state;
3039 struct usb_device *udev = td->urb->dev;
3040
3041 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3042 "Cleaning up stalled endpoint ring");
3043 /* We need to move the HW's dequeue pointer past this TD,
3044 * or it will attempt to resend it on the next doorbell ring.
3045 */
3046 xhci_find_new_dequeue_state(xhci, udev->slot_id,
3047 ep_index, stream_id, td, &deq_state);
3048
3049 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
3050 return;
3051
3052 /* HW with the reset endpoint quirk will use the saved dequeue state to
3053 * issue a configure endpoint command later.
3054 */
3055 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
3056 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3057 "Queueing new dequeue state");
3058 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
3059 ep_index, &deq_state);
3060 } else {
3061 /* Better hope no one uses the input context between now and the
3062 * reset endpoint completion!
3063 * XXX: No idea how this hardware will react when stream rings
3064 * are enabled.
3065 */
3066 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3067 "Setting up input context for "
3068 "configure endpoint command");
3069 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
3070 ep_index, &deq_state);
3071 }
3072}
3073
3074static void xhci_endpoint_disable(struct usb_hcd *hcd,
3075 struct usb_host_endpoint *host_ep)
3076{
3077 struct xhci_hcd *xhci;
3078 struct xhci_virt_device *vdev;
3079 struct xhci_virt_ep *ep;
3080 struct usb_device *udev;
3081 unsigned long flags;
3082 unsigned int ep_index;
3083
3084 xhci = hcd_to_xhci(hcd);
3085rescan:
3086 spin_lock_irqsave(&xhci->lock, flags);
3087
3088 udev = (struct usb_device *)host_ep->hcpriv;
3089 if (!udev || !udev->slot_id)
3090 goto done;
3091
3092 vdev = xhci->devs[udev->slot_id];
3093 if (!vdev)
3094 goto done;
3095
3096 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3097 ep = &vdev->eps[ep_index];
3098 if (!ep)
3099 goto done;
3100
3101 /* wait for hub_tt_work to finish clearing hub TT */
3102 if (ep->ep_state & EP_CLEARING_TT) {
3103 spin_unlock_irqrestore(&xhci->lock, flags);
3104 schedule_timeout_uninterruptible(1);
3105 goto rescan;
3106 }
3107
3108 if (ep->ep_state)
3109 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3110 ep->ep_state);
3111done:
3112 host_ep->hcpriv = NULL;
3113 spin_unlock_irqrestore(&xhci->lock, flags);
3114}
3115
3116/*
3117 * Called after usb core issues a clear halt control message.
3118 * The host side of the halt should already be cleared by a reset endpoint
3119 * command issued when the STALL event was received.
3120 *
3121 * The reset endpoint command may only be issued to endpoints in the halted
3122 * state. For software that wishes to reset the data toggle or sequence number
3123 * of an endpoint that isn't in the halted state this function will issue a
3124 * configure endpoint command with the Drop and Add bits set for the target
3125 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3126 */
3127
3128static void xhci_endpoint_reset(struct usb_hcd *hcd,
3129 struct usb_host_endpoint *host_ep)
3130{
3131 struct xhci_hcd *xhci;
3132 struct usb_device *udev;
3133 struct xhci_virt_device *vdev;
3134 struct xhci_virt_ep *ep;
3135 struct xhci_input_control_ctx *ctrl_ctx;
3136 struct xhci_command *stop_cmd, *cfg_cmd;
3137 unsigned int ep_index;
3138 unsigned long flags;
3139 u32 ep_flag;
3140 int err;
3141
3142 xhci = hcd_to_xhci(hcd);
3143 if (!host_ep->hcpriv)
3144 return;
3145 udev = (struct usb_device *) host_ep->hcpriv;
3146 vdev = xhci->devs[udev->slot_id];
3147
3148 /*
3149 * vdev may be lost due to xHC restore error and re-initialization
3150 * during S3/S4 resume. A new vdev will be allocated later by
3151 * xhci_discover_or_reset_device()
3152 */
3153 if (!udev->slot_id || !vdev)
3154 return;
3155 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3156 ep = &vdev->eps[ep_index];
3157 if (!ep)
3158 return;
3159
3160 /* Bail out if toggle is already being cleared by a endpoint reset */
3161 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3162 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3163 return;
3164 }
3165 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3166 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3167 usb_endpoint_xfer_isoc(&host_ep->desc))
3168 return;
3169
3170 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3171
3172 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3173 return;
3174
3175 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3176 if (!stop_cmd)
3177 return;
3178
3179 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3180 if (!cfg_cmd)
3181 goto cleanup;
3182
3183 spin_lock_irqsave(&xhci->lock, flags);
3184
3185 /* block queuing new trbs and ringing ep doorbell */
3186 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3187
3188 /*
3189 * Make sure endpoint ring is empty before resetting the toggle/seq.
3190 * Driver is required to synchronously cancel all transfer request.
3191 * Stop the endpoint to force xHC to update the output context
3192 */
3193
3194 if (!list_empty(&ep->ring->td_list)) {
3195 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3196 spin_unlock_irqrestore(&xhci->lock, flags);
3197 xhci_free_command(xhci, cfg_cmd);
3198 goto cleanup;
3199 }
3200
3201 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3202 ep_index, 0);
3203 if (err < 0) {
3204 spin_unlock_irqrestore(&xhci->lock, flags);
3205 xhci_free_command(xhci, cfg_cmd);
3206 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3207 __func__, err);
3208 goto cleanup;
3209 }
3210
3211 xhci_ring_cmd_db(xhci);
3212 spin_unlock_irqrestore(&xhci->lock, flags);
3213
3214 wait_for_completion(stop_cmd->completion);
3215
3216 spin_lock_irqsave(&xhci->lock, flags);
3217
3218 /* config ep command clears toggle if add and drop ep flags are set */
3219 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3220 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3221 ctrl_ctx, ep_flag, ep_flag);
3222 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3223
3224 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3225 udev->slot_id, false);
3226 if (err < 0) {
3227 spin_unlock_irqrestore(&xhci->lock, flags);
3228 xhci_free_command(xhci, cfg_cmd);
3229 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3230 __func__, err);
3231 goto cleanup;
3232 }
3233
3234 xhci_ring_cmd_db(xhci);
3235 spin_unlock_irqrestore(&xhci->lock, flags);
3236
3237 wait_for_completion(cfg_cmd->completion);
3238
3239 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3240 xhci_free_command(xhci, cfg_cmd);
3241cleanup:
3242 xhci_free_command(xhci, stop_cmd);
3243}
3244
3245static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3246 struct usb_device *udev, struct usb_host_endpoint *ep,
3247 unsigned int slot_id)
3248{
3249 int ret;
3250 unsigned int ep_index;
3251 unsigned int ep_state;
3252
3253 if (!ep)
3254 return -EINVAL;
3255 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3256 if (ret <= 0)
3257 return -EINVAL;
3258 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3259 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3260 " descriptor for ep 0x%x does not support streams\n",
3261 ep->desc.bEndpointAddress);
3262 return -EINVAL;
3263 }
3264
3265 ep_index = xhci_get_endpoint_index(&ep->desc);
3266 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3267 if (ep_state & EP_HAS_STREAMS ||
3268 ep_state & EP_GETTING_STREAMS) {
3269 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3270 "already has streams set up.\n",
3271 ep->desc.bEndpointAddress);
3272 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3273 "dynamic stream context array reallocation.\n");
3274 return -EINVAL;
3275 }
3276 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3277 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3278 "endpoint 0x%x; URBs are pending.\n",
3279 ep->desc.bEndpointAddress);
3280 return -EINVAL;
3281 }
3282 return 0;
3283}
3284
3285static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3286 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3287{
3288 unsigned int max_streams;
3289
3290 /* The stream context array size must be a power of two */
3291 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3292 /*
3293 * Find out how many primary stream array entries the host controller
3294 * supports. Later we may use secondary stream arrays (similar to 2nd
3295 * level page entries), but that's an optional feature for xHCI host
3296 * controllers. xHCs must support at least 4 stream IDs.
3297 */
3298 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3299 if (*num_stream_ctxs > max_streams) {
3300 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3301 max_streams);
3302 *num_stream_ctxs = max_streams;
3303 *num_streams = max_streams;
3304 }
3305}
3306
3307/* Returns an error code if one of the endpoint already has streams.
3308 * This does not change any data structures, it only checks and gathers
3309 * information.
3310 */
3311static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3312 struct usb_device *udev,
3313 struct usb_host_endpoint **eps, unsigned int num_eps,
3314 unsigned int *num_streams, u32 *changed_ep_bitmask)
3315{
3316 unsigned int max_streams;
3317 unsigned int endpoint_flag;
3318 int i;
3319 int ret;
3320
3321 for (i = 0; i < num_eps; i++) {
3322 ret = xhci_check_streams_endpoint(xhci, udev,
3323 eps[i], udev->slot_id);
3324 if (ret < 0)
3325 return ret;
3326
3327 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3328 if (max_streams < (*num_streams - 1)) {
3329 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3330 eps[i]->desc.bEndpointAddress,
3331 max_streams);
3332 *num_streams = max_streams+1;
3333 }
3334
3335 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3336 if (*changed_ep_bitmask & endpoint_flag)
3337 return -EINVAL;
3338 *changed_ep_bitmask |= endpoint_flag;
3339 }
3340 return 0;
3341}
3342
3343static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3344 struct usb_device *udev,
3345 struct usb_host_endpoint **eps, unsigned int num_eps)
3346{
3347 u32 changed_ep_bitmask = 0;
3348 unsigned int slot_id;
3349 unsigned int ep_index;
3350 unsigned int ep_state;
3351 int i;
3352
3353 slot_id = udev->slot_id;
3354 if (!xhci->devs[slot_id])
3355 return 0;
3356
3357 for (i = 0; i < num_eps; i++) {
3358 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3359 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3360 /* Are streams already being freed for the endpoint? */
3361 if (ep_state & EP_GETTING_NO_STREAMS) {
3362 xhci_warn(xhci, "WARN Can't disable streams for "
3363 "endpoint 0x%x, "
3364 "streams are being disabled already\n",
3365 eps[i]->desc.bEndpointAddress);
3366 return 0;
3367 }
3368 /* Are there actually any streams to free? */
3369 if (!(ep_state & EP_HAS_STREAMS) &&
3370 !(ep_state & EP_GETTING_STREAMS)) {
3371 xhci_warn(xhci, "WARN Can't disable streams for "
3372 "endpoint 0x%x, "
3373 "streams are already disabled!\n",
3374 eps[i]->desc.bEndpointAddress);
3375 xhci_warn(xhci, "WARN xhci_free_streams() called "
3376 "with non-streams endpoint\n");
3377 return 0;
3378 }
3379 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3380 }
3381 return changed_ep_bitmask;
3382}
3383
3384/*
3385 * The USB device drivers use this function (through the HCD interface in USB
3386 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3387 * coordinate mass storage command queueing across multiple endpoints (basically
3388 * a stream ID == a task ID).
3389 *
3390 * Setting up streams involves allocating the same size stream context array
3391 * for each endpoint and issuing a configure endpoint command for all endpoints.
3392 *
3393 * Don't allow the call to succeed if one endpoint only supports one stream
3394 * (which means it doesn't support streams at all).
3395 *
3396 * Drivers may get less stream IDs than they asked for, if the host controller
3397 * hardware or endpoints claim they can't support the number of requested
3398 * stream IDs.
3399 */
3400static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3401 struct usb_host_endpoint **eps, unsigned int num_eps,
3402 unsigned int num_streams, gfp_t mem_flags)
3403{
3404 int i, ret;
3405 struct xhci_hcd *xhci;
3406 struct xhci_virt_device *vdev;
3407 struct xhci_command *config_cmd;
3408 struct xhci_input_control_ctx *ctrl_ctx;
3409 unsigned int ep_index;
3410 unsigned int num_stream_ctxs;
3411 unsigned int max_packet;
3412 unsigned long flags;
3413 u32 changed_ep_bitmask = 0;
3414
3415 if (!eps)
3416 return -EINVAL;
3417
3418 /* Add one to the number of streams requested to account for
3419 * stream 0 that is reserved for xHCI usage.
3420 */
3421 num_streams += 1;
3422 xhci = hcd_to_xhci(hcd);
3423 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3424 num_streams);
3425
3426 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3427 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3428 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3429 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3430 return -ENOSYS;
3431 }
3432
3433 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3434 if (!config_cmd)
3435 return -ENOMEM;
3436
3437 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3438 if (!ctrl_ctx) {
3439 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3440 __func__);
3441 xhci_free_command(xhci, config_cmd);
3442 return -ENOMEM;
3443 }
3444
3445 /* Check to make sure all endpoints are not already configured for
3446 * streams. While we're at it, find the maximum number of streams that
3447 * all the endpoints will support and check for duplicate endpoints.
3448 */
3449 spin_lock_irqsave(&xhci->lock, flags);
3450 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3451 num_eps, &num_streams, &changed_ep_bitmask);
3452 if (ret < 0) {
3453 xhci_free_command(xhci, config_cmd);
3454 spin_unlock_irqrestore(&xhci->lock, flags);
3455 return ret;
3456 }
3457 if (num_streams <= 1) {
3458 xhci_warn(xhci, "WARN: endpoints can't handle "
3459 "more than one stream.\n");
3460 xhci_free_command(xhci, config_cmd);
3461 spin_unlock_irqrestore(&xhci->lock, flags);
3462 return -EINVAL;
3463 }
3464 vdev = xhci->devs[udev->slot_id];
3465 /* Mark each endpoint as being in transition, so
3466 * xhci_urb_enqueue() will reject all URBs.
3467 */
3468 for (i = 0; i < num_eps; i++) {
3469 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3470 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3471 }
3472 spin_unlock_irqrestore(&xhci->lock, flags);
3473
3474 /* Setup internal data structures and allocate HW data structures for
3475 * streams (but don't install the HW structures in the input context
3476 * until we're sure all memory allocation succeeded).
3477 */
3478 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3479 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3480 num_stream_ctxs, num_streams);
3481
3482 for (i = 0; i < num_eps; i++) {
3483 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3484 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3485 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3486 num_stream_ctxs,
3487 num_streams,
3488 max_packet, mem_flags);
3489 if (!vdev->eps[ep_index].stream_info)
3490 goto cleanup;
3491 /* Set maxPstreams in endpoint context and update deq ptr to
3492 * point to stream context array. FIXME
3493 */
3494 }
3495
3496 /* Set up the input context for a configure endpoint command. */
3497 for (i = 0; i < num_eps; i++) {
3498 struct xhci_ep_ctx *ep_ctx;
3499
3500 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3501 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3502
3503 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3504 vdev->out_ctx, ep_index);
3505 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3506 vdev->eps[ep_index].stream_info);
3507 }
3508 /* Tell the HW to drop its old copy of the endpoint context info
3509 * and add the updated copy from the input context.
3510 */
3511 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3512 vdev->out_ctx, ctrl_ctx,
3513 changed_ep_bitmask, changed_ep_bitmask);
3514
3515 /* Issue and wait for the configure endpoint command */
3516 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3517 false, false);
3518
3519 /* xHC rejected the configure endpoint command for some reason, so we
3520 * leave the old ring intact and free our internal streams data
3521 * structure.
3522 */
3523 if (ret < 0)
3524 goto cleanup;
3525
3526 spin_lock_irqsave(&xhci->lock, flags);
3527 for (i = 0; i < num_eps; i++) {
3528 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3529 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3530 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3531 udev->slot_id, ep_index);
3532 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3533 }
3534 xhci_free_command(xhci, config_cmd);
3535 spin_unlock_irqrestore(&xhci->lock, flags);
3536
3537 /* Subtract 1 for stream 0, which drivers can't use */
3538 return num_streams - 1;
3539
3540cleanup:
3541 /* If it didn't work, free the streams! */
3542 for (i = 0; i < num_eps; i++) {
3543 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3544 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3545 vdev->eps[ep_index].stream_info = NULL;
3546 /* FIXME Unset maxPstreams in endpoint context and
3547 * update deq ptr to point to normal string ring.
3548 */
3549 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3550 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3551 xhci_endpoint_zero(xhci, vdev, eps[i]);
3552 }
3553 xhci_free_command(xhci, config_cmd);
3554 return -ENOMEM;
3555}
3556
3557/* Transition the endpoint from using streams to being a "normal" endpoint
3558 * without streams.
3559 *
3560 * Modify the endpoint context state, submit a configure endpoint command,
3561 * and free all endpoint rings for streams if that completes successfully.
3562 */
3563static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3564 struct usb_host_endpoint **eps, unsigned int num_eps,
3565 gfp_t mem_flags)
3566{
3567 int i, ret;
3568 struct xhci_hcd *xhci;
3569 struct xhci_virt_device *vdev;
3570 struct xhci_command *command;
3571 struct xhci_input_control_ctx *ctrl_ctx;
3572 unsigned int ep_index;
3573 unsigned long flags;
3574 u32 changed_ep_bitmask;
3575
3576 xhci = hcd_to_xhci(hcd);
3577 vdev = xhci->devs[udev->slot_id];
3578
3579 /* Set up a configure endpoint command to remove the streams rings */
3580 spin_lock_irqsave(&xhci->lock, flags);
3581 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3582 udev, eps, num_eps);
3583 if (changed_ep_bitmask == 0) {
3584 spin_unlock_irqrestore(&xhci->lock, flags);
3585 return -EINVAL;
3586 }
3587
3588 /* Use the xhci_command structure from the first endpoint. We may have
3589 * allocated too many, but the driver may call xhci_free_streams() for
3590 * each endpoint it grouped into one call to xhci_alloc_streams().
3591 */
3592 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3593 command = vdev->eps[ep_index].stream_info->free_streams_command;
3594 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3595 if (!ctrl_ctx) {
3596 spin_unlock_irqrestore(&xhci->lock, flags);
3597 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3598 __func__);
3599 return -EINVAL;
3600 }
3601
3602 for (i = 0; i < num_eps; i++) {
3603 struct xhci_ep_ctx *ep_ctx;
3604
3605 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3606 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3607 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3608 EP_GETTING_NO_STREAMS;
3609
3610 xhci_endpoint_copy(xhci, command->in_ctx,
3611 vdev->out_ctx, ep_index);
3612 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3613 &vdev->eps[ep_index]);
3614 }
3615 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3616 vdev->out_ctx, ctrl_ctx,
3617 changed_ep_bitmask, changed_ep_bitmask);
3618 spin_unlock_irqrestore(&xhci->lock, flags);
3619
3620 /* Issue and wait for the configure endpoint command,
3621 * which must succeed.
3622 */
3623 ret = xhci_configure_endpoint(xhci, udev, command,
3624 false, true);
3625
3626 /* xHC rejected the configure endpoint command for some reason, so we
3627 * leave the streams rings intact.
3628 */
3629 if (ret < 0)
3630 return ret;
3631
3632 spin_lock_irqsave(&xhci->lock, flags);
3633 for (i = 0; i < num_eps; i++) {
3634 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3635 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3636 vdev->eps[ep_index].stream_info = NULL;
3637 /* FIXME Unset maxPstreams in endpoint context and
3638 * update deq ptr to point to normal string ring.
3639 */
3640 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3641 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3642 }
3643 spin_unlock_irqrestore(&xhci->lock, flags);
3644
3645 return 0;
3646}
3647
3648/*
3649 * Deletes endpoint resources for endpoints that were active before a Reset
3650 * Device command, or a Disable Slot command. The Reset Device command leaves
3651 * the control endpoint intact, whereas the Disable Slot command deletes it.
3652 *
3653 * Must be called with xhci->lock held.
3654 */
3655void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3656 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3657{
3658 int i;
3659 unsigned int num_dropped_eps = 0;
3660 unsigned int drop_flags = 0;
3661
3662 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3663 if (virt_dev->eps[i].ring) {
3664 drop_flags |= 1 << i;
3665 num_dropped_eps++;
3666 }
3667 }
3668 xhci->num_active_eps -= num_dropped_eps;
3669 if (num_dropped_eps)
3670 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3671 "Dropped %u ep ctxs, flags = 0x%x, "
3672 "%u now active.",
3673 num_dropped_eps, drop_flags,
3674 xhci->num_active_eps);
3675}
3676
3677/*
3678 * This submits a Reset Device Command, which will set the device state to 0,
3679 * set the device address to 0, and disable all the endpoints except the default
3680 * control endpoint. The USB core should come back and call
3681 * xhci_address_device(), and then re-set up the configuration. If this is
3682 * called because of a usb_reset_and_verify_device(), then the old alternate
3683 * settings will be re-installed through the normal bandwidth allocation
3684 * functions.
3685 *
3686 * Wait for the Reset Device command to finish. Remove all structures
3687 * associated with the endpoints that were disabled. Clear the input device
3688 * structure? Reset the control endpoint 0 max packet size?
3689 *
3690 * If the virt_dev to be reset does not exist or does not match the udev,
3691 * it means the device is lost, possibly due to the xHC restore error and
3692 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3693 * re-allocate the device.
3694 */
3695static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3696 struct usb_device *udev)
3697{
3698 int ret, i;
3699 unsigned long flags;
3700 struct xhci_hcd *xhci;
3701 unsigned int slot_id;
3702 struct xhci_virt_device *virt_dev;
3703 struct xhci_command *reset_device_cmd;
3704 struct xhci_slot_ctx *slot_ctx;
3705 int old_active_eps = 0;
3706
3707 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3708 if (ret <= 0)
3709 return ret;
3710 xhci = hcd_to_xhci(hcd);
3711 slot_id = udev->slot_id;
3712 virt_dev = xhci->devs[slot_id];
3713 if (!virt_dev) {
3714 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3715 "not exist. Re-allocate the device\n", slot_id);
3716 ret = xhci_alloc_dev(hcd, udev);
3717 if (ret == 1)
3718 return 0;
3719 else
3720 return -EINVAL;
3721 }
3722
3723 if (virt_dev->tt_info)
3724 old_active_eps = virt_dev->tt_info->active_eps;
3725
3726 if (virt_dev->udev != udev) {
3727 /* If the virt_dev and the udev does not match, this virt_dev
3728 * may belong to another udev.
3729 * Re-allocate the device.
3730 */
3731 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3732 "not match the udev. Re-allocate the device\n",
3733 slot_id);
3734 ret = xhci_alloc_dev(hcd, udev);
3735 if (ret == 1)
3736 return 0;
3737 else
3738 return -EINVAL;
3739 }
3740
3741 /* If device is not setup, there is no point in resetting it */
3742 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3743 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3744 SLOT_STATE_DISABLED)
3745 return 0;
3746
3747 trace_xhci_discover_or_reset_device(slot_ctx);
3748
3749 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3750 /* Allocate the command structure that holds the struct completion.
3751 * Assume we're in process context, since the normal device reset
3752 * process has to wait for the device anyway. Storage devices are
3753 * reset as part of error handling, so use GFP_NOIO instead of
3754 * GFP_KERNEL.
3755 */
3756 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3757 if (!reset_device_cmd) {
3758 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3759 return -ENOMEM;
3760 }
3761
3762 /* Attempt to submit the Reset Device command to the command ring */
3763 spin_lock_irqsave(&xhci->lock, flags);
3764
3765 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3766 if (ret) {
3767 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3768 spin_unlock_irqrestore(&xhci->lock, flags);
3769 goto command_cleanup;
3770 }
3771 xhci_ring_cmd_db(xhci);
3772 spin_unlock_irqrestore(&xhci->lock, flags);
3773
3774 /* Wait for the Reset Device command to finish */
3775 wait_for_completion(reset_device_cmd->completion);
3776
3777 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3778 * unless we tried to reset a slot ID that wasn't enabled,
3779 * or the device wasn't in the addressed or configured state.
3780 */
3781 ret = reset_device_cmd->status;
3782 switch (ret) {
3783 case COMP_COMMAND_ABORTED:
3784 case COMP_COMMAND_RING_STOPPED:
3785 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3786 ret = -ETIME;
3787 goto command_cleanup;
3788 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3789 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3790 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3791 slot_id,
3792 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3793 xhci_dbg(xhci, "Not freeing device rings.\n");
3794 /* Don't treat this as an error. May change my mind later. */
3795 ret = 0;
3796 goto command_cleanup;
3797 case COMP_SUCCESS:
3798 xhci_dbg(xhci, "Successful reset device command.\n");
3799 break;
3800 default:
3801 if (xhci_is_vendor_info_code(xhci, ret))
3802 break;
3803 xhci_warn(xhci, "Unknown completion code %u for "
3804 "reset device command.\n", ret);
3805 ret = -EINVAL;
3806 goto command_cleanup;
3807 }
3808
3809 /* Free up host controller endpoint resources */
3810 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3811 spin_lock_irqsave(&xhci->lock, flags);
3812 /* Don't delete the default control endpoint resources */
3813 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3814 spin_unlock_irqrestore(&xhci->lock, flags);
3815 }
3816
3817 /* Everything but endpoint 0 is disabled, so free the rings. */
3818 for (i = 1; i < 31; i++) {
3819 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3820
3821 if (ep->ep_state & EP_HAS_STREAMS) {
3822 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3823 xhci_get_endpoint_address(i));
3824 xhci_free_stream_info(xhci, ep->stream_info);
3825 ep->stream_info = NULL;
3826 ep->ep_state &= ~EP_HAS_STREAMS;
3827 }
3828
3829 if (ep->ring) {
3830 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3831 xhci_free_endpoint_ring(xhci, virt_dev, i);
3832 }
3833 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3834 xhci_drop_ep_from_interval_table(xhci,
3835 &virt_dev->eps[i].bw_info,
3836 virt_dev->bw_table,
3837 udev,
3838 &virt_dev->eps[i],
3839 virt_dev->tt_info);
3840 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3841 }
3842 /* If necessary, update the number of active TTs on this root port */
3843 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3844 virt_dev->flags = 0;
3845 ret = 0;
3846
3847command_cleanup:
3848 xhci_free_command(xhci, reset_device_cmd);
3849 return ret;
3850}
3851
3852/*
3853 * At this point, the struct usb_device is about to go away, the device has
3854 * disconnected, and all traffic has been stopped and the endpoints have been
3855 * disabled. Free any HC data structures associated with that device.
3856 */
3857static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3858{
3859 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3860 struct xhci_virt_device *virt_dev;
3861 struct xhci_slot_ctx *slot_ctx;
3862 int i, ret;
3863
3864#ifndef CONFIG_USB_DEFAULT_PERSIST
3865 /*
3866 * We called pm_runtime_get_noresume when the device was attached.
3867 * Decrement the counter here to allow controller to runtime suspend
3868 * if no devices remain.
3869 */
3870 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3871 pm_runtime_put_noidle(hcd->self.controller);
3872#endif
3873
3874 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3875 /* If the host is halted due to driver unload, we still need to free the
3876 * device.
3877 */
3878 if (ret <= 0 && ret != -ENODEV)
3879 return;
3880
3881 virt_dev = xhci->devs[udev->slot_id];
3882 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3883 trace_xhci_free_dev(slot_ctx);
3884
3885 /* Stop any wayward timer functions (which may grab the lock) */
3886 for (i = 0; i < 31; i++) {
3887 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3888 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3889 }
3890 virt_dev->udev = NULL;
3891 ret = xhci_disable_slot(xhci, udev->slot_id);
3892 if (ret)
3893 xhci_free_virt_device(xhci, udev->slot_id);
3894}
3895
3896int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3897{
3898 struct xhci_command *command;
3899 unsigned long flags;
3900 u32 state;
3901 int ret = 0;
3902
3903 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
3904 if (!command)
3905 return -ENOMEM;
3906
3907 xhci_debugfs_remove_slot(xhci, slot_id);
3908
3909 spin_lock_irqsave(&xhci->lock, flags);
3910 /* Don't disable the slot if the host controller is dead. */
3911 state = readl(&xhci->op_regs->status);
3912 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3913 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3914 spin_unlock_irqrestore(&xhci->lock, flags);
3915 kfree(command);
3916 return -ENODEV;
3917 }
3918
3919 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3920 slot_id);
3921 if (ret) {
3922 spin_unlock_irqrestore(&xhci->lock, flags);
3923 kfree(command);
3924 return ret;
3925 }
3926 xhci_ring_cmd_db(xhci);
3927 spin_unlock_irqrestore(&xhci->lock, flags);
3928 return ret;
3929}
3930
3931/*
3932 * Checks if we have enough host controller resources for the default control
3933 * endpoint.
3934 *
3935 * Must be called with xhci->lock held.
3936 */
3937static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3938{
3939 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3940 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3941 "Not enough ep ctxs: "
3942 "%u active, need to add 1, limit is %u.",
3943 xhci->num_active_eps, xhci->limit_active_eps);
3944 return -ENOMEM;
3945 }
3946 xhci->num_active_eps += 1;
3947 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3948 "Adding 1 ep ctx, %u now active.",
3949 xhci->num_active_eps);
3950 return 0;
3951}
3952
3953
3954/*
3955 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3956 * timed out, or allocating memory failed. Returns 1 on success.
3957 */
3958int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3959{
3960 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3961 struct xhci_virt_device *vdev;
3962 struct xhci_slot_ctx *slot_ctx;
3963 unsigned long flags;
3964 int ret, slot_id;
3965 struct xhci_command *command;
3966
3967 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3968 if (!command)
3969 return 0;
3970
3971 spin_lock_irqsave(&xhci->lock, flags);
3972 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3973 if (ret) {
3974 spin_unlock_irqrestore(&xhci->lock, flags);
3975 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3976 xhci_free_command(xhci, command);
3977 return 0;
3978 }
3979 xhci_ring_cmd_db(xhci);
3980 spin_unlock_irqrestore(&xhci->lock, flags);
3981
3982 wait_for_completion(command->completion);
3983 slot_id = command->slot_id;
3984
3985 if (!slot_id || command->status != COMP_SUCCESS) {
3986 xhci_err(xhci, "Error while assigning device slot ID\n");
3987 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3988 HCS_MAX_SLOTS(
3989 readl(&xhci->cap_regs->hcs_params1)));
3990 xhci_free_command(xhci, command);
3991 return 0;
3992 }
3993
3994 xhci_free_command(xhci, command);
3995
3996 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3997 spin_lock_irqsave(&xhci->lock, flags);
3998 ret = xhci_reserve_host_control_ep_resources(xhci);
3999 if (ret) {
4000 spin_unlock_irqrestore(&xhci->lock, flags);
4001 xhci_warn(xhci, "Not enough host resources, "
4002 "active endpoint contexts = %u\n",
4003 xhci->num_active_eps);
4004 goto disable_slot;
4005 }
4006 spin_unlock_irqrestore(&xhci->lock, flags);
4007 }
4008 /* Use GFP_NOIO, since this function can be called from
4009 * xhci_discover_or_reset_device(), which may be called as part of
4010 * mass storage driver error handling.
4011 */
4012 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4013 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4014 goto disable_slot;
4015 }
4016 vdev = xhci->devs[slot_id];
4017 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4018 trace_xhci_alloc_dev(slot_ctx);
4019
4020 udev->slot_id = slot_id;
4021
4022 xhci_debugfs_create_slot(xhci, slot_id);
4023
4024#ifndef CONFIG_USB_DEFAULT_PERSIST
4025 /*
4026 * If resetting upon resume, we can't put the controller into runtime
4027 * suspend if there is a device attached.
4028 */
4029 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4030 pm_runtime_get_noresume(hcd->self.controller);
4031#endif
4032
4033 /* Is this a LS or FS device under a HS hub? */
4034 /* Hub or peripherial? */
4035 return 1;
4036
4037disable_slot:
4038 ret = xhci_disable_slot(xhci, udev->slot_id);
4039 if (ret)
4040 xhci_free_virt_device(xhci, udev->slot_id);
4041
4042 return 0;
4043}
4044
4045/*
4046 * Issue an Address Device command and optionally send a corresponding
4047 * SetAddress request to the device.
4048 */
4049static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4050 enum xhci_setup_dev setup)
4051{
4052 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4053 unsigned long flags;
4054 struct xhci_virt_device *virt_dev;
4055 int ret = 0;
4056 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4057 struct xhci_slot_ctx *slot_ctx;
4058 struct xhci_input_control_ctx *ctrl_ctx;
4059 u64 temp_64;
4060 struct xhci_command *command = NULL;
4061
4062 mutex_lock(&xhci->mutex);
4063
4064 if (xhci->xhc_state) { /* dying, removing or halted */
4065 ret = -ESHUTDOWN;
4066 goto out;
4067 }
4068
4069 if (!udev->slot_id) {
4070 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4071 "Bad Slot ID %d", udev->slot_id);
4072 ret = -EINVAL;
4073 goto out;
4074 }
4075
4076 virt_dev = xhci->devs[udev->slot_id];
4077
4078 if (WARN_ON(!virt_dev)) {
4079 /*
4080 * In plug/unplug torture test with an NEC controller,
4081 * a zero-dereference was observed once due to virt_dev = 0.
4082 * Print useful debug rather than crash if it is observed again!
4083 */
4084 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4085 udev->slot_id);
4086 ret = -EINVAL;
4087 goto out;
4088 }
4089 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4090 trace_xhci_setup_device_slot(slot_ctx);
4091
4092 if (setup == SETUP_CONTEXT_ONLY) {
4093 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4094 SLOT_STATE_DEFAULT) {
4095 xhci_dbg(xhci, "Slot already in default state\n");
4096 goto out;
4097 }
4098 }
4099
4100 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4101 if (!command) {
4102 ret = -ENOMEM;
4103 goto out;
4104 }
4105
4106 command->in_ctx = virt_dev->in_ctx;
4107
4108 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4109 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4110 if (!ctrl_ctx) {
4111 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4112 __func__);
4113 ret = -EINVAL;
4114 goto out;
4115 }
4116 /*
4117 * If this is the first Set Address since device plug-in or
4118 * virt_device realloaction after a resume with an xHCI power loss,
4119 * then set up the slot context.
4120 */
4121 if (!slot_ctx->dev_info)
4122 xhci_setup_addressable_virt_dev(xhci, udev);
4123 /* Otherwise, update the control endpoint ring enqueue pointer. */
4124 else
4125 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4126 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4127 ctrl_ctx->drop_flags = 0;
4128
4129 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4130 le32_to_cpu(slot_ctx->dev_info) >> 27);
4131
4132 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4133 spin_lock_irqsave(&xhci->lock, flags);
4134 trace_xhci_setup_device(virt_dev);
4135 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4136 udev->slot_id, setup);
4137 if (ret) {
4138 spin_unlock_irqrestore(&xhci->lock, flags);
4139 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4140 "FIXME: allocate a command ring segment");
4141 goto out;
4142 }
4143 xhci_ring_cmd_db(xhci);
4144 spin_unlock_irqrestore(&xhci->lock, flags);
4145
4146 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4147 wait_for_completion(command->completion);
4148
4149 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4150 * the SetAddress() "recovery interval" required by USB and aborting the
4151 * command on a timeout.
4152 */
4153 switch (command->status) {
4154 case COMP_COMMAND_ABORTED:
4155 case COMP_COMMAND_RING_STOPPED:
4156 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4157 ret = -ETIME;
4158 break;
4159 case COMP_CONTEXT_STATE_ERROR:
4160 case COMP_SLOT_NOT_ENABLED_ERROR:
4161 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4162 act, udev->slot_id);
4163 ret = -EINVAL;
4164 break;
4165 case COMP_USB_TRANSACTION_ERROR:
4166 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4167
4168 mutex_unlock(&xhci->mutex);
4169 ret = xhci_disable_slot(xhci, udev->slot_id);
4170 if (!ret)
4171 xhci_alloc_dev(hcd, udev);
4172 kfree(command->completion);
4173 kfree(command);
4174 return -EPROTO;
4175 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4176 dev_warn(&udev->dev,
4177 "ERROR: Incompatible device for setup %s command\n", act);
4178 ret = -ENODEV;
4179 break;
4180 case COMP_SUCCESS:
4181 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4182 "Successful setup %s command", act);
4183 break;
4184 default:
4185 xhci_err(xhci,
4186 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4187 act, command->status);
4188 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4189 ret = -EINVAL;
4190 break;
4191 }
4192 if (ret)
4193 goto out;
4194 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4195 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4196 "Op regs DCBAA ptr = %#016llx", temp_64);
4197 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4198 "Slot ID %d dcbaa entry @%p = %#016llx",
4199 udev->slot_id,
4200 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4201 (unsigned long long)
4202 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4203 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4204 "Output Context DMA address = %#08llx",
4205 (unsigned long long)virt_dev->out_ctx->dma);
4206 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4207 le32_to_cpu(slot_ctx->dev_info) >> 27);
4208 /*
4209 * USB core uses address 1 for the roothubs, so we add one to the
4210 * address given back to us by the HC.
4211 */
4212 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4213 le32_to_cpu(slot_ctx->dev_info) >> 27);
4214 /* Zero the input context control for later use */
4215 ctrl_ctx->add_flags = 0;
4216 ctrl_ctx->drop_flags = 0;
4217 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4218 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4219
4220 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4221 "Internal device address = %d",
4222 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4223out:
4224 mutex_unlock(&xhci->mutex);
4225 if (command) {
4226 kfree(command->completion);
4227 kfree(command);
4228 }
4229 return ret;
4230}
4231
4232static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4233{
4234 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4235}
4236
4237static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4238{
4239 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4240}
4241
4242/*
4243 * Transfer the port index into real index in the HW port status
4244 * registers. Caculate offset between the port's PORTSC register
4245 * and port status base. Divide the number of per port register
4246 * to get the real index. The raw port number bases 1.
4247 */
4248int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4249{
4250 struct xhci_hub *rhub;
4251
4252 rhub = xhci_get_rhub(hcd);
4253 return rhub->ports[port1 - 1]->hw_portnum + 1;
4254}
4255
4256/*
4257 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4258 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4259 */
4260static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4261 struct usb_device *udev, u16 max_exit_latency)
4262{
4263 struct xhci_virt_device *virt_dev;
4264 struct xhci_command *command;
4265 struct xhci_input_control_ctx *ctrl_ctx;
4266 struct xhci_slot_ctx *slot_ctx;
4267 unsigned long flags;
4268 int ret;
4269
4270 spin_lock_irqsave(&xhci->lock, flags);
4271
4272 virt_dev = xhci->devs[udev->slot_id];
4273
4274 /*
4275 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4276 * xHC was re-initialized. Exit latency will be set later after
4277 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4278 */
4279
4280 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4281 spin_unlock_irqrestore(&xhci->lock, flags);
4282 return 0;
4283 }
4284
4285 /* Attempt to issue an Evaluate Context command to change the MEL. */
4286 command = xhci->lpm_command;
4287 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4288 if (!ctrl_ctx) {
4289 spin_unlock_irqrestore(&xhci->lock, flags);
4290 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4291 __func__);
4292 return -ENOMEM;
4293 }
4294
4295 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4296 spin_unlock_irqrestore(&xhci->lock, flags);
4297
4298 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4299 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4300 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4301 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4302 slot_ctx->dev_state = 0;
4303
4304 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4305 "Set up evaluate context for LPM MEL change.");
4306
4307 /* Issue and wait for the evaluate context command. */
4308 ret = xhci_configure_endpoint(xhci, udev, command,
4309 true, true);
4310
4311 if (!ret) {
4312 spin_lock_irqsave(&xhci->lock, flags);
4313 virt_dev->current_mel = max_exit_latency;
4314 spin_unlock_irqrestore(&xhci->lock, flags);
4315 }
4316 return ret;
4317}
4318
4319#ifdef CONFIG_PM
4320
4321/* BESL to HIRD Encoding array for USB2 LPM */
4322static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4323 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4324
4325/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4326static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4327 struct usb_device *udev)
4328{
4329 int u2del, besl, besl_host;
4330 int besl_device = 0;
4331 u32 field;
4332
4333 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4334 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4335
4336 if (field & USB_BESL_SUPPORT) {
4337 for (besl_host = 0; besl_host < 16; besl_host++) {
4338 if (xhci_besl_encoding[besl_host] >= u2del)
4339 break;
4340 }
4341 /* Use baseline BESL value as default */
4342 if (field & USB_BESL_BASELINE_VALID)
4343 besl_device = USB_GET_BESL_BASELINE(field);
4344 else if (field & USB_BESL_DEEP_VALID)
4345 besl_device = USB_GET_BESL_DEEP(field);
4346 } else {
4347 if (u2del <= 50)
4348 besl_host = 0;
4349 else
4350 besl_host = (u2del - 51) / 75 + 1;
4351 }
4352
4353 besl = besl_host + besl_device;
4354 if (besl > 15)
4355 besl = 15;
4356
4357 return besl;
4358}
4359
4360/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4361static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4362{
4363 u32 field;
4364 int l1;
4365 int besld = 0;
4366 int hirdm = 0;
4367
4368 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4369
4370 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4371 l1 = udev->l1_params.timeout / 256;
4372
4373 /* device has preferred BESLD */
4374 if (field & USB_BESL_DEEP_VALID) {
4375 besld = USB_GET_BESL_DEEP(field);
4376 hirdm = 1;
4377 }
4378
4379 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4380}
4381
4382static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4383 struct usb_device *udev, int enable)
4384{
4385 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4386 struct xhci_port **ports;
4387 __le32 __iomem *pm_addr, *hlpm_addr;
4388 u32 pm_val, hlpm_val, field;
4389 unsigned int port_num;
4390 unsigned long flags;
4391 int hird, exit_latency;
4392 int ret;
4393
4394 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4395 !udev->lpm_capable)
4396 return -EPERM;
4397
4398 if (!udev->parent || udev->parent->parent ||
4399 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4400 return -EPERM;
4401
4402 if (udev->usb2_hw_lpm_capable != 1)
4403 return -EPERM;
4404
4405 spin_lock_irqsave(&xhci->lock, flags);
4406
4407 ports = xhci->usb2_rhub.ports;
4408 port_num = udev->portnum - 1;
4409 pm_addr = ports[port_num]->addr + PORTPMSC;
4410 pm_val = readl(pm_addr);
4411 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4412
4413 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4414 enable ? "enable" : "disable", port_num + 1);
4415
4416 if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) {
4417 /* Host supports BESL timeout instead of HIRD */
4418 if (udev->usb2_hw_lpm_besl_capable) {
4419 /* if device doesn't have a preferred BESL value use a
4420 * default one which works with mixed HIRD and BESL
4421 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4422 */
4423 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4424 if ((field & USB_BESL_SUPPORT) &&
4425 (field & USB_BESL_BASELINE_VALID))
4426 hird = USB_GET_BESL_BASELINE(field);
4427 else
4428 hird = udev->l1_params.besl;
4429
4430 exit_latency = xhci_besl_encoding[hird];
4431 spin_unlock_irqrestore(&xhci->lock, flags);
4432
4433 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4434 * input context for link powermanagement evaluate
4435 * context commands. It is protected by hcd->bandwidth
4436 * mutex and is shared by all devices. We need to set
4437 * the max ext latency in USB 2 BESL LPM as well, so
4438 * use the same mutex and xhci_change_max_exit_latency()
4439 */
4440 mutex_lock(hcd->bandwidth_mutex);
4441 ret = xhci_change_max_exit_latency(xhci, udev,
4442 exit_latency);
4443 mutex_unlock(hcd->bandwidth_mutex);
4444
4445 if (ret < 0)
4446 return ret;
4447 spin_lock_irqsave(&xhci->lock, flags);
4448
4449 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4450 writel(hlpm_val, hlpm_addr);
4451 /* flush write */
4452 readl(hlpm_addr);
4453 } else {
4454 hird = xhci_calculate_hird_besl(xhci, udev);
4455 }
4456
4457 pm_val &= ~PORT_HIRD_MASK;
4458 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4459 writel(pm_val, pm_addr);
4460 pm_val = readl(pm_addr);
4461 pm_val |= PORT_HLE;
4462 writel(pm_val, pm_addr);
4463 /* flush write */
4464 readl(pm_addr);
4465 } else {
4466 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4467 writel(pm_val, pm_addr);
4468 /* flush write */
4469 readl(pm_addr);
4470 if (udev->usb2_hw_lpm_besl_capable) {
4471 spin_unlock_irqrestore(&xhci->lock, flags);
4472 mutex_lock(hcd->bandwidth_mutex);
4473 xhci_change_max_exit_latency(xhci, udev, 0);
4474 mutex_unlock(hcd->bandwidth_mutex);
4475 return 0;
4476 }
4477 }
4478
4479 spin_unlock_irqrestore(&xhci->lock, flags);
4480 return 0;
4481}
4482
4483/* check if a usb2 port supports a given extened capability protocol
4484 * only USB2 ports extended protocol capability values are cached.
4485 * Return 1 if capability is supported
4486 */
4487static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4488 unsigned capability)
4489{
4490 u32 port_offset, port_count;
4491 int i;
4492
4493 for (i = 0; i < xhci->num_ext_caps; i++) {
4494 if (xhci->ext_caps[i] & capability) {
4495 /* port offsets starts at 1 */
4496 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4497 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4498 if (port >= port_offset &&
4499 port < port_offset + port_count)
4500 return 1;
4501 }
4502 }
4503 return 0;
4504}
4505
4506static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4507{
4508 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4509 int portnum = udev->portnum - 1;
4510
4511 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4512 return 0;
4513
4514 /* we only support lpm for non-hub device connected to root hub yet */
4515 if (!udev->parent || udev->parent->parent ||
4516 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4517 return 0;
4518
4519 if (xhci->hw_lpm_support == 1 &&
4520 xhci_check_usb2_port_capability(
4521 xhci, portnum, XHCI_HLC)) {
4522 udev->usb2_hw_lpm_capable = 1;
4523 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4524 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4525 if (xhci_check_usb2_port_capability(xhci, portnum,
4526 XHCI_BLC))
4527 udev->usb2_hw_lpm_besl_capable = 1;
4528 }
4529
4530 return 0;
4531}
4532
4533/*---------------------- USB 3.0 Link PM functions ------------------------*/
4534
4535/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4536static unsigned long long xhci_service_interval_to_ns(
4537 struct usb_endpoint_descriptor *desc)
4538{
4539 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4540}
4541
4542static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4543 enum usb3_link_state state)
4544{
4545 unsigned long long sel;
4546 unsigned long long pel;
4547 unsigned int max_sel_pel;
4548 char *state_name;
4549
4550 switch (state) {
4551 case USB3_LPM_U1:
4552 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4553 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4554 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4555 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4556 state_name = "U1";
4557 break;
4558 case USB3_LPM_U2:
4559 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4560 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4561 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4562 state_name = "U2";
4563 break;
4564 default:
4565 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4566 __func__);
4567 return USB3_LPM_DISABLED;
4568 }
4569
4570 if (sel <= max_sel_pel && pel <= max_sel_pel)
4571 return USB3_LPM_DEVICE_INITIATED;
4572
4573 if (sel > max_sel_pel)
4574 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4575 "due to long SEL %llu ms\n",
4576 state_name, sel);
4577 else
4578 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4579 "due to long PEL %llu ms\n",
4580 state_name, pel);
4581 return USB3_LPM_DISABLED;
4582}
4583
4584/* The U1 timeout should be the maximum of the following values:
4585 * - For control endpoints, U1 system exit latency (SEL) * 3
4586 * - For bulk endpoints, U1 SEL * 5
4587 * - For interrupt endpoints:
4588 * - Notification EPs, U1 SEL * 3
4589 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4590 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4591 */
4592static unsigned long long xhci_calculate_intel_u1_timeout(
4593 struct usb_device *udev,
4594 struct usb_endpoint_descriptor *desc)
4595{
4596 unsigned long long timeout_ns;
4597 int ep_type;
4598 int intr_type;
4599
4600 ep_type = usb_endpoint_type(desc);
4601 switch (ep_type) {
4602 case USB_ENDPOINT_XFER_CONTROL:
4603 timeout_ns = udev->u1_params.sel * 3;
4604 break;
4605 case USB_ENDPOINT_XFER_BULK:
4606 timeout_ns = udev->u1_params.sel * 5;
4607 break;
4608 case USB_ENDPOINT_XFER_INT:
4609 intr_type = usb_endpoint_interrupt_type(desc);
4610 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4611 timeout_ns = udev->u1_params.sel * 3;
4612 break;
4613 }
4614 /* Otherwise the calculation is the same as isoc eps */
4615 /* fall through */
4616 case USB_ENDPOINT_XFER_ISOC:
4617 timeout_ns = xhci_service_interval_to_ns(desc);
4618 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4619 if (timeout_ns < udev->u1_params.sel * 2)
4620 timeout_ns = udev->u1_params.sel * 2;
4621 break;
4622 default:
4623 return 0;
4624 }
4625
4626 return timeout_ns;
4627}
4628
4629/* Returns the hub-encoded U1 timeout value. */
4630static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4631 struct usb_device *udev,
4632 struct usb_endpoint_descriptor *desc)
4633{
4634 unsigned long long timeout_ns;
4635
4636 /* Prevent U1 if service interval is shorter than U1 exit latency */
4637 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4638 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4639 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4640 return USB3_LPM_DISABLED;
4641 }
4642 }
4643
4644 if (xhci->quirks & XHCI_INTEL_HOST)
4645 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4646 else
4647 timeout_ns = udev->u1_params.sel;
4648
4649 /* The U1 timeout is encoded in 1us intervals.
4650 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4651 */
4652 if (timeout_ns == USB3_LPM_DISABLED)
4653 timeout_ns = 1;
4654 else
4655 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4656
4657 /* If the necessary timeout value is bigger than what we can set in the
4658 * USB 3.0 hub, we have to disable hub-initiated U1.
4659 */
4660 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4661 return timeout_ns;
4662 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4663 "due to long timeout %llu ms\n", timeout_ns);
4664 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4665}
4666
4667/* The U2 timeout should be the maximum of:
4668 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4669 * - largest bInterval of any active periodic endpoint (to avoid going
4670 * into lower power link states between intervals).
4671 * - the U2 Exit Latency of the device
4672 */
4673static unsigned long long xhci_calculate_intel_u2_timeout(
4674 struct usb_device *udev,
4675 struct usb_endpoint_descriptor *desc)
4676{
4677 unsigned long long timeout_ns;
4678 unsigned long long u2_del_ns;
4679
4680 timeout_ns = 10 * 1000 * 1000;
4681
4682 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4683 (xhci_service_interval_to_ns(desc) > timeout_ns))
4684 timeout_ns = xhci_service_interval_to_ns(desc);
4685
4686 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4687 if (u2_del_ns > timeout_ns)
4688 timeout_ns = u2_del_ns;
4689
4690 return timeout_ns;
4691}
4692
4693/* Returns the hub-encoded U2 timeout value. */
4694static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4695 struct usb_device *udev,
4696 struct usb_endpoint_descriptor *desc)
4697{
4698 unsigned long long timeout_ns;
4699
4700 /* Prevent U2 if service interval is shorter than U2 exit latency */
4701 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4702 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4703 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4704 return USB3_LPM_DISABLED;
4705 }
4706 }
4707
4708 if (xhci->quirks & XHCI_INTEL_HOST)
4709 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4710 else
4711 timeout_ns = udev->u2_params.sel;
4712
4713 /* The U2 timeout is encoded in 256us intervals */
4714 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4715 /* If the necessary timeout value is bigger than what we can set in the
4716 * USB 3.0 hub, we have to disable hub-initiated U2.
4717 */
4718 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4719 return timeout_ns;
4720 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4721 "due to long timeout %llu ms\n", timeout_ns);
4722 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4723}
4724
4725static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4726 struct usb_device *udev,
4727 struct usb_endpoint_descriptor *desc,
4728 enum usb3_link_state state,
4729 u16 *timeout)
4730{
4731 if (state == USB3_LPM_U1)
4732 return xhci_calculate_u1_timeout(xhci, udev, desc);
4733 else if (state == USB3_LPM_U2)
4734 return xhci_calculate_u2_timeout(xhci, udev, desc);
4735
4736 return USB3_LPM_DISABLED;
4737}
4738
4739static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4740 struct usb_device *udev,
4741 struct usb_endpoint_descriptor *desc,
4742 enum usb3_link_state state,
4743 u16 *timeout)
4744{
4745 u16 alt_timeout;
4746
4747 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4748 desc, state, timeout);
4749
4750 /* If we found we can't enable hub-initiated LPM, and
4751 * the U1 or U2 exit latency was too high to allow
4752 * device-initiated LPM as well, then we will disable LPM
4753 * for this device, so stop searching any further.
4754 */
4755 if (alt_timeout == USB3_LPM_DISABLED) {
4756 *timeout = alt_timeout;
4757 return -E2BIG;
4758 }
4759 if (alt_timeout > *timeout)
4760 *timeout = alt_timeout;
4761 return 0;
4762}
4763
4764static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4765 struct usb_device *udev,
4766 struct usb_host_interface *alt,
4767 enum usb3_link_state state,
4768 u16 *timeout)
4769{
4770 int j;
4771
4772 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4773 if (xhci_update_timeout_for_endpoint(xhci, udev,
4774 &alt->endpoint[j].desc, state, timeout))
4775 return -E2BIG;
4776 continue;
4777 }
4778 return 0;
4779}
4780
4781static int xhci_check_intel_tier_policy(struct usb_device *udev,
4782 enum usb3_link_state state)
4783{
4784 struct usb_device *parent;
4785 unsigned int num_hubs;
4786
4787 if (state == USB3_LPM_U2)
4788 return 0;
4789
4790 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4791 for (parent = udev->parent, num_hubs = 0; parent->parent;
4792 parent = parent->parent)
4793 num_hubs++;
4794
4795 if (num_hubs < 2)
4796 return 0;
4797
4798 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4799 " below second-tier hub.\n");
4800 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4801 "to decrease power consumption.\n");
4802 return -E2BIG;
4803}
4804
4805static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4806 struct usb_device *udev,
4807 enum usb3_link_state state)
4808{
4809 if (xhci->quirks & XHCI_INTEL_HOST)
4810 return xhci_check_intel_tier_policy(udev, state);
4811 else
4812 return 0;
4813}
4814
4815/* Returns the U1 or U2 timeout that should be enabled.
4816 * If the tier check or timeout setting functions return with a non-zero exit
4817 * code, that means the timeout value has been finalized and we shouldn't look
4818 * at any more endpoints.
4819 */
4820static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4821 struct usb_device *udev, enum usb3_link_state state)
4822{
4823 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4824 struct usb_host_config *config;
4825 char *state_name;
4826 int i;
4827 u16 timeout = USB3_LPM_DISABLED;
4828
4829 if (state == USB3_LPM_U1)
4830 state_name = "U1";
4831 else if (state == USB3_LPM_U2)
4832 state_name = "U2";
4833 else {
4834 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4835 state);
4836 return timeout;
4837 }
4838
4839 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4840 return timeout;
4841
4842 /* Gather some information about the currently installed configuration
4843 * and alternate interface settings.
4844 */
4845 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4846 state, &timeout))
4847 return timeout;
4848
4849 config = udev->actconfig;
4850 if (!config)
4851 return timeout;
4852
4853 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4854 struct usb_driver *driver;
4855 struct usb_interface *intf = config->interface[i];
4856
4857 if (!intf)
4858 continue;
4859
4860 /* Check if any currently bound drivers want hub-initiated LPM
4861 * disabled.
4862 */
4863 if (intf->dev.driver) {
4864 driver = to_usb_driver(intf->dev.driver);
4865 if (driver && driver->disable_hub_initiated_lpm) {
4866 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4867 state_name, driver->name);
4868 timeout = xhci_get_timeout_no_hub_lpm(udev,
4869 state);
4870 if (timeout == USB3_LPM_DISABLED)
4871 return timeout;
4872 }
4873 }
4874
4875 /* Not sure how this could happen... */
4876 if (!intf->cur_altsetting)
4877 continue;
4878
4879 if (xhci_update_timeout_for_interface(xhci, udev,
4880 intf->cur_altsetting,
4881 state, &timeout))
4882 return timeout;
4883 }
4884 return timeout;
4885}
4886
4887static int calculate_max_exit_latency(struct usb_device *udev,
4888 enum usb3_link_state state_changed,
4889 u16 hub_encoded_timeout)
4890{
4891 unsigned long long u1_mel_us = 0;
4892 unsigned long long u2_mel_us = 0;
4893 unsigned long long mel_us = 0;
4894 bool disabling_u1;
4895 bool disabling_u2;
4896 bool enabling_u1;
4897 bool enabling_u2;
4898
4899 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4900 hub_encoded_timeout == USB3_LPM_DISABLED);
4901 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4902 hub_encoded_timeout == USB3_LPM_DISABLED);
4903
4904 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4905 hub_encoded_timeout != USB3_LPM_DISABLED);
4906 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4907 hub_encoded_timeout != USB3_LPM_DISABLED);
4908
4909 /* If U1 was already enabled and we're not disabling it,
4910 * or we're going to enable U1, account for the U1 max exit latency.
4911 */
4912 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4913 enabling_u1)
4914 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4915 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4916 enabling_u2)
4917 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4918
4919 if (u1_mel_us > u2_mel_us)
4920 mel_us = u1_mel_us;
4921 else
4922 mel_us = u2_mel_us;
4923 /* xHCI host controller max exit latency field is only 16 bits wide. */
4924 if (mel_us > MAX_EXIT) {
4925 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4926 "is too big.\n", mel_us);
4927 return -E2BIG;
4928 }
4929 return mel_us;
4930}
4931
4932/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4933static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4934 struct usb_device *udev, enum usb3_link_state state)
4935{
4936 struct xhci_hcd *xhci;
4937 u16 hub_encoded_timeout;
4938 int mel;
4939 int ret;
4940
4941 xhci = hcd_to_xhci(hcd);
4942 /* The LPM timeout values are pretty host-controller specific, so don't
4943 * enable hub-initiated timeouts unless the vendor has provided
4944 * information about their timeout algorithm.
4945 */
4946 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4947 !xhci->devs[udev->slot_id])
4948 return USB3_LPM_DISABLED;
4949
4950 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4951 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4952 if (mel < 0) {
4953 /* Max Exit Latency is too big, disable LPM. */
4954 hub_encoded_timeout = USB3_LPM_DISABLED;
4955 mel = 0;
4956 }
4957
4958 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4959 if (ret)
4960 return ret;
4961 return hub_encoded_timeout;
4962}
4963
4964static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4965 struct usb_device *udev, enum usb3_link_state state)
4966{
4967 struct xhci_hcd *xhci;
4968 u16 mel;
4969
4970 xhci = hcd_to_xhci(hcd);
4971 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4972 !xhci->devs[udev->slot_id])
4973 return 0;
4974
4975 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4976 return xhci_change_max_exit_latency(xhci, udev, mel);
4977}
4978#else /* CONFIG_PM */
4979
4980static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4981 struct usb_device *udev, int enable)
4982{
4983 return 0;
4984}
4985
4986static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4987{
4988 return 0;
4989}
4990
4991static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4992 struct usb_device *udev, enum usb3_link_state state)
4993{
4994 return USB3_LPM_DISABLED;
4995}
4996
4997static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4998 struct usb_device *udev, enum usb3_link_state state)
4999{
5000 return 0;
5001}
5002#endif /* CONFIG_PM */
5003
5004/*-------------------------------------------------------------------------*/
5005
5006/* Once a hub descriptor is fetched for a device, we need to update the xHC's
5007 * internal data structures for the device.
5008 */
5009static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5010 struct usb_tt *tt, gfp_t mem_flags)
5011{
5012 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5013 struct xhci_virt_device *vdev;
5014 struct xhci_command *config_cmd;
5015 struct xhci_input_control_ctx *ctrl_ctx;
5016 struct xhci_slot_ctx *slot_ctx;
5017 unsigned long flags;
5018 unsigned think_time;
5019 int ret;
5020
5021 /* Ignore root hubs */
5022 if (!hdev->parent)
5023 return 0;
5024
5025 vdev = xhci->devs[hdev->slot_id];
5026 if (!vdev) {
5027 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5028 return -EINVAL;
5029 }
5030
5031 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5032 if (!config_cmd)
5033 return -ENOMEM;
5034
5035 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5036 if (!ctrl_ctx) {
5037 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5038 __func__);
5039 xhci_free_command(xhci, config_cmd);
5040 return -ENOMEM;
5041 }
5042
5043 spin_lock_irqsave(&xhci->lock, flags);
5044 if (hdev->speed == USB_SPEED_HIGH &&
5045 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5046 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5047 xhci_free_command(xhci, config_cmd);
5048 spin_unlock_irqrestore(&xhci->lock, flags);
5049 return -ENOMEM;
5050 }
5051
5052 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5053 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5054 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5055 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5056 /*
5057 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5058 * but it may be already set to 1 when setup an xHCI virtual
5059 * device, so clear it anyway.
5060 */
5061 if (tt->multi)
5062 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5063 else if (hdev->speed == USB_SPEED_FULL)
5064 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5065
5066 if (xhci->hci_version > 0x95) {
5067 xhci_dbg(xhci, "xHCI version %x needs hub "
5068 "TT think time and number of ports\n",
5069 (unsigned int) xhci->hci_version);
5070 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5071 /* Set TT think time - convert from ns to FS bit times.
5072 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5073 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5074 *
5075 * xHCI 1.0: this field shall be 0 if the device is not a
5076 * High-spped hub.
5077 */
5078 think_time = tt->think_time;
5079 if (think_time != 0)
5080 think_time = (think_time / 666) - 1;
5081 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5082 slot_ctx->tt_info |=
5083 cpu_to_le32(TT_THINK_TIME(think_time));
5084 } else {
5085 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5086 "TT think time or number of ports\n",
5087 (unsigned int) xhci->hci_version);
5088 }
5089 slot_ctx->dev_state = 0;
5090 spin_unlock_irqrestore(&xhci->lock, flags);
5091
5092 xhci_dbg(xhci, "Set up %s for hub device.\n",
5093 (xhci->hci_version > 0x95) ?
5094 "configure endpoint" : "evaluate context");
5095
5096 /* Issue and wait for the configure endpoint or
5097 * evaluate context command.
5098 */
5099 if (xhci->hci_version > 0x95)
5100 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5101 false, false);
5102 else
5103 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5104 true, false);
5105
5106 xhci_free_command(xhci, config_cmd);
5107 return ret;
5108}
5109
5110static int xhci_get_frame(struct usb_hcd *hcd)
5111{
5112 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5113 /* EHCI mods by the periodic size. Why? */
5114 return readl(&xhci->run_regs->microframe_index) >> 3;
5115}
5116
5117int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5118{
5119 struct xhci_hcd *xhci;
5120 /*
5121 * TODO: Check with DWC3 clients for sysdev according to
5122 * quirks
5123 */
5124 struct device *dev = hcd->self.sysdev;
5125 unsigned int minor_rev;
5126 int retval;
5127
5128 /* Accept arbitrarily long scatter-gather lists */
5129 hcd->self.sg_tablesize = ~0;
5130
5131 /* support to build packet from discontinuous buffers */
5132 hcd->self.no_sg_constraint = 1;
5133
5134 /* XHCI controllers don't stop the ep queue on short packets :| */
5135 hcd->self.no_stop_on_short = 1;
5136
5137 xhci = hcd_to_xhci(hcd);
5138
5139 if (usb_hcd_is_primary_hcd(hcd)) {
5140 xhci->main_hcd = hcd;
5141 xhci->usb2_rhub.hcd = hcd;
5142 /* Mark the first roothub as being USB 2.0.
5143 * The xHCI driver will register the USB 3.0 roothub.
5144 */
5145 hcd->speed = HCD_USB2;
5146 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5147 /*
5148 * USB 2.0 roothub under xHCI has an integrated TT,
5149 * (rate matching hub) as opposed to having an OHCI/UHCI
5150 * companion controller.
5151 */
5152 hcd->has_tt = 1;
5153 } else {
5154 /*
5155 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5156 * should return 0x31 for sbrn, or that the minor revision
5157 * is a two digit BCD containig minor and sub-minor numbers.
5158 * This was later clarified in xHCI 1.2.
5159 *
5160 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5161 * minor revision set to 0x1 instead of 0x10.
5162 */
5163 if (xhci->usb3_rhub.min_rev == 0x1)
5164 minor_rev = 1;
5165 else
5166 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5167
5168 switch (minor_rev) {
5169 case 2:
5170 hcd->speed = HCD_USB32;
5171 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5172 hcd->self.root_hub->rx_lanes = 2;
5173 hcd->self.root_hub->tx_lanes = 2;
5174 break;
5175 case 1:
5176 hcd->speed = HCD_USB31;
5177 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5178 break;
5179 }
5180 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5181 minor_rev,
5182 minor_rev ? "Enhanced " : "");
5183
5184 xhci->usb3_rhub.hcd = hcd;
5185 /* xHCI private pointer was set in xhci_pci_probe for the second
5186 * registered roothub.
5187 */
5188 return 0;
5189 }
5190
5191 mutex_init(&xhci->mutex);
5192 xhci->cap_regs = hcd->regs;
5193 xhci->op_regs = hcd->regs +
5194 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5195 xhci->run_regs = hcd->regs +
5196 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5197 /* Cache read-only capability registers */
5198 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5199 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5200 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5201 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5202 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5203 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5204 if (xhci->hci_version > 0x100)
5205 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5206
5207 xhci->quirks |= quirks;
5208
5209 get_quirks(dev, xhci);
5210
5211 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5212 * success event after a short transfer. This quirk will ignore such
5213 * spurious event.
5214 */
5215 if (xhci->hci_version > 0x96)
5216 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5217
5218 /* Make sure the HC is halted. */
5219 retval = xhci_halt(xhci);
5220 if (retval)
5221 return retval;
5222
5223 xhci_zero_64b_regs(xhci);
5224
5225 xhci_dbg(xhci, "Resetting HCD\n");
5226 /* Reset the internal HC memory state and registers. */
5227 retval = xhci_reset(xhci);
5228 if (retval)
5229 return retval;
5230 xhci_dbg(xhci, "Reset complete\n");
5231
5232 /*
5233 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5234 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5235 * address memory pointers actually. So, this driver clears the AC64
5236 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5237 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5238 */
5239 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5240 xhci->hcc_params &= ~BIT(0);
5241
5242 /* Set dma_mask and coherent_dma_mask to 64-bits,
5243 * if xHC supports 64-bit addressing */
5244 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5245 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5246 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5247 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5248 } else {
5249 /*
5250 * This is to avoid error in cases where a 32-bit USB
5251 * controller is used on a 64-bit capable system.
5252 */
5253 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5254 if (retval)
5255 return retval;
5256 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5257 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5258 }
5259
5260 xhci_dbg(xhci, "Calling HCD init\n");
5261 /* Initialize HCD and host controller data structures. */
5262 retval = xhci_init(hcd);
5263 if (retval)
5264 return retval;
5265 xhci_dbg(xhci, "Called HCD init\n");
5266
5267 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5268 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5269
5270 return 0;
5271}
5272EXPORT_SYMBOL_GPL(xhci_gen_setup);
5273
5274static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5275 struct usb_host_endpoint *ep)
5276{
5277 struct xhci_hcd *xhci;
5278 struct usb_device *udev;
5279 unsigned int slot_id;
5280 unsigned int ep_index;
5281 unsigned long flags;
5282
5283 xhci = hcd_to_xhci(hcd);
5284
5285 spin_lock_irqsave(&xhci->lock, flags);
5286 udev = (struct usb_device *)ep->hcpriv;
5287 slot_id = udev->slot_id;
5288 ep_index = xhci_get_endpoint_index(&ep->desc);
5289
5290 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5291 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5292 spin_unlock_irqrestore(&xhci->lock, flags);
5293}
5294
5295static const struct hc_driver xhci_hc_driver = {
5296 .description = "xhci-hcd",
5297 .product_desc = "xHCI Host Controller",
5298 .hcd_priv_size = sizeof(struct xhci_hcd),
5299
5300 /*
5301 * generic hardware linkage
5302 */
5303 .irq = xhci_irq,
5304 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED,
5305
5306 /*
5307 * basic lifecycle operations
5308 */
5309 .reset = NULL, /* set in xhci_init_driver() */
5310 .start = xhci_run,
5311 .stop = xhci_stop,
5312 .shutdown = xhci_shutdown,
5313
5314 /*
5315 * managing i/o requests and associated device resources
5316 */
5317 .map_urb_for_dma = xhci_map_urb_for_dma,
5318 .urb_enqueue = xhci_urb_enqueue,
5319 .urb_dequeue = xhci_urb_dequeue,
5320 .alloc_dev = xhci_alloc_dev,
5321 .free_dev = xhci_free_dev,
5322 .alloc_streams = xhci_alloc_streams,
5323 .free_streams = xhci_free_streams,
5324 .add_endpoint = xhci_add_endpoint,
5325 .drop_endpoint = xhci_drop_endpoint,
5326 .endpoint_disable = xhci_endpoint_disable,
5327 .endpoint_reset = xhci_endpoint_reset,
5328 .check_bandwidth = xhci_check_bandwidth,
5329 .reset_bandwidth = xhci_reset_bandwidth,
5330 .address_device = xhci_address_device,
5331 .enable_device = xhci_enable_device,
5332 .update_hub_device = xhci_update_hub_device,
5333 .reset_device = xhci_discover_or_reset_device,
5334
5335 /*
5336 * scheduling support
5337 */
5338 .get_frame_number = xhci_get_frame,
5339
5340 /*
5341 * root hub support
5342 */
5343 .hub_control = xhci_hub_control,
5344 .hub_status_data = xhci_hub_status_data,
5345 .bus_suspend = xhci_bus_suspend,
5346 .bus_resume = xhci_bus_resume,
5347 .get_resuming_ports = xhci_get_resuming_ports,
5348
5349 /*
5350 * call back when device connected and addressed
5351 */
5352 .update_device = xhci_update_device,
5353 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5354 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5355 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5356 .find_raw_port_number = xhci_find_raw_port_number,
5357 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5358};
5359
5360void xhci_init_driver(struct hc_driver *drv,
5361 const struct xhci_driver_overrides *over)
5362{
5363 BUG_ON(!over);
5364
5365 /* Copy the generic table to drv then apply the overrides */
5366 *drv = xhci_hc_driver;
5367
5368 if (over) {
5369 drv->hcd_priv_size += over->extra_priv_size;
5370 if (over->reset)
5371 drv->reset = over->reset;
5372 if (over->start)
5373 drv->start = over->start;
5374 }
5375}
5376EXPORT_SYMBOL_GPL(xhci_init_driver);
5377
5378MODULE_DESCRIPTION(DRIVER_DESC);
5379MODULE_AUTHOR(DRIVER_AUTHOR);
5380MODULE_LICENSE("GPL");
5381
5382static int __init xhci_hcd_init(void)
5383{
5384 /*
5385 * Check the compiler generated sizes of structures that must be laid
5386 * out in specific ways for hardware access.
5387 */
5388 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5389 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5390 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5391 /* xhci_device_control has eight fields, and also
5392 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5393 */
5394 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5395 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5396 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5397 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5398 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5399 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5400 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5401
5402 if (usb_disabled())
5403 return -ENODEV;
5404
5405 xhci_debugfs_create_root();
5406
5407 return 0;
5408}
5409
5410/*
5411 * If an init function is provided, an exit function must also be provided
5412 * to allow module unload.
5413 */
5414static void __exit xhci_hcd_fini(void)
5415{
5416 xhci_debugfs_remove_root();
5417}
5418
5419module_init(xhci_hcd_init);
5420module_exit(xhci_hcd_fini);