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1/*
2 * drivers/spi/spi-fsl-dspi.c
3 *
4 * Copyright 2013 Freescale Semiconductor, Inc.
5 *
6 * Freescale DSPI driver
7 * This file contains a driver for the Freescale DSPI
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/dmaengine.h>
19#include <linux/dma-mapping.h>
20#include <linux/err.h>
21#include <linux/errno.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/math64.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/pinctrl/consumer.h>
30#include <linux/platform_device.h>
31#include <linux/pm_runtime.h>
32#include <linux/regmap.h>
33#include <linux/sched.h>
34#include <linux/spi/spi.h>
35#include <linux/spi/spi_bitbang.h>
36#include <linux/time.h>
37
38#define DRIVER_NAME "fsl-dspi"
39
40#define TRAN_STATE_RX_VOID 0x01
41#define TRAN_STATE_TX_VOID 0x02
42#define TRAN_STATE_WORD_ODD_NUM 0x04
43
44#define DSPI_FIFO_SIZE 4
45#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
46
47#define SPI_MCR 0x00
48#define SPI_MCR_MASTER (1 << 31)
49#define SPI_MCR_PCSIS (0x3F << 16)
50#define SPI_MCR_CLR_TXF (1 << 11)
51#define SPI_MCR_CLR_RXF (1 << 10)
52
53#define SPI_TCR 0x08
54#define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16)
55
56#define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
57#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
58#define SPI_CTAR_CPOL(x) ((x) << 26)
59#define SPI_CTAR_CPHA(x) ((x) << 25)
60#define SPI_CTAR_LSBFE(x) ((x) << 24)
61#define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
62#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
63#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
64#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
65#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
66#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
67#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
68#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
69#define SPI_CTAR_SCALE_BITS 0xf
70
71#define SPI_CTAR0_SLAVE 0x0c
72
73#define SPI_SR 0x2c
74#define SPI_SR_EOQF 0x10000000
75#define SPI_SR_TCFQF 0x80000000
76#define SPI_SR_CLEAR 0xdaad0000
77
78#define SPI_RSER_TFFFE BIT(25)
79#define SPI_RSER_TFFFD BIT(24)
80#define SPI_RSER_RFDFE BIT(17)
81#define SPI_RSER_RFDFD BIT(16)
82
83#define SPI_RSER 0x30
84#define SPI_RSER_EOQFE 0x10000000
85#define SPI_RSER_TCFQE 0x80000000
86
87#define SPI_PUSHR 0x34
88#define SPI_PUSHR_CONT (1 << 31)
89#define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28)
90#define SPI_PUSHR_EOQ (1 << 27)
91#define SPI_PUSHR_CTCNT (1 << 26)
92#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
93#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
94
95#define SPI_PUSHR_SLAVE 0x34
96
97#define SPI_POPR 0x38
98#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
99
100#define SPI_TXFR0 0x3c
101#define SPI_TXFR1 0x40
102#define SPI_TXFR2 0x44
103#define SPI_TXFR3 0x48
104#define SPI_RXFR0 0x7c
105#define SPI_RXFR1 0x80
106#define SPI_RXFR2 0x84
107#define SPI_RXFR3 0x88
108
109#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
110#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
111#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
112#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
113
114#define SPI_CS_INIT 0x01
115#define SPI_CS_ASSERT 0x02
116#define SPI_CS_DROP 0x04
117
118#define SPI_TCR_TCNT_MAX 0x10000
119
120#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
121
122struct chip_data {
123 u32 mcr_val;
124 u32 ctar_val;
125 u16 void_write_data;
126};
127
128enum dspi_trans_mode {
129 DSPI_EOQ_MODE = 0,
130 DSPI_TCFQ_MODE,
131 DSPI_DMA_MODE,
132};
133
134struct fsl_dspi_devtype_data {
135 enum dspi_trans_mode trans_mode;
136 u8 max_clock_factor;
137};
138
139static const struct fsl_dspi_devtype_data vf610_data = {
140 .trans_mode = DSPI_DMA_MODE,
141 .max_clock_factor = 2,
142};
143
144static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
145 .trans_mode = DSPI_TCFQ_MODE,
146 .max_clock_factor = 8,
147};
148
149static const struct fsl_dspi_devtype_data ls2085a_data = {
150 .trans_mode = DSPI_TCFQ_MODE,
151 .max_clock_factor = 8,
152};
153
154struct fsl_dspi_dma {
155 /* Length of transfer in words of DSPI_FIFO_SIZE */
156 u32 curr_xfer_len;
157
158 u32 *tx_dma_buf;
159 struct dma_chan *chan_tx;
160 dma_addr_t tx_dma_phys;
161 struct completion cmd_tx_complete;
162 struct dma_async_tx_descriptor *tx_desc;
163
164 u32 *rx_dma_buf;
165 struct dma_chan *chan_rx;
166 dma_addr_t rx_dma_phys;
167 struct completion cmd_rx_complete;
168 struct dma_async_tx_descriptor *rx_desc;
169};
170
171struct fsl_dspi {
172 struct spi_master *master;
173 struct platform_device *pdev;
174
175 struct regmap *regmap;
176 int irq;
177 struct clk *clk;
178
179 struct spi_transfer *cur_transfer;
180 struct spi_message *cur_msg;
181 struct chip_data *cur_chip;
182 size_t len;
183 void *tx;
184 void *tx_end;
185 void *rx;
186 void *rx_end;
187 char dataflags;
188 u8 cs;
189 u16 void_write_data;
190 u32 cs_change;
191 const struct fsl_dspi_devtype_data *devtype_data;
192
193 wait_queue_head_t waitq;
194 u32 waitflags;
195
196 u32 spi_tcnt;
197 struct fsl_dspi_dma *dma;
198};
199
200static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word);
201
202static inline int is_double_byte_mode(struct fsl_dspi *dspi)
203{
204 unsigned int val;
205
206 regmap_read(dspi->regmap, SPI_CTAR(0), &val);
207
208 return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
209}
210
211static void dspi_tx_dma_callback(void *arg)
212{
213 struct fsl_dspi *dspi = arg;
214 struct fsl_dspi_dma *dma = dspi->dma;
215
216 complete(&dma->cmd_tx_complete);
217}
218
219static void dspi_rx_dma_callback(void *arg)
220{
221 struct fsl_dspi *dspi = arg;
222 struct fsl_dspi_dma *dma = dspi->dma;
223 int rx_word;
224 int i;
225 u16 d;
226
227 rx_word = is_double_byte_mode(dspi);
228
229 if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) {
230 for (i = 0; i < dma->curr_xfer_len; i++) {
231 d = dspi->dma->rx_dma_buf[i];
232 rx_word ? (*(u16 *)dspi->rx = d) :
233 (*(u8 *)dspi->rx = d);
234 dspi->rx += rx_word + 1;
235 }
236 }
237
238 complete(&dma->cmd_rx_complete);
239}
240
241static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
242{
243 struct fsl_dspi_dma *dma = dspi->dma;
244 struct device *dev = &dspi->pdev->dev;
245 int time_left;
246 int tx_word;
247 int i;
248
249 tx_word = is_double_byte_mode(dspi);
250
251 for (i = 0; i < dma->curr_xfer_len; i++) {
252 dspi->dma->tx_dma_buf[i] = dspi_data_to_pushr(dspi, tx_word);
253 if ((dspi->cs_change) && (!dspi->len))
254 dspi->dma->tx_dma_buf[i] &= ~SPI_PUSHR_CONT;
255 }
256
257 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
258 dma->tx_dma_phys,
259 dma->curr_xfer_len *
260 DMA_SLAVE_BUSWIDTH_4_BYTES,
261 DMA_MEM_TO_DEV,
262 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
263 if (!dma->tx_desc) {
264 dev_err(dev, "Not able to get desc for DMA xfer\n");
265 return -EIO;
266 }
267
268 dma->tx_desc->callback = dspi_tx_dma_callback;
269 dma->tx_desc->callback_param = dspi;
270 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
271 dev_err(dev, "DMA submit failed\n");
272 return -EINVAL;
273 }
274
275 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
276 dma->rx_dma_phys,
277 dma->curr_xfer_len *
278 DMA_SLAVE_BUSWIDTH_4_BYTES,
279 DMA_DEV_TO_MEM,
280 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
281 if (!dma->rx_desc) {
282 dev_err(dev, "Not able to get desc for DMA xfer\n");
283 return -EIO;
284 }
285
286 dma->rx_desc->callback = dspi_rx_dma_callback;
287 dma->rx_desc->callback_param = dspi;
288 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
289 dev_err(dev, "DMA submit failed\n");
290 return -EINVAL;
291 }
292
293 reinit_completion(&dspi->dma->cmd_rx_complete);
294 reinit_completion(&dspi->dma->cmd_tx_complete);
295
296 dma_async_issue_pending(dma->chan_rx);
297 dma_async_issue_pending(dma->chan_tx);
298
299 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
300 DMA_COMPLETION_TIMEOUT);
301 if (time_left == 0) {
302 dev_err(dev, "DMA tx timeout\n");
303 dmaengine_terminate_all(dma->chan_tx);
304 dmaengine_terminate_all(dma->chan_rx);
305 return -ETIMEDOUT;
306 }
307
308 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
309 DMA_COMPLETION_TIMEOUT);
310 if (time_left == 0) {
311 dev_err(dev, "DMA rx timeout\n");
312 dmaengine_terminate_all(dma->chan_tx);
313 dmaengine_terminate_all(dma->chan_rx);
314 return -ETIMEDOUT;
315 }
316
317 return 0;
318}
319
320static int dspi_dma_xfer(struct fsl_dspi *dspi)
321{
322 struct fsl_dspi_dma *dma = dspi->dma;
323 struct device *dev = &dspi->pdev->dev;
324 int curr_remaining_bytes;
325 int bytes_per_buffer;
326 int word = 1;
327 int ret = 0;
328
329 if (is_double_byte_mode(dspi))
330 word = 2;
331 curr_remaining_bytes = dspi->len;
332 bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
333 while (curr_remaining_bytes) {
334 /* Check if current transfer fits the DMA buffer */
335 dma->curr_xfer_len = curr_remaining_bytes / word;
336 if (dma->curr_xfer_len > bytes_per_buffer)
337 dma->curr_xfer_len = bytes_per_buffer;
338
339 ret = dspi_next_xfer_dma_submit(dspi);
340 if (ret) {
341 dev_err(dev, "DMA transfer failed\n");
342 goto exit;
343
344 } else {
345 curr_remaining_bytes -= dma->curr_xfer_len * word;
346 if (curr_remaining_bytes < 0)
347 curr_remaining_bytes = 0;
348 }
349 }
350
351exit:
352 return ret;
353}
354
355static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
356{
357 struct fsl_dspi_dma *dma;
358 struct dma_slave_config cfg;
359 struct device *dev = &dspi->pdev->dev;
360 int ret;
361
362 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
363 if (!dma)
364 return -ENOMEM;
365
366 dma->chan_rx = dma_request_slave_channel(dev, "rx");
367 if (!dma->chan_rx) {
368 dev_err(dev, "rx dma channel not available\n");
369 ret = -ENODEV;
370 return ret;
371 }
372
373 dma->chan_tx = dma_request_slave_channel(dev, "tx");
374 if (!dma->chan_tx) {
375 dev_err(dev, "tx dma channel not available\n");
376 ret = -ENODEV;
377 goto err_tx_channel;
378 }
379
380 dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
381 &dma->tx_dma_phys, GFP_KERNEL);
382 if (!dma->tx_dma_buf) {
383 ret = -ENOMEM;
384 goto err_tx_dma_buf;
385 }
386
387 dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
388 &dma->rx_dma_phys, GFP_KERNEL);
389 if (!dma->rx_dma_buf) {
390 ret = -ENOMEM;
391 goto err_rx_dma_buf;
392 }
393
394 cfg.src_addr = phy_addr + SPI_POPR;
395 cfg.dst_addr = phy_addr + SPI_PUSHR;
396 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
397 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
398 cfg.src_maxburst = 1;
399 cfg.dst_maxburst = 1;
400
401 cfg.direction = DMA_DEV_TO_MEM;
402 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
403 if (ret) {
404 dev_err(dev, "can't configure rx dma channel\n");
405 ret = -EINVAL;
406 goto err_slave_config;
407 }
408
409 cfg.direction = DMA_MEM_TO_DEV;
410 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
411 if (ret) {
412 dev_err(dev, "can't configure tx dma channel\n");
413 ret = -EINVAL;
414 goto err_slave_config;
415 }
416
417 dspi->dma = dma;
418 init_completion(&dma->cmd_tx_complete);
419 init_completion(&dma->cmd_rx_complete);
420
421 return 0;
422
423err_slave_config:
424 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
425 dma->rx_dma_buf, dma->rx_dma_phys);
426err_rx_dma_buf:
427 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
428 dma->tx_dma_buf, dma->tx_dma_phys);
429err_tx_dma_buf:
430 dma_release_channel(dma->chan_tx);
431err_tx_channel:
432 dma_release_channel(dma->chan_rx);
433
434 devm_kfree(dev, dma);
435 dspi->dma = NULL;
436
437 return ret;
438}
439
440static void dspi_release_dma(struct fsl_dspi *dspi)
441{
442 struct fsl_dspi_dma *dma = dspi->dma;
443 struct device *dev = &dspi->pdev->dev;
444
445 if (dma) {
446 if (dma->chan_tx) {
447 dma_unmap_single(dev, dma->tx_dma_phys,
448 DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
449 dma_release_channel(dma->chan_tx);
450 }
451
452 if (dma->chan_rx) {
453 dma_unmap_single(dev, dma->rx_dma_phys,
454 DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
455 dma_release_channel(dma->chan_rx);
456 }
457 }
458}
459
460static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
461 unsigned long clkrate)
462{
463 /* Valid baud rate pre-scaler values */
464 int pbr_tbl[4] = {2, 3, 5, 7};
465 int brs[16] = { 2, 4, 6, 8,
466 16, 32, 64, 128,
467 256, 512, 1024, 2048,
468 4096, 8192, 16384, 32768 };
469 int scale_needed, scale, minscale = INT_MAX;
470 int i, j;
471
472 scale_needed = clkrate / speed_hz;
473 if (clkrate % speed_hz)
474 scale_needed++;
475
476 for (i = 0; i < ARRAY_SIZE(brs); i++)
477 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
478 scale = brs[i] * pbr_tbl[j];
479 if (scale >= scale_needed) {
480 if (scale < minscale) {
481 minscale = scale;
482 *br = i;
483 *pbr = j;
484 }
485 break;
486 }
487 }
488
489 if (minscale == INT_MAX) {
490 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
491 speed_hz, clkrate);
492 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
493 *br = ARRAY_SIZE(brs) - 1;
494 }
495}
496
497static void ns_delay_scale(char *psc, char *sc, int delay_ns,
498 unsigned long clkrate)
499{
500 int pscale_tbl[4] = {1, 3, 5, 7};
501 int scale_needed, scale, minscale = INT_MAX;
502 int i, j;
503 u32 remainder;
504
505 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
506 &remainder);
507 if (remainder)
508 scale_needed++;
509
510 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
511 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
512 scale = pscale_tbl[i] * (2 << j);
513 if (scale >= scale_needed) {
514 if (scale < minscale) {
515 minscale = scale;
516 *psc = i;
517 *sc = j;
518 }
519 break;
520 }
521 }
522
523 if (minscale == INT_MAX) {
524 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
525 delay_ns, clkrate);
526 *psc = ARRAY_SIZE(pscale_tbl) - 1;
527 *sc = SPI_CTAR_SCALE_BITS;
528 }
529}
530
531static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word)
532{
533 u16 d16;
534
535 if (!(dspi->dataflags & TRAN_STATE_TX_VOID))
536 d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx;
537 else
538 d16 = dspi->void_write_data;
539
540 dspi->tx += tx_word + 1;
541 dspi->len -= tx_word + 1;
542
543 return SPI_PUSHR_TXDATA(d16) |
544 SPI_PUSHR_PCS(dspi->cs) |
545 SPI_PUSHR_CTAS(0) |
546 SPI_PUSHR_CONT;
547}
548
549static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word)
550{
551 u16 d;
552 unsigned int val;
553
554 regmap_read(dspi->regmap, SPI_POPR, &val);
555 d = SPI_POPR_RXDATA(val);
556
557 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
558 rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d);
559
560 dspi->rx += rx_word + 1;
561}
562
563static int dspi_eoq_write(struct fsl_dspi *dspi)
564{
565 int tx_count = 0;
566 int tx_word;
567 u32 dspi_pushr = 0;
568
569 tx_word = is_double_byte_mode(dspi);
570
571 while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
572 /* If we are in word mode, only have a single byte to transfer
573 * switch to byte mode temporarily. Will switch back at the
574 * end of the transfer.
575 */
576 if (tx_word && (dspi->len == 1)) {
577 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
578 regmap_update_bits(dspi->regmap, SPI_CTAR(0),
579 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
580 tx_word = 0;
581 }
582
583 dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
584
585 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
586 /* last transfer in the transfer */
587 dspi_pushr |= SPI_PUSHR_EOQ;
588 if ((dspi->cs_change) && (!dspi->len))
589 dspi_pushr &= ~SPI_PUSHR_CONT;
590 } else if (tx_word && (dspi->len == 1))
591 dspi_pushr |= SPI_PUSHR_EOQ;
592
593 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
594
595 tx_count++;
596 }
597
598 return tx_count * (tx_word + 1);
599}
600
601static int dspi_eoq_read(struct fsl_dspi *dspi)
602{
603 int rx_count = 0;
604 int rx_word = is_double_byte_mode(dspi);
605
606 while ((dspi->rx < dspi->rx_end)
607 && (rx_count < DSPI_FIFO_SIZE)) {
608 if (rx_word && (dspi->rx_end - dspi->rx) == 1)
609 rx_word = 0;
610
611 dspi_data_from_popr(dspi, rx_word);
612 rx_count++;
613 }
614
615 return rx_count;
616}
617
618static int dspi_tcfq_write(struct fsl_dspi *dspi)
619{
620 int tx_word;
621 u32 dspi_pushr = 0;
622
623 tx_word = is_double_byte_mode(dspi);
624
625 if (tx_word && (dspi->len == 1)) {
626 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
627 regmap_update_bits(dspi->regmap, SPI_CTAR(0),
628 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
629 tx_word = 0;
630 }
631
632 dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
633
634 if ((dspi->cs_change) && (!dspi->len))
635 dspi_pushr &= ~SPI_PUSHR_CONT;
636
637 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
638
639 return tx_word + 1;
640}
641
642static void dspi_tcfq_read(struct fsl_dspi *dspi)
643{
644 int rx_word = is_double_byte_mode(dspi);
645
646 if (rx_word && (dspi->rx_end - dspi->rx) == 1)
647 rx_word = 0;
648
649 dspi_data_from_popr(dspi, rx_word);
650}
651
652static int dspi_transfer_one_message(struct spi_master *master,
653 struct spi_message *message)
654{
655 struct fsl_dspi *dspi = spi_master_get_devdata(master);
656 struct spi_device *spi = message->spi;
657 struct spi_transfer *transfer;
658 int status = 0;
659 enum dspi_trans_mode trans_mode;
660 u32 spi_tcr;
661
662 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
663 dspi->spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
664
665 message->actual_length = 0;
666
667 list_for_each_entry(transfer, &message->transfers, transfer_list) {
668 dspi->cur_transfer = transfer;
669 dspi->cur_msg = message;
670 dspi->cur_chip = spi_get_ctldata(spi);
671 dspi->cs = spi->chip_select;
672 dspi->cs_change = 0;
673 if (list_is_last(&dspi->cur_transfer->transfer_list,
674 &dspi->cur_msg->transfers) || transfer->cs_change)
675 dspi->cs_change = 1;
676 dspi->void_write_data = dspi->cur_chip->void_write_data;
677
678 dspi->dataflags = 0;
679 dspi->tx = (void *)transfer->tx_buf;
680 dspi->tx_end = dspi->tx + transfer->len;
681 dspi->rx = transfer->rx_buf;
682 dspi->rx_end = dspi->rx + transfer->len;
683 dspi->len = transfer->len;
684
685 if (!dspi->rx)
686 dspi->dataflags |= TRAN_STATE_RX_VOID;
687
688 if (!dspi->tx)
689 dspi->dataflags |= TRAN_STATE_TX_VOID;
690
691 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
692 regmap_update_bits(dspi->regmap, SPI_MCR,
693 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
694 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
695 regmap_write(dspi->regmap, SPI_CTAR(0),
696 dspi->cur_chip->ctar_val);
697
698 trans_mode = dspi->devtype_data->trans_mode;
699 switch (trans_mode) {
700 case DSPI_EOQ_MODE:
701 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
702 dspi_eoq_write(dspi);
703 break;
704 case DSPI_TCFQ_MODE:
705 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
706 dspi_tcfq_write(dspi);
707 break;
708 case DSPI_DMA_MODE:
709 regmap_write(dspi->regmap, SPI_RSER,
710 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
711 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
712 status = dspi_dma_xfer(dspi);
713 break;
714 default:
715 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
716 trans_mode);
717 status = -EINVAL;
718 goto out;
719 }
720
721 if (trans_mode != DSPI_DMA_MODE) {
722 if (wait_event_interruptible(dspi->waitq,
723 dspi->waitflags))
724 dev_err(&dspi->pdev->dev,
725 "wait transfer complete fail!\n");
726 dspi->waitflags = 0;
727 }
728
729 if (transfer->delay_usecs)
730 udelay(transfer->delay_usecs);
731 }
732
733out:
734 message->status = status;
735 spi_finalize_current_message(master);
736
737 return status;
738}
739
740static int dspi_setup(struct spi_device *spi)
741{
742 struct chip_data *chip;
743 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
744 u32 cs_sck_delay = 0, sck_cs_delay = 0;
745 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
746 unsigned char pasc = 0, asc = 0, fmsz = 0;
747 unsigned long clkrate;
748
749 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
750 fmsz = spi->bits_per_word - 1;
751 } else {
752 pr_err("Invalid wordsize\n");
753 return -ENODEV;
754 }
755
756 /* Only alloc on first setup */
757 chip = spi_get_ctldata(spi);
758 if (chip == NULL) {
759 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
760 if (!chip)
761 return -ENOMEM;
762 }
763
764 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
765 &cs_sck_delay);
766
767 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
768 &sck_cs_delay);
769
770 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
771 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
772
773 chip->void_write_data = 0;
774
775 clkrate = clk_get_rate(dspi->clk);
776 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
777
778 /* Set PCS to SCK delay scale values */
779 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
780
781 /* Set After SCK delay scale values */
782 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
783
784 chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
785 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
786 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
787 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
788 | SPI_CTAR_PCSSCK(pcssck)
789 | SPI_CTAR_CSSCK(cssck)
790 | SPI_CTAR_PASC(pasc)
791 | SPI_CTAR_ASC(asc)
792 | SPI_CTAR_PBR(pbr)
793 | SPI_CTAR_BR(br);
794
795 spi_set_ctldata(spi, chip);
796
797 return 0;
798}
799
800static void dspi_cleanup(struct spi_device *spi)
801{
802 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
803
804 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
805 spi->master->bus_num, spi->chip_select);
806
807 kfree(chip);
808}
809
810static irqreturn_t dspi_interrupt(int irq, void *dev_id)
811{
812 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
813 struct spi_message *msg = dspi->cur_msg;
814 enum dspi_trans_mode trans_mode;
815 u32 spi_sr, spi_tcr;
816 u32 spi_tcnt, tcnt_diff;
817 int tx_word;
818
819 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
820 regmap_write(dspi->regmap, SPI_SR, spi_sr);
821
822
823 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
824 tx_word = is_double_byte_mode(dspi);
825
826 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
827 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
828 /*
829 * The width of SPI Transfer Counter in SPI_TCR is 16bits,
830 * so the max couner is 65535. When the counter reach 65535,
831 * it will wrap around, counter reset to zero.
832 * spi_tcnt my be less than dspi->spi_tcnt, it means the
833 * counter already wrapped around.
834 * SPI Transfer Counter is a counter of transmitted frames.
835 * The size of frame maybe two bytes.
836 */
837 tcnt_diff = ((spi_tcnt + SPI_TCR_TCNT_MAX) - dspi->spi_tcnt)
838 % SPI_TCR_TCNT_MAX;
839 tcnt_diff *= (tx_word + 1);
840 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
841 tcnt_diff--;
842
843 msg->actual_length += tcnt_diff;
844
845 dspi->spi_tcnt = spi_tcnt;
846
847 trans_mode = dspi->devtype_data->trans_mode;
848 switch (trans_mode) {
849 case DSPI_EOQ_MODE:
850 dspi_eoq_read(dspi);
851 break;
852 case DSPI_TCFQ_MODE:
853 dspi_tcfq_read(dspi);
854 break;
855 default:
856 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
857 trans_mode);
858 return IRQ_HANDLED;
859 }
860
861 if (!dspi->len) {
862 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) {
863 regmap_update_bits(dspi->regmap,
864 SPI_CTAR(0),
865 SPI_FRAME_BITS_MASK,
866 SPI_FRAME_BITS(16));
867 dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM;
868 }
869
870 dspi->waitflags = 1;
871 wake_up_interruptible(&dspi->waitq);
872 } else {
873 switch (trans_mode) {
874 case DSPI_EOQ_MODE:
875 dspi_eoq_write(dspi);
876 break;
877 case DSPI_TCFQ_MODE:
878 dspi_tcfq_write(dspi);
879 break;
880 default:
881 dev_err(&dspi->pdev->dev,
882 "unsupported trans_mode %u\n",
883 trans_mode);
884 }
885 }
886 }
887
888 return IRQ_HANDLED;
889}
890
891static const struct of_device_id fsl_dspi_dt_ids[] = {
892 { .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, },
893 { .compatible = "fsl,ls1021a-v1.0-dspi",
894 .data = (void *)&ls1021a_v1_data, },
895 { .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, },
896 { /* sentinel */ }
897};
898MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
899
900#ifdef CONFIG_PM_SLEEP
901static int dspi_suspend(struct device *dev)
902{
903 struct spi_master *master = dev_get_drvdata(dev);
904 struct fsl_dspi *dspi = spi_master_get_devdata(master);
905
906 spi_master_suspend(master);
907 clk_disable_unprepare(dspi->clk);
908
909 pinctrl_pm_select_sleep_state(dev);
910
911 return 0;
912}
913
914static int dspi_resume(struct device *dev)
915{
916 struct spi_master *master = dev_get_drvdata(dev);
917 struct fsl_dspi *dspi = spi_master_get_devdata(master);
918 int ret;
919
920 pinctrl_pm_select_default_state(dev);
921
922 ret = clk_prepare_enable(dspi->clk);
923 if (ret)
924 return ret;
925 spi_master_resume(master);
926
927 return 0;
928}
929#endif /* CONFIG_PM_SLEEP */
930
931static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
932
933static const struct regmap_config dspi_regmap_config = {
934 .reg_bits = 32,
935 .val_bits = 32,
936 .reg_stride = 4,
937 .max_register = 0x88,
938};
939
940static void dspi_init(struct fsl_dspi *dspi)
941{
942 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
943}
944
945static int dspi_probe(struct platform_device *pdev)
946{
947 struct device_node *np = pdev->dev.of_node;
948 struct spi_master *master;
949 struct fsl_dspi *dspi;
950 struct resource *res;
951 void __iomem *base;
952 int ret = 0, cs_num, bus_num;
953
954 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
955 if (!master)
956 return -ENOMEM;
957
958 dspi = spi_master_get_devdata(master);
959 dspi->pdev = pdev;
960 dspi->master = master;
961
962 master->transfer = NULL;
963 master->setup = dspi_setup;
964 master->transfer_one_message = dspi_transfer_one_message;
965 master->dev.of_node = pdev->dev.of_node;
966
967 master->cleanup = dspi_cleanup;
968 master->mode_bits = SPI_CPOL | SPI_CPHA;
969 master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
970 SPI_BPW_MASK(16);
971
972 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
973 if (ret < 0) {
974 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
975 goto out_master_put;
976 }
977 master->num_chipselect = cs_num;
978
979 ret = of_property_read_u32(np, "bus-num", &bus_num);
980 if (ret < 0) {
981 dev_err(&pdev->dev, "can't get bus-num\n");
982 goto out_master_put;
983 }
984 master->bus_num = bus_num;
985
986 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
987 if (!dspi->devtype_data) {
988 dev_err(&pdev->dev, "can't get devtype_data\n");
989 ret = -EFAULT;
990 goto out_master_put;
991 }
992
993 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
994 base = devm_ioremap_resource(&pdev->dev, res);
995 if (IS_ERR(base)) {
996 ret = PTR_ERR(base);
997 goto out_master_put;
998 }
999
1000 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
1001 &dspi_regmap_config);
1002 if (IS_ERR(dspi->regmap)) {
1003 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1004 PTR_ERR(dspi->regmap));
1005 return PTR_ERR(dspi->regmap);
1006 }
1007
1008 dspi_init(dspi);
1009 dspi->irq = platform_get_irq(pdev, 0);
1010 if (dspi->irq < 0) {
1011 dev_err(&pdev->dev, "can't get platform irq\n");
1012 ret = dspi->irq;
1013 goto out_master_put;
1014 }
1015
1016 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
1017 pdev->name, dspi);
1018 if (ret < 0) {
1019 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1020 goto out_master_put;
1021 }
1022
1023 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1024 if (IS_ERR(dspi->clk)) {
1025 ret = PTR_ERR(dspi->clk);
1026 dev_err(&pdev->dev, "unable to get clock\n");
1027 goto out_master_put;
1028 }
1029 ret = clk_prepare_enable(dspi->clk);
1030 if (ret)
1031 goto out_master_put;
1032
1033 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1034 if (dspi_request_dma(dspi, res->start)) {
1035 dev_err(&pdev->dev, "can't get dma channels\n");
1036 goto out_clk_put;
1037 }
1038 }
1039
1040 master->max_speed_hz =
1041 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1042
1043 init_waitqueue_head(&dspi->waitq);
1044 platform_set_drvdata(pdev, master);
1045
1046 ret = spi_register_master(master);
1047 if (ret != 0) {
1048 dev_err(&pdev->dev, "Problem registering DSPI master\n");
1049 goto out_clk_put;
1050 }
1051
1052 return ret;
1053
1054out_clk_put:
1055 clk_disable_unprepare(dspi->clk);
1056out_master_put:
1057 spi_master_put(master);
1058
1059 return ret;
1060}
1061
1062static int dspi_remove(struct platform_device *pdev)
1063{
1064 struct spi_master *master = platform_get_drvdata(pdev);
1065 struct fsl_dspi *dspi = spi_master_get_devdata(master);
1066
1067 /* Disconnect from the SPI framework */
1068 dspi_release_dma(dspi);
1069 clk_disable_unprepare(dspi->clk);
1070 spi_unregister_master(dspi->master);
1071
1072 return 0;
1073}
1074
1075static struct platform_driver fsl_dspi_driver = {
1076 .driver.name = DRIVER_NAME,
1077 .driver.of_match_table = fsl_dspi_dt_ids,
1078 .driver.owner = THIS_MODULE,
1079 .driver.pm = &dspi_pm,
1080 .probe = dspi_probe,
1081 .remove = dspi_remove,
1082};
1083module_platform_driver(fsl_dspi_driver);
1084
1085MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1086MODULE_LICENSE("GPL");
1087MODULE_ALIAS("platform:" DRIVER_NAME);
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4//
5// Freescale DSPI driver
6// This file contains a driver for the Freescale DSPI
7
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/dmaengine.h>
11#include <linux/dma-mapping.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/pinctrl/consumer.h>
17#include <linux/regmap.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/spi-fsl-dspi.h>
20
21#define DRIVER_NAME "fsl-dspi"
22
23#ifdef CONFIG_M5441x
24#define DSPI_FIFO_SIZE 16
25#else
26#define DSPI_FIFO_SIZE 4
27#endif
28#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
29
30#define SPI_MCR 0x00
31#define SPI_MCR_MASTER BIT(31)
32#define SPI_MCR_PCSIS (0x3F << 16)
33#define SPI_MCR_CLR_TXF BIT(11)
34#define SPI_MCR_CLR_RXF BIT(10)
35#define SPI_MCR_XSPI BIT(3)
36
37#define SPI_TCR 0x08
38#define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
39
40#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
41#define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
42#define SPI_CTAR_CPOL BIT(26)
43#define SPI_CTAR_CPHA BIT(25)
44#define SPI_CTAR_LSBFE BIT(24)
45#define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))
46#define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))
47#define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))
48#define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))
49#define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))
50#define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))
51#define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))
52#define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))
53#define SPI_CTAR_SCALE_BITS 0xf
54
55#define SPI_CTAR0_SLAVE 0x0c
56
57#define SPI_SR 0x2c
58#define SPI_SR_TCFQF BIT(31)
59#define SPI_SR_EOQF BIT(28)
60#define SPI_SR_TFUF BIT(27)
61#define SPI_SR_TFFF BIT(25)
62#define SPI_SR_CMDTCF BIT(23)
63#define SPI_SR_SPEF BIT(21)
64#define SPI_SR_RFOF BIT(19)
65#define SPI_SR_TFIWF BIT(18)
66#define SPI_SR_RFDF BIT(17)
67#define SPI_SR_CMDFFF BIT(16)
68#define SPI_SR_CLEAR (SPI_SR_TCFQF | SPI_SR_EOQF | \
69 SPI_SR_TFUF | SPI_SR_TFFF | \
70 SPI_SR_CMDTCF | SPI_SR_SPEF | \
71 SPI_SR_RFOF | SPI_SR_TFIWF | \
72 SPI_SR_RFDF | SPI_SR_CMDFFF)
73
74#define SPI_RSER_TFFFE BIT(25)
75#define SPI_RSER_TFFFD BIT(24)
76#define SPI_RSER_RFDFE BIT(17)
77#define SPI_RSER_RFDFD BIT(16)
78
79#define SPI_RSER 0x30
80#define SPI_RSER_TCFQE BIT(31)
81#define SPI_RSER_EOQFE BIT(28)
82
83#define SPI_PUSHR 0x34
84#define SPI_PUSHR_CMD_CONT BIT(15)
85#define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))
86#define SPI_PUSHR_CMD_EOQ BIT(11)
87#define SPI_PUSHR_CMD_CTCNT BIT(10)
88#define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))
89
90#define SPI_PUSHR_SLAVE 0x34
91
92#define SPI_POPR 0x38
93
94#define SPI_TXFR0 0x3c
95#define SPI_TXFR1 0x40
96#define SPI_TXFR2 0x44
97#define SPI_TXFR3 0x48
98#define SPI_RXFR0 0x7c
99#define SPI_RXFR1 0x80
100#define SPI_RXFR2 0x84
101#define SPI_RXFR3 0x88
102
103#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
104#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
105#define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
106
107#define SPI_SREX 0x13c
108
109#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
110#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
111
112/* Register offsets for regmap_pushr */
113#define PUSHR_CMD 0x0
114#define PUSHR_TX 0x2
115
116#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
117
118struct chip_data {
119 u32 ctar_val;
120 u16 void_write_data;
121};
122
123enum dspi_trans_mode {
124 DSPI_EOQ_MODE = 0,
125 DSPI_TCFQ_MODE,
126 DSPI_DMA_MODE,
127};
128
129struct fsl_dspi_devtype_data {
130 enum dspi_trans_mode trans_mode;
131 u8 max_clock_factor;
132 bool xspi_mode;
133};
134
135static const struct fsl_dspi_devtype_data vf610_data = {
136 .trans_mode = DSPI_DMA_MODE,
137 .max_clock_factor = 2,
138};
139
140static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
141 .trans_mode = DSPI_TCFQ_MODE,
142 .max_clock_factor = 8,
143 .xspi_mode = true,
144};
145
146static const struct fsl_dspi_devtype_data ls2085a_data = {
147 .trans_mode = DSPI_TCFQ_MODE,
148 .max_clock_factor = 8,
149};
150
151static const struct fsl_dspi_devtype_data coldfire_data = {
152 .trans_mode = DSPI_EOQ_MODE,
153 .max_clock_factor = 8,
154};
155
156struct fsl_dspi_dma {
157 /* Length of transfer in words of DSPI_FIFO_SIZE */
158 u32 curr_xfer_len;
159
160 u32 *tx_dma_buf;
161 struct dma_chan *chan_tx;
162 dma_addr_t tx_dma_phys;
163 struct completion cmd_tx_complete;
164 struct dma_async_tx_descriptor *tx_desc;
165
166 u32 *rx_dma_buf;
167 struct dma_chan *chan_rx;
168 dma_addr_t rx_dma_phys;
169 struct completion cmd_rx_complete;
170 struct dma_async_tx_descriptor *rx_desc;
171};
172
173struct fsl_dspi {
174 struct spi_controller *ctlr;
175 struct platform_device *pdev;
176
177 struct regmap *regmap;
178 struct regmap *regmap_pushr;
179 int irq;
180 struct clk *clk;
181
182 struct spi_transfer *cur_transfer;
183 struct spi_message *cur_msg;
184 struct chip_data *cur_chip;
185 size_t len;
186 const void *tx;
187 void *rx;
188 void *rx_end;
189 u16 void_write_data;
190 u16 tx_cmd;
191 u8 bits_per_word;
192 u8 bytes_per_word;
193 const struct fsl_dspi_devtype_data *devtype_data;
194
195 wait_queue_head_t waitq;
196 u32 waitflags;
197
198 struct fsl_dspi_dma *dma;
199};
200
201static u32 dspi_pop_tx(struct fsl_dspi *dspi)
202{
203 u32 txdata = 0;
204
205 if (dspi->tx) {
206 if (dspi->bytes_per_word == 1)
207 txdata = *(u8 *)dspi->tx;
208 else if (dspi->bytes_per_word == 2)
209 txdata = *(u16 *)dspi->tx;
210 else /* dspi->bytes_per_word == 4 */
211 txdata = *(u32 *)dspi->tx;
212 dspi->tx += dspi->bytes_per_word;
213 }
214 dspi->len -= dspi->bytes_per_word;
215 return txdata;
216}
217
218static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
219{
220 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
221
222 if (spi_controller_is_slave(dspi->ctlr))
223 return data;
224
225 if (dspi->len > 0)
226 cmd |= SPI_PUSHR_CMD_CONT;
227 return cmd << 16 | data;
228}
229
230static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
231{
232 if (!dspi->rx)
233 return;
234
235 /* Mask off undefined bits */
236 rxdata &= (1 << dspi->bits_per_word) - 1;
237
238 if (dspi->bytes_per_word == 1)
239 *(u8 *)dspi->rx = rxdata;
240 else if (dspi->bytes_per_word == 2)
241 *(u16 *)dspi->rx = rxdata;
242 else /* dspi->bytes_per_word == 4 */
243 *(u32 *)dspi->rx = rxdata;
244 dspi->rx += dspi->bytes_per_word;
245}
246
247static void dspi_tx_dma_callback(void *arg)
248{
249 struct fsl_dspi *dspi = arg;
250 struct fsl_dspi_dma *dma = dspi->dma;
251
252 complete(&dma->cmd_tx_complete);
253}
254
255static void dspi_rx_dma_callback(void *arg)
256{
257 struct fsl_dspi *dspi = arg;
258 struct fsl_dspi_dma *dma = dspi->dma;
259 int i;
260
261 if (dspi->rx) {
262 for (i = 0; i < dma->curr_xfer_len; i++)
263 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
264 }
265
266 complete(&dma->cmd_rx_complete);
267}
268
269static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
270{
271 struct device *dev = &dspi->pdev->dev;
272 struct fsl_dspi_dma *dma = dspi->dma;
273 int time_left;
274 int i;
275
276 for (i = 0; i < dma->curr_xfer_len; i++)
277 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
278
279 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
280 dma->tx_dma_phys,
281 dma->curr_xfer_len *
282 DMA_SLAVE_BUSWIDTH_4_BYTES,
283 DMA_MEM_TO_DEV,
284 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
285 if (!dma->tx_desc) {
286 dev_err(dev, "Not able to get desc for DMA xfer\n");
287 return -EIO;
288 }
289
290 dma->tx_desc->callback = dspi_tx_dma_callback;
291 dma->tx_desc->callback_param = dspi;
292 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
293 dev_err(dev, "DMA submit failed\n");
294 return -EINVAL;
295 }
296
297 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
298 dma->rx_dma_phys,
299 dma->curr_xfer_len *
300 DMA_SLAVE_BUSWIDTH_4_BYTES,
301 DMA_DEV_TO_MEM,
302 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
303 if (!dma->rx_desc) {
304 dev_err(dev, "Not able to get desc for DMA xfer\n");
305 return -EIO;
306 }
307
308 dma->rx_desc->callback = dspi_rx_dma_callback;
309 dma->rx_desc->callback_param = dspi;
310 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
311 dev_err(dev, "DMA submit failed\n");
312 return -EINVAL;
313 }
314
315 reinit_completion(&dspi->dma->cmd_rx_complete);
316 reinit_completion(&dspi->dma->cmd_tx_complete);
317
318 dma_async_issue_pending(dma->chan_rx);
319 dma_async_issue_pending(dma->chan_tx);
320
321 if (spi_controller_is_slave(dspi->ctlr)) {
322 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
323 return 0;
324 }
325
326 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
327 DMA_COMPLETION_TIMEOUT);
328 if (time_left == 0) {
329 dev_err(dev, "DMA tx timeout\n");
330 dmaengine_terminate_all(dma->chan_tx);
331 dmaengine_terminate_all(dma->chan_rx);
332 return -ETIMEDOUT;
333 }
334
335 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
336 DMA_COMPLETION_TIMEOUT);
337 if (time_left == 0) {
338 dev_err(dev, "DMA rx timeout\n");
339 dmaengine_terminate_all(dma->chan_tx);
340 dmaengine_terminate_all(dma->chan_rx);
341 return -ETIMEDOUT;
342 }
343
344 return 0;
345}
346
347static int dspi_dma_xfer(struct fsl_dspi *dspi)
348{
349 struct spi_message *message = dspi->cur_msg;
350 struct device *dev = &dspi->pdev->dev;
351 struct fsl_dspi_dma *dma = dspi->dma;
352 int curr_remaining_bytes;
353 int bytes_per_buffer;
354 int ret = 0;
355
356 curr_remaining_bytes = dspi->len;
357 bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
358 while (curr_remaining_bytes) {
359 /* Check if current transfer fits the DMA buffer */
360 dma->curr_xfer_len = curr_remaining_bytes
361 / dspi->bytes_per_word;
362 if (dma->curr_xfer_len > bytes_per_buffer)
363 dma->curr_xfer_len = bytes_per_buffer;
364
365 ret = dspi_next_xfer_dma_submit(dspi);
366 if (ret) {
367 dev_err(dev, "DMA transfer failed\n");
368 goto exit;
369
370 } else {
371 const int len =
372 dma->curr_xfer_len * dspi->bytes_per_word;
373 curr_remaining_bytes -= len;
374 message->actual_length += len;
375 if (curr_remaining_bytes < 0)
376 curr_remaining_bytes = 0;
377 }
378 }
379
380exit:
381 return ret;
382}
383
384static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
385{
386 struct device *dev = &dspi->pdev->dev;
387 struct dma_slave_config cfg;
388 struct fsl_dspi_dma *dma;
389 int ret;
390
391 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
392 if (!dma)
393 return -ENOMEM;
394
395 dma->chan_rx = dma_request_slave_channel(dev, "rx");
396 if (!dma->chan_rx) {
397 dev_err(dev, "rx dma channel not available\n");
398 ret = -ENODEV;
399 return ret;
400 }
401
402 dma->chan_tx = dma_request_slave_channel(dev, "tx");
403 if (!dma->chan_tx) {
404 dev_err(dev, "tx dma channel not available\n");
405 ret = -ENODEV;
406 goto err_tx_channel;
407 }
408
409 dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
410 &dma->tx_dma_phys, GFP_KERNEL);
411 if (!dma->tx_dma_buf) {
412 ret = -ENOMEM;
413 goto err_tx_dma_buf;
414 }
415
416 dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
417 &dma->rx_dma_phys, GFP_KERNEL);
418 if (!dma->rx_dma_buf) {
419 ret = -ENOMEM;
420 goto err_rx_dma_buf;
421 }
422
423 cfg.src_addr = phy_addr + SPI_POPR;
424 cfg.dst_addr = phy_addr + SPI_PUSHR;
425 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
426 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
427 cfg.src_maxburst = 1;
428 cfg.dst_maxburst = 1;
429
430 cfg.direction = DMA_DEV_TO_MEM;
431 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
432 if (ret) {
433 dev_err(dev, "can't configure rx dma channel\n");
434 ret = -EINVAL;
435 goto err_slave_config;
436 }
437
438 cfg.direction = DMA_MEM_TO_DEV;
439 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
440 if (ret) {
441 dev_err(dev, "can't configure tx dma channel\n");
442 ret = -EINVAL;
443 goto err_slave_config;
444 }
445
446 dspi->dma = dma;
447 init_completion(&dma->cmd_tx_complete);
448 init_completion(&dma->cmd_rx_complete);
449
450 return 0;
451
452err_slave_config:
453 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
454 dma->rx_dma_buf, dma->rx_dma_phys);
455err_rx_dma_buf:
456 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
457 dma->tx_dma_buf, dma->tx_dma_phys);
458err_tx_dma_buf:
459 dma_release_channel(dma->chan_tx);
460err_tx_channel:
461 dma_release_channel(dma->chan_rx);
462
463 devm_kfree(dev, dma);
464 dspi->dma = NULL;
465
466 return ret;
467}
468
469static void dspi_release_dma(struct fsl_dspi *dspi)
470{
471 struct fsl_dspi_dma *dma = dspi->dma;
472 struct device *dev = &dspi->pdev->dev;
473
474 if (!dma)
475 return;
476
477 if (dma->chan_tx) {
478 dma_unmap_single(dev, dma->tx_dma_phys,
479 DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
480 dma_release_channel(dma->chan_tx);
481 }
482
483 if (dma->chan_rx) {
484 dma_unmap_single(dev, dma->rx_dma_phys,
485 DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
486 dma_release_channel(dma->chan_rx);
487 }
488}
489
490static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
491 unsigned long clkrate)
492{
493 /* Valid baud rate pre-scaler values */
494 int pbr_tbl[4] = {2, 3, 5, 7};
495 int brs[16] = { 2, 4, 6, 8,
496 16, 32, 64, 128,
497 256, 512, 1024, 2048,
498 4096, 8192, 16384, 32768 };
499 int scale_needed, scale, minscale = INT_MAX;
500 int i, j;
501
502 scale_needed = clkrate / speed_hz;
503 if (clkrate % speed_hz)
504 scale_needed++;
505
506 for (i = 0; i < ARRAY_SIZE(brs); i++)
507 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
508 scale = brs[i] * pbr_tbl[j];
509 if (scale >= scale_needed) {
510 if (scale < minscale) {
511 minscale = scale;
512 *br = i;
513 *pbr = j;
514 }
515 break;
516 }
517 }
518
519 if (minscale == INT_MAX) {
520 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
521 speed_hz, clkrate);
522 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
523 *br = ARRAY_SIZE(brs) - 1;
524 }
525}
526
527static void ns_delay_scale(char *psc, char *sc, int delay_ns,
528 unsigned long clkrate)
529{
530 int scale_needed, scale, minscale = INT_MAX;
531 int pscale_tbl[4] = {1, 3, 5, 7};
532 u32 remainder;
533 int i, j;
534
535 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
536 &remainder);
537 if (remainder)
538 scale_needed++;
539
540 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
541 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
542 scale = pscale_tbl[i] * (2 << j);
543 if (scale >= scale_needed) {
544 if (scale < minscale) {
545 minscale = scale;
546 *psc = i;
547 *sc = j;
548 }
549 break;
550 }
551 }
552
553 if (minscale == INT_MAX) {
554 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
555 delay_ns, clkrate);
556 *psc = ARRAY_SIZE(pscale_tbl) - 1;
557 *sc = SPI_CTAR_SCALE_BITS;
558 }
559}
560
561static void fifo_write(struct fsl_dspi *dspi)
562{
563 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
564}
565
566static void cmd_fifo_write(struct fsl_dspi *dspi)
567{
568 u16 cmd = dspi->tx_cmd;
569
570 if (dspi->len > 0)
571 cmd |= SPI_PUSHR_CMD_CONT;
572 regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd);
573}
574
575static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata)
576{
577 regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata);
578}
579
580static void dspi_tcfq_write(struct fsl_dspi *dspi)
581{
582 /* Clear transfer count */
583 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
584
585 if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) {
586 /* Write two TX FIFO entries first, and then the corresponding
587 * CMD FIFO entry.
588 */
589 u32 data = dspi_pop_tx(dspi);
590
591 if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE) {
592 /* LSB */
593 tx_fifo_write(dspi, data & 0xFFFF);
594 tx_fifo_write(dspi, data >> 16);
595 } else {
596 /* MSB */
597 tx_fifo_write(dspi, data >> 16);
598 tx_fifo_write(dspi, data & 0xFFFF);
599 }
600 cmd_fifo_write(dspi);
601 } else {
602 /* Write one entry to both TX FIFO and CMD FIFO
603 * simultaneously.
604 */
605 fifo_write(dspi);
606 }
607}
608
609static u32 fifo_read(struct fsl_dspi *dspi)
610{
611 u32 rxdata = 0;
612
613 regmap_read(dspi->regmap, SPI_POPR, &rxdata);
614 return rxdata;
615}
616
617static void dspi_tcfq_read(struct fsl_dspi *dspi)
618{
619 dspi_push_rx(dspi, fifo_read(dspi));
620}
621
622static void dspi_eoq_write(struct fsl_dspi *dspi)
623{
624 int fifo_size = DSPI_FIFO_SIZE;
625 u16 xfer_cmd = dspi->tx_cmd;
626
627 /* Fill TX FIFO with as many transfers as possible */
628 while (dspi->len && fifo_size--) {
629 dspi->tx_cmd = xfer_cmd;
630 /* Request EOQF for last transfer in FIFO */
631 if (dspi->len == dspi->bytes_per_word || fifo_size == 0)
632 dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
633 /* Clear transfer count for first transfer in FIFO */
634 if (fifo_size == (DSPI_FIFO_SIZE - 1))
635 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
636 /* Write combined TX FIFO and CMD FIFO entry */
637 fifo_write(dspi);
638 }
639}
640
641static void dspi_eoq_read(struct fsl_dspi *dspi)
642{
643 int fifo_size = DSPI_FIFO_SIZE;
644
645 /* Read one FIFO entry and push to rx buffer */
646 while ((dspi->rx < dspi->rx_end) && fifo_size--)
647 dspi_push_rx(dspi, fifo_read(dspi));
648}
649
650static int dspi_rxtx(struct fsl_dspi *dspi)
651{
652 struct spi_message *msg = dspi->cur_msg;
653 enum dspi_trans_mode trans_mode;
654 u16 spi_tcnt;
655 u32 spi_tcr;
656
657 /* Get transfer counter (in number of SPI transfers). It was
658 * reset to 0 when transfer(s) were started.
659 */
660 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
661 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
662 /* Update total number of bytes that were transferred */
663 msg->actual_length += spi_tcnt * dspi->bytes_per_word;
664
665 trans_mode = dspi->devtype_data->trans_mode;
666 if (trans_mode == DSPI_EOQ_MODE)
667 dspi_eoq_read(dspi);
668 else if (trans_mode == DSPI_TCFQ_MODE)
669 dspi_tcfq_read(dspi);
670
671 if (!dspi->len)
672 /* Success! */
673 return 0;
674
675 if (trans_mode == DSPI_EOQ_MODE)
676 dspi_eoq_write(dspi);
677 else if (trans_mode == DSPI_TCFQ_MODE)
678 dspi_tcfq_write(dspi);
679
680 return -EINPROGRESS;
681}
682
683static int dspi_poll(struct fsl_dspi *dspi)
684{
685 int tries = 1000;
686 u32 spi_sr;
687
688 do {
689 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
690 regmap_write(dspi->regmap, SPI_SR, spi_sr);
691
692 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF))
693 break;
694 } while (--tries);
695
696 if (!tries)
697 return -ETIMEDOUT;
698
699 return dspi_rxtx(dspi);
700}
701
702static irqreturn_t dspi_interrupt(int irq, void *dev_id)
703{
704 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
705 u32 spi_sr;
706
707 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
708 regmap_write(dspi->regmap, SPI_SR, spi_sr);
709
710 if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)))
711 return IRQ_NONE;
712
713 if (dspi_rxtx(dspi) == 0) {
714 dspi->waitflags = 1;
715 wake_up_interruptible(&dspi->waitq);
716 }
717
718 return IRQ_HANDLED;
719}
720
721static int dspi_transfer_one_message(struct spi_controller *ctlr,
722 struct spi_message *message)
723{
724 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
725 struct spi_device *spi = message->spi;
726 enum dspi_trans_mode trans_mode;
727 struct spi_transfer *transfer;
728 int status = 0;
729
730 message->actual_length = 0;
731
732 list_for_each_entry(transfer, &message->transfers, transfer_list) {
733 dspi->cur_transfer = transfer;
734 dspi->cur_msg = message;
735 dspi->cur_chip = spi_get_ctldata(spi);
736 /* Prepare command word for CMD FIFO */
737 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
738 SPI_PUSHR_CMD_PCS(spi->chip_select);
739 if (list_is_last(&dspi->cur_transfer->transfer_list,
740 &dspi->cur_msg->transfers)) {
741 /* Leave PCS activated after last transfer when
742 * cs_change is set.
743 */
744 if (transfer->cs_change)
745 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
746 } else {
747 /* Keep PCS active between transfers in same message
748 * when cs_change is not set, and de-activate PCS
749 * between transfers in the same message when
750 * cs_change is set.
751 */
752 if (!transfer->cs_change)
753 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
754 }
755
756 dspi->void_write_data = dspi->cur_chip->void_write_data;
757
758 dspi->tx = transfer->tx_buf;
759 dspi->rx = transfer->rx_buf;
760 dspi->rx_end = dspi->rx + transfer->len;
761 dspi->len = transfer->len;
762 /* Validated transfer specific frame size (defaults applied) */
763 dspi->bits_per_word = transfer->bits_per_word;
764 if (transfer->bits_per_word <= 8)
765 dspi->bytes_per_word = 1;
766 else if (transfer->bits_per_word <= 16)
767 dspi->bytes_per_word = 2;
768 else
769 dspi->bytes_per_word = 4;
770
771 regmap_update_bits(dspi->regmap, SPI_MCR,
772 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
773 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
774 regmap_write(dspi->regmap, SPI_CTAR(0),
775 dspi->cur_chip->ctar_val |
776 SPI_FRAME_BITS(transfer->bits_per_word));
777 if (dspi->devtype_data->xspi_mode)
778 regmap_write(dspi->regmap, SPI_CTARE(0),
779 SPI_FRAME_EBITS(transfer->bits_per_word) |
780 SPI_CTARE_DTCP(1));
781
782 trans_mode = dspi->devtype_data->trans_mode;
783 switch (trans_mode) {
784 case DSPI_EOQ_MODE:
785 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
786 dspi_eoq_write(dspi);
787 break;
788 case DSPI_TCFQ_MODE:
789 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
790 dspi_tcfq_write(dspi);
791 break;
792 case DSPI_DMA_MODE:
793 regmap_write(dspi->regmap, SPI_RSER,
794 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
795 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
796 status = dspi_dma_xfer(dspi);
797 break;
798 default:
799 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
800 trans_mode);
801 status = -EINVAL;
802 goto out;
803 }
804
805 if (!dspi->irq) {
806 do {
807 status = dspi_poll(dspi);
808 } while (status == -EINPROGRESS);
809 } else if (trans_mode != DSPI_DMA_MODE) {
810 status = wait_event_interruptible(dspi->waitq,
811 dspi->waitflags);
812 dspi->waitflags = 0;
813 }
814 if (status)
815 dev_err(&dspi->pdev->dev,
816 "Waiting for transfer to complete failed!\n");
817
818 if (transfer->delay_usecs)
819 udelay(transfer->delay_usecs);
820 }
821
822out:
823 message->status = status;
824 spi_finalize_current_message(ctlr);
825
826 return status;
827}
828
829static int dspi_setup(struct spi_device *spi)
830{
831 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
832 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
833 u32 cs_sck_delay = 0, sck_cs_delay = 0;
834 struct fsl_dspi_platform_data *pdata;
835 unsigned char pasc = 0, asc = 0;
836 struct chip_data *chip;
837 unsigned long clkrate;
838
839 /* Only alloc on first setup */
840 chip = spi_get_ctldata(spi);
841 if (chip == NULL) {
842 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
843 if (!chip)
844 return -ENOMEM;
845 }
846
847 pdata = dev_get_platdata(&dspi->pdev->dev);
848
849 if (!pdata) {
850 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
851 &cs_sck_delay);
852
853 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
854 &sck_cs_delay);
855 } else {
856 cs_sck_delay = pdata->cs_sck_delay;
857 sck_cs_delay = pdata->sck_cs_delay;
858 }
859
860 chip->void_write_data = 0;
861
862 clkrate = clk_get_rate(dspi->clk);
863 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
864
865 /* Set PCS to SCK delay scale values */
866 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
867
868 /* Set After SCK delay scale values */
869 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
870
871 chip->ctar_val = 0;
872 if (spi->mode & SPI_CPOL)
873 chip->ctar_val |= SPI_CTAR_CPOL;
874 if (spi->mode & SPI_CPHA)
875 chip->ctar_val |= SPI_CTAR_CPHA;
876
877 if (!spi_controller_is_slave(dspi->ctlr)) {
878 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
879 SPI_CTAR_CSSCK(cssck) |
880 SPI_CTAR_PASC(pasc) |
881 SPI_CTAR_ASC(asc) |
882 SPI_CTAR_PBR(pbr) |
883 SPI_CTAR_BR(br);
884
885 if (spi->mode & SPI_LSB_FIRST)
886 chip->ctar_val |= SPI_CTAR_LSBFE;
887 }
888
889 spi_set_ctldata(spi, chip);
890
891 return 0;
892}
893
894static void dspi_cleanup(struct spi_device *spi)
895{
896 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
897
898 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
899 spi->controller->bus_num, spi->chip_select);
900
901 kfree(chip);
902}
903
904static const struct of_device_id fsl_dspi_dt_ids[] = {
905 { .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
906 { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
907 { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, },
908 { /* sentinel */ }
909};
910MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
911
912#ifdef CONFIG_PM_SLEEP
913static int dspi_suspend(struct device *dev)
914{
915 struct spi_controller *ctlr = dev_get_drvdata(dev);
916 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
917
918 spi_controller_suspend(ctlr);
919 clk_disable_unprepare(dspi->clk);
920
921 pinctrl_pm_select_sleep_state(dev);
922
923 return 0;
924}
925
926static int dspi_resume(struct device *dev)
927{
928 struct spi_controller *ctlr = dev_get_drvdata(dev);
929 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
930 int ret;
931
932 pinctrl_pm_select_default_state(dev);
933
934 ret = clk_prepare_enable(dspi->clk);
935 if (ret)
936 return ret;
937 spi_controller_resume(ctlr);
938
939 return 0;
940}
941#endif /* CONFIG_PM_SLEEP */
942
943static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
944
945static const struct regmap_range dspi_volatile_ranges[] = {
946 regmap_reg_range(SPI_MCR, SPI_TCR),
947 regmap_reg_range(SPI_SR, SPI_SR),
948 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
949};
950
951static const struct regmap_access_table dspi_volatile_table = {
952 .yes_ranges = dspi_volatile_ranges,
953 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
954};
955
956static const struct regmap_config dspi_regmap_config = {
957 .reg_bits = 32,
958 .val_bits = 32,
959 .reg_stride = 4,
960 .max_register = 0x88,
961 .volatile_table = &dspi_volatile_table,
962};
963
964static const struct regmap_range dspi_xspi_volatile_ranges[] = {
965 regmap_reg_range(SPI_MCR, SPI_TCR),
966 regmap_reg_range(SPI_SR, SPI_SR),
967 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
968 regmap_reg_range(SPI_SREX, SPI_SREX),
969};
970
971static const struct regmap_access_table dspi_xspi_volatile_table = {
972 .yes_ranges = dspi_xspi_volatile_ranges,
973 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
974};
975
976static const struct regmap_config dspi_xspi_regmap_config[] = {
977 {
978 .reg_bits = 32,
979 .val_bits = 32,
980 .reg_stride = 4,
981 .max_register = 0x13c,
982 .volatile_table = &dspi_xspi_volatile_table,
983 },
984 {
985 .name = "pushr",
986 .reg_bits = 16,
987 .val_bits = 16,
988 .reg_stride = 2,
989 .max_register = 0x2,
990 },
991};
992
993static void dspi_init(struct fsl_dspi *dspi)
994{
995 unsigned int mcr = SPI_MCR_PCSIS;
996
997 if (dspi->devtype_data->xspi_mode)
998 mcr |= SPI_MCR_XSPI;
999 if (!spi_controller_is_slave(dspi->ctlr))
1000 mcr |= SPI_MCR_MASTER;
1001
1002 regmap_write(dspi->regmap, SPI_MCR, mcr);
1003 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
1004 if (dspi->devtype_data->xspi_mode)
1005 regmap_write(dspi->regmap, SPI_CTARE(0),
1006 SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1));
1007}
1008
1009static int dspi_probe(struct platform_device *pdev)
1010{
1011 struct device_node *np = pdev->dev.of_node;
1012 const struct regmap_config *regmap_config;
1013 struct fsl_dspi_platform_data *pdata;
1014 struct spi_controller *ctlr;
1015 int ret, cs_num, bus_num;
1016 struct fsl_dspi *dspi;
1017 struct resource *res;
1018 void __iomem *base;
1019
1020 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
1021 if (!ctlr)
1022 return -ENOMEM;
1023
1024 dspi = spi_controller_get_devdata(ctlr);
1025 dspi->pdev = pdev;
1026 dspi->ctlr = ctlr;
1027
1028 ctlr->setup = dspi_setup;
1029 ctlr->transfer_one_message = dspi_transfer_one_message;
1030 ctlr->dev.of_node = pdev->dev.of_node;
1031
1032 ctlr->cleanup = dspi_cleanup;
1033 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1034
1035 pdata = dev_get_platdata(&pdev->dev);
1036 if (pdata) {
1037 ctlr->num_chipselect = pdata->cs_num;
1038 ctlr->bus_num = pdata->bus_num;
1039
1040 dspi->devtype_data = &coldfire_data;
1041 } else {
1042
1043 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1044 if (ret < 0) {
1045 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1046 goto out_ctlr_put;
1047 }
1048 ctlr->num_chipselect = cs_num;
1049
1050 ret = of_property_read_u32(np, "bus-num", &bus_num);
1051 if (ret < 0) {
1052 dev_err(&pdev->dev, "can't get bus-num\n");
1053 goto out_ctlr_put;
1054 }
1055 ctlr->bus_num = bus_num;
1056
1057 if (of_property_read_bool(np, "spi-slave"))
1058 ctlr->slave = true;
1059
1060 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1061 if (!dspi->devtype_data) {
1062 dev_err(&pdev->dev, "can't get devtype_data\n");
1063 ret = -EFAULT;
1064 goto out_ctlr_put;
1065 }
1066 }
1067
1068 if (dspi->devtype_data->xspi_mode)
1069 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1070 else
1071 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1072
1073 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1074 base = devm_ioremap_resource(&pdev->dev, res);
1075 if (IS_ERR(base)) {
1076 ret = PTR_ERR(base);
1077 goto out_ctlr_put;
1078 }
1079
1080 if (dspi->devtype_data->xspi_mode)
1081 regmap_config = &dspi_xspi_regmap_config[0];
1082 else
1083 regmap_config = &dspi_regmap_config;
1084 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1085 if (IS_ERR(dspi->regmap)) {
1086 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1087 PTR_ERR(dspi->regmap));
1088 ret = PTR_ERR(dspi->regmap);
1089 goto out_ctlr_put;
1090 }
1091
1092 if (dspi->devtype_data->xspi_mode) {
1093 dspi->regmap_pushr = devm_regmap_init_mmio(
1094 &pdev->dev, base + SPI_PUSHR,
1095 &dspi_xspi_regmap_config[1]);
1096 if (IS_ERR(dspi->regmap_pushr)) {
1097 dev_err(&pdev->dev,
1098 "failed to init pushr regmap: %ld\n",
1099 PTR_ERR(dspi->regmap_pushr));
1100 ret = PTR_ERR(dspi->regmap_pushr);
1101 goto out_ctlr_put;
1102 }
1103 }
1104
1105 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1106 if (IS_ERR(dspi->clk)) {
1107 ret = PTR_ERR(dspi->clk);
1108 dev_err(&pdev->dev, "unable to get clock\n");
1109 goto out_ctlr_put;
1110 }
1111 ret = clk_prepare_enable(dspi->clk);
1112 if (ret)
1113 goto out_ctlr_put;
1114
1115 dspi_init(dspi);
1116
1117 dspi->irq = platform_get_irq(pdev, 0);
1118 if (dspi->irq <= 0) {
1119 dev_info(&pdev->dev,
1120 "can't get platform irq, using poll mode\n");
1121 dspi->irq = 0;
1122 goto poll_mode;
1123 }
1124
1125 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt,
1126 IRQF_SHARED, pdev->name, dspi);
1127 if (ret < 0) {
1128 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1129 goto out_clk_put;
1130 }
1131
1132 init_waitqueue_head(&dspi->waitq);
1133
1134poll_mode:
1135 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1136 ret = dspi_request_dma(dspi, res->start);
1137 if (ret < 0) {
1138 dev_err(&pdev->dev, "can't get dma channels\n");
1139 goto out_clk_put;
1140 }
1141 }
1142
1143 ctlr->max_speed_hz =
1144 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1145
1146 platform_set_drvdata(pdev, ctlr);
1147
1148 ret = spi_register_controller(ctlr);
1149 if (ret != 0) {
1150 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1151 goto out_clk_put;
1152 }
1153
1154 return ret;
1155
1156out_clk_put:
1157 clk_disable_unprepare(dspi->clk);
1158out_ctlr_put:
1159 spi_controller_put(ctlr);
1160
1161 return ret;
1162}
1163
1164static int dspi_remove(struct platform_device *pdev)
1165{
1166 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1167 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
1168
1169 /* Disconnect from the SPI framework */
1170 dspi_release_dma(dspi);
1171 clk_disable_unprepare(dspi->clk);
1172 spi_unregister_controller(dspi->ctlr);
1173
1174 return 0;
1175}
1176
1177static struct platform_driver fsl_dspi_driver = {
1178 .driver.name = DRIVER_NAME,
1179 .driver.of_match_table = fsl_dspi_dt_ids,
1180 .driver.owner = THIS_MODULE,
1181 .driver.pm = &dspi_pm,
1182 .probe = dspi_probe,
1183 .remove = dspi_remove,
1184};
1185module_platform_driver(fsl_dspi_driver);
1186
1187MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1188MODULE_LICENSE("GPL");
1189MODULE_ALIAS("platform:" DRIVER_NAME);