1/*
 2 * Freescale eSDHC controller driver generics for OF and pltfm.
 3 *
 4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
 5 * Copyright (c) 2009 MontaVista Software, Inc.
 6 * Copyright (c) 2010 Pengutronix e.K.
 7 *   Author: Wolfram Sang <w.sang@pengutronix.de>
 8 *
 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
15#define _DRIVERS_MMC_SDHCI_ESDHC_H
16
17/*
18 * Ops and quirks for the Freescale eSDHC controller.
19 */
20
21#define ESDHC_DEFAULT_QUIRKS	(SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
 
22				SDHCI_QUIRK_NO_BUSY_IRQ | \
23				SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
24				SDHCI_QUIRK_PIO_NEEDS_DELAY | \
25				SDHCI_QUIRK_NO_HISPD_BIT)
26
27#define ESDHC_PROCTL		0x28
28
29#define ESDHC_SYSTEM_CONTROL	0x2c
30#define ESDHC_CLOCK_MASK	0x0000fff0
31#define ESDHC_PREDIV_SHIFT	8
32#define ESDHC_DIVIDER_SHIFT	4
33#define ESDHC_CLOCK_PEREN	0x00000004
34#define ESDHC_CLOCK_HCKEN	0x00000002
35#define ESDHC_CLOCK_IPGEN	0x00000001
36
37/* pltfm-specific */
38#define ESDHC_HOST_CONTROL_LE	0x20
39
40/*
41 * P2020 interpretation of the SDHCI_HOST_CONTROL register
42 */
43#define ESDHC_CTRL_4BITBUS          (0x1 << 1)
44#define ESDHC_CTRL_8BITBUS          (0x2 << 1)
45#define ESDHC_CTRL_BUSWIDTH_MASK    (0x3 << 1)
46
47/* OF-specific */
48#define ESDHC_DMA_SYSCTL	0x40c
49#define ESDHC_DMA_SNOOP		0x00000040
50
51#define ESDHC_HOST_CONTROL_RES	0x01
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
52
53#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Freescale eSDHC controller driver generics for OF and pltfm.
 4 *
 5 * Copyright (c) 2007 Freescale Semiconductor, Inc.
 6 * Copyright (c) 2009 MontaVista Software, Inc.
 7 * Copyright (c) 2010 Pengutronix e.K.
 8 *   Author: Wolfram Sang <w.sang@pengutronix.de>
 
 
 
 
 9 */
10
11#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
12#define _DRIVERS_MMC_SDHCI_ESDHC_H
13
14/*
15 * Ops and quirks for the Freescale eSDHC controller.
16 */
17
18#define ESDHC_DEFAULT_QUIRKS	(SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
19				SDHCI_QUIRK_32BIT_DMA_ADDR | \
20				SDHCI_QUIRK_NO_BUSY_IRQ | \
21				SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
22				SDHCI_QUIRK_PIO_NEEDS_DELAY | \
23				SDHCI_QUIRK_NO_HISPD_BIT)
24
 
 
 
 
 
 
 
 
 
 
25/* pltfm-specific */
26#define ESDHC_HOST_CONTROL_LE	0x20
27
28/*
29 * eSDHC register definition
30 */
 
 
 
 
 
 
 
31
32/* Present State Register */
33#define ESDHC_PRSSTAT			0x24
34#define ESDHC_CLOCK_STABLE		0x00000008
35
36/* Protocol Control Register */
37#define ESDHC_PROCTL			0x28
38#define ESDHC_VOLT_SEL			0x00000400
39#define ESDHC_CTRL_4BITBUS		(0x1 << 1)
40#define ESDHC_CTRL_8BITBUS		(0x2 << 1)
41#define ESDHC_CTRL_BUSWIDTH_MASK	(0x3 << 1)
42#define ESDHC_HOST_CONTROL_RES		0x01
43
44/* System Control Register */
45#define ESDHC_SYSTEM_CONTROL		0x2c
46#define ESDHC_CLOCK_MASK		0x0000fff0
47#define ESDHC_PREDIV_SHIFT		8
48#define ESDHC_DIVIDER_SHIFT		4
49#define ESDHC_CLOCK_SDCLKEN		0x00000008
50#define ESDHC_CLOCK_PEREN		0x00000004
51#define ESDHC_CLOCK_HCKEN		0x00000002
52#define ESDHC_CLOCK_IPGEN		0x00000001
53
54/* Host Controller Capabilities Register 2 */
55#define ESDHC_CAPABILITIES_1		0x114
56
57/* Tuning Block Control Register */
58#define ESDHC_TBCTL			0x120
59#define ESDHC_HS400_WNDW_ADJUST		0x00000040
60#define ESDHC_HS400_MODE		0x00000010
61#define ESDHC_TB_EN			0x00000004
62#define ESDHC_TBPTR			0x128
63
64/* SD Clock Control Register */
65#define ESDHC_SDCLKCTL			0x144
66#define ESDHC_LPBK_CLK_SEL		0x80000000
67#define ESDHC_CMD_CLK_CTL		0x00008000
68
69/* SD Timing Control Register */
70#define ESDHC_SDTIMNGCTL		0x148
71#define ESDHC_FLW_CTL_BG		0x00008000
72
73/* DLL Config 0 Register */
74#define ESDHC_DLLCFG0			0x160
75#define ESDHC_DLL_ENABLE		0x80000000
76#define ESDHC_DLL_FREQ_SEL		0x08000000
77
78/* DLL Config 1 Register */
79#define ESDHC_DLLCFG1			0x164
80#define ESDHC_DLL_PD_PULSE_STRETCH_SEL	0x80000000
81
82/* DLL Status 0 Register */
83#define ESDHC_DLLSTAT0			0x170
84#define ESDHC_DLL_STS_SLV_LOCK		0x08000000
85
86/* Control Register for DMA transfer */
87#define ESDHC_DMA_SYSCTL		0x40c
88#define ESDHC_PERIPHERAL_CLK_SEL	0x00080000
89#define ESDHC_FLUSH_ASYNC_FIFO		0x00040000
90#define ESDHC_DMA_SNOOP			0x00000040
91
92#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */