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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_TTM_H__
25#define __AMDGPU_TTM_H__
26
27#include "gpu_scheduler.h"
28
29#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
30#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
31#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
32
33#define AMDGPU_PL_FLAG_GDS (TTM_PL_FLAG_PRIV << 0)
34#define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
35#define AMDGPU_PL_FLAG_OA (TTM_PL_FLAG_PRIV << 2)
36
37#define AMDGPU_TTM_LRU_SIZE 20
38
39struct amdgpu_mman_lru {
40 struct list_head *lru[TTM_NUM_MEM_TYPES];
41 struct list_head *swap_lru;
42};
43
44struct amdgpu_mman {
45 struct ttm_bo_global_ref bo_global_ref;
46 struct drm_global_reference mem_global_ref;
47 struct ttm_bo_device bdev;
48 bool mem_global_referenced;
49 bool initialized;
50
51#if defined(CONFIG_DEBUG_FS)
52 struct dentry *vram;
53 struct dentry *gtt;
54#endif
55
56 /* buffer handling */
57 const struct amdgpu_buffer_funcs *buffer_funcs;
58 struct amdgpu_ring *buffer_funcs_ring;
59 /* Scheduler entity for buffer moves */
60 struct amd_sched_entity entity;
61
62 /* custom LRU management */
63 struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE];
64 /* guard for log2_size array, don't add anything in between */
65 struct amdgpu_mman_lru guard;
66};
67
68extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
69extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
70
71int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
72 struct ttm_buffer_object *tbo,
73 const struct ttm_place *place,
74 struct ttm_mem_reg *mem);
75
76int amdgpu_copy_buffer(struct amdgpu_ring *ring,
77 uint64_t src_offset,
78 uint64_t dst_offset,
79 uint32_t byte_count,
80 struct reservation_object *resv,
81 struct dma_fence **fence, bool direct_submit);
82int amdgpu_fill_buffer(struct amdgpu_bo *bo,
83 uint32_t src_data,
84 struct reservation_object *resv,
85 struct dma_fence **fence);
86
87int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
88bool amdgpu_ttm_is_bound(struct ttm_tt *ttm);
89int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem);
90
91#endif
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_TTM_H__
25#define __AMDGPU_TTM_H__
26
27#include "amdgpu.h"
28#include <drm/gpu_scheduler.h>
29
30#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
31#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
32#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
33
34#define AMDGPU_PL_FLAG_GDS (TTM_PL_FLAG_PRIV << 0)
35#define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
36#define AMDGPU_PL_FLAG_OA (TTM_PL_FLAG_PRIV << 2)
37
38#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
39#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
40
41#define AMDGPU_POISON 0xd0bed0be
42
43struct amdgpu_mman {
44 struct ttm_bo_device bdev;
45 bool mem_global_referenced;
46 bool initialized;
47 void __iomem *aper_base_kaddr;
48
49#if defined(CONFIG_DEBUG_FS)
50 struct dentry *debugfs_entries[8];
51#endif
52
53 /* buffer handling */
54 const struct amdgpu_buffer_funcs *buffer_funcs;
55 struct amdgpu_ring *buffer_funcs_ring;
56 bool buffer_funcs_enabled;
57
58 struct mutex gtt_window_lock;
59 /* Scheduler entity for buffer moves */
60 struct drm_sched_entity entity;
61};
62
63struct amdgpu_copy_mem {
64 struct ttm_buffer_object *bo;
65 struct ttm_mem_reg *mem;
66 unsigned long offset;
67};
68
69extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
70extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
71
72bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
73uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
74int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
75
76u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
77uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
78uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
79
80int amdgpu_ttm_init(struct amdgpu_device *adev);
81void amdgpu_ttm_late_init(struct amdgpu_device *adev);
82void amdgpu_ttm_fini(struct amdgpu_device *adev);
83void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
84 bool enable);
85
86int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
87 uint64_t dst_offset, uint32_t byte_count,
88 struct dma_resv *resv,
89 struct dma_fence **fence, bool direct_submit,
90 bool vm_needs_flush);
91int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
92 struct amdgpu_copy_mem *src,
93 struct amdgpu_copy_mem *dst,
94 uint64_t size,
95 struct dma_resv *resv,
96 struct dma_fence **f);
97int amdgpu_fill_buffer(struct amdgpu_bo *bo,
98 uint32_t src_data,
99 struct dma_resv *resv,
100 struct dma_fence **fence);
101
102int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
103int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
104int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
105
106#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
107int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages);
108bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
109#else
110static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
111 struct page **pages)
112{
113 return -EPERM;
114}
115static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
116{
117 return false;
118}
119#endif
120
121void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
122int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
123 uint32_t flags);
124bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
125struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
126bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
127 unsigned long end);
128bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
129 int *last_invalidated);
130bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
131bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
132uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
133uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
134 struct ttm_mem_reg *mem);
135
136#endif