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1/*
2 * SuperH Timer Support - CMT
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/irq.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/pm_domain.h>
30#include <linux/pm_runtime.h>
31#include <linux/sh_timer.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
34
35struct sh_cmt_device;
36
37/*
38 * The CMT comes in 5 different identified flavours, depending not only on the
39 * SoC but also on the particular instance. The following table lists the main
40 * characteristics of those flavours.
41 *
42 * 16B 32B 32B-F 48B 48B-2
43 * -----------------------------------------------------------------------------
44 * Channels 2 1/4 1 6 2/8
45 * Control Width 16 16 16 16 32
46 * Counter Width 16 32 32 32/48 32/48
47 * Shared Start/Stop Y Y Y Y N
48 *
49 * The 48-bit gen2 version has a per-channel start/stop register located in the
50 * channel registers block. All other versions have a shared start/stop register
51 * located in the global space.
52 *
53 * Channels are indexed from 0 to N-1 in the documentation. The channel index
54 * infers the start/stop bit position in the control register and the channel
55 * registers block address. Some CMT instances have a subset of channels
56 * available, in which case the index in the documentation doesn't match the
57 * "real" index as implemented in hardware. This is for instance the case with
58 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * in the documentation but using start/stop bit 5 and having its registers
60 * block at 0x60.
61 *
62 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
63 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
64 */
65
66enum sh_cmt_model {
67 SH_CMT_16BIT,
68 SH_CMT_32BIT,
69 SH_CMT_32BIT_FAST,
70 SH_CMT_48BIT,
71 SH_CMT_48BIT_GEN2,
72};
73
74struct sh_cmt_info {
75 enum sh_cmt_model model;
76
77 unsigned long width; /* 16 or 32 bit version of hardware block */
78 unsigned long overflow_bit;
79 unsigned long clear_bits;
80
81 /* callbacks for CMSTR and CMCSR access */
82 unsigned long (*read_control)(void __iomem *base, unsigned long offs);
83 void (*write_control)(void __iomem *base, unsigned long offs,
84 unsigned long value);
85
86 /* callbacks for CMCNT and CMCOR access */
87 unsigned long (*read_count)(void __iomem *base, unsigned long offs);
88 void (*write_count)(void __iomem *base, unsigned long offs,
89 unsigned long value);
90};
91
92struct sh_cmt_channel {
93 struct sh_cmt_device *cmt;
94
95 unsigned int index; /* Index in the documentation */
96 unsigned int hwidx; /* Real hardware index */
97
98 void __iomem *iostart;
99 void __iomem *ioctrl;
100
101 unsigned int timer_bit;
102 unsigned long flags;
103 unsigned long match_value;
104 unsigned long next_match_value;
105 unsigned long max_match_value;
106 unsigned long rate;
107 raw_spinlock_t lock;
108 struct clock_event_device ced;
109 struct clocksource cs;
110 unsigned long total_cycles;
111 bool cs_enabled;
112};
113
114struct sh_cmt_device {
115 struct platform_device *pdev;
116
117 const struct sh_cmt_info *info;
118
119 void __iomem *mapbase;
120 struct clk *clk;
121
122 raw_spinlock_t lock; /* Protect the shared start/stop register */
123
124 struct sh_cmt_channel *channels;
125 unsigned int num_channels;
126 unsigned int hw_channels;
127
128 bool has_clockevent;
129 bool has_clocksource;
130};
131
132#define SH_CMT16_CMCSR_CMF (1 << 7)
133#define SH_CMT16_CMCSR_CMIE (1 << 6)
134#define SH_CMT16_CMCSR_CKS8 (0 << 0)
135#define SH_CMT16_CMCSR_CKS32 (1 << 0)
136#define SH_CMT16_CMCSR_CKS128 (2 << 0)
137#define SH_CMT16_CMCSR_CKS512 (3 << 0)
138#define SH_CMT16_CMCSR_CKS_MASK (3 << 0)
139
140#define SH_CMT32_CMCSR_CMF (1 << 15)
141#define SH_CMT32_CMCSR_OVF (1 << 14)
142#define SH_CMT32_CMCSR_WRFLG (1 << 13)
143#define SH_CMT32_CMCSR_STTF (1 << 12)
144#define SH_CMT32_CMCSR_STPF (1 << 11)
145#define SH_CMT32_CMCSR_SSIE (1 << 10)
146#define SH_CMT32_CMCSR_CMS (1 << 9)
147#define SH_CMT32_CMCSR_CMM (1 << 8)
148#define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7)
149#define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
150#define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
151#define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
152#define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
153#define SH_CMT32_CMCSR_DBGIVD (1 << 3)
154#define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
155#define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0)
156#define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0)
157#define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
158#define SH_CMT32_CMCSR_CKS_MASK (7 << 0)
159
160static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
161{
162 return ioread16(base + (offs << 1));
163}
164
165static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
166{
167 return ioread32(base + (offs << 2));
168}
169
170static void sh_cmt_write16(void __iomem *base, unsigned long offs,
171 unsigned long value)
172{
173 iowrite16(value, base + (offs << 1));
174}
175
176static void sh_cmt_write32(void __iomem *base, unsigned long offs,
177 unsigned long value)
178{
179 iowrite32(value, base + (offs << 2));
180}
181
182static const struct sh_cmt_info sh_cmt_info[] = {
183 [SH_CMT_16BIT] = {
184 .model = SH_CMT_16BIT,
185 .width = 16,
186 .overflow_bit = SH_CMT16_CMCSR_CMF,
187 .clear_bits = ~SH_CMT16_CMCSR_CMF,
188 .read_control = sh_cmt_read16,
189 .write_control = sh_cmt_write16,
190 .read_count = sh_cmt_read16,
191 .write_count = sh_cmt_write16,
192 },
193 [SH_CMT_32BIT] = {
194 .model = SH_CMT_32BIT,
195 .width = 32,
196 .overflow_bit = SH_CMT32_CMCSR_CMF,
197 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
198 .read_control = sh_cmt_read16,
199 .write_control = sh_cmt_write16,
200 .read_count = sh_cmt_read32,
201 .write_count = sh_cmt_write32,
202 },
203 [SH_CMT_32BIT_FAST] = {
204 .model = SH_CMT_32BIT_FAST,
205 .width = 32,
206 .overflow_bit = SH_CMT32_CMCSR_CMF,
207 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
208 .read_control = sh_cmt_read16,
209 .write_control = sh_cmt_write16,
210 .read_count = sh_cmt_read32,
211 .write_count = sh_cmt_write32,
212 },
213 [SH_CMT_48BIT] = {
214 .model = SH_CMT_48BIT,
215 .width = 32,
216 .overflow_bit = SH_CMT32_CMCSR_CMF,
217 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
218 .read_control = sh_cmt_read32,
219 .write_control = sh_cmt_write32,
220 .read_count = sh_cmt_read32,
221 .write_count = sh_cmt_write32,
222 },
223 [SH_CMT_48BIT_GEN2] = {
224 .model = SH_CMT_48BIT_GEN2,
225 .width = 32,
226 .overflow_bit = SH_CMT32_CMCSR_CMF,
227 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
228 .read_control = sh_cmt_read32,
229 .write_control = sh_cmt_write32,
230 .read_count = sh_cmt_read32,
231 .write_count = sh_cmt_write32,
232 },
233};
234
235#define CMCSR 0 /* channel register */
236#define CMCNT 1 /* channel register */
237#define CMCOR 2 /* channel register */
238
239static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
240{
241 if (ch->iostart)
242 return ch->cmt->info->read_control(ch->iostart, 0);
243 else
244 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
245}
246
247static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch,
248 unsigned long value)
249{
250 if (ch->iostart)
251 ch->cmt->info->write_control(ch->iostart, 0, value);
252 else
253 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
254}
255
256static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
257{
258 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
259}
260
261static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch,
262 unsigned long value)
263{
264 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
265}
266
267static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
268{
269 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
270}
271
272static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch,
273 unsigned long value)
274{
275 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
276}
277
278static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch,
279 unsigned long value)
280{
281 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
282}
283
284static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
285 int *has_wrapped)
286{
287 unsigned long v1, v2, v3;
288 int o1, o2;
289
290 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
291
292 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
293 do {
294 o2 = o1;
295 v1 = sh_cmt_read_cmcnt(ch);
296 v2 = sh_cmt_read_cmcnt(ch);
297 v3 = sh_cmt_read_cmcnt(ch);
298 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
299 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
300 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
301
302 *has_wrapped = o1;
303 return v2;
304}
305
306static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
307{
308 unsigned long flags, value;
309
310 /* start stop register shared by multiple timer channels */
311 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
312 value = sh_cmt_read_cmstr(ch);
313
314 if (start)
315 value |= 1 << ch->timer_bit;
316 else
317 value &= ~(1 << ch->timer_bit);
318
319 sh_cmt_write_cmstr(ch, value);
320 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
321}
322
323static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate)
324{
325 int k, ret;
326
327 pm_runtime_get_sync(&ch->cmt->pdev->dev);
328 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
329
330 /* enable clock */
331 ret = clk_enable(ch->cmt->clk);
332 if (ret) {
333 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
334 ch->index);
335 goto err0;
336 }
337
338 /* make sure channel is disabled */
339 sh_cmt_start_stop_ch(ch, 0);
340
341 /* configure channel, periodic mode and maximum timeout */
342 if (ch->cmt->info->width == 16) {
343 *rate = clk_get_rate(ch->cmt->clk) / 512;
344 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
345 SH_CMT16_CMCSR_CKS512);
346 } else {
347 *rate = clk_get_rate(ch->cmt->clk) / 8;
348 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
349 SH_CMT32_CMCSR_CMTOUT_IE |
350 SH_CMT32_CMCSR_CMR_IRQ |
351 SH_CMT32_CMCSR_CKS_RCLK8);
352 }
353
354 sh_cmt_write_cmcor(ch, 0xffffffff);
355 sh_cmt_write_cmcnt(ch, 0);
356
357 /*
358 * According to the sh73a0 user's manual, as CMCNT can be operated
359 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
360 * modifying CMCNT register; two RCLK cycles are necessary before
361 * this register is either read or any modification of the value
362 * it holds is reflected in the LSI's actual operation.
363 *
364 * While at it, we're supposed to clear out the CMCNT as of this
365 * moment, so make sure it's processed properly here. This will
366 * take RCLKx2 at maximum.
367 */
368 for (k = 0; k < 100; k++) {
369 if (!sh_cmt_read_cmcnt(ch))
370 break;
371 udelay(1);
372 }
373
374 if (sh_cmt_read_cmcnt(ch)) {
375 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
376 ch->index);
377 ret = -ETIMEDOUT;
378 goto err1;
379 }
380
381 /* enable channel */
382 sh_cmt_start_stop_ch(ch, 1);
383 return 0;
384 err1:
385 /* stop clock */
386 clk_disable(ch->cmt->clk);
387
388 err0:
389 return ret;
390}
391
392static void sh_cmt_disable(struct sh_cmt_channel *ch)
393{
394 /* disable channel */
395 sh_cmt_start_stop_ch(ch, 0);
396
397 /* disable interrupts in CMT block */
398 sh_cmt_write_cmcsr(ch, 0);
399
400 /* stop clock */
401 clk_disable(ch->cmt->clk);
402
403 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
404 pm_runtime_put(&ch->cmt->pdev->dev);
405}
406
407/* private flags */
408#define FLAG_CLOCKEVENT (1 << 0)
409#define FLAG_CLOCKSOURCE (1 << 1)
410#define FLAG_REPROGRAM (1 << 2)
411#define FLAG_SKIPEVENT (1 << 3)
412#define FLAG_IRQCONTEXT (1 << 4)
413
414static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
415 int absolute)
416{
417 unsigned long new_match;
418 unsigned long value = ch->next_match_value;
419 unsigned long delay = 0;
420 unsigned long now = 0;
421 int has_wrapped;
422
423 now = sh_cmt_get_counter(ch, &has_wrapped);
424 ch->flags |= FLAG_REPROGRAM; /* force reprogram */
425
426 if (has_wrapped) {
427 /* we're competing with the interrupt handler.
428 * -> let the interrupt handler reprogram the timer.
429 * -> interrupt number two handles the event.
430 */
431 ch->flags |= FLAG_SKIPEVENT;
432 return;
433 }
434
435 if (absolute)
436 now = 0;
437
438 do {
439 /* reprogram the timer hardware,
440 * but don't save the new match value yet.
441 */
442 new_match = now + value + delay;
443 if (new_match > ch->max_match_value)
444 new_match = ch->max_match_value;
445
446 sh_cmt_write_cmcor(ch, new_match);
447
448 now = sh_cmt_get_counter(ch, &has_wrapped);
449 if (has_wrapped && (new_match > ch->match_value)) {
450 /* we are changing to a greater match value,
451 * so this wrap must be caused by the counter
452 * matching the old value.
453 * -> first interrupt reprograms the timer.
454 * -> interrupt number two handles the event.
455 */
456 ch->flags |= FLAG_SKIPEVENT;
457 break;
458 }
459
460 if (has_wrapped) {
461 /* we are changing to a smaller match value,
462 * so the wrap must be caused by the counter
463 * matching the new value.
464 * -> save programmed match value.
465 * -> let isr handle the event.
466 */
467 ch->match_value = new_match;
468 break;
469 }
470
471 /* be safe: verify hardware settings */
472 if (now < new_match) {
473 /* timer value is below match value, all good.
474 * this makes sure we won't miss any match events.
475 * -> save programmed match value.
476 * -> let isr handle the event.
477 */
478 ch->match_value = new_match;
479 break;
480 }
481
482 /* the counter has reached a value greater
483 * than our new match value. and since the
484 * has_wrapped flag isn't set we must have
485 * programmed a too close event.
486 * -> increase delay and retry.
487 */
488 if (delay)
489 delay <<= 1;
490 else
491 delay = 1;
492
493 if (!delay)
494 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
495 ch->index);
496
497 } while (delay);
498}
499
500static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
501{
502 if (delta > ch->max_match_value)
503 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
504 ch->index);
505
506 ch->next_match_value = delta;
507 sh_cmt_clock_event_program_verify(ch, 0);
508}
509
510static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
511{
512 unsigned long flags;
513
514 raw_spin_lock_irqsave(&ch->lock, flags);
515 __sh_cmt_set_next(ch, delta);
516 raw_spin_unlock_irqrestore(&ch->lock, flags);
517}
518
519static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
520{
521 struct sh_cmt_channel *ch = dev_id;
522
523 /* clear flags */
524 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
525 ch->cmt->info->clear_bits);
526
527 /* update clock source counter to begin with if enabled
528 * the wrap flag should be cleared by the timer specific
529 * isr before we end up here.
530 */
531 if (ch->flags & FLAG_CLOCKSOURCE)
532 ch->total_cycles += ch->match_value + 1;
533
534 if (!(ch->flags & FLAG_REPROGRAM))
535 ch->next_match_value = ch->max_match_value;
536
537 ch->flags |= FLAG_IRQCONTEXT;
538
539 if (ch->flags & FLAG_CLOCKEVENT) {
540 if (!(ch->flags & FLAG_SKIPEVENT)) {
541 if (clockevent_state_oneshot(&ch->ced)) {
542 ch->next_match_value = ch->max_match_value;
543 ch->flags |= FLAG_REPROGRAM;
544 }
545
546 ch->ced.event_handler(&ch->ced);
547 }
548 }
549
550 ch->flags &= ~FLAG_SKIPEVENT;
551
552 if (ch->flags & FLAG_REPROGRAM) {
553 ch->flags &= ~FLAG_REPROGRAM;
554 sh_cmt_clock_event_program_verify(ch, 1);
555
556 if (ch->flags & FLAG_CLOCKEVENT)
557 if ((clockevent_state_shutdown(&ch->ced))
558 || (ch->match_value == ch->next_match_value))
559 ch->flags &= ~FLAG_REPROGRAM;
560 }
561
562 ch->flags &= ~FLAG_IRQCONTEXT;
563
564 return IRQ_HANDLED;
565}
566
567static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
568{
569 int ret = 0;
570 unsigned long flags;
571
572 raw_spin_lock_irqsave(&ch->lock, flags);
573
574 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
575 ret = sh_cmt_enable(ch, &ch->rate);
576
577 if (ret)
578 goto out;
579 ch->flags |= flag;
580
581 /* setup timeout if no clockevent */
582 if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
583 __sh_cmt_set_next(ch, ch->max_match_value);
584 out:
585 raw_spin_unlock_irqrestore(&ch->lock, flags);
586
587 return ret;
588}
589
590static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
591{
592 unsigned long flags;
593 unsigned long f;
594
595 raw_spin_lock_irqsave(&ch->lock, flags);
596
597 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
598 ch->flags &= ~flag;
599
600 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
601 sh_cmt_disable(ch);
602
603 /* adjust the timeout to maximum if only clocksource left */
604 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
605 __sh_cmt_set_next(ch, ch->max_match_value);
606
607 raw_spin_unlock_irqrestore(&ch->lock, flags);
608}
609
610static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
611{
612 return container_of(cs, struct sh_cmt_channel, cs);
613}
614
615static u64 sh_cmt_clocksource_read(struct clocksource *cs)
616{
617 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
618 unsigned long flags, raw;
619 unsigned long value;
620 int has_wrapped;
621
622 raw_spin_lock_irqsave(&ch->lock, flags);
623 value = ch->total_cycles;
624 raw = sh_cmt_get_counter(ch, &has_wrapped);
625
626 if (unlikely(has_wrapped))
627 raw += ch->match_value + 1;
628 raw_spin_unlock_irqrestore(&ch->lock, flags);
629
630 return value + raw;
631}
632
633static int sh_cmt_clocksource_enable(struct clocksource *cs)
634{
635 int ret;
636 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
637
638 WARN_ON(ch->cs_enabled);
639
640 ch->total_cycles = 0;
641
642 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
643 if (!ret) {
644 __clocksource_update_freq_hz(cs, ch->rate);
645 ch->cs_enabled = true;
646 }
647 return ret;
648}
649
650static void sh_cmt_clocksource_disable(struct clocksource *cs)
651{
652 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
653
654 WARN_ON(!ch->cs_enabled);
655
656 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
657 ch->cs_enabled = false;
658}
659
660static void sh_cmt_clocksource_suspend(struct clocksource *cs)
661{
662 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
663
664 if (!ch->cs_enabled)
665 return;
666
667 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
668 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
669}
670
671static void sh_cmt_clocksource_resume(struct clocksource *cs)
672{
673 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
674
675 if (!ch->cs_enabled)
676 return;
677
678 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
679 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
680}
681
682static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
683 const char *name)
684{
685 struct clocksource *cs = &ch->cs;
686
687 cs->name = name;
688 cs->rating = 125;
689 cs->read = sh_cmt_clocksource_read;
690 cs->enable = sh_cmt_clocksource_enable;
691 cs->disable = sh_cmt_clocksource_disable;
692 cs->suspend = sh_cmt_clocksource_suspend;
693 cs->resume = sh_cmt_clocksource_resume;
694 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
695 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
696
697 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
698 ch->index);
699
700 /* Register with dummy 1 Hz value, gets updated in ->enable() */
701 clocksource_register_hz(cs, 1);
702 return 0;
703}
704
705static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
706{
707 return container_of(ced, struct sh_cmt_channel, ced);
708}
709
710static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
711{
712 struct clock_event_device *ced = &ch->ced;
713
714 sh_cmt_start(ch, FLAG_CLOCKEVENT);
715
716 /* TODO: calculate good shift from rate and counter bit width */
717
718 ced->shift = 32;
719 ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift);
720 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
721 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
722
723 if (periodic)
724 sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1);
725 else
726 sh_cmt_set_next(ch, ch->max_match_value);
727}
728
729static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
730{
731 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
732
733 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
734 return 0;
735}
736
737static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
738 int periodic)
739{
740 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
741
742 /* deal with old setting first */
743 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
744 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
745
746 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
747 ch->index, periodic ? "periodic" : "oneshot");
748 sh_cmt_clock_event_start(ch, periodic);
749 return 0;
750}
751
752static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
753{
754 return sh_cmt_clock_event_set_state(ced, 0);
755}
756
757static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
758{
759 return sh_cmt_clock_event_set_state(ced, 1);
760}
761
762static int sh_cmt_clock_event_next(unsigned long delta,
763 struct clock_event_device *ced)
764{
765 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
766
767 BUG_ON(!clockevent_state_oneshot(ced));
768 if (likely(ch->flags & FLAG_IRQCONTEXT))
769 ch->next_match_value = delta - 1;
770 else
771 sh_cmt_set_next(ch, delta - 1);
772
773 return 0;
774}
775
776static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
777{
778 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
779
780 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
781 clk_unprepare(ch->cmt->clk);
782}
783
784static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
785{
786 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
787
788 clk_prepare(ch->cmt->clk);
789 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
790}
791
792static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
793 const char *name)
794{
795 struct clock_event_device *ced = &ch->ced;
796 int irq;
797 int ret;
798
799 irq = platform_get_irq(ch->cmt->pdev, ch->index);
800 if (irq < 0) {
801 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
802 ch->index);
803 return irq;
804 }
805
806 ret = request_irq(irq, sh_cmt_interrupt,
807 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
808 dev_name(&ch->cmt->pdev->dev), ch);
809 if (ret) {
810 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
811 ch->index, irq);
812 return ret;
813 }
814
815 ced->name = name;
816 ced->features = CLOCK_EVT_FEAT_PERIODIC;
817 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
818 ced->rating = 125;
819 ced->cpumask = cpu_possible_mask;
820 ced->set_next_event = sh_cmt_clock_event_next;
821 ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
822 ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
823 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
824 ced->suspend = sh_cmt_clock_event_suspend;
825 ced->resume = sh_cmt_clock_event_resume;
826
827 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
828 ch->index);
829 clockevents_register_device(ced);
830
831 return 0;
832}
833
834static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
835 bool clockevent, bool clocksource)
836{
837 int ret;
838
839 if (clockevent) {
840 ch->cmt->has_clockevent = true;
841 ret = sh_cmt_register_clockevent(ch, name);
842 if (ret < 0)
843 return ret;
844 }
845
846 if (clocksource) {
847 ch->cmt->has_clocksource = true;
848 sh_cmt_register_clocksource(ch, name);
849 }
850
851 return 0;
852}
853
854static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
855 unsigned int hwidx, bool clockevent,
856 bool clocksource, struct sh_cmt_device *cmt)
857{
858 int ret;
859
860 /* Skip unused channels. */
861 if (!clockevent && !clocksource)
862 return 0;
863
864 ch->cmt = cmt;
865 ch->index = index;
866 ch->hwidx = hwidx;
867
868 /*
869 * Compute the address of the channel control register block. For the
870 * timers with a per-channel start/stop register, compute its address
871 * as well.
872 */
873 switch (cmt->info->model) {
874 case SH_CMT_16BIT:
875 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
876 break;
877 case SH_CMT_32BIT:
878 case SH_CMT_48BIT:
879 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
880 break;
881 case SH_CMT_32BIT_FAST:
882 /*
883 * The 32-bit "fast" timer has a single channel at hwidx 5 but
884 * is located at offset 0x40 instead of 0x60 for some reason.
885 */
886 ch->ioctrl = cmt->mapbase + 0x40;
887 break;
888 case SH_CMT_48BIT_GEN2:
889 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
890 ch->ioctrl = ch->iostart + 0x10;
891 break;
892 }
893
894 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
895 ch->max_match_value = ~0;
896 else
897 ch->max_match_value = (1 << cmt->info->width) - 1;
898
899 ch->match_value = ch->max_match_value;
900 raw_spin_lock_init(&ch->lock);
901
902 ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;
903
904 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
905 clockevent, clocksource);
906 if (ret) {
907 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
908 ch->index);
909 return ret;
910 }
911 ch->cs_enabled = false;
912
913 return 0;
914}
915
916static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
917{
918 struct resource *mem;
919
920 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
921 if (!mem) {
922 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
923 return -ENXIO;
924 }
925
926 cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
927 if (cmt->mapbase == NULL) {
928 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
929 return -ENXIO;
930 }
931
932 return 0;
933}
934
935static const struct platform_device_id sh_cmt_id_table[] = {
936 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
937 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
938 { }
939};
940MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
941
942static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
943 { .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] },
944 { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] },
945 { .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
946 { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT_48BIT_GEN2] },
947 { }
948};
949MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
950
951static int sh_cmt_parse_dt(struct sh_cmt_device *cmt)
952{
953 struct device_node *np = cmt->pdev->dev.of_node;
954
955 return of_property_read_u32(np, "renesas,channels-mask",
956 &cmt->hw_channels);
957}
958
959static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
960{
961 unsigned int mask;
962 unsigned int i;
963 int ret;
964
965 cmt->pdev = pdev;
966 raw_spin_lock_init(&cmt->lock);
967
968 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
969 const struct of_device_id *id;
970
971 id = of_match_node(sh_cmt_of_table, pdev->dev.of_node);
972 cmt->info = id->data;
973
974 ret = sh_cmt_parse_dt(cmt);
975 if (ret < 0)
976 return ret;
977 } else if (pdev->dev.platform_data) {
978 struct sh_timer_config *cfg = pdev->dev.platform_data;
979 const struct platform_device_id *id = pdev->id_entry;
980
981 cmt->info = (const struct sh_cmt_info *)id->driver_data;
982 cmt->hw_channels = cfg->channels_mask;
983 } else {
984 dev_err(&cmt->pdev->dev, "missing platform data\n");
985 return -ENXIO;
986 }
987
988 /* Get hold of clock. */
989 cmt->clk = clk_get(&cmt->pdev->dev, "fck");
990 if (IS_ERR(cmt->clk)) {
991 dev_err(&cmt->pdev->dev, "cannot get clock\n");
992 return PTR_ERR(cmt->clk);
993 }
994
995 ret = clk_prepare(cmt->clk);
996 if (ret < 0)
997 goto err_clk_put;
998
999 /* Map the memory resource(s). */
1000 ret = sh_cmt_map_memory(cmt);
1001 if (ret < 0)
1002 goto err_clk_unprepare;
1003
1004 /* Allocate and setup the channels. */
1005 cmt->num_channels = hweight8(cmt->hw_channels);
1006 cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),
1007 GFP_KERNEL);
1008 if (cmt->channels == NULL) {
1009 ret = -ENOMEM;
1010 goto err_unmap;
1011 }
1012
1013 /*
1014 * Use the first channel as a clock event device and the second channel
1015 * as a clock source. If only one channel is available use it for both.
1016 */
1017 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1018 unsigned int hwidx = ffs(mask) - 1;
1019 bool clocksource = i == 1 || cmt->num_channels == 1;
1020 bool clockevent = i == 0;
1021
1022 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1023 clockevent, clocksource, cmt);
1024 if (ret < 0)
1025 goto err_unmap;
1026
1027 mask &= ~(1 << hwidx);
1028 }
1029
1030 platform_set_drvdata(pdev, cmt);
1031
1032 return 0;
1033
1034err_unmap:
1035 kfree(cmt->channels);
1036 iounmap(cmt->mapbase);
1037err_clk_unprepare:
1038 clk_unprepare(cmt->clk);
1039err_clk_put:
1040 clk_put(cmt->clk);
1041 return ret;
1042}
1043
1044static int sh_cmt_probe(struct platform_device *pdev)
1045{
1046 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1047 int ret;
1048
1049 if (!is_early_platform_device(pdev)) {
1050 pm_runtime_set_active(&pdev->dev);
1051 pm_runtime_enable(&pdev->dev);
1052 }
1053
1054 if (cmt) {
1055 dev_info(&pdev->dev, "kept as earlytimer\n");
1056 goto out;
1057 }
1058
1059 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1060 if (cmt == NULL)
1061 return -ENOMEM;
1062
1063 ret = sh_cmt_setup(cmt, pdev);
1064 if (ret) {
1065 kfree(cmt);
1066 pm_runtime_idle(&pdev->dev);
1067 return ret;
1068 }
1069 if (is_early_platform_device(pdev))
1070 return 0;
1071
1072 out:
1073 if (cmt->has_clockevent || cmt->has_clocksource)
1074 pm_runtime_irq_safe(&pdev->dev);
1075 else
1076 pm_runtime_idle(&pdev->dev);
1077
1078 return 0;
1079}
1080
1081static int sh_cmt_remove(struct platform_device *pdev)
1082{
1083 return -EBUSY; /* cannot unregister clockevent and clocksource */
1084}
1085
1086static struct platform_driver sh_cmt_device_driver = {
1087 .probe = sh_cmt_probe,
1088 .remove = sh_cmt_remove,
1089 .driver = {
1090 .name = "sh_cmt",
1091 .of_match_table = of_match_ptr(sh_cmt_of_table),
1092 },
1093 .id_table = sh_cmt_id_table,
1094};
1095
1096static int __init sh_cmt_init(void)
1097{
1098 return platform_driver_register(&sh_cmt_device_driver);
1099}
1100
1101static void __exit sh_cmt_exit(void)
1102{
1103 platform_driver_unregister(&sh_cmt_device_driver);
1104}
1105
1106early_platform_init("earlytimer", &sh_cmt_device_driver);
1107subsys_initcall(sh_cmt_init);
1108module_exit(sh_cmt_exit);
1109
1110MODULE_AUTHOR("Magnus Damm");
1111MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1112MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH Timer Support - CMT
4 *
5 * Copyright (C) 2008 Magnus Damm
6 */
7
8#include <linux/clk.h>
9#include <linux/clockchips.h>
10#include <linux/clocksource.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/platform_device.h>
22#include <linux/pm_domain.h>
23#include <linux/pm_runtime.h>
24#include <linux/sh_timer.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27
28struct sh_cmt_device;
29
30/*
31 * The CMT comes in 5 different identified flavours, depending not only on the
32 * SoC but also on the particular instance. The following table lists the main
33 * characteristics of those flavours.
34 *
35 * 16B 32B 32B-F 48B R-Car Gen2
36 * -----------------------------------------------------------------------------
37 * Channels 2 1/4 1 6 2/8
38 * Control Width 16 16 16 16 32
39 * Counter Width 16 32 32 32/48 32/48
40 * Shared Start/Stop Y Y Y Y N
41 *
42 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
43 * located in the channel registers block. All other versions have a shared
44 * start/stop register located in the global space.
45 *
46 * Channels are indexed from 0 to N-1 in the documentation. The channel index
47 * infers the start/stop bit position in the control register and the channel
48 * registers block address. Some CMT instances have a subset of channels
49 * available, in which case the index in the documentation doesn't match the
50 * "real" index as implemented in hardware. This is for instance the case with
51 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
52 * in the documentation but using start/stop bit 5 and having its registers
53 * block at 0x60.
54 *
55 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
56 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
57 */
58
59enum sh_cmt_model {
60 SH_CMT_16BIT,
61 SH_CMT_32BIT,
62 SH_CMT_48BIT,
63 SH_CMT0_RCAR_GEN2,
64 SH_CMT1_RCAR_GEN2,
65};
66
67struct sh_cmt_info {
68 enum sh_cmt_model model;
69
70 unsigned int channels_mask;
71
72 unsigned long width; /* 16 or 32 bit version of hardware block */
73 u32 overflow_bit;
74 u32 clear_bits;
75
76 /* callbacks for CMSTR and CMCSR access */
77 u32 (*read_control)(void __iomem *base, unsigned long offs);
78 void (*write_control)(void __iomem *base, unsigned long offs,
79 u32 value);
80
81 /* callbacks for CMCNT and CMCOR access */
82 u32 (*read_count)(void __iomem *base, unsigned long offs);
83 void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
84};
85
86struct sh_cmt_channel {
87 struct sh_cmt_device *cmt;
88
89 unsigned int index; /* Index in the documentation */
90 unsigned int hwidx; /* Real hardware index */
91
92 void __iomem *iostart;
93 void __iomem *ioctrl;
94
95 unsigned int timer_bit;
96 unsigned long flags;
97 u32 match_value;
98 u32 next_match_value;
99 u32 max_match_value;
100 raw_spinlock_t lock;
101 struct clock_event_device ced;
102 struct clocksource cs;
103 u64 total_cycles;
104 bool cs_enabled;
105};
106
107struct sh_cmt_device {
108 struct platform_device *pdev;
109
110 const struct sh_cmt_info *info;
111
112 void __iomem *mapbase;
113 struct clk *clk;
114 unsigned long rate;
115
116 raw_spinlock_t lock; /* Protect the shared start/stop register */
117
118 struct sh_cmt_channel *channels;
119 unsigned int num_channels;
120 unsigned int hw_channels;
121
122 bool has_clockevent;
123 bool has_clocksource;
124};
125
126#define SH_CMT16_CMCSR_CMF (1 << 7)
127#define SH_CMT16_CMCSR_CMIE (1 << 6)
128#define SH_CMT16_CMCSR_CKS8 (0 << 0)
129#define SH_CMT16_CMCSR_CKS32 (1 << 0)
130#define SH_CMT16_CMCSR_CKS128 (2 << 0)
131#define SH_CMT16_CMCSR_CKS512 (3 << 0)
132#define SH_CMT16_CMCSR_CKS_MASK (3 << 0)
133
134#define SH_CMT32_CMCSR_CMF (1 << 15)
135#define SH_CMT32_CMCSR_OVF (1 << 14)
136#define SH_CMT32_CMCSR_WRFLG (1 << 13)
137#define SH_CMT32_CMCSR_STTF (1 << 12)
138#define SH_CMT32_CMCSR_STPF (1 << 11)
139#define SH_CMT32_CMCSR_SSIE (1 << 10)
140#define SH_CMT32_CMCSR_CMS (1 << 9)
141#define SH_CMT32_CMCSR_CMM (1 << 8)
142#define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7)
143#define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
144#define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
145#define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
146#define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
147#define SH_CMT32_CMCSR_DBGIVD (1 << 3)
148#define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
149#define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0)
150#define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0)
151#define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
152#define SH_CMT32_CMCSR_CKS_MASK (7 << 0)
153
154static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
155{
156 return ioread16(base + (offs << 1));
157}
158
159static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
160{
161 return ioread32(base + (offs << 2));
162}
163
164static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
165{
166 iowrite16(value, base + (offs << 1));
167}
168
169static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
170{
171 iowrite32(value, base + (offs << 2));
172}
173
174static const struct sh_cmt_info sh_cmt_info[] = {
175 [SH_CMT_16BIT] = {
176 .model = SH_CMT_16BIT,
177 .width = 16,
178 .overflow_bit = SH_CMT16_CMCSR_CMF,
179 .clear_bits = ~SH_CMT16_CMCSR_CMF,
180 .read_control = sh_cmt_read16,
181 .write_control = sh_cmt_write16,
182 .read_count = sh_cmt_read16,
183 .write_count = sh_cmt_write16,
184 },
185 [SH_CMT_32BIT] = {
186 .model = SH_CMT_32BIT,
187 .width = 32,
188 .overflow_bit = SH_CMT32_CMCSR_CMF,
189 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
190 .read_control = sh_cmt_read16,
191 .write_control = sh_cmt_write16,
192 .read_count = sh_cmt_read32,
193 .write_count = sh_cmt_write32,
194 },
195 [SH_CMT_48BIT] = {
196 .model = SH_CMT_48BIT,
197 .channels_mask = 0x3f,
198 .width = 32,
199 .overflow_bit = SH_CMT32_CMCSR_CMF,
200 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
201 .read_control = sh_cmt_read32,
202 .write_control = sh_cmt_write32,
203 .read_count = sh_cmt_read32,
204 .write_count = sh_cmt_write32,
205 },
206 [SH_CMT0_RCAR_GEN2] = {
207 .model = SH_CMT0_RCAR_GEN2,
208 .channels_mask = 0x60,
209 .width = 32,
210 .overflow_bit = SH_CMT32_CMCSR_CMF,
211 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
212 .read_control = sh_cmt_read32,
213 .write_control = sh_cmt_write32,
214 .read_count = sh_cmt_read32,
215 .write_count = sh_cmt_write32,
216 },
217 [SH_CMT1_RCAR_GEN2] = {
218 .model = SH_CMT1_RCAR_GEN2,
219 .channels_mask = 0xff,
220 .width = 32,
221 .overflow_bit = SH_CMT32_CMCSR_CMF,
222 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
223 .read_control = sh_cmt_read32,
224 .write_control = sh_cmt_write32,
225 .read_count = sh_cmt_read32,
226 .write_count = sh_cmt_write32,
227 },
228};
229
230#define CMCSR 0 /* channel register */
231#define CMCNT 1 /* channel register */
232#define CMCOR 2 /* channel register */
233
234static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
235{
236 if (ch->iostart)
237 return ch->cmt->info->read_control(ch->iostart, 0);
238 else
239 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
240}
241
242static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
243{
244 if (ch->iostart)
245 ch->cmt->info->write_control(ch->iostart, 0, value);
246 else
247 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
248}
249
250static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
251{
252 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
253}
254
255static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
256{
257 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
258}
259
260static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
261{
262 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
263}
264
265static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
266{
267 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
268}
269
270static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
271{
272 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
273}
274
275static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
276{
277 u32 v1, v2, v3;
278 u32 o1, o2;
279
280 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
281
282 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
283 do {
284 o2 = o1;
285 v1 = sh_cmt_read_cmcnt(ch);
286 v2 = sh_cmt_read_cmcnt(ch);
287 v3 = sh_cmt_read_cmcnt(ch);
288 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
289 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
290 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
291
292 *has_wrapped = o1;
293 return v2;
294}
295
296static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
297{
298 unsigned long flags;
299 u32 value;
300
301 /* start stop register shared by multiple timer channels */
302 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
303 value = sh_cmt_read_cmstr(ch);
304
305 if (start)
306 value |= 1 << ch->timer_bit;
307 else
308 value &= ~(1 << ch->timer_bit);
309
310 sh_cmt_write_cmstr(ch, value);
311 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
312}
313
314static int sh_cmt_enable(struct sh_cmt_channel *ch)
315{
316 int k, ret;
317
318 pm_runtime_get_sync(&ch->cmt->pdev->dev);
319 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
320
321 /* enable clock */
322 ret = clk_enable(ch->cmt->clk);
323 if (ret) {
324 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
325 ch->index);
326 goto err0;
327 }
328
329 /* make sure channel is disabled */
330 sh_cmt_start_stop_ch(ch, 0);
331
332 /* configure channel, periodic mode and maximum timeout */
333 if (ch->cmt->info->width == 16) {
334 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
335 SH_CMT16_CMCSR_CKS512);
336 } else {
337 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
338 SH_CMT32_CMCSR_CMTOUT_IE |
339 SH_CMT32_CMCSR_CMR_IRQ |
340 SH_CMT32_CMCSR_CKS_RCLK8);
341 }
342
343 sh_cmt_write_cmcor(ch, 0xffffffff);
344 sh_cmt_write_cmcnt(ch, 0);
345
346 /*
347 * According to the sh73a0 user's manual, as CMCNT can be operated
348 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
349 * modifying CMCNT register; two RCLK cycles are necessary before
350 * this register is either read or any modification of the value
351 * it holds is reflected in the LSI's actual operation.
352 *
353 * While at it, we're supposed to clear out the CMCNT as of this
354 * moment, so make sure it's processed properly here. This will
355 * take RCLKx2 at maximum.
356 */
357 for (k = 0; k < 100; k++) {
358 if (!sh_cmt_read_cmcnt(ch))
359 break;
360 udelay(1);
361 }
362
363 if (sh_cmt_read_cmcnt(ch)) {
364 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
365 ch->index);
366 ret = -ETIMEDOUT;
367 goto err1;
368 }
369
370 /* enable channel */
371 sh_cmt_start_stop_ch(ch, 1);
372 return 0;
373 err1:
374 /* stop clock */
375 clk_disable(ch->cmt->clk);
376
377 err0:
378 return ret;
379}
380
381static void sh_cmt_disable(struct sh_cmt_channel *ch)
382{
383 /* disable channel */
384 sh_cmt_start_stop_ch(ch, 0);
385
386 /* disable interrupts in CMT block */
387 sh_cmt_write_cmcsr(ch, 0);
388
389 /* stop clock */
390 clk_disable(ch->cmt->clk);
391
392 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
393 pm_runtime_put(&ch->cmt->pdev->dev);
394}
395
396/* private flags */
397#define FLAG_CLOCKEVENT (1 << 0)
398#define FLAG_CLOCKSOURCE (1 << 1)
399#define FLAG_REPROGRAM (1 << 2)
400#define FLAG_SKIPEVENT (1 << 3)
401#define FLAG_IRQCONTEXT (1 << 4)
402
403static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
404 int absolute)
405{
406 u32 value = ch->next_match_value;
407 u32 new_match;
408 u32 delay = 0;
409 u32 now = 0;
410 u32 has_wrapped;
411
412 now = sh_cmt_get_counter(ch, &has_wrapped);
413 ch->flags |= FLAG_REPROGRAM; /* force reprogram */
414
415 if (has_wrapped) {
416 /* we're competing with the interrupt handler.
417 * -> let the interrupt handler reprogram the timer.
418 * -> interrupt number two handles the event.
419 */
420 ch->flags |= FLAG_SKIPEVENT;
421 return;
422 }
423
424 if (absolute)
425 now = 0;
426
427 do {
428 /* reprogram the timer hardware,
429 * but don't save the new match value yet.
430 */
431 new_match = now + value + delay;
432 if (new_match > ch->max_match_value)
433 new_match = ch->max_match_value;
434
435 sh_cmt_write_cmcor(ch, new_match);
436
437 now = sh_cmt_get_counter(ch, &has_wrapped);
438 if (has_wrapped && (new_match > ch->match_value)) {
439 /* we are changing to a greater match value,
440 * so this wrap must be caused by the counter
441 * matching the old value.
442 * -> first interrupt reprograms the timer.
443 * -> interrupt number two handles the event.
444 */
445 ch->flags |= FLAG_SKIPEVENT;
446 break;
447 }
448
449 if (has_wrapped) {
450 /* we are changing to a smaller match value,
451 * so the wrap must be caused by the counter
452 * matching the new value.
453 * -> save programmed match value.
454 * -> let isr handle the event.
455 */
456 ch->match_value = new_match;
457 break;
458 }
459
460 /* be safe: verify hardware settings */
461 if (now < new_match) {
462 /* timer value is below match value, all good.
463 * this makes sure we won't miss any match events.
464 * -> save programmed match value.
465 * -> let isr handle the event.
466 */
467 ch->match_value = new_match;
468 break;
469 }
470
471 /* the counter has reached a value greater
472 * than our new match value. and since the
473 * has_wrapped flag isn't set we must have
474 * programmed a too close event.
475 * -> increase delay and retry.
476 */
477 if (delay)
478 delay <<= 1;
479 else
480 delay = 1;
481
482 if (!delay)
483 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
484 ch->index);
485
486 } while (delay);
487}
488
489static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
490{
491 if (delta > ch->max_match_value)
492 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
493 ch->index);
494
495 ch->next_match_value = delta;
496 sh_cmt_clock_event_program_verify(ch, 0);
497}
498
499static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
500{
501 unsigned long flags;
502
503 raw_spin_lock_irqsave(&ch->lock, flags);
504 __sh_cmt_set_next(ch, delta);
505 raw_spin_unlock_irqrestore(&ch->lock, flags);
506}
507
508static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
509{
510 struct sh_cmt_channel *ch = dev_id;
511
512 /* clear flags */
513 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
514 ch->cmt->info->clear_bits);
515
516 /* update clock source counter to begin with if enabled
517 * the wrap flag should be cleared by the timer specific
518 * isr before we end up here.
519 */
520 if (ch->flags & FLAG_CLOCKSOURCE)
521 ch->total_cycles += ch->match_value + 1;
522
523 if (!(ch->flags & FLAG_REPROGRAM))
524 ch->next_match_value = ch->max_match_value;
525
526 ch->flags |= FLAG_IRQCONTEXT;
527
528 if (ch->flags & FLAG_CLOCKEVENT) {
529 if (!(ch->flags & FLAG_SKIPEVENT)) {
530 if (clockevent_state_oneshot(&ch->ced)) {
531 ch->next_match_value = ch->max_match_value;
532 ch->flags |= FLAG_REPROGRAM;
533 }
534
535 ch->ced.event_handler(&ch->ced);
536 }
537 }
538
539 ch->flags &= ~FLAG_SKIPEVENT;
540
541 if (ch->flags & FLAG_REPROGRAM) {
542 ch->flags &= ~FLAG_REPROGRAM;
543 sh_cmt_clock_event_program_verify(ch, 1);
544
545 if (ch->flags & FLAG_CLOCKEVENT)
546 if ((clockevent_state_shutdown(&ch->ced))
547 || (ch->match_value == ch->next_match_value))
548 ch->flags &= ~FLAG_REPROGRAM;
549 }
550
551 ch->flags &= ~FLAG_IRQCONTEXT;
552
553 return IRQ_HANDLED;
554}
555
556static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
557{
558 int ret = 0;
559 unsigned long flags;
560
561 raw_spin_lock_irqsave(&ch->lock, flags);
562
563 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
564 ret = sh_cmt_enable(ch);
565
566 if (ret)
567 goto out;
568 ch->flags |= flag;
569
570 /* setup timeout if no clockevent */
571 if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
572 __sh_cmt_set_next(ch, ch->max_match_value);
573 out:
574 raw_spin_unlock_irqrestore(&ch->lock, flags);
575
576 return ret;
577}
578
579static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
580{
581 unsigned long flags;
582 unsigned long f;
583
584 raw_spin_lock_irqsave(&ch->lock, flags);
585
586 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
587 ch->flags &= ~flag;
588
589 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
590 sh_cmt_disable(ch);
591
592 /* adjust the timeout to maximum if only clocksource left */
593 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
594 __sh_cmt_set_next(ch, ch->max_match_value);
595
596 raw_spin_unlock_irqrestore(&ch->lock, flags);
597}
598
599static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
600{
601 return container_of(cs, struct sh_cmt_channel, cs);
602}
603
604static u64 sh_cmt_clocksource_read(struct clocksource *cs)
605{
606 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
607 unsigned long flags;
608 u32 has_wrapped;
609 u64 value;
610 u32 raw;
611
612 raw_spin_lock_irqsave(&ch->lock, flags);
613 value = ch->total_cycles;
614 raw = sh_cmt_get_counter(ch, &has_wrapped);
615
616 if (unlikely(has_wrapped))
617 raw += ch->match_value + 1;
618 raw_spin_unlock_irqrestore(&ch->lock, flags);
619
620 return value + raw;
621}
622
623static int sh_cmt_clocksource_enable(struct clocksource *cs)
624{
625 int ret;
626 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
627
628 WARN_ON(ch->cs_enabled);
629
630 ch->total_cycles = 0;
631
632 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
633 if (!ret)
634 ch->cs_enabled = true;
635
636 return ret;
637}
638
639static void sh_cmt_clocksource_disable(struct clocksource *cs)
640{
641 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
642
643 WARN_ON(!ch->cs_enabled);
644
645 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
646 ch->cs_enabled = false;
647}
648
649static void sh_cmt_clocksource_suspend(struct clocksource *cs)
650{
651 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
652
653 if (!ch->cs_enabled)
654 return;
655
656 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
657 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
658}
659
660static void sh_cmt_clocksource_resume(struct clocksource *cs)
661{
662 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
663
664 if (!ch->cs_enabled)
665 return;
666
667 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
668 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
669}
670
671static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
672 const char *name)
673{
674 struct clocksource *cs = &ch->cs;
675
676 cs->name = name;
677 cs->rating = 125;
678 cs->read = sh_cmt_clocksource_read;
679 cs->enable = sh_cmt_clocksource_enable;
680 cs->disable = sh_cmt_clocksource_disable;
681 cs->suspend = sh_cmt_clocksource_suspend;
682 cs->resume = sh_cmt_clocksource_resume;
683 cs->mask = CLOCKSOURCE_MASK(sizeof(u64) * 8);
684 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
685
686 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
687 ch->index);
688
689 clocksource_register_hz(cs, ch->cmt->rate);
690 return 0;
691}
692
693static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
694{
695 return container_of(ced, struct sh_cmt_channel, ced);
696}
697
698static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
699{
700 sh_cmt_start(ch, FLAG_CLOCKEVENT);
701
702 if (periodic)
703 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
704 else
705 sh_cmt_set_next(ch, ch->max_match_value);
706}
707
708static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
709{
710 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
711
712 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
713 return 0;
714}
715
716static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
717 int periodic)
718{
719 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
720
721 /* deal with old setting first */
722 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
723 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
724
725 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
726 ch->index, periodic ? "periodic" : "oneshot");
727 sh_cmt_clock_event_start(ch, periodic);
728 return 0;
729}
730
731static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
732{
733 return sh_cmt_clock_event_set_state(ced, 0);
734}
735
736static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
737{
738 return sh_cmt_clock_event_set_state(ced, 1);
739}
740
741static int sh_cmt_clock_event_next(unsigned long delta,
742 struct clock_event_device *ced)
743{
744 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
745
746 BUG_ON(!clockevent_state_oneshot(ced));
747 if (likely(ch->flags & FLAG_IRQCONTEXT))
748 ch->next_match_value = delta - 1;
749 else
750 sh_cmt_set_next(ch, delta - 1);
751
752 return 0;
753}
754
755static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
756{
757 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
758
759 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
760 clk_unprepare(ch->cmt->clk);
761}
762
763static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
764{
765 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
766
767 clk_prepare(ch->cmt->clk);
768 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
769}
770
771static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
772 const char *name)
773{
774 struct clock_event_device *ced = &ch->ced;
775 int irq;
776 int ret;
777
778 irq = platform_get_irq(ch->cmt->pdev, ch->index);
779 if (irq < 0)
780 return irq;
781
782 ret = request_irq(irq, sh_cmt_interrupt,
783 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
784 dev_name(&ch->cmt->pdev->dev), ch);
785 if (ret) {
786 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
787 ch->index, irq);
788 return ret;
789 }
790
791 ced->name = name;
792 ced->features = CLOCK_EVT_FEAT_PERIODIC;
793 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
794 ced->rating = 125;
795 ced->cpumask = cpu_possible_mask;
796 ced->set_next_event = sh_cmt_clock_event_next;
797 ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
798 ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
799 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
800 ced->suspend = sh_cmt_clock_event_suspend;
801 ced->resume = sh_cmt_clock_event_resume;
802
803 /* TODO: calculate good shift from rate and counter bit width */
804 ced->shift = 32;
805 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
806 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
807 ced->max_delta_ticks = ch->max_match_value;
808 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
809 ced->min_delta_ticks = 0x1f;
810
811 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
812 ch->index);
813 clockevents_register_device(ced);
814
815 return 0;
816}
817
818static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
819 bool clockevent, bool clocksource)
820{
821 int ret;
822
823 if (clockevent) {
824 ch->cmt->has_clockevent = true;
825 ret = sh_cmt_register_clockevent(ch, name);
826 if (ret < 0)
827 return ret;
828 }
829
830 if (clocksource) {
831 ch->cmt->has_clocksource = true;
832 sh_cmt_register_clocksource(ch, name);
833 }
834
835 return 0;
836}
837
838static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
839 unsigned int hwidx, bool clockevent,
840 bool clocksource, struct sh_cmt_device *cmt)
841{
842 int ret;
843
844 /* Skip unused channels. */
845 if (!clockevent && !clocksource)
846 return 0;
847
848 ch->cmt = cmt;
849 ch->index = index;
850 ch->hwidx = hwidx;
851 ch->timer_bit = hwidx;
852
853 /*
854 * Compute the address of the channel control register block. For the
855 * timers with a per-channel start/stop register, compute its address
856 * as well.
857 */
858 switch (cmt->info->model) {
859 case SH_CMT_16BIT:
860 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
861 break;
862 case SH_CMT_32BIT:
863 case SH_CMT_48BIT:
864 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
865 break;
866 case SH_CMT0_RCAR_GEN2:
867 case SH_CMT1_RCAR_GEN2:
868 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
869 ch->ioctrl = ch->iostart + 0x10;
870 ch->timer_bit = 0;
871 break;
872 }
873
874 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
875 ch->max_match_value = ~0;
876 else
877 ch->max_match_value = (1 << cmt->info->width) - 1;
878
879 ch->match_value = ch->max_match_value;
880 raw_spin_lock_init(&ch->lock);
881
882 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
883 clockevent, clocksource);
884 if (ret) {
885 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
886 ch->index);
887 return ret;
888 }
889 ch->cs_enabled = false;
890
891 return 0;
892}
893
894static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
895{
896 struct resource *mem;
897
898 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
899 if (!mem) {
900 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
901 return -ENXIO;
902 }
903
904 cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
905 if (cmt->mapbase == NULL) {
906 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
907 return -ENXIO;
908 }
909
910 return 0;
911}
912
913static const struct platform_device_id sh_cmt_id_table[] = {
914 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
915 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
916 { }
917};
918MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
919
920static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
921 {
922 /* deprecated, preserved for backward compatibility */
923 .compatible = "renesas,cmt-48",
924 .data = &sh_cmt_info[SH_CMT_48BIT]
925 },
926 {
927 /* deprecated, preserved for backward compatibility */
928 .compatible = "renesas,cmt-48-gen2",
929 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
930 },
931 {
932 .compatible = "renesas,r8a7740-cmt1",
933 .data = &sh_cmt_info[SH_CMT_48BIT]
934 },
935 {
936 .compatible = "renesas,sh73a0-cmt1",
937 .data = &sh_cmt_info[SH_CMT_48BIT]
938 },
939 {
940 .compatible = "renesas,rcar-gen2-cmt0",
941 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
942 },
943 {
944 .compatible = "renesas,rcar-gen2-cmt1",
945 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
946 },
947 {
948 .compatible = "renesas,rcar-gen3-cmt0",
949 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
950 },
951 {
952 .compatible = "renesas,rcar-gen3-cmt1",
953 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
954 },
955 { }
956};
957MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
958
959static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
960{
961 unsigned int mask;
962 unsigned int i;
963 int ret;
964
965 cmt->pdev = pdev;
966 raw_spin_lock_init(&cmt->lock);
967
968 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
969 cmt->info = of_device_get_match_data(&pdev->dev);
970 cmt->hw_channels = cmt->info->channels_mask;
971 } else if (pdev->dev.platform_data) {
972 struct sh_timer_config *cfg = pdev->dev.platform_data;
973 const struct platform_device_id *id = pdev->id_entry;
974
975 cmt->info = (const struct sh_cmt_info *)id->driver_data;
976 cmt->hw_channels = cfg->channels_mask;
977 } else {
978 dev_err(&cmt->pdev->dev, "missing platform data\n");
979 return -ENXIO;
980 }
981
982 /* Get hold of clock. */
983 cmt->clk = clk_get(&cmt->pdev->dev, "fck");
984 if (IS_ERR(cmt->clk)) {
985 dev_err(&cmt->pdev->dev, "cannot get clock\n");
986 return PTR_ERR(cmt->clk);
987 }
988
989 ret = clk_prepare(cmt->clk);
990 if (ret < 0)
991 goto err_clk_put;
992
993 /* Determine clock rate. */
994 ret = clk_enable(cmt->clk);
995 if (ret < 0)
996 goto err_clk_unprepare;
997
998 if (cmt->info->width == 16)
999 cmt->rate = clk_get_rate(cmt->clk) / 512;
1000 else
1001 cmt->rate = clk_get_rate(cmt->clk) / 8;
1002
1003 clk_disable(cmt->clk);
1004
1005 /* Map the memory resource(s). */
1006 ret = sh_cmt_map_memory(cmt);
1007 if (ret < 0)
1008 goto err_clk_unprepare;
1009
1010 /* Allocate and setup the channels. */
1011 cmt->num_channels = hweight8(cmt->hw_channels);
1012 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1013 GFP_KERNEL);
1014 if (cmt->channels == NULL) {
1015 ret = -ENOMEM;
1016 goto err_unmap;
1017 }
1018
1019 /*
1020 * Use the first channel as a clock event device and the second channel
1021 * as a clock source. If only one channel is available use it for both.
1022 */
1023 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1024 unsigned int hwidx = ffs(mask) - 1;
1025 bool clocksource = i == 1 || cmt->num_channels == 1;
1026 bool clockevent = i == 0;
1027
1028 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1029 clockevent, clocksource, cmt);
1030 if (ret < 0)
1031 goto err_unmap;
1032
1033 mask &= ~(1 << hwidx);
1034 }
1035
1036 platform_set_drvdata(pdev, cmt);
1037
1038 return 0;
1039
1040err_unmap:
1041 kfree(cmt->channels);
1042 iounmap(cmt->mapbase);
1043err_clk_unprepare:
1044 clk_unprepare(cmt->clk);
1045err_clk_put:
1046 clk_put(cmt->clk);
1047 return ret;
1048}
1049
1050static int sh_cmt_probe(struct platform_device *pdev)
1051{
1052 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1053 int ret;
1054
1055 if (!is_early_platform_device(pdev)) {
1056 pm_runtime_set_active(&pdev->dev);
1057 pm_runtime_enable(&pdev->dev);
1058 }
1059
1060 if (cmt) {
1061 dev_info(&pdev->dev, "kept as earlytimer\n");
1062 goto out;
1063 }
1064
1065 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1066 if (cmt == NULL)
1067 return -ENOMEM;
1068
1069 ret = sh_cmt_setup(cmt, pdev);
1070 if (ret) {
1071 kfree(cmt);
1072 pm_runtime_idle(&pdev->dev);
1073 return ret;
1074 }
1075 if (is_early_platform_device(pdev))
1076 return 0;
1077
1078 out:
1079 if (cmt->has_clockevent || cmt->has_clocksource)
1080 pm_runtime_irq_safe(&pdev->dev);
1081 else
1082 pm_runtime_idle(&pdev->dev);
1083
1084 return 0;
1085}
1086
1087static int sh_cmt_remove(struct platform_device *pdev)
1088{
1089 return -EBUSY; /* cannot unregister clockevent and clocksource */
1090}
1091
1092static struct platform_driver sh_cmt_device_driver = {
1093 .probe = sh_cmt_probe,
1094 .remove = sh_cmt_remove,
1095 .driver = {
1096 .name = "sh_cmt",
1097 .of_match_table = of_match_ptr(sh_cmt_of_table),
1098 },
1099 .id_table = sh_cmt_id_table,
1100};
1101
1102static int __init sh_cmt_init(void)
1103{
1104 return platform_driver_register(&sh_cmt_device_driver);
1105}
1106
1107static void __exit sh_cmt_exit(void)
1108{
1109 platform_driver_unregister(&sh_cmt_device_driver);
1110}
1111
1112early_platform_init("earlytimer", &sh_cmt_device_driver);
1113subsys_initcall(sh_cmt_init);
1114module_exit(sh_cmt_exit);
1115
1116MODULE_AUTHOR("Magnus Damm");
1117MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1118MODULE_LICENSE("GPL v2");