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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV MMR definitions
7 *
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef _ASM_IA64_UV_UV_MMRS_H
12#define _ASM_IA64_UV_UV_MMRS_H
13
14#define UV_MMR_ENABLE (1UL << 63)
15
16/* ========================================================================= */
17/* UVH_BAU_DATA_CONFIG */
18/* ========================================================================= */
19#define UVH_BAU_DATA_CONFIG 0x61680UL
20#define UVH_BAU_DATA_CONFIG_32 0x0438
21
22#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
23#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
24#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
25#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
26#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
27#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
28#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
29#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
30#define UVH_BAU_DATA_CONFIG_P_SHFT 13
31#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
32#define UVH_BAU_DATA_CONFIG_T_SHFT 15
33#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
34#define UVH_BAU_DATA_CONFIG_M_SHFT 16
35#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
36#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
37#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
38
39union uvh_bau_data_config_u {
40 unsigned long v;
41 struct uvh_bau_data_config_s {
42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
45 unsigned long status : 1; /* RO */
46 unsigned long p : 1; /* RO */
47 unsigned long rsvd_14 : 1; /* */
48 unsigned long t : 1; /* RO */
49 unsigned long m : 1; /* RW */
50 unsigned long rsvd_17_31: 15; /* */
51 unsigned long apic_id : 32; /* RW */
52 } s;
53};
54
55/* ========================================================================= */
56/* UVH_EVENT_OCCURRED0 */
57/* ========================================================================= */
58#define UVH_EVENT_OCCURRED0 0x70000UL
59#define UVH_EVENT_OCCURRED0_32 0x005e8
60
61#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
62#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
63#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
64#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
65#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
66#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
67#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
68#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
69#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
70#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
71#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
72#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
73#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
74#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
75#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
76#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
77#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
78#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
79#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
80#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
81#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
82#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
83#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
84#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
85#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
86#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
87#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
88#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
89#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
90#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
91#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
92#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
93#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
94#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
95#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
96#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
97#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
98#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
99#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
100#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
101#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
102#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
103#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
104#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
105#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
106#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
107#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
108#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
109#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
110#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
111#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
112#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
113#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
114#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
115#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
116#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
117#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
118#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
119#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
120#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
121#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
122#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
123#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
124#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
125#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
126#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
127#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
128#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
129#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
130#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
131#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
132#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
133#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
134#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
135#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
136#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
137#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
138#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
139#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
140#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
141#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
142#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
143#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
144#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
145#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
146#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
147#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
148#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
149#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
150#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
151#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
152#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
153#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
154#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
155#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
156#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
157#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
158#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
159#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
160#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
161#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
162#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
163#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
164#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
165#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
166#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
167#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
168#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
169#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
170#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
171#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
172#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
173#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
174#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
175union uvh_event_occurred0_u {
176 unsigned long v;
177 struct uvh_event_occurred0_s {
178 unsigned long lb_hcerr : 1; /* RW, W1C */
179 unsigned long gr0_hcerr : 1; /* RW, W1C */
180 unsigned long gr1_hcerr : 1; /* RW, W1C */
181 unsigned long lh_hcerr : 1; /* RW, W1C */
182 unsigned long rh_hcerr : 1; /* RW, W1C */
183 unsigned long xn_hcerr : 1; /* RW, W1C */
184 unsigned long si_hcerr : 1; /* RW, W1C */
185 unsigned long lb_aoerr0 : 1; /* RW, W1C */
186 unsigned long gr0_aoerr0 : 1; /* RW, W1C */
187 unsigned long gr1_aoerr0 : 1; /* RW, W1C */
188 unsigned long lh_aoerr0 : 1; /* RW, W1C */
189 unsigned long rh_aoerr0 : 1; /* RW, W1C */
190 unsigned long xn_aoerr0 : 1; /* RW, W1C */
191 unsigned long si_aoerr0 : 1; /* RW, W1C */
192 unsigned long lb_aoerr1 : 1; /* RW, W1C */
193 unsigned long gr0_aoerr1 : 1; /* RW, W1C */
194 unsigned long gr1_aoerr1 : 1; /* RW, W1C */
195 unsigned long lh_aoerr1 : 1; /* RW, W1C */
196 unsigned long rh_aoerr1 : 1; /* RW, W1C */
197 unsigned long xn_aoerr1 : 1; /* RW, W1C */
198 unsigned long si_aoerr1 : 1; /* RW, W1C */
199 unsigned long rh_vpi_int : 1; /* RW, W1C */
200 unsigned long system_shutdown_int : 1; /* RW, W1C */
201 unsigned long lb_irq_int_0 : 1; /* RW, W1C */
202 unsigned long lb_irq_int_1 : 1; /* RW, W1C */
203 unsigned long lb_irq_int_2 : 1; /* RW, W1C */
204 unsigned long lb_irq_int_3 : 1; /* RW, W1C */
205 unsigned long lb_irq_int_4 : 1; /* RW, W1C */
206 unsigned long lb_irq_int_5 : 1; /* RW, W1C */
207 unsigned long lb_irq_int_6 : 1; /* RW, W1C */
208 unsigned long lb_irq_int_7 : 1; /* RW, W1C */
209 unsigned long lb_irq_int_8 : 1; /* RW, W1C */
210 unsigned long lb_irq_int_9 : 1; /* RW, W1C */
211 unsigned long lb_irq_int_10 : 1; /* RW, W1C */
212 unsigned long lb_irq_int_11 : 1; /* RW, W1C */
213 unsigned long lb_irq_int_12 : 1; /* RW, W1C */
214 unsigned long lb_irq_int_13 : 1; /* RW, W1C */
215 unsigned long lb_irq_int_14 : 1; /* RW, W1C */
216 unsigned long lb_irq_int_15 : 1; /* RW, W1C */
217 unsigned long l1_nmi_int : 1; /* RW, W1C */
218 unsigned long stop_clock : 1; /* RW, W1C */
219 unsigned long asic_to_l1 : 1; /* RW, W1C */
220 unsigned long l1_to_asic : 1; /* RW, W1C */
221 unsigned long ltc_int : 1; /* RW, W1C */
222 unsigned long la_seq_trigger : 1; /* RW, W1C */
223 unsigned long ipi_int : 1; /* RW, W1C */
224 unsigned long extio_int0 : 1; /* RW, W1C */
225 unsigned long extio_int1 : 1; /* RW, W1C */
226 unsigned long extio_int2 : 1; /* RW, W1C */
227 unsigned long extio_int3 : 1; /* RW, W1C */
228 unsigned long profile_int : 1; /* RW, W1C */
229 unsigned long rtc0 : 1; /* RW, W1C */
230 unsigned long rtc1 : 1; /* RW, W1C */
231 unsigned long rtc2 : 1; /* RW, W1C */
232 unsigned long rtc3 : 1; /* RW, W1C */
233 unsigned long bau_data : 1; /* RW, W1C */
234 unsigned long power_management_req : 1; /* RW, W1C */
235 unsigned long rsvd_57_63 : 7; /* */
236 } s;
237};
238
239/* ========================================================================= */
240/* UVH_EVENT_OCCURRED0_ALIAS */
241/* ========================================================================= */
242#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
243#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
244
245/* ========================================================================= */
246/* UVH_GR0_TLB_INT0_CONFIG */
247/* ========================================================================= */
248#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
249
250#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
251#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
252#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
253#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
254#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
255#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
256#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
257#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
258#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
259#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
260#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
261#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
262#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
263#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
264#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
265#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
266
267union uvh_gr0_tlb_int0_config_u {
268 unsigned long v;
269 struct uvh_gr0_tlb_int0_config_s {
270 unsigned long vector_ : 8; /* RW */
271 unsigned long dm : 3; /* RW */
272 unsigned long destmode : 1; /* RW */
273 unsigned long status : 1; /* RO */
274 unsigned long p : 1; /* RO */
275 unsigned long rsvd_14 : 1; /* */
276 unsigned long t : 1; /* RO */
277 unsigned long m : 1; /* RW */
278 unsigned long rsvd_17_31: 15; /* */
279 unsigned long apic_id : 32; /* RW */
280 } s;
281};
282
283/* ========================================================================= */
284/* UVH_GR0_TLB_INT1_CONFIG */
285/* ========================================================================= */
286#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
287
288#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
289#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
290#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
291#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
292#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
293#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
294#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
295#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
296#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
297#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
298#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
299#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
300#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
301#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
302#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
303#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
304
305union uvh_gr0_tlb_int1_config_u {
306 unsigned long v;
307 struct uvh_gr0_tlb_int1_config_s {
308 unsigned long vector_ : 8; /* RW */
309 unsigned long dm : 3; /* RW */
310 unsigned long destmode : 1; /* RW */
311 unsigned long status : 1; /* RO */
312 unsigned long p : 1; /* RO */
313 unsigned long rsvd_14 : 1; /* */
314 unsigned long t : 1; /* RO */
315 unsigned long m : 1; /* RW */
316 unsigned long rsvd_17_31: 15; /* */
317 unsigned long apic_id : 32; /* RW */
318 } s;
319};
320
321/* ========================================================================= */
322/* UVH_GR1_TLB_INT0_CONFIG */
323/* ========================================================================= */
324#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
325
326#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
327#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
328#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
329#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
330#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
331#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
332#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
333#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
334#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
335#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
336#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
337#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
338#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
339#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
340#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
341#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
342
343union uvh_gr1_tlb_int0_config_u {
344 unsigned long v;
345 struct uvh_gr1_tlb_int0_config_s {
346 unsigned long vector_ : 8; /* RW */
347 unsigned long dm : 3; /* RW */
348 unsigned long destmode : 1; /* RW */
349 unsigned long status : 1; /* RO */
350 unsigned long p : 1; /* RO */
351 unsigned long rsvd_14 : 1; /* */
352 unsigned long t : 1; /* RO */
353 unsigned long m : 1; /* RW */
354 unsigned long rsvd_17_31: 15; /* */
355 unsigned long apic_id : 32; /* RW */
356 } s;
357};
358
359/* ========================================================================= */
360/* UVH_GR1_TLB_INT1_CONFIG */
361/* ========================================================================= */
362#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
363
364#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
365#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
366#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
367#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
368#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
369#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
370#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
371#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
372#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
373#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
374#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
375#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
376#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
377#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
378#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
379#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
380
381union uvh_gr1_tlb_int1_config_u {
382 unsigned long v;
383 struct uvh_gr1_tlb_int1_config_s {
384 unsigned long vector_ : 8; /* RW */
385 unsigned long dm : 3; /* RW */
386 unsigned long destmode : 1; /* RW */
387 unsigned long status : 1; /* RO */
388 unsigned long p : 1; /* RO */
389 unsigned long rsvd_14 : 1; /* */
390 unsigned long t : 1; /* RO */
391 unsigned long m : 1; /* RW */
392 unsigned long rsvd_17_31: 15; /* */
393 unsigned long apic_id : 32; /* RW */
394 } s;
395};
396
397/* ========================================================================= */
398/* UVH_INT_CMPB */
399/* ========================================================================= */
400#define UVH_INT_CMPB 0x22080UL
401
402#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
403#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
404
405union uvh_int_cmpb_u {
406 unsigned long v;
407 struct uvh_int_cmpb_s {
408 unsigned long real_time_cmpb : 56; /* RW */
409 unsigned long rsvd_56_63 : 8; /* */
410 } s;
411};
412
413/* ========================================================================= */
414/* UVH_INT_CMPC */
415/* ========================================================================= */
416#define UVH_INT_CMPC 0x22100UL
417
418#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
419#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
420
421union uvh_int_cmpc_u {
422 unsigned long v;
423 struct uvh_int_cmpc_s {
424 unsigned long real_time_cmpc : 56; /* RW */
425 unsigned long rsvd_56_63 : 8; /* */
426 } s;
427};
428
429/* ========================================================================= */
430/* UVH_INT_CMPD */
431/* ========================================================================= */
432#define UVH_INT_CMPD 0x22180UL
433
434#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
435#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
436
437union uvh_int_cmpd_u {
438 unsigned long v;
439 struct uvh_int_cmpd_s {
440 unsigned long real_time_cmpd : 56; /* RW */
441 unsigned long rsvd_56_63 : 8; /* */
442 } s;
443};
444
445/* ========================================================================= */
446/* UVH_NODE_ID */
447/* ========================================================================= */
448#define UVH_NODE_ID 0x0UL
449
450#define UVH_NODE_ID_FORCE1_SHFT 0
451#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
452#define UVH_NODE_ID_MANUFACTURER_SHFT 1
453#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
454#define UVH_NODE_ID_PART_NUMBER_SHFT 12
455#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
456#define UVH_NODE_ID_REVISION_SHFT 28
457#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
458#define UVH_NODE_ID_NODE_ID_SHFT 32
459#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
460#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
461#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
462#define UVH_NODE_ID_NI_PORT_SHFT 56
463#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
464
465union uvh_node_id_u {
466 unsigned long v;
467 struct uvh_node_id_s {
468 unsigned long force1 : 1; /* RO */
469 unsigned long manufacturer : 11; /* RO */
470 unsigned long part_number : 16; /* RO */
471 unsigned long revision : 4; /* RO */
472 unsigned long node_id : 15; /* RW */
473 unsigned long rsvd_47 : 1; /* */
474 unsigned long nodes_per_bit : 7; /* RW */
475 unsigned long rsvd_55 : 1; /* */
476 unsigned long ni_port : 4; /* RO */
477 unsigned long rsvd_60_63 : 4; /* */
478 } s;
479};
480
481/* ========================================================================= */
482/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
483/* ========================================================================= */
484#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
485
486#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
487#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
488
489union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
490 unsigned long v;
491 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
492 unsigned long rsvd_0_23 : 24; /* */
493 unsigned long dest_base : 22; /* RW */
494 unsigned long rsvd_46_63: 18; /* */
495 } s;
496};
497
498/* ========================================================================= */
499/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
500/* ========================================================================= */
501#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
502
503#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
504#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
505
506union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
507 unsigned long v;
508 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
509 unsigned long rsvd_0_23 : 24; /* */
510 unsigned long dest_base : 22; /* RW */
511 unsigned long rsvd_46_63: 18; /* */
512 } s;
513};
514
515/* ========================================================================= */
516/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
517/* ========================================================================= */
518#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
519
520#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
521#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
522
523union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
524 unsigned long v;
525 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
526 unsigned long rsvd_0_23 : 24; /* */
527 unsigned long dest_base : 22; /* RW */
528 unsigned long rsvd_46_63: 18; /* */
529 } s;
530};
531
532/* ========================================================================= */
533/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
534/* ========================================================================= */
535#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
536
537#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
538#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
539#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
540#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
541#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
542#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
543#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
544#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
545
546union uvh_rh_gam_gru_overlay_config_mmr_u {
547 unsigned long v;
548 struct uvh_rh_gam_gru_overlay_config_mmr_s {
549 unsigned long rsvd_0_27: 28; /* */
550 unsigned long base : 18; /* RW */
551 unsigned long rsvd_46_47: 2; /* */
552 unsigned long gr4 : 1; /* RW */
553 unsigned long rsvd_49_51: 3; /* */
554 unsigned long n_gru : 4; /* RW */
555 unsigned long rsvd_56_62: 7; /* */
556 unsigned long enable : 1; /* RW */
557 } s;
558};
559
560/* ========================================================================= */
561/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
562/* ========================================================================= */
563#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
564
565#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
566#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
567#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
568#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
569#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
570#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
571
572union uvh_rh_gam_mmr_overlay_config_mmr_u {
573 unsigned long v;
574 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
575 unsigned long rsvd_0_25: 26; /* */
576 unsigned long base : 20; /* RW */
577 unsigned long dual_hub : 1; /* RW */
578 unsigned long rsvd_47_62: 16; /* */
579 unsigned long enable : 1; /* RW */
580 } s;
581};
582
583/* ========================================================================= */
584/* UVH_RTC */
585/* ========================================================================= */
586#define UVH_RTC 0x340000UL
587
588#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
589#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
590
591union uvh_rtc_u {
592 unsigned long v;
593 struct uvh_rtc_s {
594 unsigned long real_time_clock : 56; /* RW */
595 unsigned long rsvd_56_63 : 8; /* */
596 } s;
597};
598
599/* ========================================================================= */
600/* UVH_RTC1_INT_CONFIG */
601/* ========================================================================= */
602#define UVH_RTC1_INT_CONFIG 0x615c0UL
603
604#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
605#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
606#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
607#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
608#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
609#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
610#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
611#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
612#define UVH_RTC1_INT_CONFIG_P_SHFT 13
613#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
614#define UVH_RTC1_INT_CONFIG_T_SHFT 15
615#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
616#define UVH_RTC1_INT_CONFIG_M_SHFT 16
617#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
618#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
619#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
620
621union uvh_rtc1_int_config_u {
622 unsigned long v;
623 struct uvh_rtc1_int_config_s {
624 unsigned long vector_ : 8; /* RW */
625 unsigned long dm : 3; /* RW */
626 unsigned long destmode : 1; /* RW */
627 unsigned long status : 1; /* RO */
628 unsigned long p : 1; /* RO */
629 unsigned long rsvd_14 : 1; /* */
630 unsigned long t : 1; /* RO */
631 unsigned long m : 1; /* RW */
632 unsigned long rsvd_17_31: 15; /* */
633 unsigned long apic_id : 32; /* RW */
634 } s;
635};
636
637/* ========================================================================= */
638/* UVH_RTC2_INT_CONFIG */
639/* ========================================================================= */
640#define UVH_RTC2_INT_CONFIG 0x61600UL
641
642#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
643#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
644#define UVH_RTC2_INT_CONFIG_DM_SHFT 8
645#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
646#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
647#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
648#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
649#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
650#define UVH_RTC2_INT_CONFIG_P_SHFT 13
651#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
652#define UVH_RTC2_INT_CONFIG_T_SHFT 15
653#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
654#define UVH_RTC2_INT_CONFIG_M_SHFT 16
655#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
656#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
657#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
658
659union uvh_rtc2_int_config_u {
660 unsigned long v;
661 struct uvh_rtc2_int_config_s {
662 unsigned long vector_ : 8; /* RW */
663 unsigned long dm : 3; /* RW */
664 unsigned long destmode : 1; /* RW */
665 unsigned long status : 1; /* RO */
666 unsigned long p : 1; /* RO */
667 unsigned long rsvd_14 : 1; /* */
668 unsigned long t : 1; /* RO */
669 unsigned long m : 1; /* RW */
670 unsigned long rsvd_17_31: 15; /* */
671 unsigned long apic_id : 32; /* RW */
672 } s;
673};
674
675/* ========================================================================= */
676/* UVH_RTC3_INT_CONFIG */
677/* ========================================================================= */
678#define UVH_RTC3_INT_CONFIG 0x61640UL
679
680#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
681#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
682#define UVH_RTC3_INT_CONFIG_DM_SHFT 8
683#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
684#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
685#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
686#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
687#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
688#define UVH_RTC3_INT_CONFIG_P_SHFT 13
689#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
690#define UVH_RTC3_INT_CONFIG_T_SHFT 15
691#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
692#define UVH_RTC3_INT_CONFIG_M_SHFT 16
693#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
694#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
695#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
696
697union uvh_rtc3_int_config_u {
698 unsigned long v;
699 struct uvh_rtc3_int_config_s {
700 unsigned long vector_ : 8; /* RW */
701 unsigned long dm : 3; /* RW */
702 unsigned long destmode : 1; /* RW */
703 unsigned long status : 1; /* RO */
704 unsigned long p : 1; /* RO */
705 unsigned long rsvd_14 : 1; /* */
706 unsigned long t : 1; /* RO */
707 unsigned long m : 1; /* RW */
708 unsigned long rsvd_17_31: 15; /* */
709 unsigned long apic_id : 32; /* RW */
710 } s;
711};
712
713/* ========================================================================= */
714/* UVH_RTC_INC_RATIO */
715/* ========================================================================= */
716#define UVH_RTC_INC_RATIO 0x350000UL
717
718#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
719#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
720#define UVH_RTC_INC_RATIO_RATIO_SHFT 20
721#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
722
723union uvh_rtc_inc_ratio_u {
724 unsigned long v;
725 struct uvh_rtc_inc_ratio_s {
726 unsigned long fraction : 20; /* RW */
727 unsigned long ratio : 3; /* RW */
728 unsigned long rsvd_23_63: 41; /* */
729 } s;
730};
731
732/* ========================================================================= */
733/* UVH_SI_ADDR_MAP_CONFIG */
734/* ========================================================================= */
735#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
736
737#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
738#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
739#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
740#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
741
742union uvh_si_addr_map_config_u {
743 unsigned long v;
744 struct uvh_si_addr_map_config_s {
745 unsigned long m_skt : 6; /* RW */
746 unsigned long rsvd_6_7: 2; /* */
747 unsigned long n_skt : 4; /* RW */
748 unsigned long rsvd_12_63: 52; /* */
749 } s;
750};
751
752/* ========================================================================= */
753/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
754/* ========================================================================= */
755#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
756
757#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
758#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
759#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
760#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
761#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
762#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
763
764union uvh_si_alias0_overlay_config_u {
765 unsigned long v;
766 struct uvh_si_alias0_overlay_config_s {
767 unsigned long rsvd_0_23: 24; /* */
768 unsigned long base : 8; /* RW */
769 unsigned long rsvd_32_47: 16; /* */
770 unsigned long m_alias : 5; /* RW */
771 unsigned long rsvd_53_62: 10; /* */
772 unsigned long enable : 1; /* RW */
773 } s;
774};
775
776/* ========================================================================= */
777/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
778/* ========================================================================= */
779#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
780
781#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
782#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
783#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
784#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
785#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
786#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
787
788union uvh_si_alias1_overlay_config_u {
789 unsigned long v;
790 struct uvh_si_alias1_overlay_config_s {
791 unsigned long rsvd_0_23: 24; /* */
792 unsigned long base : 8; /* RW */
793 unsigned long rsvd_32_47: 16; /* */
794 unsigned long m_alias : 5; /* RW */
795 unsigned long rsvd_53_62: 10; /* */
796 unsigned long enable : 1; /* RW */
797 } s;
798};
799
800/* ========================================================================= */
801/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
802/* ========================================================================= */
803#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
804
805#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
806#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
807#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
808#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
809#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
810#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
811
812union uvh_si_alias2_overlay_config_u {
813 unsigned long v;
814 struct uvh_si_alias2_overlay_config_s {
815 unsigned long rsvd_0_23: 24; /* */
816 unsigned long base : 8; /* RW */
817 unsigned long rsvd_32_47: 16; /* */
818 unsigned long m_alias : 5; /* RW */
819 unsigned long rsvd_53_62: 10; /* */
820 unsigned long enable : 1; /* RW */
821 } s;
822};
823
824
825#endif /* _ASM_IA64_UV_UV_MMRS_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV MMR definitions
7 *
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef _ASM_IA64_UV_UV_MMRS_H
12#define _ASM_IA64_UV_UV_MMRS_H
13
14#define UV_MMR_ENABLE (1UL << 63)
15
16/* ========================================================================= */
17/* UVH_BAU_DATA_CONFIG */
18/* ========================================================================= */
19#define UVH_BAU_DATA_CONFIG 0x61680UL
20#define UVH_BAU_DATA_CONFIG_32 0x0438
21
22#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
23#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
24#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
25#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
26#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
27#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
28#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
29#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
30#define UVH_BAU_DATA_CONFIG_P_SHFT 13
31#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
32#define UVH_BAU_DATA_CONFIG_T_SHFT 15
33#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
34#define UVH_BAU_DATA_CONFIG_M_SHFT 16
35#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
36#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
37#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
38
39union uvh_bau_data_config_u {
40 unsigned long v;
41 struct uvh_bau_data_config_s {
42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
45 unsigned long status : 1; /* RO */
46 unsigned long p : 1; /* RO */
47 unsigned long rsvd_14 : 1; /* */
48 unsigned long t : 1; /* RO */
49 unsigned long m : 1; /* RW */
50 unsigned long rsvd_17_31: 15; /* */
51 unsigned long apic_id : 32; /* RW */
52 } s;
53};
54
55/* ========================================================================= */
56/* UVH_EVENT_OCCURRED0 */
57/* ========================================================================= */
58#define UVH_EVENT_OCCURRED0 0x70000UL
59#define UVH_EVENT_OCCURRED0_32 0x005e8
60
61#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
62#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
63#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
64#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
65#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
66#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
67#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
68#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
69#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
70#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
71#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
72#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
73#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
74#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
75#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
76#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
77#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
78#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
79#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
80#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
81#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
82#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
83#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
84#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
85#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
86#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
87#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
88#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
89#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
90#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
91#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
92#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
93#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
94#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
95#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
96#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
97#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
98#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
99#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
100#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
101#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
102#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
103#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
104#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
105#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
106#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
107#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
108#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
109#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
110#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
111#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
112#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
113#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
114#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
115#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
116#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
117#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
118#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
119#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
120#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
121#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
122#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
123#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
124#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
125#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
126#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
127#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
128#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
129#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
130#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
131#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
132#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
133#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
134#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
135#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
136#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
137#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
138#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
139#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
140#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
141#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
142#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
143#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
144#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
145#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
146#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
147#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
148#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
149#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
150#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
151#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
152#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
153#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
154#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
155#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
156#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
157#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
158#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
159#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
160#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
161#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
162#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
163#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
164#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
165#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
166#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
167#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
168#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
169#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
170#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
171#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
172#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
173#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
174#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
175union uvh_event_occurred0_u {
176 unsigned long v;
177 struct uvh_event_occurred0_s {
178 unsigned long lb_hcerr : 1; /* RW, W1C */
179 unsigned long gr0_hcerr : 1; /* RW, W1C */
180 unsigned long gr1_hcerr : 1; /* RW, W1C */
181 unsigned long lh_hcerr : 1; /* RW, W1C */
182 unsigned long rh_hcerr : 1; /* RW, W1C */
183 unsigned long xn_hcerr : 1; /* RW, W1C */
184 unsigned long si_hcerr : 1; /* RW, W1C */
185 unsigned long lb_aoerr0 : 1; /* RW, W1C */
186 unsigned long gr0_aoerr0 : 1; /* RW, W1C */
187 unsigned long gr1_aoerr0 : 1; /* RW, W1C */
188 unsigned long lh_aoerr0 : 1; /* RW, W1C */
189 unsigned long rh_aoerr0 : 1; /* RW, W1C */
190 unsigned long xn_aoerr0 : 1; /* RW, W1C */
191 unsigned long si_aoerr0 : 1; /* RW, W1C */
192 unsigned long lb_aoerr1 : 1; /* RW, W1C */
193 unsigned long gr0_aoerr1 : 1; /* RW, W1C */
194 unsigned long gr1_aoerr1 : 1; /* RW, W1C */
195 unsigned long lh_aoerr1 : 1; /* RW, W1C */
196 unsigned long rh_aoerr1 : 1; /* RW, W1C */
197 unsigned long xn_aoerr1 : 1; /* RW, W1C */
198 unsigned long si_aoerr1 : 1; /* RW, W1C */
199 unsigned long rh_vpi_int : 1; /* RW, W1C */
200 unsigned long system_shutdown_int : 1; /* RW, W1C */
201 unsigned long lb_irq_int_0 : 1; /* RW, W1C */
202 unsigned long lb_irq_int_1 : 1; /* RW, W1C */
203 unsigned long lb_irq_int_2 : 1; /* RW, W1C */
204 unsigned long lb_irq_int_3 : 1; /* RW, W1C */
205 unsigned long lb_irq_int_4 : 1; /* RW, W1C */
206 unsigned long lb_irq_int_5 : 1; /* RW, W1C */
207 unsigned long lb_irq_int_6 : 1; /* RW, W1C */
208 unsigned long lb_irq_int_7 : 1; /* RW, W1C */
209 unsigned long lb_irq_int_8 : 1; /* RW, W1C */
210 unsigned long lb_irq_int_9 : 1; /* RW, W1C */
211 unsigned long lb_irq_int_10 : 1; /* RW, W1C */
212 unsigned long lb_irq_int_11 : 1; /* RW, W1C */
213 unsigned long lb_irq_int_12 : 1; /* RW, W1C */
214 unsigned long lb_irq_int_13 : 1; /* RW, W1C */
215 unsigned long lb_irq_int_14 : 1; /* RW, W1C */
216 unsigned long lb_irq_int_15 : 1; /* RW, W1C */
217 unsigned long l1_nmi_int : 1; /* RW, W1C */
218 unsigned long stop_clock : 1; /* RW, W1C */
219 unsigned long asic_to_l1 : 1; /* RW, W1C */
220 unsigned long l1_to_asic : 1; /* RW, W1C */
221 unsigned long ltc_int : 1; /* RW, W1C */
222 unsigned long la_seq_trigger : 1; /* RW, W1C */
223 unsigned long ipi_int : 1; /* RW, W1C */
224 unsigned long extio_int0 : 1; /* RW, W1C */
225 unsigned long extio_int1 : 1; /* RW, W1C */
226 unsigned long extio_int2 : 1; /* RW, W1C */
227 unsigned long extio_int3 : 1; /* RW, W1C */
228 unsigned long profile_int : 1; /* RW, W1C */
229 unsigned long rtc0 : 1; /* RW, W1C */
230 unsigned long rtc1 : 1; /* RW, W1C */
231 unsigned long rtc2 : 1; /* RW, W1C */
232 unsigned long rtc3 : 1; /* RW, W1C */
233 unsigned long bau_data : 1; /* RW, W1C */
234 unsigned long power_management_req : 1; /* RW, W1C */
235 unsigned long rsvd_57_63 : 7; /* */
236 } s;
237};
238
239/* ========================================================================= */
240/* UVH_EVENT_OCCURRED0_ALIAS */
241/* ========================================================================= */
242#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
243#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
244
245/* ========================================================================= */
246/* UVH_GR0_TLB_INT0_CONFIG */
247/* ========================================================================= */
248#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
249
250#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
251#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
252#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
253#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
254#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
255#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
256#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
257#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
258#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
259#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
260#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
261#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
262#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
263#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
264#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
265#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
266
267union uvh_gr0_tlb_int0_config_u {
268 unsigned long v;
269 struct uvh_gr0_tlb_int0_config_s {
270 unsigned long vector_ : 8; /* RW */
271 unsigned long dm : 3; /* RW */
272 unsigned long destmode : 1; /* RW */
273 unsigned long status : 1; /* RO */
274 unsigned long p : 1; /* RO */
275 unsigned long rsvd_14 : 1; /* */
276 unsigned long t : 1; /* RO */
277 unsigned long m : 1; /* RW */
278 unsigned long rsvd_17_31: 15; /* */
279 unsigned long apic_id : 32; /* RW */
280 } s;
281};
282
283/* ========================================================================= */
284/* UVH_GR0_TLB_INT1_CONFIG */
285/* ========================================================================= */
286#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
287
288#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
289#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
290#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
291#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
292#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
293#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
294#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
295#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
296#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
297#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
298#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
299#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
300#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
301#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
302#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
303#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
304
305union uvh_gr0_tlb_int1_config_u {
306 unsigned long v;
307 struct uvh_gr0_tlb_int1_config_s {
308 unsigned long vector_ : 8; /* RW */
309 unsigned long dm : 3; /* RW */
310 unsigned long destmode : 1; /* RW */
311 unsigned long status : 1; /* RO */
312 unsigned long p : 1; /* RO */
313 unsigned long rsvd_14 : 1; /* */
314 unsigned long t : 1; /* RO */
315 unsigned long m : 1; /* RW */
316 unsigned long rsvd_17_31: 15; /* */
317 unsigned long apic_id : 32; /* RW */
318 } s;
319};
320
321/* ========================================================================= */
322/* UVH_GR1_TLB_INT0_CONFIG */
323/* ========================================================================= */
324#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
325
326#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
327#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
328#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
329#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
330#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
331#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
332#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
333#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
334#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
335#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
336#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
337#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
338#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
339#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
340#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
341#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
342
343union uvh_gr1_tlb_int0_config_u {
344 unsigned long v;
345 struct uvh_gr1_tlb_int0_config_s {
346 unsigned long vector_ : 8; /* RW */
347 unsigned long dm : 3; /* RW */
348 unsigned long destmode : 1; /* RW */
349 unsigned long status : 1; /* RO */
350 unsigned long p : 1; /* RO */
351 unsigned long rsvd_14 : 1; /* */
352 unsigned long t : 1; /* RO */
353 unsigned long m : 1; /* RW */
354 unsigned long rsvd_17_31: 15; /* */
355 unsigned long apic_id : 32; /* RW */
356 } s;
357};
358
359/* ========================================================================= */
360/* UVH_GR1_TLB_INT1_CONFIG */
361/* ========================================================================= */
362#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
363
364#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
365#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
366#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
367#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
368#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
369#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
370#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
371#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
372#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
373#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
374#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
375#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
376#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
377#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
378#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
379#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
380
381union uvh_gr1_tlb_int1_config_u {
382 unsigned long v;
383 struct uvh_gr1_tlb_int1_config_s {
384 unsigned long vector_ : 8; /* RW */
385 unsigned long dm : 3; /* RW */
386 unsigned long destmode : 1; /* RW */
387 unsigned long status : 1; /* RO */
388 unsigned long p : 1; /* RO */
389 unsigned long rsvd_14 : 1; /* */
390 unsigned long t : 1; /* RO */
391 unsigned long m : 1; /* RW */
392 unsigned long rsvd_17_31: 15; /* */
393 unsigned long apic_id : 32; /* RW */
394 } s;
395};
396
397/* ========================================================================= */
398/* UVH_INT_CMPB */
399/* ========================================================================= */
400#define UVH_INT_CMPB 0x22080UL
401
402#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
403#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
404
405union uvh_int_cmpb_u {
406 unsigned long v;
407 struct uvh_int_cmpb_s {
408 unsigned long real_time_cmpb : 56; /* RW */
409 unsigned long rsvd_56_63 : 8; /* */
410 } s;
411};
412
413/* ========================================================================= */
414/* UVH_INT_CMPC */
415/* ========================================================================= */
416#define UVH_INT_CMPC 0x22100UL
417
418#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
419#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
420
421union uvh_int_cmpc_u {
422 unsigned long v;
423 struct uvh_int_cmpc_s {
424 unsigned long real_time_cmpc : 56; /* RW */
425 unsigned long rsvd_56_63 : 8; /* */
426 } s;
427};
428
429/* ========================================================================= */
430/* UVH_INT_CMPD */
431/* ========================================================================= */
432#define UVH_INT_CMPD 0x22180UL
433
434#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
435#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
436
437union uvh_int_cmpd_u {
438 unsigned long v;
439 struct uvh_int_cmpd_s {
440 unsigned long real_time_cmpd : 56; /* RW */
441 unsigned long rsvd_56_63 : 8; /* */
442 } s;
443};
444
445/* ========================================================================= */
446/* UVH_NODE_ID */
447/* ========================================================================= */
448#define UVH_NODE_ID 0x0UL
449
450#define UVH_NODE_ID_FORCE1_SHFT 0
451#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
452#define UVH_NODE_ID_MANUFACTURER_SHFT 1
453#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
454#define UVH_NODE_ID_PART_NUMBER_SHFT 12
455#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
456#define UVH_NODE_ID_REVISION_SHFT 28
457#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
458#define UVH_NODE_ID_NODE_ID_SHFT 32
459#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
460#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
461#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
462#define UVH_NODE_ID_NI_PORT_SHFT 56
463#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
464
465union uvh_node_id_u {
466 unsigned long v;
467 struct uvh_node_id_s {
468 unsigned long force1 : 1; /* RO */
469 unsigned long manufacturer : 11; /* RO */
470 unsigned long part_number : 16; /* RO */
471 unsigned long revision : 4; /* RO */
472 unsigned long node_id : 15; /* RW */
473 unsigned long rsvd_47 : 1; /* */
474 unsigned long nodes_per_bit : 7; /* RW */
475 unsigned long rsvd_55 : 1; /* */
476 unsigned long ni_port : 4; /* RO */
477 unsigned long rsvd_60_63 : 4; /* */
478 } s;
479};
480
481/* ========================================================================= */
482/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
483/* ========================================================================= */
484#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
485
486#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
487#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
488
489union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
490 unsigned long v;
491 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
492 unsigned long rsvd_0_23 : 24; /* */
493 unsigned long dest_base : 22; /* RW */
494 unsigned long rsvd_46_63: 18; /* */
495 } s;
496};
497
498/* ========================================================================= */
499/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
500/* ========================================================================= */
501#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
502
503#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
504#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
505
506union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
507 unsigned long v;
508 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
509 unsigned long rsvd_0_23 : 24; /* */
510 unsigned long dest_base : 22; /* RW */
511 unsigned long rsvd_46_63: 18; /* */
512 } s;
513};
514
515/* ========================================================================= */
516/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
517/* ========================================================================= */
518#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
519
520#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
521#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
522
523union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
524 unsigned long v;
525 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
526 unsigned long rsvd_0_23 : 24; /* */
527 unsigned long dest_base : 22; /* RW */
528 unsigned long rsvd_46_63: 18; /* */
529 } s;
530};
531
532/* ========================================================================= */
533/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
534/* ========================================================================= */
535#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
536
537#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
538#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
539#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
540#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
541#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
542#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
543#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
544#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
545
546union uvh_rh_gam_gru_overlay_config_mmr_u {
547 unsigned long v;
548 struct uvh_rh_gam_gru_overlay_config_mmr_s {
549 unsigned long rsvd_0_27: 28; /* */
550 unsigned long base : 18; /* RW */
551 unsigned long rsvd_46_47: 2; /* */
552 unsigned long gr4 : 1; /* RW */
553 unsigned long rsvd_49_51: 3; /* */
554 unsigned long n_gru : 4; /* RW */
555 unsigned long rsvd_56_62: 7; /* */
556 unsigned long enable : 1; /* RW */
557 } s;
558};
559
560/* ========================================================================= */
561/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
562/* ========================================================================= */
563#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
564
565#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
566#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
567#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
568#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
569#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
570#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
571
572union uvh_rh_gam_mmr_overlay_config_mmr_u {
573 unsigned long v;
574 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
575 unsigned long rsvd_0_25: 26; /* */
576 unsigned long base : 20; /* RW */
577 unsigned long dual_hub : 1; /* RW */
578 unsigned long rsvd_47_62: 16; /* */
579 unsigned long enable : 1; /* RW */
580 } s;
581};
582
583/* ========================================================================= */
584/* UVH_RTC */
585/* ========================================================================= */
586#define UVH_RTC 0x340000UL
587
588#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
589#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
590
591union uvh_rtc_u {
592 unsigned long v;
593 struct uvh_rtc_s {
594 unsigned long real_time_clock : 56; /* RW */
595 unsigned long rsvd_56_63 : 8; /* */
596 } s;
597};
598
599/* ========================================================================= */
600/* UVH_RTC1_INT_CONFIG */
601/* ========================================================================= */
602#define UVH_RTC1_INT_CONFIG 0x615c0UL
603
604#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
605#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
606#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
607#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
608#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
609#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
610#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
611#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
612#define UVH_RTC1_INT_CONFIG_P_SHFT 13
613#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
614#define UVH_RTC1_INT_CONFIG_T_SHFT 15
615#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
616#define UVH_RTC1_INT_CONFIG_M_SHFT 16
617#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
618#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
619#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
620
621union uvh_rtc1_int_config_u {
622 unsigned long v;
623 struct uvh_rtc1_int_config_s {
624 unsigned long vector_ : 8; /* RW */
625 unsigned long dm : 3; /* RW */
626 unsigned long destmode : 1; /* RW */
627 unsigned long status : 1; /* RO */
628 unsigned long p : 1; /* RO */
629 unsigned long rsvd_14 : 1; /* */
630 unsigned long t : 1; /* RO */
631 unsigned long m : 1; /* RW */
632 unsigned long rsvd_17_31: 15; /* */
633 unsigned long apic_id : 32; /* RW */
634 } s;
635};
636
637/* ========================================================================= */
638/* UVH_RTC2_INT_CONFIG */
639/* ========================================================================= */
640#define UVH_RTC2_INT_CONFIG 0x61600UL
641
642#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
643#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
644#define UVH_RTC2_INT_CONFIG_DM_SHFT 8
645#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
646#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
647#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
648#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
649#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
650#define UVH_RTC2_INT_CONFIG_P_SHFT 13
651#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
652#define UVH_RTC2_INT_CONFIG_T_SHFT 15
653#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
654#define UVH_RTC2_INT_CONFIG_M_SHFT 16
655#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
656#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
657#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
658
659union uvh_rtc2_int_config_u {
660 unsigned long v;
661 struct uvh_rtc2_int_config_s {
662 unsigned long vector_ : 8; /* RW */
663 unsigned long dm : 3; /* RW */
664 unsigned long destmode : 1; /* RW */
665 unsigned long status : 1; /* RO */
666 unsigned long p : 1; /* RO */
667 unsigned long rsvd_14 : 1; /* */
668 unsigned long t : 1; /* RO */
669 unsigned long m : 1; /* RW */
670 unsigned long rsvd_17_31: 15; /* */
671 unsigned long apic_id : 32; /* RW */
672 } s;
673};
674
675/* ========================================================================= */
676/* UVH_RTC3_INT_CONFIG */
677/* ========================================================================= */
678#define UVH_RTC3_INT_CONFIG 0x61640UL
679
680#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
681#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
682#define UVH_RTC3_INT_CONFIG_DM_SHFT 8
683#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
684#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
685#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
686#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
687#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
688#define UVH_RTC3_INT_CONFIG_P_SHFT 13
689#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
690#define UVH_RTC3_INT_CONFIG_T_SHFT 15
691#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
692#define UVH_RTC3_INT_CONFIG_M_SHFT 16
693#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
694#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
695#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
696
697union uvh_rtc3_int_config_u {
698 unsigned long v;
699 struct uvh_rtc3_int_config_s {
700 unsigned long vector_ : 8; /* RW */
701 unsigned long dm : 3; /* RW */
702 unsigned long destmode : 1; /* RW */
703 unsigned long status : 1; /* RO */
704 unsigned long p : 1; /* RO */
705 unsigned long rsvd_14 : 1; /* */
706 unsigned long t : 1; /* RO */
707 unsigned long m : 1; /* RW */
708 unsigned long rsvd_17_31: 15; /* */
709 unsigned long apic_id : 32; /* RW */
710 } s;
711};
712
713/* ========================================================================= */
714/* UVH_RTC_INC_RATIO */
715/* ========================================================================= */
716#define UVH_RTC_INC_RATIO 0x350000UL
717
718#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
719#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
720#define UVH_RTC_INC_RATIO_RATIO_SHFT 20
721#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
722
723union uvh_rtc_inc_ratio_u {
724 unsigned long v;
725 struct uvh_rtc_inc_ratio_s {
726 unsigned long fraction : 20; /* RW */
727 unsigned long ratio : 3; /* RW */
728 unsigned long rsvd_23_63: 41; /* */
729 } s;
730};
731
732/* ========================================================================= */
733/* UVH_SI_ADDR_MAP_CONFIG */
734/* ========================================================================= */
735#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
736
737#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
738#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
739#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
740#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
741
742union uvh_si_addr_map_config_u {
743 unsigned long v;
744 struct uvh_si_addr_map_config_s {
745 unsigned long m_skt : 6; /* RW */
746 unsigned long rsvd_6_7: 2; /* */
747 unsigned long n_skt : 4; /* RW */
748 unsigned long rsvd_12_63: 52; /* */
749 } s;
750};
751
752/* ========================================================================= */
753/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
754/* ========================================================================= */
755#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
756
757#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
758#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
759#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
760#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
761#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
762#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
763
764union uvh_si_alias0_overlay_config_u {
765 unsigned long v;
766 struct uvh_si_alias0_overlay_config_s {
767 unsigned long rsvd_0_23: 24; /* */
768 unsigned long base : 8; /* RW */
769 unsigned long rsvd_32_47: 16; /* */
770 unsigned long m_alias : 5; /* RW */
771 unsigned long rsvd_53_62: 10; /* */
772 unsigned long enable : 1; /* RW */
773 } s;
774};
775
776/* ========================================================================= */
777/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
778/* ========================================================================= */
779#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
780
781#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
782#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
783#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
784#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
785#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
786#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
787
788union uvh_si_alias1_overlay_config_u {
789 unsigned long v;
790 struct uvh_si_alias1_overlay_config_s {
791 unsigned long rsvd_0_23: 24; /* */
792 unsigned long base : 8; /* RW */
793 unsigned long rsvd_32_47: 16; /* */
794 unsigned long m_alias : 5; /* RW */
795 unsigned long rsvd_53_62: 10; /* */
796 unsigned long enable : 1; /* RW */
797 } s;
798};
799
800/* ========================================================================= */
801/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
802/* ========================================================================= */
803#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
804
805#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
806#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
807#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
808#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
809#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
810#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
811
812union uvh_si_alias2_overlay_config_u {
813 unsigned long v;
814 struct uvh_si_alias2_overlay_config_s {
815 unsigned long rsvd_0_23: 24; /* */
816 unsigned long base : 8; /* RW */
817 unsigned long rsvd_32_47: 16; /* */
818 unsigned long m_alias : 5; /* RW */
819 unsigned long rsvd_53_62: 10; /* */
820 unsigned long enable : 1; /* RW */
821 } s;
822};
823
824
825#endif /* _ASM_IA64_UV_UV_MMRS_H */