1/*
   2 * linux/drivers/video/omap2/dss/dsi.c
   3 *
   4 * Copyright (C) 2009 Nokia Corporation
   5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify it
   8 * under the terms of the GNU General Public License version 2 as published by
   9 * the Free Software Foundation.
  10 *
  11 * This program is distributed in the hope that it will be useful, but WITHOUT
  12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 * more details.
  15 *
  16 * You should have received a copy of the GNU General Public License along with
  17 * this program.  If not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#define DSS_SUBSYS_NAME "DSI"
  21
  22#include <linux/kernel.h>
 
 
  23#include <linux/io.h>
  24#include <linux/clk.h>
  25#include <linux/device.h>
  26#include <linux/err.h>
  27#include <linux/interrupt.h>
 
  28#include <linux/delay.h>
 
  29#include <linux/mutex.h>
  30#include <linux/module.h>
  31#include <linux/semaphore.h>
  32#include <linux/seq_file.h>
  33#include <linux/platform_device.h>
  34#include <linux/regulator/consumer.h>
  35#include <linux/wait.h>
  36#include <linux/workqueue.h>
  37#include <linux/sched.h>
  38#include <linux/slab.h>
  39#include <linux/debugfs.h>
  40#include <linux/pm_runtime.h>
  41#include <linux/of.h>
 
  42#include <linux/of_platform.h>
  43#include <linux/component.h>
 
  44
 
 
 
  45#include <video/mipi_display.h>
  46
  47#include "omapdss.h"
  48#include "dss.h"
  49#include "dss_features.h"
  50
  51#define DSI_CATCH_MISSING_TE
  52
  53struct dsi_reg { u16 module; u16 idx; };
  54
  55#define DSI_REG(mod, idx)		((const struct dsi_reg) { mod, idx })
 
  56
  57/* DSI Protocol Engine */
 
  58
  59#define DSI_PROTO			0
  60#define DSI_PROTO_SZ			0x200
  61
  62#define DSI_REVISION			DSI_REG(DSI_PROTO, 0x0000)
  63#define DSI_SYSCONFIG			DSI_REG(DSI_PROTO, 0x0010)
  64#define DSI_SYSSTATUS			DSI_REG(DSI_PROTO, 0x0014)
  65#define DSI_IRQSTATUS			DSI_REG(DSI_PROTO, 0x0018)
  66#define DSI_IRQENABLE			DSI_REG(DSI_PROTO, 0x001C)
  67#define DSI_CTRL			DSI_REG(DSI_PROTO, 0x0040)
  68#define DSI_GNQ				DSI_REG(DSI_PROTO, 0x0044)
  69#define DSI_COMPLEXIO_CFG1		DSI_REG(DSI_PROTO, 0x0048)
  70#define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(DSI_PROTO, 0x004C)
  71#define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(DSI_PROTO, 0x0050)
  72#define DSI_CLK_CTRL			DSI_REG(DSI_PROTO, 0x0054)
  73#define DSI_TIMING1			DSI_REG(DSI_PROTO, 0x0058)
  74#define DSI_TIMING2			DSI_REG(DSI_PROTO, 0x005C)
  75#define DSI_VM_TIMING1			DSI_REG(DSI_PROTO, 0x0060)
  76#define DSI_VM_TIMING2			DSI_REG(DSI_PROTO, 0x0064)
  77#define DSI_VM_TIMING3			DSI_REG(DSI_PROTO, 0x0068)
  78#define DSI_CLK_TIMING			DSI_REG(DSI_PROTO, 0x006C)
  79#define DSI_TX_FIFO_VC_SIZE		DSI_REG(DSI_PROTO, 0x0070)
  80#define DSI_RX_FIFO_VC_SIZE		DSI_REG(DSI_PROTO, 0x0074)
  81#define DSI_COMPLEXIO_CFG2		DSI_REG(DSI_PROTO, 0x0078)
  82#define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(DSI_PROTO, 0x007C)
  83#define DSI_VM_TIMING4			DSI_REG(DSI_PROTO, 0x0080)
  84#define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(DSI_PROTO, 0x0084)
  85#define DSI_VM_TIMING5			DSI_REG(DSI_PROTO, 0x0088)
  86#define DSI_VM_TIMING6			DSI_REG(DSI_PROTO, 0x008C)
  87#define DSI_VM_TIMING7			DSI_REG(DSI_PROTO, 0x0090)
  88#define DSI_STOPCLK_TIMING		DSI_REG(DSI_PROTO, 0x0094)
  89#define DSI_VC_CTRL(n)			DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
  90#define DSI_VC_TE(n)			DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
  91#define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
  92#define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
  93#define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
  94#define DSI_VC_IRQSTATUS(n)		DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
  95#define DSI_VC_IRQENABLE(n)		DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
  96
  97/* DSIPHY_SCP */
  98
  99#define DSI_PHY				1
 100#define DSI_PHY_OFFSET			0x200
 101#define DSI_PHY_SZ			0x40
 102
 103#define DSI_DSIPHY_CFG0			DSI_REG(DSI_PHY, 0x0000)
 104#define DSI_DSIPHY_CFG1			DSI_REG(DSI_PHY, 0x0004)
 105#define DSI_DSIPHY_CFG2			DSI_REG(DSI_PHY, 0x0008)
 106#define DSI_DSIPHY_CFG5			DSI_REG(DSI_PHY, 0x0014)
 107#define DSI_DSIPHY_CFG10		DSI_REG(DSI_PHY, 0x0028)
 108
 109/* DSI_PLL_CTRL_SCP */
 110
 111#define DSI_PLL				2
 112#define DSI_PLL_OFFSET			0x300
 113#define DSI_PLL_SZ			0x20
 114
 115#define DSI_PLL_CONTROL			DSI_REG(DSI_PLL, 0x0000)
 116#define DSI_PLL_STATUS			DSI_REG(DSI_PLL, 0x0004)
 117#define DSI_PLL_GO			DSI_REG(DSI_PLL, 0x0008)
 118#define DSI_PLL_CONFIGURATION1		DSI_REG(DSI_PLL, 0x000C)
 119#define DSI_PLL_CONFIGURATION2		DSI_REG(DSI_PLL, 0x0010)
 120
 121#define REG_GET(dsidev, idx, start, end) \
 122	FLD_GET(dsi_read_reg(dsidev, idx), start, end)
 123
 124#define REG_FLD_MOD(dsidev, idx, val, start, end) \
 125	dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
 126
 127/* Global interrupts */
 128#define DSI_IRQ_VC0		(1 << 0)
 129#define DSI_IRQ_VC1		(1 << 1)
 130#define DSI_IRQ_VC2		(1 << 2)
 131#define DSI_IRQ_VC3		(1 << 3)
 132#define DSI_IRQ_WAKEUP		(1 << 4)
 133#define DSI_IRQ_RESYNC		(1 << 5)
 134#define DSI_IRQ_PLL_LOCK	(1 << 7)
 135#define DSI_IRQ_PLL_UNLOCK	(1 << 8)
 136#define DSI_IRQ_PLL_RECALL	(1 << 9)
 137#define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)
 138#define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)
 139#define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)
 140#define DSI_IRQ_TE_TRIGGER	(1 << 16)
 141#define DSI_IRQ_ACK_TRIGGER	(1 << 17)
 142#define DSI_IRQ_SYNC_LOST	(1 << 18)
 143#define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)
 144#define DSI_IRQ_TA_TIMEOUT	(1 << 20)
 145#define DSI_IRQ_ERROR_MASK \
 146	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
 147	DSI_IRQ_TA_TIMEOUT)
 148#define DSI_IRQ_CHANNEL_MASK	0xf
 149
 150/* Virtual channel interrupts */
 151#define DSI_VC_IRQ_CS		(1 << 0)
 152#define DSI_VC_IRQ_ECC_CORR	(1 << 1)
 153#define DSI_VC_IRQ_PACKET_SENT	(1 << 2)
 154#define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)
 155#define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)
 156#define DSI_VC_IRQ_BTA		(1 << 5)
 157#define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)
 158#define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)
 159#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
 160#define DSI_VC_IRQ_ERROR_MASK \
 161	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
 162	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
 163	DSI_VC_IRQ_FIFO_TX_UDF)
 164
 165/* ComplexIO interrupts */
 166#define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)
 167#define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)
 168#define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)
 169#define DSI_CIO_IRQ_ERRSYNCESC4		(1 << 3)
 170#define DSI_CIO_IRQ_ERRSYNCESC5		(1 << 4)
 171#define DSI_CIO_IRQ_ERRESC1		(1 << 5)
 172#define DSI_CIO_IRQ_ERRESC2		(1 << 6)
 173#define DSI_CIO_IRQ_ERRESC3		(1 << 7)
 174#define DSI_CIO_IRQ_ERRESC4		(1 << 8)
 175#define DSI_CIO_IRQ_ERRESC5		(1 << 9)
 176#define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)
 177#define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)
 178#define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)
 179#define DSI_CIO_IRQ_ERRCONTROL4		(1 << 13)
 180#define DSI_CIO_IRQ_ERRCONTROL5		(1 << 14)
 181#define DSI_CIO_IRQ_STATEULPS1		(1 << 15)
 182#define DSI_CIO_IRQ_STATEULPS2		(1 << 16)
 183#define DSI_CIO_IRQ_STATEULPS3		(1 << 17)
 184#define DSI_CIO_IRQ_STATEULPS4		(1 << 18)
 185#define DSI_CIO_IRQ_STATEULPS5		(1 << 19)
 186#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)
 187#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)
 188#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)
 189#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)
 190#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)
 191#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)
 192#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4	(1 << 26)
 193#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4	(1 << 27)
 194#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5	(1 << 28)
 195#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5	(1 << 29)
 196#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)
 197#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)
 198#define DSI_CIO_IRQ_ERROR_MASK \
 199	(DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
 200	 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
 201	 DSI_CIO_IRQ_ERRSYNCESC5 | \
 202	 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
 203	 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
 204	 DSI_CIO_IRQ_ERRESC5 | \
 205	 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
 206	 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
 207	 DSI_CIO_IRQ_ERRCONTROL5 | \
 208	 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
 209	 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
 210	 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
 211	 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
 212	 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
 213
 214typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
 215
 216static int dsi_display_init_dispc(struct platform_device *dsidev,
 217	enum omap_channel channel);
 218static void dsi_display_uninit_dispc(struct platform_device *dsidev,
 219	enum omap_channel channel);
 220
 221static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
 222
 223/* DSI PLL HSDIV indices */
 224#define HSDIV_DISPC	0
 225#define HSDIV_DSI	1
 226
 227#define DSI_MAX_NR_ISRS                2
 228#define DSI_MAX_NR_LANES	5
 229
 230enum dsi_lane_function {
 231	DSI_LANE_UNUSED	= 0,
 232	DSI_LANE_CLK,
 233	DSI_LANE_DATA1,
 234	DSI_LANE_DATA2,
 235	DSI_LANE_DATA3,
 236	DSI_LANE_DATA4,
 237};
 238
 239struct dsi_lane_config {
 240	enum dsi_lane_function function;
 241	u8 polarity;
 242};
 243
 244struct dsi_isr_data {
 245	omap_dsi_isr_t	isr;
 246	void		*arg;
 247	u32		mask;
 248};
 249
 250enum fifo_size {
 251	DSI_FIFO_SIZE_0		= 0,
 252	DSI_FIFO_SIZE_32	= 1,
 253	DSI_FIFO_SIZE_64	= 2,
 254	DSI_FIFO_SIZE_96	= 3,
 255	DSI_FIFO_SIZE_128	= 4,
 256};
 257
 258enum dsi_vc_source {
 259	DSI_VC_SOURCE_L4 = 0,
 260	DSI_VC_SOURCE_VP,
 261};
 262
 263struct dsi_irq_stats {
 264	unsigned long last_reset;
 265	unsigned irq_count;
 266	unsigned dsi_irqs[32];
 267	unsigned vc_irqs[4][32];
 268	unsigned cio_irqs[32];
 269};
 270
 271struct dsi_isr_tables {
 272	struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
 273	struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
 274	struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
 275};
 276
 277struct dsi_clk_calc_ctx {
 278	struct platform_device *dsidev;
 279	struct dss_pll *pll;
 280
 281	/* inputs */
 282
 283	const struct omap_dss_dsi_config *config;
 284
 285	unsigned long req_pck_min, req_pck_nom, req_pck_max;
 286
 287	/* outputs */
 288
 289	struct dss_pll_clock_info dsi_cinfo;
 290	struct dispc_clock_info dispc_cinfo;
 291
 292	struct videomode vm;
 293	struct omap_dss_dsi_videomode_timings dsi_vm;
 294};
 295
 296struct dsi_lp_clock_info {
 297	unsigned long lp_clk;
 298	u16 lp_clk_div;
 299};
 300
 301struct dsi_data {
 302	struct platform_device *pdev;
 303	void __iomem *proto_base;
 304	void __iomem *phy_base;
 305	void __iomem *pll_base;
 306
 307	int module_id;
 308
 309	int irq;
 310
 311	bool is_enabled;
 312
 313	struct clk *dss_clk;
 314
 315	struct dispc_clock_info user_dispc_cinfo;
 316	struct dss_pll_clock_info user_dsi_cinfo;
 317
 318	struct dsi_lp_clock_info user_lp_cinfo;
 319	struct dsi_lp_clock_info current_lp_cinfo;
 320
 321	struct dss_pll pll;
 322
 323	bool vdds_dsi_enabled;
 324	struct regulator *vdds_dsi_reg;
 325
 326	struct {
 327		enum dsi_vc_source source;
 328		struct omap_dss_device *dssdev;
 329		enum fifo_size tx_fifo_size;
 330		enum fifo_size rx_fifo_size;
 331		int vc_id;
 332	} vc[4];
 333
 334	struct mutex lock;
 335	struct semaphore bus_lock;
 336
 337	spinlock_t irq_lock;
 338	struct dsi_isr_tables isr_tables;
 339	/* space for a copy used by the interrupt handler */
 340	struct dsi_isr_tables isr_tables_copy;
 341
 342	int update_channel;
 343#ifdef DSI_PERF_MEASURE
 344	unsigned update_bytes;
 345#endif
 346
 347	bool te_enabled;
 348	bool ulps_enabled;
 349
 350	void (*framedone_callback)(int, void *);
 351	void *framedone_data;
 352
 353	struct delayed_work framedone_timeout_work;
 354
 355#ifdef DSI_CATCH_MISSING_TE
 356	struct timer_list te_timer;
 357#endif
 358
 359	unsigned long cache_req_pck;
 360	unsigned long cache_clk_freq;
 361	struct dss_pll_clock_info cache_cinfo;
 362
 363	u32		errors;
 364	spinlock_t	errors_lock;
 365#ifdef DSI_PERF_MEASURE
 366	ktime_t perf_setup_time;
 367	ktime_t perf_start_time;
 368#endif
 369	int debug_read;
 370	int debug_write;
 371
 372#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 373	spinlock_t irq_stats_lock;
 374	struct dsi_irq_stats irq_stats;
 375#endif
 376
 377	unsigned num_lanes_supported;
 378	unsigned line_buffer_size;
 379
 380	struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
 381	unsigned num_lanes_used;
 382
 383	unsigned scp_clk_refcount;
 384
 385	struct dss_lcd_mgr_config mgr_config;
 386	struct videomode vm;
 387	enum omap_dss_dsi_pixel_format pix_fmt;
 388	enum omap_dss_dsi_mode mode;
 389	struct omap_dss_dsi_videomode_timings vm_timings;
 390
 391	struct omap_dss_device output;
 392};
 393
 394struct dsi_packet_sent_handler_data {
 395	struct platform_device *dsidev;
 396	struct completion *completion;
 397};
 398
 399struct dsi_module_id_data {
 400	u32 address;
 401	int id;
 402};
 403
 404static const struct of_device_id dsi_of_match[];
 405
 406#ifdef DSI_PERF_MEASURE
 407static bool dsi_perf;
 408module_param(dsi_perf, bool, 0644);
 409#endif
 410
 411static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
 412{
 413	return dev_get_drvdata(&dsidev->dev);
 414}
 415
 416static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
 
 
 
 417{
 418	return to_platform_device(dssdev->dev);
 419}
 420
 421static struct platform_device *dsi_get_dsidev_from_id(int module)
 422{
 423	struct omap_dss_device *out;
 424	enum omap_dss_output_id	id;
 425
 426	switch (module) {
 427	case 0:
 428		id = OMAP_DSS_OUTPUT_DSI1;
 429		break;
 430	case 1:
 431		id = OMAP_DSS_OUTPUT_DSI2;
 432		break;
 433	default:
 434		return NULL;
 435	}
 436
 437	out = omap_dss_get_output(id);
 438
 439	return out ? to_platform_device(out->dev) : NULL;
 440}
 441
 442static inline void dsi_write_reg(struct platform_device *dsidev,
 443		const struct dsi_reg idx, u32 val)
 444{
 445	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 446	void __iomem *base;
 447
 448	switch(idx.module) {
 449		case DSI_PROTO: base = dsi->proto_base; break;
 450		case DSI_PHY: base = dsi->phy_base; break;
 451		case DSI_PLL: base = dsi->pll_base; break;
 452		default: return;
 453	}
 454
 455	__raw_writel(val, base + idx.idx);
 456}
 457
 458static inline u32 dsi_read_reg(struct platform_device *dsidev,
 459		const struct dsi_reg idx)
 460{
 461	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 462	void __iomem *base;
 463
 464	switch(idx.module) {
 465		case DSI_PROTO: base = dsi->proto_base; break;
 466		case DSI_PHY: base = dsi->phy_base; break;
 467		case DSI_PLL: base = dsi->pll_base; break;
 468		default: return 0;
 469	}
 470
 471	return __raw_readl(base + idx.idx);
 472}
 473
 474static void dsi_bus_lock(struct omap_dss_device *dssdev)
 475{
 476	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 477	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 478
 479	down(&dsi->bus_lock);
 480}
 481
 482static void dsi_bus_unlock(struct omap_dss_device *dssdev)
 483{
 484	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 485	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 486
 487	up(&dsi->bus_lock);
 488}
 489
 490static bool dsi_bus_is_locked(struct platform_device *dsidev)
 491{
 492	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 493
 494	return dsi->bus_lock.count == 0;
 495}
 496
 497static void dsi_completion_handler(void *data, u32 mask)
 498{
 499	complete((struct completion *)data);
 500}
 501
 502static inline int wait_for_bit_change(struct platform_device *dsidev,
 503		const struct dsi_reg idx, int bitnum, int value)
 
 504{
 505	unsigned long timeout;
 506	ktime_t wait;
 507	int t;
 508
 509	/* first busyloop to see if the bit changes right away */
 510	t = 100;
 511	while (t-- > 0) {
 512		if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 513			return value;
 514	}
 515
 516	/* then loop for 500ms, sleeping for 1ms in between */
 517	timeout = jiffies + msecs_to_jiffies(500);
 518	while (time_before(jiffies, timeout)) {
 519		if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 520			return value;
 521
 522		wait = ns_to_ktime(1000 * 1000);
 523		set_current_state(TASK_UNINTERRUPTIBLE);
 524		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
 525	}
 526
 527	return !value;
 528}
 529
 530u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 531{
 532	switch (fmt) {
 533	case OMAP_DSS_DSI_FMT_RGB888:
 534	case OMAP_DSS_DSI_FMT_RGB666:
 535		return 24;
 536	case OMAP_DSS_DSI_FMT_RGB666_PACKED:
 537		return 18;
 538	case OMAP_DSS_DSI_FMT_RGB565:
 539		return 16;
 540	default:
 541		BUG();
 542		return 0;
 543	}
 544}
 545
 546#ifdef DSI_PERF_MEASURE
 547static void dsi_perf_mark_setup(struct platform_device *dsidev)
 548{
 549	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 550	dsi->perf_setup_time = ktime_get();
 551}
 552
 553static void dsi_perf_mark_start(struct platform_device *dsidev)
 554{
 555	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 556	dsi->perf_start_time = ktime_get();
 557}
 558
 559static void dsi_perf_show(struct platform_device *dsidev, const char *name)
 560{
 561	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 562	ktime_t t, setup_time, trans_time;
 563	u32 total_bytes;
 564	u32 setup_us, trans_us, total_us;
 565
 566	if (!dsi_perf)
 567		return;
 568
 569	t = ktime_get();
 570
 571	setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
 572	setup_us = (u32)ktime_to_us(setup_time);
 573	if (setup_us == 0)
 574		setup_us = 1;
 575
 576	trans_time = ktime_sub(t, dsi->perf_start_time);
 577	trans_us = (u32)ktime_to_us(trans_time);
 578	if (trans_us == 0)
 579		trans_us = 1;
 580
 581	total_us = setup_us + trans_us;
 582
 583	total_bytes = dsi->update_bytes;
 584
 585	printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
 586			"%u bytes, %u kbytes/sec\n",
 587			name,
 588			setup_us,
 589			trans_us,
 590			total_us,
 591			1000*1000 / total_us,
 592			total_bytes,
 593			total_bytes * 1000 / total_us);
 594}
 595#else
 596static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
 597{
 598}
 599
 600static inline void dsi_perf_mark_start(struct platform_device *dsidev)
 601{
 602}
 603
 604static inline void dsi_perf_show(struct platform_device *dsidev,
 605		const char *name)
 606{
 607}
 608#endif
 609
 610static int verbose_irq;
 611
 612static void print_irq_status(u32 status)
 613{
 614	if (status == 0)
 615		return;
 616
 617	if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
 618		return;
 619
 620#define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
 621
 622	pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 623		status,
 624		verbose_irq ? PIS(VC0) : "",
 625		verbose_irq ? PIS(VC1) : "",
 626		verbose_irq ? PIS(VC2) : "",
 627		verbose_irq ? PIS(VC3) : "",
 628		PIS(WAKEUP),
 629		PIS(RESYNC),
 630		PIS(PLL_LOCK),
 631		PIS(PLL_UNLOCK),
 632		PIS(PLL_RECALL),
 633		PIS(COMPLEXIO_ERR),
 634		PIS(HS_TX_TIMEOUT),
 635		PIS(LP_RX_TIMEOUT),
 636		PIS(TE_TRIGGER),
 637		PIS(ACK_TRIGGER),
 638		PIS(SYNC_LOST),
 639		PIS(LDO_POWER_GOOD),
 640		PIS(TA_TIMEOUT));
 641#undef PIS
 642}
 643
 644static void print_irq_status_vc(int channel, u32 status)
 645{
 646	if (status == 0)
 647		return;
 648
 649	if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
 650		return;
 651
 652#define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
 653
 654	pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
 655		channel,
 656		status,
 657		PIS(CS),
 658		PIS(ECC_CORR),
 659		PIS(ECC_NO_CORR),
 660		verbose_irq ? PIS(PACKET_SENT) : "",
 661		PIS(BTA),
 662		PIS(FIFO_TX_OVF),
 663		PIS(FIFO_RX_OVF),
 664		PIS(FIFO_TX_UDF),
 665		PIS(PP_BUSY_CHANGE));
 666#undef PIS
 667}
 668
 669static void print_irq_status_cio(u32 status)
 670{
 671	if (status == 0)
 672		return;
 673
 674#define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
 675
 676	pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 677		status,
 678		PIS(ERRSYNCESC1),
 679		PIS(ERRSYNCESC2),
 680		PIS(ERRSYNCESC3),
 681		PIS(ERRESC1),
 682		PIS(ERRESC2),
 683		PIS(ERRESC3),
 684		PIS(ERRCONTROL1),
 685		PIS(ERRCONTROL2),
 686		PIS(ERRCONTROL3),
 687		PIS(STATEULPS1),
 688		PIS(STATEULPS2),
 689		PIS(STATEULPS3),
 690		PIS(ERRCONTENTIONLP0_1),
 691		PIS(ERRCONTENTIONLP1_1),
 692		PIS(ERRCONTENTIONLP0_2),
 693		PIS(ERRCONTENTIONLP1_2),
 694		PIS(ERRCONTENTIONLP0_3),
 695		PIS(ERRCONTENTIONLP1_3),
 696		PIS(ULPSACTIVENOT_ALL0),
 697		PIS(ULPSACTIVENOT_ALL1));
 698#undef PIS
 699}
 700
 701#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 702static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
 703		u32 *vcstatus, u32 ciostatus)
 704{
 705	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 706	int i;
 707
 708	spin_lock(&dsi->irq_stats_lock);
 709
 710	dsi->irq_stats.irq_count++;
 711	dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
 712
 713	for (i = 0; i < 4; ++i)
 714		dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
 715
 716	dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
 717
 718	spin_unlock(&dsi->irq_stats_lock);
 719}
 720#else
 721#define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
 722#endif
 723
 724static int debug_irq;
 725
 726static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
 727		u32 *vcstatus, u32 ciostatus)
 728{
 729	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 730	int i;
 731
 732	if (irqstatus & DSI_IRQ_ERROR_MASK) {
 733		DSSERR("DSI error, irqstatus %x\n", irqstatus);
 734		print_irq_status(irqstatus);
 735		spin_lock(&dsi->errors_lock);
 736		dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
 737		spin_unlock(&dsi->errors_lock);
 738	} else if (debug_irq) {
 739		print_irq_status(irqstatus);
 740	}
 741
 742	for (i = 0; i < 4; ++i) {
 743		if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
 744			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
 745				       i, vcstatus[i]);
 746			print_irq_status_vc(i, vcstatus[i]);
 747		} else if (debug_irq) {
 748			print_irq_status_vc(i, vcstatus[i]);
 749		}
 750	}
 751
 752	if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
 753		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 754		print_irq_status_cio(ciostatus);
 755	} else if (debug_irq) {
 756		print_irq_status_cio(ciostatus);
 757	}
 758}
 759
 760static void dsi_call_isrs(struct dsi_isr_data *isr_array,
 761		unsigned isr_array_size, u32 irqstatus)
 762{
 763	struct dsi_isr_data *isr_data;
 764	int i;
 765
 766	for (i = 0; i < isr_array_size; i++) {
 767		isr_data = &isr_array[i];
 768		if (isr_data->isr && isr_data->mask & irqstatus)
 769			isr_data->isr(isr_data->arg, irqstatus);
 770	}
 771}
 772
 773static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
 774		u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 775{
 776	int i;
 777
 778	dsi_call_isrs(isr_tables->isr_table,
 779			ARRAY_SIZE(isr_tables->isr_table),
 780			irqstatus);
 781
 782	for (i = 0; i < 4; ++i) {
 783		if (vcstatus[i] == 0)
 784			continue;
 785		dsi_call_isrs(isr_tables->isr_table_vc[i],
 786				ARRAY_SIZE(isr_tables->isr_table_vc[i]),
 787				vcstatus[i]);
 788	}
 789
 790	if (ciostatus != 0)
 791		dsi_call_isrs(isr_tables->isr_table_cio,
 792				ARRAY_SIZE(isr_tables->isr_table_cio),
 793				ciostatus);
 794}
 795
 796static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 797{
 798	struct platform_device *dsidev;
 799	struct dsi_data *dsi;
 800	u32 irqstatus, vcstatus[4], ciostatus;
 801	int i;
 802
 803	dsidev = (struct platform_device *) arg;
 804	dsi = dsi_get_dsidrv_data(dsidev);
 805
 806	if (!dsi->is_enabled)
 807		return IRQ_NONE;
 808
 809	spin_lock(&dsi->irq_lock);
 810
 811	irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
 812
 813	/* IRQ is not for us */
 814	if (!irqstatus) {
 815		spin_unlock(&dsi->irq_lock);
 816		return IRQ_NONE;
 817	}
 818
 819	dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 820	/* flush posted write */
 821	dsi_read_reg(dsidev, DSI_IRQSTATUS);
 822
 823	for (i = 0; i < 4; ++i) {
 824		if ((irqstatus & (1 << i)) == 0) {
 825			vcstatus[i] = 0;
 826			continue;
 827		}
 828
 829		vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 830
 831		dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
 832		/* flush posted write */
 833		dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 834	}
 835
 836	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
 837		ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 838
 839		dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 840		/* flush posted write */
 841		dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 842	} else {
 843		ciostatus = 0;
 844	}
 845
 846#ifdef DSI_CATCH_MISSING_TE
 847	if (irqstatus & DSI_IRQ_TE_TRIGGER)
 848		del_timer(&dsi->te_timer);
 849#endif
 850
 851	/* make a copy and unlock, so that isrs can unregister
 852	 * themselves */
 853	memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
 854		sizeof(dsi->isr_tables));
 855
 856	spin_unlock(&dsi->irq_lock);
 857
 858	dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
 859
 860	dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
 861
 862	dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
 863
 864	return IRQ_HANDLED;
 865}
 866
 867/* dsi->irq_lock has to be locked by the caller */
 868static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
 869		struct dsi_isr_data *isr_array,
 870		unsigned isr_array_size, u32 default_mask,
 871		const struct dsi_reg enable_reg,
 872		const struct dsi_reg status_reg)
 
 873{
 874	struct dsi_isr_data *isr_data;
 875	u32 mask;
 876	u32 old_mask;
 877	int i;
 878
 879	mask = default_mask;
 880
 881	for (i = 0; i < isr_array_size; i++) {
 882		isr_data = &isr_array[i];
 883
 884		if (isr_data->isr == NULL)
 885			continue;
 886
 887		mask |= isr_data->mask;
 888	}
 889
 890	old_mask = dsi_read_reg(dsidev, enable_reg);
 891	/* clear the irqstatus for newly enabled irqs */
 892	dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
 893	dsi_write_reg(dsidev, enable_reg, mask);
 894
 895	/* flush posted writes */
 896	dsi_read_reg(dsidev, enable_reg);
 897	dsi_read_reg(dsidev, status_reg);
 898}
 899
 900/* dsi->irq_lock has to be locked by the caller */
 901static void _omap_dsi_set_irqs(struct platform_device *dsidev)
 902{
 903	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 904	u32 mask = DSI_IRQ_ERROR_MASK;
 905#ifdef DSI_CATCH_MISSING_TE
 906	mask |= DSI_IRQ_TE_TRIGGER;
 907#endif
 908	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
 909			ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
 910			DSI_IRQENABLE, DSI_IRQSTATUS);
 911}
 912
 913/* dsi->irq_lock has to be locked by the caller */
 914static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
 915{
 916	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 917
 918	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
 919			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
 920			DSI_VC_IRQ_ERROR_MASK,
 921			DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 922}
 923
 924/* dsi->irq_lock has to be locked by the caller */
 925static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
 926{
 927	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 928
 929	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
 930			ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
 931			DSI_CIO_IRQ_ERROR_MASK,
 932			DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
 933}
 934
 935static void _dsi_initialize_irq(struct platform_device *dsidev)
 936{
 937	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 938	unsigned long flags;
 939	int vc;
 940
 941	spin_lock_irqsave(&dsi->irq_lock, flags);
 942
 943	memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
 944
 945	_omap_dsi_set_irqs(dsidev);
 946	for (vc = 0; vc < 4; ++vc)
 947		_omap_dsi_set_irqs_vc(dsidev, vc);
 948	_omap_dsi_set_irqs_cio(dsidev);
 949
 950	spin_unlock_irqrestore(&dsi->irq_lock, flags);
 951}
 952
 953static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 954		struct dsi_isr_data *isr_array, unsigned isr_array_size)
 955{
 956	struct dsi_isr_data *isr_data;
 957	int free_idx;
 958	int i;
 959
 960	BUG_ON(isr == NULL);
 961
 962	/* check for duplicate entry and find a free slot */
 963	free_idx = -1;
 964	for (i = 0; i < isr_array_size; i++) {
 965		isr_data = &isr_array[i];
 966
 967		if (isr_data->isr == isr && isr_data->arg == arg &&
 968				isr_data->mask == mask) {
 969			return -EINVAL;
 970		}
 971
 972		if (isr_data->isr == NULL && free_idx == -1)
 973			free_idx = i;
 974	}
 975
 976	if (free_idx == -1)
 977		return -EBUSY;
 978
 979	isr_data = &isr_array[free_idx];
 980	isr_data->isr = isr;
 981	isr_data->arg = arg;
 982	isr_data->mask = mask;
 983
 984	return 0;
 985}
 986
 987static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 988		struct dsi_isr_data *isr_array, unsigned isr_array_size)
 989{
 990	struct dsi_isr_data *isr_data;
 991	int i;
 992
 993	for (i = 0; i < isr_array_size; i++) {
 994		isr_data = &isr_array[i];
 995		if (isr_data->isr != isr || isr_data->arg != arg ||
 996				isr_data->mask != mask)
 997			continue;
 998
 999		isr_data->isr = NULL;
1000		isr_data->arg = NULL;
1001		isr_data->mask = 0;
1002
1003		return 0;
1004	}
1005
1006	return -EINVAL;
1007}
1008
1009static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
1010		void *arg, u32 mask)
1011{
1012	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1013	unsigned long flags;
1014	int r;
1015
1016	spin_lock_irqsave(&dsi->irq_lock, flags);
1017
1018	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1019			ARRAY_SIZE(dsi->isr_tables.isr_table));
1020
1021	if (r == 0)
1022		_omap_dsi_set_irqs(dsidev);
1023
1024	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1025
1026	return r;
1027}
1028
1029static int dsi_unregister_isr(struct platform_device *dsidev,
1030		omap_dsi_isr_t isr, void *arg, u32 mask)
1031{
1032	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1033	unsigned long flags;
1034	int r;
1035
1036	spin_lock_irqsave(&dsi->irq_lock, flags);
1037
1038	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1039			ARRAY_SIZE(dsi->isr_tables.isr_table));
1040
1041	if (r == 0)
1042		_omap_dsi_set_irqs(dsidev);
1043
1044	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1045
1046	return r;
1047}
1048
1049static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1050		omap_dsi_isr_t isr, void *arg, u32 mask)
1051{
1052	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1053	unsigned long flags;
1054	int r;
1055
1056	spin_lock_irqsave(&dsi->irq_lock, flags);
1057
1058	r = _dsi_register_isr(isr, arg, mask,
1059			dsi->isr_tables.isr_table_vc[channel],
1060			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1061
1062	if (r == 0)
1063		_omap_dsi_set_irqs_vc(dsidev, channel);
1064
1065	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1066
1067	return r;
1068}
1069
1070static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1071		omap_dsi_isr_t isr, void *arg, u32 mask)
1072{
1073	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1074	unsigned long flags;
1075	int r;
1076
1077	spin_lock_irqsave(&dsi->irq_lock, flags);
1078
1079	r = _dsi_unregister_isr(isr, arg, mask,
1080			dsi->isr_tables.isr_table_vc[channel],
1081			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1082
1083	if (r == 0)
1084		_omap_dsi_set_irqs_vc(dsidev, channel);
1085
1086	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1087
1088	return r;
1089}
1090
1091static int dsi_register_isr_cio(struct platform_device *dsidev,
1092		omap_dsi_isr_t isr, void *arg, u32 mask)
1093{
1094	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1095	unsigned long flags;
1096	int r;
1097
1098	spin_lock_irqsave(&dsi->irq_lock, flags);
1099
1100	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1101			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1102
1103	if (r == 0)
1104		_omap_dsi_set_irqs_cio(dsidev);
1105
1106	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1107
1108	return r;
1109}
1110
1111static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1112		omap_dsi_isr_t isr, void *arg, u32 mask)
1113{
1114	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1115	unsigned long flags;
1116	int r;
1117
1118	spin_lock_irqsave(&dsi->irq_lock, flags);
1119
1120	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1121			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1122
1123	if (r == 0)
1124		_omap_dsi_set_irqs_cio(dsidev);
1125
1126	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1127
1128	return r;
1129}
1130
1131static u32 dsi_get_errors(struct platform_device *dsidev)
1132{
1133	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1134	unsigned long flags;
1135	u32 e;
 
1136	spin_lock_irqsave(&dsi->errors_lock, flags);
1137	e = dsi->errors;
1138	dsi->errors = 0;
1139	spin_unlock_irqrestore(&dsi->errors_lock, flags);
1140	return e;
1141}
1142
1143static int dsi_runtime_get(struct platform_device *dsidev)
1144{
1145	int r;
1146	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1147
1148	DSSDBG("dsi_runtime_get\n");
1149
1150	r = pm_runtime_get_sync(&dsi->pdev->dev);
1151	WARN_ON(r < 0);
1152	return r < 0 ? r : 0;
 
 
 
1153}
1154
1155static void dsi_runtime_put(struct platform_device *dsidev)
1156{
1157	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1158	int r;
1159
1160	DSSDBG("dsi_runtime_put\n");
1161
1162	r = pm_runtime_put_sync(&dsi->pdev->dev);
1163	WARN_ON(r < 0 && r != -ENOSYS);
1164}
1165
1166static int dsi_regulator_init(struct platform_device *dsidev)
1167{
1168	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1169	struct regulator *vdds_dsi;
1170
1171	if (dsi->vdds_dsi_reg != NULL)
1172		return 0;
1173
1174	vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd");
1175
1176	if (IS_ERR(vdds_dsi)) {
1177		if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1178			DSSERR("can't get DSI VDD regulator\n");
1179		return PTR_ERR(vdds_dsi);
1180	}
1181
1182	dsi->vdds_dsi_reg = vdds_dsi;
1183
1184	return 0;
1185}
1186
1187static void _dsi_print_reset_status(struct platform_device *dsidev)
1188{
1189	u32 l;
1190	int b0, b1, b2;
1191
1192	/* A dummy read using the SCP interface to any DSIPHY register is
1193	 * required after DSIPHY reset to complete the reset of the DSI complex
1194	 * I/O. */
1195	l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1196
1197	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1198		b0 = 28;
1199		b1 = 27;
1200		b2 = 26;
1201	} else {
1202		b0 = 24;
1203		b1 = 25;
1204		b2 = 26;
1205	}
1206
1207#define DSI_FLD_GET(fld, start, end)\
1208	FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1209
1210	pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1211		DSI_FLD_GET(PLL_STATUS, 0, 0),
1212		DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1213		DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1214		DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1215		DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1216		DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1217		DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1218		DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1219
1220#undef DSI_FLD_GET
1221}
1222
1223static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1224{
1225	DSSDBG("dsi_if_enable(%d)\n", enable);
1226
1227	enable = enable ? 1 : 0;
1228	REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1229
1230	if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1231			DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1232			return -EIO;
1233	}
1234
1235	return 0;
1236}
1237
1238static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1239{
1240	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1241
1242	return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1243}
1244
1245static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1246{
1247	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1248
1249	return dsi->pll.cinfo.clkout[HSDIV_DSI];
1250}
1251
1252static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1253{
1254	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1255
1256	return dsi->pll.cinfo.clkdco / 16;
1257}
1258
1259static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1260{
1261	unsigned long r;
1262	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1263
1264	if (dss_get_dsi_clk_source(dsi->module_id) == DSS_CLK_SRC_FCK) {
 
1265		/* DSI FCLK source is DSS_CLK_FCK */
1266		r = clk_get_rate(dsi->dss_clk);
1267	} else {
1268		/* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1269		r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1270	}
1271
1272	return r;
1273}
1274
1275static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1276		unsigned long lp_clk_min, unsigned long lp_clk_max,
1277		struct dsi_lp_clock_info *lp_cinfo)
1278{
1279	unsigned lp_clk_div;
1280	unsigned long lp_clk;
1281
1282	lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1283	lp_clk = dsi_fclk / 2 / lp_clk_div;
1284
1285	if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1286		return -EINVAL;
1287
1288	lp_cinfo->lp_clk_div = lp_clk_div;
1289	lp_cinfo->lp_clk = lp_clk;
1290
1291	return 0;
1292}
1293
1294static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1295{
1296	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1297	unsigned long dsi_fclk;
1298	unsigned lp_clk_div;
1299	unsigned long lp_clk;
1300	unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
1301
1302
1303	lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1304
1305	if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1306		return -EINVAL;
1307
1308	dsi_fclk = dsi_fclk_rate(dsidev);
1309
1310	lp_clk = dsi_fclk / 2 / lp_clk_div;
1311
1312	DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1313	dsi->current_lp_cinfo.lp_clk = lp_clk;
1314	dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1315
1316	/* LP_CLK_DIVISOR */
1317	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1318
1319	/* LP_RX_SYNCHRO_ENABLE */
1320	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1321
1322	return 0;
1323}
1324
1325static void dsi_enable_scp_clk(struct platform_device *dsidev)
1326{
1327	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1328
1329	if (dsi->scp_clk_refcount++ == 0)
1330		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1331}
1332
1333static void dsi_disable_scp_clk(struct platform_device *dsidev)
1334{
1335	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1336
1337	WARN_ON(dsi->scp_clk_refcount == 0);
1338	if (--dsi->scp_clk_refcount == 0)
1339		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1340}
1341
1342enum dsi_pll_power_state {
1343	DSI_PLL_POWER_OFF	= 0x0,
1344	DSI_PLL_POWER_ON_HSCLK	= 0x1,
1345	DSI_PLL_POWER_ON_ALL	= 0x2,
1346	DSI_PLL_POWER_ON_DIV	= 0x3,
1347};
1348
1349static int dsi_pll_power(struct platform_device *dsidev,
1350		enum dsi_pll_power_state state)
1351{
1352	int t = 0;
1353
1354	/* DSI-PLL power command 0x3 is not working */
1355	if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1356			state == DSI_PLL_POWER_ON_DIV)
1357		state = DSI_PLL_POWER_ON_ALL;
1358
1359	/* PLL_PWR_CMD */
1360	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1361
1362	/* PLL_PWR_STATUS */
1363	while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1364		if (++t > 1000) {
1365			DSSERR("Failed to set DSI PLL power mode to %d\n",
1366					state);
1367			return -ENODEV;
1368		}
1369		udelay(1);
1370	}
1371
1372	return 0;
1373}
1374
1375
1376static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo)
 
1377{
1378	unsigned long max_dsi_fck;
1379
1380	max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1381
1382	cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1383	cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1384}
1385
1386static int dsi_pll_enable(struct dss_pll *pll)
1387{
1388	struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1389	struct platform_device *dsidev = dsi->pdev;
1390	int r = 0;
1391
1392	DSSDBG("PLL init\n");
1393
1394	r = dsi_regulator_init(dsidev);
1395	if (r)
1396		return r;
1397
1398	r = dsi_runtime_get(dsidev);
1399	if (r)
1400		return r;
1401
1402	/*
1403	 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1404	 */
1405	dsi_enable_scp_clk(dsidev);
1406
1407	if (!dsi->vdds_dsi_enabled) {
1408		r = regulator_enable(dsi->vdds_dsi_reg);
1409		if (r)
1410			goto err0;
1411		dsi->vdds_dsi_enabled = true;
1412	}
1413
1414	/* XXX PLL does not come out of reset without this... */
1415	dispc_pck_free_enable(1);
1416
1417	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1418		DSSERR("PLL not coming out of reset.\n");
1419		r = -ENODEV;
1420		dispc_pck_free_enable(0);
1421		goto err1;
1422	}
1423
1424	/* XXX ... but if left on, we get problems when planes do not
1425	 * fill the whole display. No idea about this */
1426	dispc_pck_free_enable(0);
1427
1428	r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL);
1429
1430	if (r)
1431		goto err1;
1432
1433	DSSDBG("PLL init done\n");
1434
1435	return 0;
1436err1:
1437	if (dsi->vdds_dsi_enabled) {
1438		regulator_disable(dsi->vdds_dsi_reg);
1439		dsi->vdds_dsi_enabled = false;
1440	}
1441err0:
1442	dsi_disable_scp_clk(dsidev);
1443	dsi_runtime_put(dsidev);
1444	return r;
1445}
1446
1447static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1448{
1449	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1450
1451	dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1452	if (disconnect_lanes) {
1453		WARN_ON(!dsi->vdds_dsi_enabled);
1454		regulator_disable(dsi->vdds_dsi_reg);
1455		dsi->vdds_dsi_enabled = false;
1456	}
1457
1458	dsi_disable_scp_clk(dsidev);
1459	dsi_runtime_put(dsidev);
1460
1461	DSSDBG("PLL uninit done\n");
1462}
1463
1464static void dsi_pll_disable(struct dss_pll *pll)
1465{
1466	struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1467	struct platform_device *dsidev = dsi->pdev;
1468
1469	dsi_pll_uninit(dsidev, true);
1470}
1471
1472static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1473		struct seq_file *s)
1474{
1475	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1476	struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1477	enum dss_clk_source dispc_clk_src, dsi_clk_src;
1478	int dsi_module = dsi->module_id;
1479	struct dss_pll *pll = &dsi->pll;
1480
1481	dispc_clk_src = dss_get_dispc_clk_source();
1482	dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1483
1484	if (dsi_runtime_get(dsidev))
1485		return;
1486
1487	seq_printf(s,	"- DSI%d PLL -\n", dsi_module + 1);
1488
1489	seq_printf(s,	"dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1490
1491	seq_printf(s,	"Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1492
1493	seq_printf(s,	"CLKIN4DDR\t%-16lum %u\n",
1494			cinfo->clkdco, cinfo->m);
1495
1496	seq_printf(s,	"DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1497			dss_get_clk_source_name(dsi_module == 0 ?
1498				DSS_CLK_SRC_PLL1_1 :
1499				DSS_CLK_SRC_PLL2_1),
1500			cinfo->clkout[HSDIV_DISPC],
1501			cinfo->mX[HSDIV_DISPC],
1502			dispc_clk_src == DSS_CLK_SRC_FCK ?
1503			"off" : "on");
1504
1505	seq_printf(s,	"DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1506			dss_get_clk_source_name(dsi_module == 0 ?
1507				DSS_CLK_SRC_PLL1_2 :
1508				DSS_CLK_SRC_PLL2_2),
1509			cinfo->clkout[HSDIV_DSI],
1510			cinfo->mX[HSDIV_DSI],
1511			dsi_clk_src == DSS_CLK_SRC_FCK ?
1512			"off" : "on");
1513
1514	seq_printf(s,	"- DSI%d -\n", dsi_module + 1);
1515
1516	seq_printf(s,	"dsi fclk source = %s\n",
1517			dss_get_clk_source_name(dsi_clk_src));
1518
1519	seq_printf(s,	"DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1520
1521	seq_printf(s,	"DDR_CLK\t\t%lu\n",
1522			cinfo->clkdco / 4);
1523
1524	seq_printf(s,	"TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1525
1526	seq_printf(s,	"LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1527
1528	dsi_runtime_put(dsidev);
1529}
1530
1531void dsi_dump_clocks(struct seq_file *s)
1532{
1533	struct platform_device *dsidev;
1534	int i;
1535
1536	for  (i = 0; i < MAX_NUM_DSI; i++) {
1537		dsidev = dsi_get_dsidev_from_id(i);
1538		if (dsidev)
1539			dsi_dump_dsidev_clocks(dsidev, s);
1540	}
1541}
1542
1543#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1544static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1545		struct seq_file *s)
1546{
1547	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1548	unsigned long flags;
1549	struct dsi_irq_stats stats;
1550
1551	spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1552
1553	stats = dsi->irq_stats;
1554	memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1555	dsi->irq_stats.last_reset = jiffies;
1556
1557	spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1558
1559	seq_printf(s, "period %u ms\n",
1560			jiffies_to_msecs(jiffies - stats.last_reset));
1561
1562	seq_printf(s, "irqs %d\n", stats.irq_count);
1563#define PIS(x) \
1564	seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1565
1566	seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1567	PIS(VC0);
1568	PIS(VC1);
1569	PIS(VC2);
1570	PIS(VC3);
1571	PIS(WAKEUP);
1572	PIS(RESYNC);
1573	PIS(PLL_LOCK);
1574	PIS(PLL_UNLOCK);
1575	PIS(PLL_RECALL);
1576	PIS(COMPLEXIO_ERR);
1577	PIS(HS_TX_TIMEOUT);
1578	PIS(LP_RX_TIMEOUT);
1579	PIS(TE_TRIGGER);
1580	PIS(ACK_TRIGGER);
1581	PIS(SYNC_LOST);
1582	PIS(LDO_POWER_GOOD);
1583	PIS(TA_TIMEOUT);
1584#undef PIS
1585
1586#define PIS(x) \
1587	seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1588			stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1589			stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1590			stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1591			stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1592
1593	seq_printf(s, "-- VC interrupts --\n");
1594	PIS(CS);
1595	PIS(ECC_CORR);
1596	PIS(PACKET_SENT);
1597	PIS(FIFO_TX_OVF);
1598	PIS(FIFO_RX_OVF);
1599	PIS(BTA);
1600	PIS(ECC_NO_CORR);
1601	PIS(FIFO_TX_UDF);
1602	PIS(PP_BUSY_CHANGE);
1603#undef PIS
1604
1605#define PIS(x) \
1606	seq_printf(s, "%-20s %10d\n", #x, \
1607			stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1608
1609	seq_printf(s, "-- CIO interrupts --\n");
1610	PIS(ERRSYNCESC1);
1611	PIS(ERRSYNCESC2);
1612	PIS(ERRSYNCESC3);
1613	PIS(ERRESC1);
1614	PIS(ERRESC2);
1615	PIS(ERRESC3);
1616	PIS(ERRCONTROL1);
1617	PIS(ERRCONTROL2);
1618	PIS(ERRCONTROL3);
1619	PIS(STATEULPS1);
1620	PIS(STATEULPS2);
1621	PIS(STATEULPS3);
1622	PIS(ERRCONTENTIONLP0_1);
1623	PIS(ERRCONTENTIONLP1_1);
1624	PIS(ERRCONTENTIONLP0_2);
1625	PIS(ERRCONTENTIONLP1_2);
1626	PIS(ERRCONTENTIONLP0_3);
1627	PIS(ERRCONTENTIONLP1_3);
1628	PIS(ULPSACTIVENOT_ALL0);
1629	PIS(ULPSACTIVENOT_ALL1);
1630#undef PIS
1631}
1632
1633static void dsi1_dump_irqs(struct seq_file *s)
1634{
1635	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1636
1637	dsi_dump_dsidev_irqs(dsidev, s);
1638}
1639
1640static void dsi2_dump_irqs(struct seq_file *s)
1641{
1642	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1643
1644	dsi_dump_dsidev_irqs(dsidev, s);
1645}
1646#endif
1647
1648static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1649		struct seq_file *s)
1650{
1651#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1652
1653	if (dsi_runtime_get(dsidev))
1654		return;
1655	dsi_enable_scp_clk(dsidev);
1656
 
1657	DUMPREG(DSI_REVISION);
1658	DUMPREG(DSI_SYSCONFIG);
1659	DUMPREG(DSI_SYSSTATUS);
1660	DUMPREG(DSI_IRQSTATUS);
1661	DUMPREG(DSI_IRQENABLE);
1662	DUMPREG(DSI_CTRL);
1663	DUMPREG(DSI_COMPLEXIO_CFG1);
1664	DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1665	DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1666	DUMPREG(DSI_CLK_CTRL);
1667	DUMPREG(DSI_TIMING1);
1668	DUMPREG(DSI_TIMING2);
1669	DUMPREG(DSI_VM_TIMING1);
1670	DUMPREG(DSI_VM_TIMING2);
1671	DUMPREG(DSI_VM_TIMING3);
1672	DUMPREG(DSI_CLK_TIMING);
1673	DUMPREG(DSI_TX_FIFO_VC_SIZE);
1674	DUMPREG(DSI_RX_FIFO_VC_SIZE);
1675	DUMPREG(DSI_COMPLEXIO_CFG2);
1676	DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1677	DUMPREG(DSI_VM_TIMING4);
1678	DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1679	DUMPREG(DSI_VM_TIMING5);
1680	DUMPREG(DSI_VM_TIMING6);
1681	DUMPREG(DSI_VM_TIMING7);
1682	DUMPREG(DSI_STOPCLK_TIMING);
1683
1684	DUMPREG(DSI_VC_CTRL(0));
1685	DUMPREG(DSI_VC_TE(0));
1686	DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1687	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1688	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1689	DUMPREG(DSI_VC_IRQSTATUS(0));
1690	DUMPREG(DSI_VC_IRQENABLE(0));
1691
1692	DUMPREG(DSI_VC_CTRL(1));
1693	DUMPREG(DSI_VC_TE(1));
1694	DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1695	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1696	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1697	DUMPREG(DSI_VC_IRQSTATUS(1));
1698	DUMPREG(DSI_VC_IRQENABLE(1));
1699
1700	DUMPREG(DSI_VC_CTRL(2));
1701	DUMPREG(DSI_VC_TE(2));
1702	DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1703	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1704	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1705	DUMPREG(DSI_VC_IRQSTATUS(2));
1706	DUMPREG(DSI_VC_IRQENABLE(2));
1707
1708	DUMPREG(DSI_VC_CTRL(3));
1709	DUMPREG(DSI_VC_TE(3));
1710	DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1711	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1712	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1713	DUMPREG(DSI_VC_IRQSTATUS(3));
1714	DUMPREG(DSI_VC_IRQENABLE(3));
1715
1716	DUMPREG(DSI_DSIPHY_CFG0);
1717	DUMPREG(DSI_DSIPHY_CFG1);
1718	DUMPREG(DSI_DSIPHY_CFG2);
1719	DUMPREG(DSI_DSIPHY_CFG5);
1720
1721	DUMPREG(DSI_PLL_CONTROL);
1722	DUMPREG(DSI_PLL_STATUS);
1723	DUMPREG(DSI_PLL_GO);
1724	DUMPREG(DSI_PLL_CONFIGURATION1);
1725	DUMPREG(DSI_PLL_CONFIGURATION2);
1726
1727	dsi_disable_scp_clk(dsidev);
1728	dsi_runtime_put(dsidev);
1729#undef DUMPREG
1730}
1731
1732static void dsi1_dump_regs(struct seq_file *s)
1733{
1734	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1735
1736	dsi_dump_dsidev_regs(dsidev, s);
1737}
1738
1739static void dsi2_dump_regs(struct seq_file *s)
1740{
1741	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1742
1743	dsi_dump_dsidev_regs(dsidev, s);
1744}
1745
1746enum dsi_cio_power_state {
1747	DSI_COMPLEXIO_POWER_OFF		= 0x0,
1748	DSI_COMPLEXIO_POWER_ON		= 0x1,
1749	DSI_COMPLEXIO_POWER_ULPS	= 0x2,
1750};
1751
1752static int dsi_cio_power(struct platform_device *dsidev,
1753		enum dsi_cio_power_state state)
1754{
1755	int t = 0;
1756
1757	/* PWR_CMD */
1758	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1759
1760	/* PWR_STATUS */
1761	while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1762			26, 25) != state) {
1763		if (++t > 1000) {
1764			DSSERR("failed to set complexio power state to "
1765					"%d\n", state);
1766			return -ENODEV;
1767		}
1768		udelay(1);
1769	}
1770
1771	return 0;
1772}
1773
1774static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1775{
1776	int val;
1777
1778	/* line buffer on OMAP3 is 1024 x 24bits */
1779	/* XXX: for some reason using full buffer size causes
1780	 * considerable TX slowdown with update sizes that fill the
1781	 * whole buffer */
1782	if (!dss_has_feature(FEAT_DSI_GNQ))
1783		return 1023 * 3;
1784
1785	val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1786
1787	switch (val) {
1788	case 1:
1789		return 512 * 3;		/* 512x24 bits */
1790	case 2:
1791		return 682 * 3;		/* 682x24 bits */
1792	case 3:
1793		return 853 * 3;		/* 853x24 bits */
1794	case 4:
1795		return 1024 * 3;	/* 1024x24 bits */
1796	case 5:
1797		return 1194 * 3;	/* 1194x24 bits */
1798	case 6:
1799		return 1365 * 3;	/* 1365x24 bits */
1800	case 7:
1801		return 1920 * 3;	/* 1920x24 bits */
1802	default:
1803		BUG();
1804		return 0;
1805	}
1806}
1807
1808static int dsi_set_lane_config(struct platform_device *dsidev)
1809{
1810	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1811	static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1812	static const enum dsi_lane_function functions[] = {
1813		DSI_LANE_CLK,
1814		DSI_LANE_DATA1,
1815		DSI_LANE_DATA2,
1816		DSI_LANE_DATA3,
1817		DSI_LANE_DATA4,
1818	};
1819	u32 r;
1820	int i;
1821
1822	r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1823
1824	for (i = 0; i < dsi->num_lanes_used; ++i) {
1825		unsigned offset = offsets[i];
1826		unsigned polarity, lane_number;
1827		unsigned t;
1828
1829		for (t = 0; t < dsi->num_lanes_supported; ++t)
1830			if (dsi->lanes[t].function == functions[i])
1831				break;
1832
1833		if (t == dsi->num_lanes_supported)
1834			return -EINVAL;
1835
1836		lane_number = t;
1837		polarity = dsi->lanes[t].polarity;
1838
1839		r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1840		r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1841	}
1842
1843	/* clear the unused lanes */
1844	for (; i < dsi->num_lanes_supported; ++i) {
1845		unsigned offset = offsets[i];
1846
1847		r = FLD_MOD(r, 0, offset + 2, offset);
1848		r = FLD_MOD(r, 0, offset + 3, offset + 3);
1849	}
1850
1851	dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
1852
1853	return 0;
1854}
1855
1856static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
1857{
1858	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1859
1860	/* convert time in ns to ddr ticks, rounding up */
1861	unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
 
1862	return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1863}
1864
1865static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
1866{
1867	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1868
1869	unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
 
1870	return ddr * 1000 * 1000 / (ddr_clk / 1000);
1871}
1872
1873static void dsi_cio_timings(struct platform_device *dsidev)
1874{
1875	u32 r;
1876	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1877	u32 tlpx_half, tclk_trail, tclk_zero;
1878	u32 tclk_prepare;
1879
1880	/* calculate timings */
1881
1882	/* 1 * DDR_CLK = 2 * UI */
1883
1884	/* min 40ns + 4*UI	max 85ns + 6*UI */
1885	ths_prepare = ns2ddr(dsidev, 70) + 2;
1886
1887	/* min 145ns + 10*UI */
1888	ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
1889
1890	/* min max(8*UI, 60ns+4*UI) */
1891	ths_trail = ns2ddr(dsidev, 60) + 5;
1892
1893	/* min 100ns */
1894	ths_exit = ns2ddr(dsidev, 145);
1895
1896	/* tlpx min 50n */
1897	tlpx_half = ns2ddr(dsidev, 25);
1898
1899	/* min 60ns */
1900	tclk_trail = ns2ddr(dsidev, 60) + 2;
1901
1902	/* min 38ns, max 95ns */
1903	tclk_prepare = ns2ddr(dsidev, 65);
1904
1905	/* min tclk-prepare + tclk-zero = 300ns */
1906	tclk_zero = ns2ddr(dsidev, 260);
1907
1908	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1909		ths_prepare, ddr2ns(dsidev, ths_prepare),
1910		ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
1911	DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1912			ths_trail, ddr2ns(dsidev, ths_trail),
1913			ths_exit, ddr2ns(dsidev, ths_exit));
1914
1915	DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1916			"tclk_zero %u (%uns)\n",
1917			tlpx_half, ddr2ns(dsidev, tlpx_half),
1918			tclk_trail, ddr2ns(dsidev, tclk_trail),
1919			tclk_zero, ddr2ns(dsidev, tclk_zero));
1920	DSSDBG("tclk_prepare %u (%uns)\n",
1921			tclk_prepare, ddr2ns(dsidev, tclk_prepare));
1922
1923	/* program timings */
1924
1925	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
1926	r = FLD_MOD(r, ths_prepare, 31, 24);
1927	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1928	r = FLD_MOD(r, ths_trail, 15, 8);
1929	r = FLD_MOD(r, ths_exit, 7, 0);
1930	dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
1931
1932	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
1933	r = FLD_MOD(r, tlpx_half, 20, 16);
1934	r = FLD_MOD(r, tclk_trail, 15, 8);
1935	r = FLD_MOD(r, tclk_zero, 7, 0);
1936
1937	if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
1938		r = FLD_MOD(r, 0, 21, 21);	/* DCCEN = disable */
1939		r = FLD_MOD(r, 1, 22, 22);	/* CLKINP_DIVBY2EN = enable */
1940		r = FLD_MOD(r, 1, 23, 23);	/* CLKINP_SEL = enable */
1941	}
1942
1943	dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
1944
1945	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
1946	r = FLD_MOD(r, tclk_prepare, 7, 0);
1947	dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
1948}
1949
1950/* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1951static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
1952		unsigned mask_p, unsigned mask_n)
1953{
1954	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1955	int i;
1956	u32 l;
1957	u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1958
1959	l = 0;
1960
1961	for (i = 0; i < dsi->num_lanes_supported; ++i) {
1962		unsigned p = dsi->lanes[i].polarity;
1963
1964		if (mask_p & (1 << i))
1965			l |= 1 << (i * 2 + (p ? 0 : 1));
1966
1967		if (mask_n & (1 << i))
1968			l |= 1 << (i * 2 + (p ? 1 : 0));
1969	}
1970
1971	/*
1972	 * Bits in REGLPTXSCPDAT4TO0DXDY:
1973	 * 17: DY0 18: DX0
1974	 * 19: DY1 20: DX1
1975	 * 21: DY2 22: DX2
1976	 * 23: DY3 24: DX3
1977	 * 25: DY4 26: DX4
1978	 */
1979
1980	/* Set the lane override configuration */
1981
1982	/* REGLPTXSCPDAT4TO0DXDY */
1983	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
1984
1985	/* Enable lane override */
1986
1987	/* ENLPTXSCPDAT */
1988	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
1989}
1990
1991static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
1992{
1993	/* Disable lane override */
1994	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1995	/* Reset the lane override configuration */
1996	/* REGLPTXSCPDAT4TO0DXDY */
1997	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
1998}
1999
2000static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2001{
2002	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2003	int t, i;
2004	bool in_use[DSI_MAX_NR_LANES];
2005	static const u8 offsets_old[] = { 28, 27, 26 };
2006	static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2007	const u8 *offsets;
2008
2009	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2010		offsets = offsets_old;
2011	else
2012		offsets = offsets_new;
2013
2014	for (i = 0; i < dsi->num_lanes_supported; ++i)
2015		in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2016
2017	t = 100000;
2018	while (true) {
2019		u32 l;
2020		int ok;
2021
2022		l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2023
2024		ok = 0;
2025		for (i = 0; i < dsi->num_lanes_supported; ++i) {
2026			if (!in_use[i] || (l & (1 << offsets[i])))
2027				ok++;
2028		}
2029
2030		if (ok == dsi->num_lanes_supported)
2031			break;
2032
2033		if (--t == 0) {
2034			for (i = 0; i < dsi->num_lanes_supported; ++i) {
2035				if (!in_use[i] || (l & (1 << offsets[i])))
2036					continue;
2037
2038				DSSERR("CIO TXCLKESC%d domain not coming " \
2039						"out of reset\n", i);
2040			}
2041			return -EIO;
2042		}
2043	}
2044
2045	return 0;
2046}
2047
2048/* return bitmask of enabled lanes, lane0 being the lsb */
2049static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2050{
2051	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2052	unsigned mask = 0;
2053	int i;
2054
2055	for (i = 0; i < dsi->num_lanes_supported; ++i) {
2056		if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2057			mask |= 1 << i;
2058	}
2059
2060	return mask;
2061}
2062
2063static int dsi_cio_init(struct platform_device *dsidev)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2064{
2065	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2066	int r;
2067	u32 l;
2068
2069	DSSDBG("DSI CIO init starts");
2070
2071	r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2072	if (r)
2073		return r;
2074
2075	dsi_enable_scp_clk(dsidev);
2076
2077	/* A dummy read using the SCP interface to any DSIPHY register is
2078	 * required after DSIPHY reset to complete the reset of the DSI complex
2079	 * I/O. */
2080	dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2081
2082	if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2083		DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2084		r = -EIO;
2085		goto err_scp_clk_dom;
2086	}
2087
2088	r = dsi_set_lane_config(dsidev);
2089	if (r)
2090		goto err_scp_clk_dom;
2091
2092	/* set TX STOP MODE timer to maximum for this operation */
2093	l = dsi_read_reg(dsidev, DSI_TIMING1);
2094	l = FLD_MOD(l, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
2095	l = FLD_MOD(l, 1, 14, 14);	/* STOP_STATE_X16_IO */
2096	l = FLD_MOD(l, 1, 13, 13);	/* STOP_STATE_X4_IO */
2097	l = FLD_MOD(l, 0x1fff, 12, 0);	/* STOP_STATE_COUNTER_IO */
2098	dsi_write_reg(dsidev, DSI_TIMING1, l);
2099
2100	if (dsi->ulps_enabled) {
2101		unsigned mask_p;
2102		int i;
2103
2104		DSSDBG("manual ulps exit\n");
2105
2106		/* ULPS is exited by Mark-1 state for 1ms, followed by
2107		 * stop state. DSS HW cannot do this via the normal
2108		 * ULPS exit sequence, as after reset the DSS HW thinks
2109		 * that we are not in ULPS mode, and refuses to send the
2110		 * sequence. So we need to send the ULPS exit sequence
2111		 * manually by setting positive lines high and negative lines
2112		 * low for 1ms.
2113		 */
2114
2115		mask_p = 0;
2116
2117		for (i = 0; i < dsi->num_lanes_supported; ++i) {
2118			if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2119				continue;
2120			mask_p |= 1 << i;
2121		}
2122
2123		dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2124	}
2125
2126	r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2127	if (r)
2128		goto err_cio_pwr;
2129
2130	if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2131		DSSERR("CIO PWR clock domain not coming out of reset.\n");
2132		r = -ENODEV;
2133		goto err_cio_pwr_dom;
2134	}
2135
2136	dsi_if_enable(dsidev, true);
2137	dsi_if_enable(dsidev, false);
2138	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2139
2140	r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2141	if (r)
2142		goto err_tx_clk_esc_rst;
2143
2144	if (dsi->ulps_enabled) {
2145		/* Keep Mark-1 state for 1ms (as per DSI spec) */
2146		ktime_t wait = ns_to_ktime(1000 * 1000);
2147		set_current_state(TASK_UNINTERRUPTIBLE);
2148		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2149
2150		/* Disable the override. The lanes should be set to Mark-11
2151		 * state by the HW */
2152		dsi_cio_disable_lane_override(dsidev);
2153	}
2154
2155	/* FORCE_TX_STOP_MODE_IO */
2156	REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2157
2158	dsi_cio_timings(dsidev);
2159
2160	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2161		/* DDR_CLK_ALWAYS_ON */
2162		REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2163			dsi->vm_timings.ddr_clk_always_on, 13, 13);
2164	}
2165
2166	dsi->ulps_enabled = false;
 
 
 
2167
2168	DSSDBG("CIO init done\n");
2169
2170	return 0;
2171
2172err_tx_clk_esc_rst:
2173	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2174err_cio_pwr_dom:
2175	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2176err_cio_pwr:
2177	if (dsi->ulps_enabled)
2178		dsi_cio_disable_lane_override(dsidev);
2179err_scp_clk_dom:
2180	dsi_disable_scp_clk(dsidev);
2181	dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2182	return r;
2183}
2184
2185static void dsi_cio_uninit(struct platform_device *dsidev)
2186{
2187	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2188
2189	/* DDR_CLK_ALWAYS_ON */
2190	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2191
2192	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2193	dsi_disable_scp_clk(dsidev);
2194	dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2195}
2196
2197static void dsi_config_tx_fifo(struct platform_device *dsidev,
2198		enum fifo_size size1, enum fifo_size size2,
2199		enum fifo_size size3, enum fifo_size size4)
2200{
2201	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2202	u32 r = 0;
2203	int add = 0;
2204	int i;
2205
2206	dsi->vc[0].tx_fifo_size = size1;
2207	dsi->vc[1].tx_fifo_size = size2;
2208	dsi->vc[2].tx_fifo_size = size3;
2209	dsi->vc[3].tx_fifo_size = size4;
2210
2211	for (i = 0; i < 4; i++) {
2212		u8 v;
2213		int size = dsi->vc[i].tx_fifo_size;
2214
2215		if (add + size > 4) {
2216			DSSERR("Illegal FIFO configuration\n");
2217			BUG();
2218			return;
2219		}
2220
2221		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2222		r |= v << (8 * i);
2223		/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2224		add += size;
2225	}
2226
2227	dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2228}
2229
2230static void dsi_config_rx_fifo(struct platform_device *dsidev,
2231		enum fifo_size size1, enum fifo_size size2,
2232		enum fifo_size size3, enum fifo_size size4)
2233{
2234	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2235	u32 r = 0;
2236	int add = 0;
2237	int i;
2238
2239	dsi->vc[0].rx_fifo_size = size1;
2240	dsi->vc[1].rx_fifo_size = size2;
2241	dsi->vc[2].rx_fifo_size = size3;
2242	dsi->vc[3].rx_fifo_size = size4;
2243
2244	for (i = 0; i < 4; i++) {
2245		u8 v;
2246		int size = dsi->vc[i].rx_fifo_size;
2247
2248		if (add + size > 4) {
2249			DSSERR("Illegal FIFO configuration\n");
2250			BUG();
2251			return;
2252		}
2253
2254		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2255		r |= v << (8 * i);
2256		/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2257		add += size;
2258	}
2259
2260	dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2261}
2262
2263static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2264{
2265	u32 r;
2266
2267	r = dsi_read_reg(dsidev, DSI_TIMING1);
2268	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
2269	dsi_write_reg(dsidev, DSI_TIMING1, r);
2270
2271	if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2272		DSSERR("TX_STOP bit not going down\n");
2273		return -EIO;
2274	}
2275
2276	return 0;
2277}
2278
2279static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2280{
2281	return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2282}
2283
2284static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2285{
2286	struct dsi_packet_sent_handler_data *vp_data =
2287		(struct dsi_packet_sent_handler_data *) data;
2288	struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2289	const int channel = dsi->update_channel;
2290	u8 bit = dsi->te_enabled ? 30 : 31;
2291
2292	if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2293		complete(vp_data->completion);
2294}
2295
2296static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2297{
2298	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2299	DECLARE_COMPLETION_ONSTACK(completion);
2300	struct dsi_packet_sent_handler_data vp_data = {
2301		.dsidev = dsidev,
2302		.completion = &completion
2303	};
2304	int r = 0;
2305	u8 bit;
2306
2307	bit = dsi->te_enabled ? 30 : 31;
2308
2309	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2310		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2311	if (r)
2312		goto err0;
2313
2314	/* Wait for completion only if TE_EN/TE_START is still set */
2315	if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2316		if (wait_for_completion_timeout(&completion,
2317				msecs_to_jiffies(10)) == 0) {
2318			DSSERR("Failed to complete previous frame transfer\n");
2319			r = -EIO;
2320			goto err1;
2321		}
2322	}
2323
2324	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2325		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2326
2327	return 0;
2328err1:
2329	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2330		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2331err0:
2332	return r;
2333}
2334
2335static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2336{
2337	struct dsi_packet_sent_handler_data *l4_data =
2338		(struct dsi_packet_sent_handler_data *) data;
2339	struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2340	const int channel = dsi->update_channel;
2341
2342	if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2343		complete(l4_data->completion);
2344}
2345
2346static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2347{
2348	DECLARE_COMPLETION_ONSTACK(completion);
2349	struct dsi_packet_sent_handler_data l4_data = {
2350		.dsidev = dsidev,
2351		.completion = &completion
2352	};
2353	int r = 0;
2354
2355	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2356		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2357	if (r)
2358		goto err0;
2359
2360	/* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2361	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2362		if (wait_for_completion_timeout(&completion,
2363				msecs_to_jiffies(10)) == 0) {
2364			DSSERR("Failed to complete previous l4 transfer\n");
2365			r = -EIO;
2366			goto err1;
2367		}
2368	}
2369
2370	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2371		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2372
2373	return 0;
2374err1:
2375	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2376		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2377err0:
2378	return r;
2379}
2380
2381static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2382{
2383	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2384
2385	WARN_ON(!dsi_bus_is_locked(dsidev));
2386
2387	WARN_ON(in_interrupt());
2388
2389	if (!dsi_vc_is_enabled(dsidev, channel))
2390		return 0;
2391
2392	switch (dsi->vc[channel].source) {
2393	case DSI_VC_SOURCE_VP:
2394		return dsi_sync_vc_vp(dsidev, channel);
2395	case DSI_VC_SOURCE_L4:
2396		return dsi_sync_vc_l4(dsidev, channel);
2397	default:
2398		BUG();
2399		return -EINVAL;
2400	}
2401}
2402
2403static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2404		bool enable)
2405{
2406	DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2407			channel, enable);
2408
2409	enable = enable ? 1 : 0;
2410
2411	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2412
2413	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2414		0, enable) != enable) {
2415			DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2416			return -EIO;
2417	}
2418
2419	return 0;
2420}
2421
2422static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2423{
2424	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2425	u32 r;
2426
2427	DSSDBG("Initial config of virtual channel %d", channel);
2428
2429	r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2430
2431	if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2432		DSSERR("VC(%d) busy when trying to configure it!\n",
2433				channel);
2434
2435	r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2436	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2437	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2438	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2439	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2440	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2441	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2442	if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2443		r = FLD_MOD(r, 3, 11, 10);	/* OCP_WIDTH = 32 bit */
2444
2445	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2446	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2447
2448	dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2449
2450	dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2451}
2452
2453static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2454		enum dsi_vc_source source)
2455{
2456	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2457
2458	if (dsi->vc[channel].source == source)
2459		return 0;
2460
2461	DSSDBG("Source config of virtual channel %d", channel);
2462
2463	dsi_sync_vc(dsidev, channel);
2464
2465	dsi_vc_enable(dsidev, channel, 0);
2466
2467	/* VC_BUSY */
2468	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2469		DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2470		return -EIO;
2471	}
2472
2473	/* SOURCE, 0 = L4, 1 = video port */
2474	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2475
2476	/* DCS_CMD_ENABLE */
2477	if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2478		bool enable = source == DSI_VC_SOURCE_VP;
2479		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2480	}
2481
2482	dsi_vc_enable(dsidev, channel, 1);
2483
2484	dsi->vc[channel].source = source;
2485
2486	return 0;
2487}
2488
2489static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2490		bool enable)
2491{
2492	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2493	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2494
2495	DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2496
2497	WARN_ON(!dsi_bus_is_locked(dsidev));
 
2498
2499	dsi_vc_enable(dsidev, channel, 0);
2500	dsi_if_enable(dsidev, 0);
2501
2502	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
 
2503
2504	dsi_vc_enable(dsidev, channel, 1);
2505	dsi_if_enable(dsidev, 1);
2506
2507	dsi_force_tx_stop_mode_io(dsidev);
 
2508
2509	/* start the DDR clock by sending a NULL packet */
2510	if (dsi->vm_timings.ddr_clk_always_on && enable)
2511		dsi_vc_send_null(dssdev, channel);
2512}
2513
2514static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2515{
2516	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2517		u32 val;
2518		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2519		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2520				(val >> 0) & 0xff,
2521				(val >> 8) & 0xff,
2522				(val >> 16) & 0xff,
2523				(val >> 24) & 0xff);
2524	}
2525}
2526
2527static void dsi_show_rx_ack_with_err(u16 err)
2528{
2529	DSSERR("\tACK with ERROR (%#x):\n", err);
2530	if (err & (1 << 0))
2531		DSSERR("\t\tSoT Error\n");
2532	if (err & (1 << 1))
2533		DSSERR("\t\tSoT Sync Error\n");
2534	if (err & (1 << 2))
2535		DSSERR("\t\tEoT Sync Error\n");
2536	if (err & (1 << 3))
2537		DSSERR("\t\tEscape Mode Entry Command Error\n");
2538	if (err & (1 << 4))
2539		DSSERR("\t\tLP Transmit Sync Error\n");
2540	if (err & (1 << 5))
2541		DSSERR("\t\tHS Receive Timeout Error\n");
2542	if (err & (1 << 6))
2543		DSSERR("\t\tFalse Control Error\n");
2544	if (err & (1 << 7))
2545		DSSERR("\t\t(reserved7)\n");
2546	if (err & (1 << 8))
2547		DSSERR("\t\tECC Error, single-bit (corrected)\n");
2548	if (err & (1 << 9))
2549		DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2550	if (err & (1 << 10))
2551		DSSERR("\t\tChecksum Error\n");
2552	if (err & (1 << 11))
2553		DSSERR("\t\tData type not recognized\n");
2554	if (err & (1 << 12))
2555		DSSERR("\t\tInvalid VC ID\n");
2556	if (err & (1 << 13))
2557		DSSERR("\t\tInvalid Transmission Length\n");
2558	if (err & (1 << 14))
2559		DSSERR("\t\t(reserved14)\n");
2560	if (err & (1 << 15))
2561		DSSERR("\t\tDSI Protocol Violation\n");
2562}
2563
2564static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2565		int channel)
2566{
2567	/* RX_FIFO_NOT_EMPTY */
2568	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2569		u32 val;
2570		u8 dt;
2571		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2572		DSSERR("\trawval %#08x\n", val);
2573		dt = FLD_GET(val, 5, 0);
2574		if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2575			u16 err = FLD_GET(val, 23, 8);
2576			dsi_show_rx_ack_with_err(err);
2577		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2578			DSSERR("\tDCS short response, 1 byte: %#x\n",
2579					FLD_GET(val, 23, 8));
2580		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2581			DSSERR("\tDCS short response, 2 byte: %#x\n",
2582					FLD_GET(val, 23, 8));
2583		} else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2584			DSSERR("\tDCS long response, len %d\n",
2585					FLD_GET(val, 23, 8));
2586			dsi_vc_flush_long_data(dsidev, channel);
2587		} else {
2588			DSSERR("\tunknown datatype 0x%02x\n", dt);
2589		}
2590	}
2591	return 0;
2592}
2593
2594static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2595{
2596	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2597
2598	if (dsi->debug_write || dsi->debug_read)
2599		DSSDBG("dsi_vc_send_bta %d\n", channel);
2600
2601	WARN_ON(!dsi_bus_is_locked(dsidev));
2602
2603	/* RX_FIFO_NOT_EMPTY */
2604	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2605		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2606		dsi_vc_flush_receive_data(dsidev, channel);
2607	}
2608
2609	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2610
2611	/* flush posted write */
2612	dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2613
2614	return 0;
2615}
2616
2617static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2618{
2619	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2620	DECLARE_COMPLETION_ONSTACK(completion);
2621	int r = 0;
2622	u32 err;
2623
2624	r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2625			&completion, DSI_VC_IRQ_BTA);
2626	if (r)
2627		goto err0;
2628
2629	r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2630			DSI_IRQ_ERROR_MASK);
2631	if (r)
2632		goto err1;
2633
2634	r = dsi_vc_send_bta(dsidev, channel);
2635	if (r)
2636		goto err2;
2637
2638	if (wait_for_completion_timeout(&completion,
2639				msecs_to_jiffies(500)) == 0) {
2640		DSSERR("Failed to receive BTA\n");
2641		r = -EIO;
2642		goto err2;
2643	}
2644
2645	err = dsi_get_errors(dsidev);
2646	if (err) {
2647		DSSERR("Error while sending BTA: %x\n", err);
2648		r = -EIO;
2649		goto err2;
2650	}
2651err2:
2652	dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2653			DSI_IRQ_ERROR_MASK);
2654err1:
2655	dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2656			&completion, DSI_VC_IRQ_BTA);
2657err0:
2658	return r;
2659}
2660
2661static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2662		int channel, u8 data_type, u16 len, u8 ecc)
 
2663{
2664	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2665	u32 val;
2666	u8 data_id;
2667
2668	WARN_ON(!dsi_bus_is_locked(dsidev));
2669
2670	data_id = data_type | dsi->vc[channel].vc_id << 6;
2671
2672	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2673		FLD_VAL(ecc, 31, 24);
2674
2675	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2676}
2677
2678static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2679		int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2680{
2681	u32 val;
2682
2683	val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
2684
2685/*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2686			b1, b2, b3, b4, val); */
2687
2688	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2689}
2690
2691static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2692		u8 data_type, u8 *data, u16 len, u8 ecc)
2693{
2694	/*u32 val; */
2695	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2696	int i;
2697	u8 *p;
2698	int r = 0;
2699	u8 b1, b2, b3, b4;
2700
2701	if (dsi->debug_write)
2702		DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2703
2704	/* len + header */
2705	if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2706		DSSERR("unable to send long packet: packet too long.\n");
2707		return -EINVAL;
2708	}
2709
2710	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2711
2712	dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2713
2714	p = data;
2715	for (i = 0; i < len >> 2; i++) {
2716		if (dsi->debug_write)
2717			DSSDBG("\tsending full packet %d\n", i);
2718
2719		b1 = *p++;
2720		b2 = *p++;
2721		b3 = *p++;
2722		b4 = *p++;
2723
2724		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2725	}
2726
2727	i = len % 4;
2728	if (i) {
2729		b1 = 0; b2 = 0; b3 = 0;
2730
2731		if (dsi->debug_write)
2732			DSSDBG("\tsending remainder bytes %d\n", i);
2733
2734		switch (i) {
2735		case 3:
2736			b1 = *p++;
2737			b2 = *p++;
2738			b3 = *p++;
2739			break;
2740		case 2:
2741			b1 = *p++;
2742			b2 = *p++;
2743			break;
2744		case 1:
2745			b1 = *p++;
2746			break;
2747		}
2748
2749		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2750	}
2751
2752	return r;
2753}
2754
2755static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2756		u8 data_type, u16 data, u8 ecc)
2757{
2758	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 
2759	u32 r;
2760	u8 data_id;
2761
2762	WARN_ON(!dsi_bus_is_locked(dsidev));
 
 
2763
2764	if (dsi->debug_write)
2765		DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2766				channel,
2767				data_type, data & 0xff, (data >> 8) & 0xff);
2768
2769	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
 
 
2770
2771	if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2772		DSSERR("ERROR FIFO FULL, aborting transfer\n");
2773		return -EINVAL;
2774	}
2775
2776	data_id = data_type | dsi->vc[channel].vc_id << 6;
 
2777
2778	r = (data_id << 0) | (data << 8) | (ecc << 24);
2779
2780	dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2781
2782	return 0;
2783}
2784
2785static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2786{
2787	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2788
2789	return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2790		0, 0);
2791}
2792
2793static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
2794		int channel, u8 *data, int len, enum dss_dsi_content_type type)
2795{
2796	int r;
2797
2798	if (len == 0) {
2799		BUG_ON(type == DSS_DSI_CONTENT_DCS);
2800		r = dsi_vc_send_short(dsidev, channel,
2801				MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2802	} else if (len == 1) {
2803		r = dsi_vc_send_short(dsidev, channel,
2804				type == DSS_DSI_CONTENT_GENERIC ?
2805				MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2806				MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2807	} else if (len == 2) {
2808		r = dsi_vc_send_short(dsidev, channel,
2809				type == DSS_DSI_CONTENT_GENERIC ?
2810				MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2811				MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2812				data[0] | (data[1] << 8), 0);
2813	} else {
2814		r = dsi_vc_send_long(dsidev, channel,
2815				type == DSS_DSI_CONTENT_GENERIC ?
2816				MIPI_DSI_GENERIC_LONG_WRITE :
2817				MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2818	}
2819
2820	return r;
2821}
2822
2823static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2824		u8 *data, int len)
2825{
2826	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2827
2828	return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2829			DSS_DSI_CONTENT_DCS);
2830}
2831
2832static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2833		u8 *data, int len)
2834{
2835	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 
 
 
2836
2837	return dsi_vc_write_nosync_common(dsidev, channel, data, len,
2838			DSS_DSI_CONTENT_GENERIC);
2839}
2840
2841static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
2842		u8 *data, int len, enum dss_dsi_content_type type)
2843{
2844	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2845	int r;
2846
2847	r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
2848	if (r)
2849		goto err;
2850
2851	r = dsi_vc_send_bta_sync(dssdev, channel);
2852	if (r)
2853		goto err;
2854
2855	/* RX_FIFO_NOT_EMPTY */
2856	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2857		DSSERR("rx fifo not empty after write, dumping data:\n");
2858		dsi_vc_flush_receive_data(dsidev, channel);
2859		r = -EIO;
2860		goto err;
2861	}
2862
2863	return 0;
2864err:
2865	DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2866			channel, data[0], len);
2867	return r;
2868}
2869
2870static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2871		int len)
2872{
2873	return dsi_vc_write_common(dssdev, channel, data, len,
2874			DSS_DSI_CONTENT_DCS);
2875}
2876
2877static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2878		int len)
2879{
2880	return dsi_vc_write_common(dssdev, channel, data, len,
2881			DSS_DSI_CONTENT_GENERIC);
2882}
2883
2884static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
2885		int channel, u8 dcs_cmd)
2886{
2887	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2888	int r;
2889
2890	if (dsi->debug_read)
2891		DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2892			channel, dcs_cmd);
 
 
 
2893
2894	r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
2895	if (r) {
2896		DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
2897			" failed\n", channel, dcs_cmd);
2898		return r;
2899	}
2900
2901	return 0;
2902}
2903
2904static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
2905		int channel, u8 *reqdata, int reqlen)
2906{
2907	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2908	u16 data;
2909	u8 data_type;
2910	int r;
2911
2912	if (dsi->debug_read)
2913		DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
2914			channel, reqlen);
2915
2916	if (reqlen == 0) {
2917		data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
2918		data = 0;
2919	} else if (reqlen == 1) {
2920		data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
2921		data = reqdata[0];
2922	} else if (reqlen == 2) {
2923		data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
2924		data = reqdata[0] | (reqdata[1] << 8);
2925	} else {
2926		BUG();
2927		return -EINVAL;
2928	}
2929
2930	r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
2931	if (r) {
2932		DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
2933			" failed\n", channel, reqlen);
2934		return r;
2935	}
2936
2937	return 0;
2938}
2939
2940static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
2941		u8 *buf, int buflen, enum dss_dsi_content_type type)
2942{
2943	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2944	u32 val;
2945	u8 dt;
2946	int r;
2947
2948	/* RX_FIFO_NOT_EMPTY */
2949	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
2950		DSSERR("RX fifo empty when trying to read.\n");
2951		r = -EIO;
2952		goto err;
2953	}
2954
2955	val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2956	if (dsi->debug_read)
2957		DSSDBG("\theader: %08x\n", val);
2958	dt = FLD_GET(val, 5, 0);
2959	if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2960		u16 err = FLD_GET(val, 23, 8);
2961		dsi_show_rx_ack_with_err(err);
2962		r = -EIO;
2963		goto err;
2964
2965	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2966			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2967			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2968		u8 data = FLD_GET(val, 15, 8);
2969		if (dsi->debug_read)
2970			DSSDBG("\t%s short response, 1 byte: %02x\n",
2971				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2972				"DCS", data);
2973
2974		if (buflen < 1) {
2975			r = -EIO;
2976			goto err;
2977		}
2978
2979		buf[0] = data;
2980
2981		return 1;
2982	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2983			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
2984			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
2985		u16 data = FLD_GET(val, 23, 8);
2986		if (dsi->debug_read)
2987			DSSDBG("\t%s short response, 2 byte: %04x\n",
2988				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2989				"DCS", data);
2990
2991		if (buflen < 2) {
2992			r = -EIO;
2993			goto err;
2994		}
2995
2996		buf[0] = data & 0xff;
2997		buf[1] = (data >> 8) & 0xff;
2998
2999		return 2;
3000	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3001			MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3002			MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3003		int w;
3004		int len = FLD_GET(val, 23, 8);
3005		if (dsi->debug_read)
3006			DSSDBG("\t%s long response, len %d\n",
3007				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3008				"DCS", len);
3009
3010		if (len > buflen) {
3011			r = -EIO;
3012			goto err;
3013		}
3014
3015		/* two byte checksum ends the packet, not included in len */
3016		for (w = 0; w < len + 2;) {
3017			int b;
3018			val = dsi_read_reg(dsidev,
3019				DSI_VC_SHORT_PACKET_HEADER(channel));
3020			if (dsi->debug_read)
3021				DSSDBG("\t\t%02x %02x %02x %02x\n",
3022						(val >> 0) & 0xff,
3023						(val >> 8) & 0xff,
3024						(val >> 16) & 0xff,
3025						(val >> 24) & 0xff);
3026
3027			for (b = 0; b < 4; ++b) {
3028				if (w < len)
3029					buf[w] = (val >> (b * 8)) & 0xff;
3030				/* we discard the 2 byte checksum */
3031				++w;
3032			}
3033		}
3034
3035		return len;
3036	} else {
3037		DSSERR("\tunknown datatype 0x%02x\n", dt);
3038		r = -EIO;
3039		goto err;
3040	}
3041
3042err:
3043	DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3044		type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3045
3046	return r;
3047}
3048
3049static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3050		u8 *buf, int buflen)
3051{
3052	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 
3053	int r;
3054
3055	r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
 
 
 
3056	if (r)
3057		goto err;
3058
3059	r = dsi_vc_send_bta_sync(dssdev, channel);
3060	if (r)
3061		goto err;
3062
3063	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3064		DSS_DSI_CONTENT_DCS);
3065	if (r < 0)
3066		goto err;
3067
3068	if (r != buflen) {
3069		r = -EIO;
3070		goto err;
3071	}
3072
3073	return 0;
3074err:
3075	DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3076	return r;
3077}
3078
3079static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3080		u8 *reqdata, int reqlen, u8 *buf, int buflen)
3081{
3082	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3083	int r;
3084
3085	r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3086	if (r)
3087		return r;
3088
3089	r = dsi_vc_send_bta_sync(dssdev, channel);
3090	if (r)
3091		return r;
3092
3093	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3094		DSS_DSI_CONTENT_GENERIC);
3095	if (r < 0)
3096		return r;
3097
3098	if (r != buflen) {
3099		r = -EIO;
3100		return r;
3101	}
3102
3103	return 0;
3104}
3105
3106static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3107		u16 len)
3108{
3109	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3110
3111	return dsi_vc_send_short(dsidev, channel,
3112			MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3113}
3114
3115static int dsi_enter_ulps(struct platform_device *dsidev)
3116{
3117	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3118	DECLARE_COMPLETION_ONSTACK(completion);
3119	int r, i;
3120	unsigned mask;
3121
3122	DSSDBG("Entering ULPS");
3123
3124	WARN_ON(!dsi_bus_is_locked(dsidev));
3125
3126	WARN_ON(dsi->ulps_enabled);
3127
3128	if (dsi->ulps_enabled)
3129		return 0;
3130
3131	/* DDR_CLK_ALWAYS_ON */
3132	if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3133		dsi_if_enable(dsidev, 0);
3134		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3135		dsi_if_enable(dsidev, 1);
3136	}
3137
3138	dsi_sync_vc(dsidev, 0);
3139	dsi_sync_vc(dsidev, 1);
3140	dsi_sync_vc(dsidev, 2);
3141	dsi_sync_vc(dsidev, 3);
3142
3143	dsi_force_tx_stop_mode_io(dsidev);
3144
3145	dsi_vc_enable(dsidev, 0, false);
3146	dsi_vc_enable(dsidev, 1, false);
3147	dsi_vc_enable(dsidev, 2, false);
3148	dsi_vc_enable(dsidev, 3, false);
3149
3150	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {	/* HS_BUSY */
3151		DSSERR("HS busy when enabling ULPS\n");
3152		return -EIO;
3153	}
3154
3155	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {	/* LP_BUSY */
3156		DSSERR("LP busy when enabling ULPS\n");
3157		return -EIO;
3158	}
3159
3160	r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3161			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3162	if (r)
3163		return r;
3164
3165	mask = 0;
3166
3167	for (i = 0; i < dsi->num_lanes_supported; ++i) {
3168		if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3169			continue;
3170		mask |= 1 << i;
3171	}
3172	/* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3173	/* LANEx_ULPS_SIG2 */
3174	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3175
3176	/* flush posted write and wait for SCP interface to finish the write */
3177	dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3178
3179	if (wait_for_completion_timeout(&completion,
3180				msecs_to_jiffies(1000)) == 0) {
3181		DSSERR("ULPS enable timeout\n");
3182		r = -EIO;
3183		goto err;
3184	}
3185
3186	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3187			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3188
3189	/* Reset LANEx_ULPS_SIG2 */
3190	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3191
3192	/* flush posted write and wait for SCP interface to finish the write */
3193	dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3194
3195	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3196
3197	dsi_if_enable(dsidev, false);
3198
3199	dsi->ulps_enabled = true;
3200
3201	return 0;
3202
3203err:
3204	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3205			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3206	return r;
3207}
3208
3209static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3210		unsigned ticks, bool x4, bool x16)
3211{
3212	unsigned long fck;
3213	unsigned long total_ticks;
3214	u32 r;
3215
3216	BUG_ON(ticks > 0x1fff);
3217
3218	/* ticks in DSI_FCK */
3219	fck = dsi_fclk_rate(dsidev);
3220
3221	r = dsi_read_reg(dsidev, DSI_TIMING2);
3222	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */
3223	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* LP_RX_TO_X16 */
3224	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* LP_RX_TO_X4 */
3225	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */
3226	dsi_write_reg(dsidev, DSI_TIMING2, r);
3227
3228	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3229
3230	DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3231			total_ticks,
3232			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3233			(total_ticks * 1000) / (fck / 1000 / 1000));
3234}
3235
3236static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3237		bool x8, bool x16)
3238{
3239	unsigned long fck;
3240	unsigned long total_ticks;
3241	u32 r;
3242
3243	BUG_ON(ticks > 0x1fff);
3244
3245	/* ticks in DSI_FCK */
3246	fck = dsi_fclk_rate(dsidev);
3247
3248	r = dsi_read_reg(dsidev, DSI_TIMING1);
3249	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */
3250	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* TA_TO_X16 */
3251	r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);	/* TA_TO_X8 */
3252	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */
3253	dsi_write_reg(dsidev, DSI_TIMING1, r);
3254
3255	total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3256
3257	DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3258			total_ticks,
3259			ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3260			(total_ticks * 1000) / (fck / 1000 / 1000));
3261}
3262
3263static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3264		unsigned ticks, bool x4, bool x16)
3265{
3266	unsigned long fck;
3267	unsigned long total_ticks;
3268	u32 r;
3269
3270	BUG_ON(ticks > 0x1fff);
3271
3272	/* ticks in DSI_FCK */
3273	fck = dsi_fclk_rate(dsidev);
3274
3275	r = dsi_read_reg(dsidev, DSI_TIMING1);
3276	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
3277	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* STOP_STATE_X16_IO */
3278	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* STOP_STATE_X4_IO */
3279	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */
3280	dsi_write_reg(dsidev, DSI_TIMING1, r);
3281
3282	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3283
3284	DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3285			total_ticks,
3286			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3287			(total_ticks * 1000) / (fck / 1000 / 1000));
3288}
3289
3290static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3291		unsigned ticks, bool x4, bool x16)
3292{
3293	unsigned long fck;
3294	unsigned long total_ticks;
3295	u32 r;
3296
3297	BUG_ON(ticks > 0x1fff);
3298
3299	/* ticks in TxByteClkHS */
3300	fck = dsi_get_txbyteclkhs(dsidev);
3301
3302	r = dsi_read_reg(dsidev, DSI_TIMING2);
3303	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */
3304	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* HS_TX_TO_X16 */
3305	r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);	/* HS_TX_TO_X8 (4 really) */
3306	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */
3307	dsi_write_reg(dsidev, DSI_TIMING2, r);
3308
3309	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3310
3311	DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3312			total_ticks,
3313			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3314			(total_ticks * 1000) / (fck / 1000 / 1000));
3315}
3316
3317static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3318{
3319	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3320	int num_line_buffers;
3321
3322	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3323		int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3324		struct videomode *vm = &dsi->vm;
3325		/*
3326		 * Don't use line buffers if width is greater than the video
3327		 * port's line buffer size
3328		 */
3329		if (dsi->line_buffer_size <= vm->hactive * bpp / 8)
3330			num_line_buffers = 0;
3331		else
3332			num_line_buffers = 2;
3333	} else {
3334		/* Use maximum number of line buffers in command mode */
3335		num_line_buffers = 2;
3336	}
3337
3338	/* LINE_BUFFER */
3339	REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3340}
3341
3342static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3343{
3344	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3345	bool sync_end;
3346	u32 r;
3347
3348	if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3349		sync_end = true;
3350	else
3351		sync_end = false;
3352
3353	r = dsi_read_reg(dsidev, DSI_CTRL);
3354	r = FLD_MOD(r, 1, 9, 9);		/* VP_DE_POL */
3355	r = FLD_MOD(r, 1, 10, 10);		/* VP_HSYNC_POL */
3356	r = FLD_MOD(r, 1, 11, 11);		/* VP_VSYNC_POL */
3357	r = FLD_MOD(r, 1, 15, 15);		/* VP_VSYNC_START */
3358	r = FLD_MOD(r, sync_end, 16, 16);	/* VP_VSYNC_END */
3359	r = FLD_MOD(r, 1, 17, 17);		/* VP_HSYNC_START */
3360	r = FLD_MOD(r, sync_end, 18, 18);	/* VP_HSYNC_END */
3361	dsi_write_reg(dsidev, DSI_CTRL, r);
3362}
3363
3364static void dsi_config_blanking_modes(struct platform_device *dsidev)
3365{
3366	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3367	int blanking_mode = dsi->vm_timings.blanking_mode;
3368	int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3369	int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3370	int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3371	u32 r;
3372
3373	/*
3374	 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3375	 * 1 = Long blanking packets are sent in corresponding blanking periods
3376	 */
3377	r = dsi_read_reg(dsidev, DSI_CTRL);
3378	r = FLD_MOD(r, blanking_mode, 20, 20);		/* BLANKING_MODE */
3379	r = FLD_MOD(r, hfp_blanking_mode, 21, 21);	/* HFP_BLANKING */
3380	r = FLD_MOD(r, hbp_blanking_mode, 22, 22);	/* HBP_BLANKING */
3381	r = FLD_MOD(r, hsa_blanking_mode, 23, 23);	/* HSA_BLANKING */
3382	dsi_write_reg(dsidev, DSI_CTRL, r);
3383}
3384
3385/*
3386 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3387 * results in maximum transition time for data and clock lanes to enter and
3388 * exit HS mode. Hence, this is the scenario where the least amount of command
3389 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3390 * clock cycles that can be used to interleave command mode data in HS so that
3391 * all scenarios are satisfied.
3392 */
3393static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3394		int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3395{
3396	int transition;
3397
3398	/*
3399	 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3400	 * time of data lanes only, if it isn't set, we need to consider HS
3401	 * transition time of both data and clock lanes. HS transition time
3402	 * of Scenario 3 is considered.
3403	 */
3404	if (ddr_alwon) {
3405		transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3406	} else {
3407		int trans1, trans2;
3408		trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3409		trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3410				enter_hs + 1;
3411		transition = max(trans1, trans2);
3412	}
3413
3414	return blank > transition ? blank - transition : 0;
3415}
3416
3417/*
3418 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3419 * results in maximum transition time for data lanes to enter and exit LP mode.
3420 * Hence, this is the scenario where the least amount of command mode data can
3421 * be interleaved. We program the minimum amount of bytes that can be
3422 * interleaved in LP so that all scenarios are satisfied.
3423 */
3424static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3425		int lp_clk_div, int tdsi_fclk)
3426{
3427	int trans_lp;	/* time required for a LP transition, in TXBYTECLKHS */
3428	int tlp_avail;	/* time left for interleaving commands, in CLKIN4DDR */
3429	int ttxclkesc;	/* period of LP transmit escape clock, in CLKIN4DDR */
3430	int thsbyte_clk = 16;	/* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3431	int lp_inter;	/* cmd mode data that can be interleaved, in bytes */
3432
3433	/* maximum LP transition time according to Scenario 1 */
3434	trans_lp = exit_hs + max(enter_hs, 2) + 1;
3435
3436	/* CLKIN4DDR = 16 * TXBYTECLKHS */
3437	tlp_avail = thsbyte_clk * (blank - trans_lp);
3438
3439	ttxclkesc = tdsi_fclk * lp_clk_div;
3440
3441	lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3442			26) / 16;
3443
3444	return max(lp_inter, 0);
3445}
3446
3447static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3448{
3449	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3450	int blanking_mode;
3451	int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3452	int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3453	int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3454	int tclk_trail, ths_exit, exiths_clk;
3455	bool ddr_alwon;
3456	struct videomode *vm = &dsi->vm;
3457	int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3458	int ndl = dsi->num_lanes_used - 1;
3459	int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3460	int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3461	int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3462	int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3463	int bl_interleave_hs = 0, bl_interleave_lp = 0;
3464	u32 r;
3465
3466	r = dsi_read_reg(dsidev, DSI_CTRL);
3467	blanking_mode = FLD_GET(r, 20, 20);
3468	hfp_blanking_mode = FLD_GET(r, 21, 21);
3469	hbp_blanking_mode = FLD_GET(r, 22, 22);
3470	hsa_blanking_mode = FLD_GET(r, 23, 23);
3471
3472	r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3473	hbp = FLD_GET(r, 11, 0);
3474	hfp = FLD_GET(r, 23, 12);
3475	hsa = FLD_GET(r, 31, 24);
3476
3477	r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3478	ddr_clk_post = FLD_GET(r, 7, 0);
3479	ddr_clk_pre = FLD_GET(r, 15, 8);
3480
3481	r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3482	exit_hs_mode_lat = FLD_GET(r, 15, 0);
3483	enter_hs_mode_lat = FLD_GET(r, 31, 16);
3484
3485	r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3486	lp_clk_div = FLD_GET(r, 12, 0);
3487	ddr_alwon = FLD_GET(r, 13, 13);
3488
3489	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3490	ths_exit = FLD_GET(r, 7, 0);
3491
3492	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3493	tclk_trail = FLD_GET(r, 15, 8);
3494
3495	exiths_clk = ths_exit + tclk_trail;
3496
3497	width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3498	bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3499
3500	if (!hsa_blanking_mode) {
3501		hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3502					enter_hs_mode_lat, exit_hs_mode_lat,
3503					exiths_clk, ddr_clk_pre, ddr_clk_post);
3504		hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3505					enter_hs_mode_lat, exit_hs_mode_lat,
3506					lp_clk_div, dsi_fclk_hsdiv);
3507	}
3508
3509	if (!hfp_blanking_mode) {
3510		hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3511					enter_hs_mode_lat, exit_hs_mode_lat,
3512					exiths_clk, ddr_clk_pre, ddr_clk_post);
3513		hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3514					enter_hs_mode_lat, exit_hs_mode_lat,
3515					lp_clk_div, dsi_fclk_hsdiv);
3516	}
3517
3518	if (!hbp_blanking_mode) {
3519		hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3520					enter_hs_mode_lat, exit_hs_mode_lat,
3521					exiths_clk, ddr_clk_pre, ddr_clk_post);
3522
3523		hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3524					enter_hs_mode_lat, exit_hs_mode_lat,
3525					lp_clk_div, dsi_fclk_hsdiv);
3526	}
3527
3528	if (!blanking_mode) {
3529		bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3530					enter_hs_mode_lat, exit_hs_mode_lat,
3531					exiths_clk, ddr_clk_pre, ddr_clk_post);
3532
3533		bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3534					enter_hs_mode_lat, exit_hs_mode_lat,
3535					lp_clk_div, dsi_fclk_hsdiv);
3536	}
3537
3538	DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3539		hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3540		bl_interleave_hs);
3541
3542	DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3543		hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3544		bl_interleave_lp);
3545
3546	r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3547	r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3548	r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3549	r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3550	dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3551
3552	r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3553	r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3554	r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3555	r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3556	dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3557
3558	r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3559	r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3560	r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3561	dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3562}
3563
3564static int dsi_proto_config(struct platform_device *dsidev)
3565{
3566	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3567	u32 r;
3568	int buswidth = 0;
3569
3570	dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3571			DSI_FIFO_SIZE_32,
3572			DSI_FIFO_SIZE_32,
3573			DSI_FIFO_SIZE_32);
3574
3575	dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3576			DSI_FIFO_SIZE_32,
3577			DSI_FIFO_SIZE_32,
3578			DSI_FIFO_SIZE_32);
3579
3580	/* XXX what values for the timeouts? */
3581	dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3582	dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3583	dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3584	dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3585
3586	switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3587	case 16:
3588		buswidth = 0;
3589		break;
3590	case 18:
3591		buswidth = 1;
3592		break;
3593	case 24:
3594		buswidth = 2;
3595		break;
3596	default:
3597		BUG();
3598		return -EINVAL;
3599	}
3600
3601	r = dsi_read_reg(dsidev, DSI_CTRL);
3602	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
3603	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
3604	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
3605	r = FLD_MOD(r, 1, 4, 4);	/* VP_CLK_RATIO, always 1, see errata*/
3606	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3607	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
3608	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */
3609	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */
3610	if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3611		r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */
3612		/* DCS_CMD_CODE, 1=start, 0=continue */
3613		r = FLD_MOD(r, 0, 25, 25);
3614	}
3615
3616	dsi_write_reg(dsidev, DSI_CTRL, r);
3617
3618	dsi_config_vp_num_line_buffers(dsidev);
3619
3620	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3621		dsi_config_vp_sync_events(dsidev);
3622		dsi_config_blanking_modes(dsidev);
3623		dsi_config_cmd_mode_interleaving(dsidev);
3624	}
3625
3626	dsi_vc_initial_config(dsidev, 0);
3627	dsi_vc_initial_config(dsidev, 1);
3628	dsi_vc_initial_config(dsidev, 2);
3629	dsi_vc_initial_config(dsidev, 3);
3630
3631	return 0;
3632}
3633
3634static void dsi_proto_timings(struct platform_device *dsidev)
3635{
3636	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3637	unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3638	unsigned tclk_pre, tclk_post;
3639	unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3640	unsigned ths_trail, ths_exit;
3641	unsigned ddr_clk_pre, ddr_clk_post;
3642	unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3643	unsigned ths_eot;
3644	int ndl = dsi->num_lanes_used - 1;
3645	u32 r;
3646
3647	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3648	ths_prepare = FLD_GET(r, 31, 24);
3649	ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3650	ths_zero = ths_prepare_ths_zero - ths_prepare;
3651	ths_trail = FLD_GET(r, 15, 8);
3652	ths_exit = FLD_GET(r, 7, 0);
3653
3654	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3655	tlpx = FLD_GET(r, 20, 16) * 2;
3656	tclk_trail = FLD_GET(r, 15, 8);
3657	tclk_zero = FLD_GET(r, 7, 0);
3658
3659	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3660	tclk_prepare = FLD_GET(r, 7, 0);
3661
3662	/* min 8*UI */
3663	tclk_pre = 20;
3664	/* min 60ns + 52*UI */
3665	tclk_post = ns2ddr(dsidev, 60) + 26;
3666
3667	ths_eot = DIV_ROUND_UP(4, ndl);
3668
3669	ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3670			4);
3671	ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3672
3673	BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3674	BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3675
3676	r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3677	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3678	r = FLD_MOD(r, ddr_clk_post, 7, 0);
3679	dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3680
3681	DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3682			ddr_clk_pre,
3683			ddr_clk_post);
3684
3685	enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3686		DIV_ROUND_UP(ths_prepare, 4) +
3687		DIV_ROUND_UP(ths_zero + 3, 4);
3688
3689	exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3690
3691	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3692		FLD_VAL(exit_hs_mode_lat, 15, 0);
3693	dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3694
3695	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3696			enter_hs_mode_lat, exit_hs_mode_lat);
3697
3698	 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3699		/* TODO: Implement a video mode check_timings function */
3700		int hsa = dsi->vm_timings.hsa;
3701		int hfp = dsi->vm_timings.hfp;
3702		int hbp = dsi->vm_timings.hbp;
3703		int vsa = dsi->vm_timings.vsa;
3704		int vfp = dsi->vm_timings.vfp;
3705		int vbp = dsi->vm_timings.vbp;
3706		int window_sync = dsi->vm_timings.window_sync;
3707		bool hsync_end;
3708		struct videomode *vm = &dsi->vm;
3709		int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3710		int tl, t_he, width_bytes;
3711
3712		hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3713		t_he = hsync_end ?
3714			((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3715
3716		width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3717
3718		/* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3719		tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3720			DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3721
3722		DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3723			hfp, hsync_end ? hsa : 0, tl);
3724		DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3725			vsa, vm->vactive);
3726
3727		r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3728		r = FLD_MOD(r, hbp, 11, 0);	/* HBP */
3729		r = FLD_MOD(r, hfp, 23, 12);	/* HFP */
3730		r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);	/* HSA */
3731		dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3732
3733		r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3734		r = FLD_MOD(r, vbp, 7, 0);	/* VBP */
3735		r = FLD_MOD(r, vfp, 15, 8);	/* VFP */
3736		r = FLD_MOD(r, vsa, 23, 16);	/* VSA */
3737		r = FLD_MOD(r, window_sync, 27, 24);	/* WINDOW_SYNC */
3738		dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3739
3740		r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3741		r = FLD_MOD(r, vm->vactive, 14, 0);	/* VACT */
3742		r = FLD_MOD(r, tl, 31, 16);		/* TL */
3743		dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3744	}
3745}
3746
3747static int dsi_configure_pins(struct omap_dss_device *dssdev,
3748		const struct omap_dsi_pin_config *pin_cfg)
3749{
3750	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3751	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3752	int num_pins;
3753	const int *pins;
3754	struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3755	int num_lanes;
3756	int i;
3757
3758	static const enum dsi_lane_function functions[] = {
3759		DSI_LANE_CLK,
3760		DSI_LANE_DATA1,
3761		DSI_LANE_DATA2,
3762		DSI_LANE_DATA3,
3763		DSI_LANE_DATA4,
3764	};
3765
3766	num_pins = pin_cfg->num_pins;
3767	pins = pin_cfg->pins;
3768
3769	if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3770			|| num_pins % 2 != 0)
3771		return -EINVAL;
3772
3773	for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3774		lanes[i].function = DSI_LANE_UNUSED;
3775
3776	num_lanes = 0;
3777
3778	for (i = 0; i < num_pins; i += 2) {
3779		u8 lane, pol;
3780		int dx, dy;
3781
3782		dx = pins[i];
3783		dy = pins[i + 1];
3784
3785		if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3786			return -EINVAL;
3787
3788		if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3789			return -EINVAL;
3790
3791		if (dx & 1) {
3792			if (dy != dx - 1)
3793				return -EINVAL;
3794			pol = 1;
3795		} else {
3796			if (dy != dx + 1)
3797				return -EINVAL;
3798			pol = 0;
3799		}
3800
3801		lane = dx / 2;
3802
3803		lanes[lane].function = functions[i / 2];
3804		lanes[lane].polarity = pol;
3805		num_lanes++;
3806	}
3807
3808	memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3809	dsi->num_lanes_used = num_lanes;
3810
3811	return 0;
3812}
3813
3814static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3815{
3816	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3817	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3818	enum omap_channel dispc_channel = dssdev->dispc_channel;
3819	int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3820	struct omap_dss_device *out = &dsi->output;
3821	u8 data_type;
3822	u16 word_count;
3823	int r;
3824
3825	if (!out->dispc_channel_connected) {
3826		DSSERR("failed to enable display: no output/manager\n");
3827		return -ENODEV;
 
 
 
 
 
 
 
 
 
 
 
 
3828	}
3829
3830	r = dsi_display_init_dispc(dsidev, dispc_channel);
3831	if (r)
3832		goto err_init_dispc;
3833
3834	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3835		switch (dsi->pix_fmt) {
3836		case OMAP_DSS_DSI_FMT_RGB888:
3837			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3838			break;
3839		case OMAP_DSS_DSI_FMT_RGB666:
3840			data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3841			break;
3842		case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3843			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3844			break;
3845		case OMAP_DSS_DSI_FMT_RGB565:
3846			data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3847			break;
3848		default:
3849			r = -EINVAL;
3850			goto err_pix_fmt;
3851		}
3852
3853		dsi_if_enable(dsidev, false);
3854		dsi_vc_enable(dsidev, channel, false);
 
 
3855
3856		/* MODE, 1 = video mode */
3857		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3858
3859		word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
 
 
3860
3861		dsi_vc_write_long_header(dsidev, channel, data_type,
3862				word_count, 0);
 
 
3863
3864		dsi_vc_enable(dsidev, channel, true);
3865		dsi_if_enable(dsidev, true);
 
 
3866	}
3867
3868	r = dss_mgr_enable(dispc_channel);
 
 
 
 
 
 
3869	if (r)
3870		goto err_mgr_enable;
3871
3872	return 0;
3873
3874err_mgr_enable:
3875	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3876		dsi_if_enable(dsidev, false);
3877		dsi_vc_enable(dsidev, channel, false);
3878	}
3879err_pix_fmt:
3880	dsi_display_uninit_dispc(dsidev, dispc_channel);
3881err_init_dispc:
3882	return r;
3883}
3884
3885static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3886{
3887	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3888	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3889	enum omap_channel dispc_channel = dssdev->dispc_channel;
3890
3891	if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3892		dsi_if_enable(dsidev, false);
3893		dsi_vc_enable(dsidev, channel, false);
3894
3895		/* MODE, 0 = command mode */
3896		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
3897
3898		dsi_vc_enable(dsidev, channel, true);
3899		dsi_if_enable(dsidev, true);
3900	}
3901
3902	dss_mgr_disable(dispc_channel);
3903
3904	dsi_display_uninit_dispc(dsidev, dispc_channel);
3905}
3906
3907static void dsi_update_screen_dispc(struct platform_device *dsidev)
3908{
3909	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3910	enum omap_channel dispc_channel = dsi->output.dispc_channel;
3911	unsigned bytespp;
3912	unsigned bytespl;
3913	unsigned bytespf;
3914	unsigned total_len;
3915	unsigned packet_payload;
3916	unsigned packet_len;
3917	u32 l;
3918	int r;
3919	const unsigned channel = dsi->update_channel;
3920	const unsigned line_buf_size = dsi->line_buffer_size;
3921	u16 w = dsi->vm.hactive;
3922	u16 h = dsi->vm.vactive;
3923
3924	DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3925
3926	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
3927
3928	bytespp	= dsi_get_pixel_size(dsi->pix_fmt) / 8;
3929	bytespl = w * bytespp;
3930	bytespf = bytespl * h;
3931
3932	/* NOTE: packet_payload has to be equal to N * bytespl, where N is
3933	 * number of lines in a packet.  See errata about VP_CLK_RATIO */
3934
3935	if (bytespf < line_buf_size)
3936		packet_payload = bytespf;
3937	else
3938		packet_payload = (line_buf_size) / bytespl * bytespl;
3939
3940	packet_len = packet_payload + 1;	/* 1 byte for DCS cmd */
3941	total_len = (bytespf / packet_payload) * packet_len;
3942
3943	if (bytespf % packet_payload)
3944		total_len += (bytespf % packet_payload) + 1;
3945
3946	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3947	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3948
3949	dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
3950		packet_len, 0);
3951
3952	if (dsi->te_enabled)
3953		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3954	else
3955		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3956	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3957
3958	/* We put SIDLEMODE to no-idle for the duration of the transfer,
3959	 * because DSS interrupts are not capable of waking up the CPU and the
3960	 * framedone interrupt could be delayed for quite a long time. I think
3961	 * the same goes for any DSS interrupts, but for some reason I have not
3962	 * seen the problem anywhere else than here.
3963	 */
3964	dispc_disable_sidle();
3965
3966	dsi_perf_mark_start(dsidev);
3967
3968	r = schedule_delayed_work(&dsi->framedone_timeout_work,
3969		msecs_to_jiffies(250));
3970	BUG_ON(r == 0);
3971
3972	dss_mgr_set_timings(dispc_channel, &dsi->vm);
3973
3974	dss_mgr_start_update(dispc_channel);
3975
3976	if (dsi->te_enabled) {
3977		/* disable LP_RX_TO, so that we can receive TE.  Time to wait
3978		 * for TE is longer than the timer allows */
3979		REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3980
3981		dsi_vc_send_bta(dsidev, channel);
3982
3983#ifdef DSI_CATCH_MISSING_TE
3984		mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3985#endif
3986	}
3987}
3988
3989#ifdef DSI_CATCH_MISSING_TE
3990static void dsi_te_timeout(unsigned long arg)
3991{
3992	DSSERR("TE not received for 250ms!\n");
3993}
3994#endif
3995
3996static void dsi_handle_framedone(struct platform_device *dsidev, int error)
3997{
3998	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3999
4000	/* SIDLEMODE back to smart-idle */
4001	dispc_enable_sidle();
4002
4003	if (dsi->te_enabled) {
4004		/* enable LP_RX_TO again after the TE */
4005		REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4006	}
4007
4008	dsi->framedone_callback(error, dsi->framedone_data);
4009
4010	if (!error)
4011		dsi_perf_show(dsidev, "DISPC");
4012}
4013
4014static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4015{
4016	struct dsi_data *dsi = container_of(work, struct dsi_data,
4017			framedone_timeout_work.work);
4018	/* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4019	 * 250ms which would conflict with this timeout work. What should be
4020	 * done is first cancel the transfer on the HW, and then cancel the
4021	 * possibly scheduled framedone work. However, cancelling the transfer
4022	 * on the HW is buggy, and would probably require resetting the whole
4023	 * DSI */
4024
4025	DSSERR("Framedone not received for 250ms!\n");
4026
4027	dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4028}
4029
4030static void dsi_framedone_irq_callback(void *data)
4031{
4032	struct platform_device *dsidev = (struct platform_device *) data;
4033	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4034
4035	/* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4036	 * turns itself off. However, DSI still has the pixels in its buffers,
4037	 * and is sending the data.
4038	 */
4039
4040	cancel_delayed_work(&dsi->framedone_timeout_work);
4041
4042	dsi_handle_framedone(dsidev, 0);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4043}
4044
4045static int dsi_update(struct omap_dss_device *dssdev, int channel,
4046		void (*callback)(int, void *), void *data)
4047{
4048	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4049	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4050	u16 dw, dh;
 
 
 
 
4051
4052	dsi_perf_mark_setup(dsidev);
4053
4054	dsi->update_channel = channel;
 
4055
4056	dsi->framedone_callback = callback;
4057	dsi->framedone_data = data;
 
 
4058
4059	dw = dsi->vm.hactive;
4060	dh = dsi->vm.vactive;
4061
4062#ifdef DSI_PERF_MEASURE
4063	dsi->update_bytes = dw * dh *
4064		dsi_get_pixel_size(dsi->pix_fmt) / 8;
4065#endif
4066	dsi_update_screen_dispc(dsidev);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4067
4068	return 0;
 
 
 
 
 
 
 
 
 
4069}
4070
4071/* Display funcs */
4072
4073static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4074{
4075	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4076	struct dispc_clock_info dispc_cinfo;
4077	int r;
4078	unsigned long fck;
4079
4080	fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4081
4082	dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4083	dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4084
4085	r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4086	if (r) {
4087		DSSERR("Failed to calc dispc clocks\n");
4088		return r;
4089	}
4090
4091	dsi->mgr_config.clock_info = dispc_cinfo;
4092
4093	return 0;
4094}
4095
4096static int dsi_display_init_dispc(struct platform_device *dsidev,
4097		enum omap_channel channel)
4098{
4099	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4100	int r;
4101
4102	dss_select_lcd_clk_source(channel, dsi->module_id == 0 ?
4103			DSS_CLK_SRC_PLL1_1 :
4104			DSS_CLK_SRC_PLL2_1);
4105
4106	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4107		r = dss_mgr_register_framedone_handler(channel,
4108				dsi_framedone_irq_callback, dsidev);
4109		if (r) {
4110			DSSERR("can't register FRAMEDONE handler\n");
4111			goto err;
4112		}
4113
4114		dsi->mgr_config.stallmode = true;
4115		dsi->mgr_config.fifohandcheck = true;
4116	} else {
4117		dsi->mgr_config.stallmode = false;
4118		dsi->mgr_config.fifohandcheck = false;
4119	}
4120
4121	/*
4122	 * override interlace, logic level and edge related parameters in
4123	 * videomode with default values
4124	 */
4125	dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
4126	dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
4127	dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
4128	dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
4129	dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
4130	dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
4131	dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
4132	dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
4133	dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH;
4134	dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4135	dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4136
4137	dss_mgr_set_timings(channel, &dsi->vm);
4138
4139	r = dsi_configure_dispc_clocks(dsidev);
4140	if (r)
4141		goto err1;
4142
4143	dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4144	dsi->mgr_config.video_port_width =
4145			dsi_get_pixel_size(dsi->pix_fmt);
4146	dsi->mgr_config.lcden_sig_polarity = 0;
4147
4148	dss_mgr_set_lcd_config(channel, &dsi->mgr_config);
4149
4150	return 0;
4151err1:
4152	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4153		dss_mgr_unregister_framedone_handler(channel,
4154				dsi_framedone_irq_callback, dsidev);
4155err:
4156	dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK);
4157	return r;
4158}
4159
4160static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4161		enum omap_channel channel)
4162{
4163	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4164
4165	if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4166		dss_mgr_unregister_framedone_handler(channel,
4167				dsi_framedone_irq_callback, dsidev);
4168
4169	dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK);
4170}
4171
4172static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4173{
4174	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4175	struct dss_pll_clock_info cinfo;
4176	int r;
4177
4178	cinfo = dsi->user_dsi_cinfo;
4179
4180	r = dss_pll_set_config(&dsi->pll, &cinfo);
4181	if (r) {
4182		DSSERR("Failed to set dsi clocks\n");
4183		return r;
4184	}
4185
4186	return 0;
4187}
4188
4189static int dsi_display_init_dsi(struct platform_device *dsidev)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4190{
4191	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4192	int r;
4193
4194	r = dss_pll_enable(&dsi->pll);
4195	if (r)
4196		goto err0;
4197
4198	r = dsi_configure_dsi_clocks(dsidev);
4199	if (r)
4200		goto err1;
4201
4202	dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4203			DSS_CLK_SRC_PLL1_2 :
4204			DSS_CLK_SRC_PLL2_2);
4205
4206	DSSDBG("PLL OK\n");
4207
4208	r = dsi_cio_init(dsidev);
 
 
 
 
 
 
 
 
4209	if (r)
4210		goto err2;
4211
4212	_dsi_print_reset_status(dsidev);
4213
4214	dsi_proto_timings(dsidev);
4215	dsi_set_lp_clk_divisor(dsidev);
4216
4217	if (1)
4218		_dsi_print_reset_status(dsidev);
4219
4220	r = dsi_proto_config(dsidev);
4221	if (r)
4222		goto err3;
4223
4224	/* enable interface */
4225	dsi_vc_enable(dsidev, 0, 1);
4226	dsi_vc_enable(dsidev, 1, 1);
4227	dsi_vc_enable(dsidev, 2, 1);
4228	dsi_vc_enable(dsidev, 3, 1);
4229	dsi_if_enable(dsidev, 1);
4230	dsi_force_tx_stop_mode_io(dsidev);
4231
4232	return 0;
4233err3:
4234	dsi_cio_uninit(dsidev);
4235err2:
4236	dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK);
 
4237err1:
4238	dss_pll_disable(&dsi->pll);
4239err0:
 
 
4240	return r;
4241}
4242
4243static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4244		bool disconnect_lanes, bool enter_ulps)
4245{
4246	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4247
4248	if (enter_ulps && !dsi->ulps_enabled)
4249		dsi_enter_ulps(dsidev);
4250
4251	/* disable interface */
4252	dsi_if_enable(dsidev, 0);
4253	dsi_vc_enable(dsidev, 0, 0);
4254	dsi_vc_enable(dsidev, 1, 0);
4255	dsi_vc_enable(dsidev, 2, 0);
4256	dsi_vc_enable(dsidev, 3, 0);
4257
4258	dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK);
4259	dsi_cio_uninit(dsidev);
4260	dsi_pll_uninit(dsidev, disconnect_lanes);
 
 
 
4261}
4262
4263static int dsi_display_enable(struct omap_dss_device *dssdev)
4264{
4265	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4266	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4267	int r = 0;
4268
4269	DSSDBG("dsi_display_enable\n");
4270
4271	WARN_ON(!dsi_bus_is_locked(dsidev));
 
4272
4273	mutex_lock(&dsi->lock);
4274
4275	r = dsi_runtime_get(dsidev);
4276	if (r)
4277		goto err_get_dsi;
4278
4279	_dsi_initialize_irq(dsidev);
4280
4281	r = dsi_display_init_dsi(dsidev);
4282	if (r)
4283		goto err_init_dsi;
4284
 
 
4285	mutex_unlock(&dsi->lock);
4286
4287	return 0;
4288
4289err_init_dsi:
4290	dsi_runtime_put(dsidev);
4291err_get_dsi:
4292	mutex_unlock(&dsi->lock);
4293	DSSDBG("dsi_display_enable FAILED\n");
4294	return r;
4295}
4296
4297static void dsi_display_disable(struct omap_dss_device *dssdev,
4298		bool disconnect_lanes, bool enter_ulps)
4299{
4300	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4301	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4302
4303	DSSDBG("dsi_display_disable\n");
4304
4305	WARN_ON(!dsi_bus_is_locked(dsidev));
4306
4307	mutex_lock(&dsi->lock);
4308
4309	dsi_sync_vc(dsidev, 0);
4310	dsi_sync_vc(dsidev, 1);
4311	dsi_sync_vc(dsidev, 2);
4312	dsi_sync_vc(dsidev, 3);
4313
4314	dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4315
4316	dsi_runtime_put(dsidev);
 
 
4317
4318	mutex_unlock(&dsi->lock);
4319}
4320
4321static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4322{
4323	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4324	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4325
4326	dsi->te_enabled = enable;
 
 
 
 
 
 
 
 
4327	return 0;
4328}
4329
4330#ifdef PRINT_VERBOSE_VM_TIMINGS
4331static void print_dsi_vm(const char *str,
4332		const struct omap_dss_dsi_videomode_timings *t)
4333{
4334	unsigned long byteclk = t->hsclk / 4;
4335	int bl, wc, pps, tot;
4336
4337	wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4338	pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4339	bl = t->hss + t->hsa + t->hse + t->hbp + t->hfront_porch;
4340	tot = bl + pps;
4341
4342#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4343
4344	pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4345			"%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4346			str,
4347			byteclk,
4348			t->hss, t->hsa, t->hse, t->hbp, pps, t->hfront_porch,
4349			bl, pps, tot,
4350			TO_DSI_T(t->hss),
4351			TO_DSI_T(t->hsa),
4352			TO_DSI_T(t->hse),
4353			TO_DSI_T(t->hbp),
4354			TO_DSI_T(pps),
4355			TO_DSI_T(t->hfront_porch),
4356
4357			TO_DSI_T(bl),
4358			TO_DSI_T(pps),
4359
4360			TO_DSI_T(tot));
4361#undef TO_DSI_T
4362}
4363
4364static void print_dispc_vm(const char *str, const struct videomode *vm)
4365{
4366	unsigned long pck = vm->pixelclock;
4367	int hact, bl, tot;
4368
4369	hact = vm->hactive;
4370	bl = vm->hsync_len + vm->hbp + vm->hfront_porch;
4371	tot = hact + bl;
4372
4373#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4374
4375	pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4376			"%u/%u/%u/%u = %u + %u = %u\n",
4377			str,
4378			pck,
4379			vm->hsync_len, vm->hbp, hact, vm->hfront_porch,
4380			bl, hact, tot,
4381			TO_DISPC_T(vm->hsync_len),
4382			TO_DISPC_T(vm->hbp),
4383			TO_DISPC_T(hact),
4384			TO_DISPC_T(vm->hfront_porch),
4385			TO_DISPC_T(bl),
4386			TO_DISPC_T(hact),
4387			TO_DISPC_T(tot));
4388#undef TO_DISPC_T
4389}
4390
4391/* note: this is not quite accurate */
4392static void print_dsi_dispc_vm(const char *str,
4393		const struct omap_dss_dsi_videomode_timings *t)
4394{
4395	struct videomode vm = { 0 };
4396	unsigned long byteclk = t->hsclk / 4;
4397	unsigned long pck;
4398	u64 dsi_tput;
4399	int dsi_hact, dsi_htot;
4400
4401	dsi_tput = (u64)byteclk * t->ndl * 8;
4402	pck = (u32)div64_u64(dsi_tput, t->bitspp);
4403	dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4404	dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfront_porch;
4405
4406	vm.pixelclock = pck;
4407	vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4408	vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4409	vm.hfront_porch = div64_u64((u64)t->hfront_porch * pck, byteclk);
4410	vm.hactive = t->hact;
4411
4412	print_dispc_vm(str, &vm);
4413}
4414#endif /* PRINT_VERBOSE_VM_TIMINGS */
4415
4416static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4417		unsigned long pck, void *data)
4418{
4419	struct dsi_clk_calc_ctx *ctx = data;
4420	struct videomode *vm = &ctx->vm;
4421
4422	ctx->dispc_cinfo.lck_div = lckd;
4423	ctx->dispc_cinfo.pck_div = pckd;
4424	ctx->dispc_cinfo.lck = lck;
4425	ctx->dispc_cinfo.pck = pck;
4426
4427	*vm = *ctx->config->vm;
4428	vm->pixelclock = pck;
4429	vm->hactive = ctx->config->vm->hactive;
4430	vm->vactive = ctx->config->vm->vactive;
4431	vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1;
4432	vm->vfront_porch = vm->vback_porch = 0;
4433
4434	return true;
4435}
4436
4437static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4438		void *data)
4439{
4440	struct dsi_clk_calc_ctx *ctx = data;
4441
4442	ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4443	ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4444
4445	return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4446			dsi_cm_calc_dispc_cb, ctx);
 
4447}
4448
4449static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4450		unsigned long clkdco, void *data)
4451{
4452	struct dsi_clk_calc_ctx *ctx = data;
 
4453
4454	ctx->dsi_cinfo.n = n;
4455	ctx->dsi_cinfo.m = m;
4456	ctx->dsi_cinfo.fint = fint;
4457	ctx->dsi_cinfo.clkdco = clkdco;
4458
4459	return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4460			dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4461			dsi_cm_calc_hsdiv_cb, ctx);
4462}
4463
4464static bool dsi_cm_calc(struct dsi_data *dsi,
4465		const struct omap_dss_dsi_config *cfg,
4466		struct dsi_clk_calc_ctx *ctx)
4467{
4468	unsigned long clkin;
4469	int bitspp, ndl;
4470	unsigned long pll_min, pll_max;
4471	unsigned long pck, txbyteclk;
4472
4473	clkin = clk_get_rate(dsi->pll.clkin);
4474	bitspp = dsi_get_pixel_size(cfg->pixel_format);
4475	ndl = dsi->num_lanes_used - 1;
4476
4477	/*
4478	 * Here we should calculate minimum txbyteclk to be able to send the
4479	 * frame in time, and also to handle TE. That's not very simple, though,
4480	 * especially as we go to LP between each pixel packet due to HW
4481	 * "feature". So let's just estimate very roughly and multiply by 1.5.
4482	 */
4483	pck = cfg->vm->pixelclock;
4484	pck = pck * 3 / 2;
4485	txbyteclk = pck * bitspp / 8 / ndl;
4486
4487	memset(ctx, 0, sizeof(*ctx));
4488	ctx->dsidev = dsi->pdev;
4489	ctx->pll = &dsi->pll;
4490	ctx->config = cfg;
4491	ctx->req_pck_min = pck;
4492	ctx->req_pck_nom = pck;
4493	ctx->req_pck_max = pck * 3 / 2;
4494
4495	pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4496	pll_max = cfg->hs_clk_max * 4;
4497
4498	return dss_pll_calc_a(ctx->pll, clkin,
4499			pll_min, pll_max,
4500			dsi_cm_calc_pll_cb, ctx);
4501}
4502
4503static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4504{
4505	struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4506	const struct omap_dss_dsi_config *cfg = ctx->config;
4507	int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4508	int ndl = dsi->num_lanes_used - 1;
4509	unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4510	unsigned long byteclk = hsclk / 4;
4511
4512	unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4513	int xres;
4514	int panel_htot, panel_hbl; /* pixels */
4515	int dispc_htot, dispc_hbl; /* pixels */
4516	int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4517	int hfp, hsa, hbp;
4518	const struct videomode *req_vm;
4519	struct videomode *dispc_vm;
4520	struct omap_dss_dsi_videomode_timings *dsi_vm;
4521	u64 dsi_tput, dispc_tput;
4522
4523	dsi_tput = (u64)byteclk * ndl * 8;
4524
4525	req_vm = cfg->vm;
4526	req_pck_min = ctx->req_pck_min;
4527	req_pck_max = ctx->req_pck_max;
4528	req_pck_nom = ctx->req_pck_nom;
4529
4530	dispc_pck = ctx->dispc_cinfo.pck;
4531	dispc_tput = (u64)dispc_pck * bitspp;
4532
4533	xres = req_vm->hactive;
4534
4535	panel_hbl = req_vm->hfront_porch + req_vm->hback_porch +
4536		    req_vm->hsync_len;
4537	panel_htot = xres + panel_hbl;
4538
4539	dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4540
4541	/*
4542	 * When there are no line buffers, DISPC and DSI must have the
4543	 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4544	 */
4545	if (dsi->line_buffer_size < xres * bitspp / 8) {
4546		if (dispc_tput != dsi_tput)
4547			return false;
4548	} else {
4549		if (dispc_tput < dsi_tput)
4550			return false;
4551	}
4552
4553	/* DSI tput must be over the min requirement */
4554	if (dsi_tput < (u64)bitspp * req_pck_min)
4555		return false;
4556
4557	/* When non-burst mode, DSI tput must be below max requirement. */
4558	if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4559		if (dsi_tput > (u64)bitspp * req_pck_max)
4560			return false;
4561	}
4562
4563	hss = DIV_ROUND_UP(4, ndl);
4564
4565	if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4566		if (ndl == 3 && req_vm->hsync_len == 0)
4567			hse = 1;
4568		else
4569			hse = DIV_ROUND_UP(4, ndl);
4570	} else {
4571		hse = 0;
4572	}
4573
4574	/* DSI htot to match the panel's nominal pck */
4575	dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4576
4577	/* fail if there would be no time for blanking */
4578	if (dsi_htot < hss + hse + dsi_hact)
4579		return false;
4580
4581	/* total DSI blanking needed to achieve panel's TL */
4582	dsi_hbl = dsi_htot - dsi_hact;
4583
4584	/* DISPC htot to match the DSI TL */
4585	dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4586
4587	/* verify that the DSI and DISPC TLs are the same */
4588	if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4589		return false;
4590
4591	dispc_hbl = dispc_htot - xres;
4592
4593	/* setup DSI videomode */
4594
4595	dsi_vm = &ctx->dsi_vm;
4596	memset(dsi_vm, 0, sizeof(*dsi_vm));
4597
4598	dsi_vm->hsclk = hsclk;
4599
4600	dsi_vm->ndl = ndl;
4601	dsi_vm->bitspp = bitspp;
4602
4603	if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4604		hsa = 0;
4605	} else if (ndl == 3 && req_vm->hsync_len == 0) {
4606		hsa = 0;
4607	} else {
4608		hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom);
4609		hsa = max(hsa - hse, 1);
4610	}
4611
4612	hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom);
4613	hbp = max(hbp, 1);
4614
4615	hfp = dsi_hbl - (hss + hsa + hse + hbp);
4616	if (hfp < 1) {
4617		int t;
4618		/* we need to take cycles from hbp */
4619
4620		t = 1 - hfp;
4621		hbp = max(hbp - t, 1);
4622		hfp = dsi_hbl - (hss + hsa + hse + hbp);
4623
4624		if (hfp < 1 && hsa > 0) {
4625			/* we need to take cycles from hsa */
4626			t = 1 - hfp;
4627			hsa = max(hsa - t, 1);
4628			hfp = dsi_hbl - (hss + hsa + hse + hbp);
4629		}
4630	}
4631
4632	if (hfp < 1)
4633		return false;
4634
4635	dsi_vm->hss = hss;
4636	dsi_vm->hsa = hsa;
4637	dsi_vm->hse = hse;
4638	dsi_vm->hbp = hbp;
4639	dsi_vm->hact = xres;
4640	dsi_vm->hfp = hfp;
4641
4642	dsi_vm->vsa = req_vm->vsync_len;
4643	dsi_vm->vbp = req_vm->vback_porch;
4644	dsi_vm->vact = req_vm->vactive;
4645	dsi_vm->vfp = req_vm->vfront_porch;
4646
4647	dsi_vm->trans_mode = cfg->trans_mode;
4648
4649	dsi_vm->blanking_mode = 0;
4650	dsi_vm->hsa_blanking_mode = 1;
4651	dsi_vm->hfp_blanking_mode = 1;
4652	dsi_vm->hbp_blanking_mode = 1;
4653
4654	dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4655	dsi_vm->window_sync = 4;
4656
4657	/* setup DISPC videomode */
4658
4659	dispc_vm = &ctx->vm;
4660	*dispc_vm = *req_vm;
4661	dispc_vm->pixelclock = dispc_pck;
4662
4663	if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4664		hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck,
4665				req_pck_nom);
4666		hsa = max(hsa, 1);
4667	} else {
4668		hsa = 1;
4669	}
4670
4671	hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom);
4672	hbp = max(hbp, 1);
4673
4674	hfp = dispc_hbl - hsa - hbp;
4675	if (hfp < 1) {
4676		int t;
4677		/* we need to take cycles from hbp */
4678
4679		t = 1 - hfp;
4680		hbp = max(hbp - t, 1);
4681		hfp = dispc_hbl - hsa - hbp;
4682
4683		if (hfp < 1) {
4684			/* we need to take cycles from hsa */
4685			t = 1 - hfp;
4686			hsa = max(hsa - t, 1);
4687			hfp = dispc_hbl - hsa - hbp;
4688		}
4689	}
4690
4691	if (hfp < 1)
4692		return false;
4693
4694	dispc_vm->hfront_porch = hfp;
4695	dispc_vm->hsync_len = hsa;
4696	dispc_vm->hback_porch = hbp;
4697
4698	return true;
4699}
4700
4701
4702static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4703		unsigned long pck, void *data)
4704{
4705	struct dsi_clk_calc_ctx *ctx = data;
4706
4707	ctx->dispc_cinfo.lck_div = lckd;
4708	ctx->dispc_cinfo.pck_div = pckd;
4709	ctx->dispc_cinfo.lck = lck;
4710	ctx->dispc_cinfo.pck = pck;
4711
4712	if (dsi_vm_calc_blanking(ctx) == false)
4713		return false;
4714
4715#ifdef PRINT_VERBOSE_VM_TIMINGS
4716	print_dispc_vm("dispc", &ctx->vm);
4717	print_dsi_vm("dsi  ", &ctx->dsi_vm);
4718	print_dispc_vm("req  ", ctx->config->vm);
4719	print_dsi_dispc_vm("act  ", &ctx->dsi_vm);
4720#endif
4721
4722	return true;
4723}
4724
4725static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4726		void *data)
4727{
4728	struct dsi_clk_calc_ctx *ctx = data;
4729	unsigned long pck_max;
4730
4731	ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4732	ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4733
4734	/*
4735	 * In burst mode we can let the dispc pck be arbitrarily high, but it
4736	 * limits our scaling abilities. So for now, don't aim too high.
4737	 */
4738
4739	if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4740		pck_max = ctx->req_pck_max + 10000000;
4741	else
4742		pck_max = ctx->req_pck_max;
4743
4744	return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
4745			dsi_vm_calc_dispc_cb, ctx);
 
4746}
4747
4748static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4749		unsigned long clkdco, void *data)
4750{
4751	struct dsi_clk_calc_ctx *ctx = data;
 
4752
4753	ctx->dsi_cinfo.n = n;
4754	ctx->dsi_cinfo.m = m;
4755	ctx->dsi_cinfo.fint = fint;
4756	ctx->dsi_cinfo.clkdco = clkdco;
4757
4758	return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4759			dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
4760			dsi_vm_calc_hsdiv_cb, ctx);
4761}
4762
4763static bool dsi_vm_calc(struct dsi_data *dsi,
4764		const struct omap_dss_dsi_config *cfg,
4765		struct dsi_clk_calc_ctx *ctx)
4766{
4767	const struct videomode *vm = cfg->vm;
4768	unsigned long clkin;
4769	unsigned long pll_min;
4770	unsigned long pll_max;
4771	int ndl = dsi->num_lanes_used - 1;
4772	int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4773	unsigned long byteclk_min;
4774
4775	clkin = clk_get_rate(dsi->pll.clkin);
4776
4777	memset(ctx, 0, sizeof(*ctx));
4778	ctx->dsidev = dsi->pdev;
4779	ctx->pll = &dsi->pll;
4780	ctx->config = cfg;
4781
4782	/* these limits should come from the panel driver */
4783	ctx->req_pck_min = vm->pixelclock - 1000;
4784	ctx->req_pck_nom = vm->pixelclock;
4785	ctx->req_pck_max = vm->pixelclock + 1000;
4786
4787	byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4788	pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4789
4790	if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4791		pll_max = cfg->hs_clk_max * 4;
4792	} else {
4793		unsigned long byteclk_max;
4794		byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4795				ndl * 8);
4796
4797		pll_max = byteclk_max * 4 * 4;
4798	}
4799
4800	return dss_pll_calc_a(ctx->pll, clkin,
4801			pll_min, pll_max,
4802			dsi_vm_calc_pll_cb, ctx);
4803}
4804
4805static int dsi_set_config(struct omap_dss_device *dssdev,
4806		const struct omap_dss_dsi_config *config)
4807{
4808	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4809	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4810	struct dsi_clk_calc_ctx ctx;
 
 
 
 
 
 
 
 
4811	bool ok;
4812	int r;
4813
4814	mutex_lock(&dsi->lock);
4815
4816	dsi->pix_fmt = config->pixel_format;
4817	dsi->mode = config->mode;
 
4818
4819	if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4820		ok = dsi_vm_calc(dsi, config, &ctx);
4821	else
4822		ok = dsi_cm_calc(dsi, config, &ctx);
4823
4824	if (!ok) {
4825		DSSERR("failed to find suitable DSI clock settings\n");
4826		r = -EINVAL;
4827		goto err;
4828	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4829
4830	dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
4831
4832	r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4833		config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4834	if (r) {
4835		DSSERR("failed to find suitable DSI LP clock settings\n");
4836		goto err;
4837	}
4838
 
4839	dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4840	dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4841
4842	dsi->vm = ctx.vm;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4843	dsi->vm_timings = ctx.dsi_vm;
4844
4845	mutex_unlock(&dsi->lock);
4846
4847	return 0;
4848err:
4849	mutex_unlock(&dsi->lock);
4850
4851	return r;
4852}
4853
4854/*
4855 * Return a hardcoded channel for the DSI output. This should work for
4856 * current use cases, but this can be later expanded to either resolve
4857 * the channel in some more dynamic manner, or get the channel as a user
4858 * parameter.
4859 */
4860static enum omap_channel dsi_get_channel(int module_id)
4861{
4862	switch (omapdss_get_version()) {
4863	case OMAPDSS_VER_OMAP24xx:
4864	case OMAPDSS_VER_AM43xx:
4865		DSSWARN("DSI not supported\n");
4866		return OMAP_DSS_CHANNEL_LCD;
4867
4868	case OMAPDSS_VER_OMAP34xx_ES1:
4869	case OMAPDSS_VER_OMAP34xx_ES3:
4870	case OMAPDSS_VER_OMAP3630:
4871	case OMAPDSS_VER_AM35xx:
4872		return OMAP_DSS_CHANNEL_LCD;
4873
4874	case OMAPDSS_VER_OMAP4430_ES1:
4875	case OMAPDSS_VER_OMAP4430_ES2:
4876	case OMAPDSS_VER_OMAP4:
4877		switch (module_id) {
4878		case 0:
4879			return OMAP_DSS_CHANNEL_LCD;
4880		case 1:
4881			return OMAP_DSS_CHANNEL_LCD2;
4882		default:
4883			DSSWARN("unsupported module id\n");
4884			return OMAP_DSS_CHANNEL_LCD;
4885		}
4886
4887	case OMAPDSS_VER_OMAP5:
4888		switch (module_id) {
4889		case 0:
4890			return OMAP_DSS_CHANNEL_LCD;
4891		case 1:
4892			return OMAP_DSS_CHANNEL_LCD3;
4893		default:
4894			DSSWARN("unsupported module id\n");
4895			return OMAP_DSS_CHANNEL_LCD;
4896		}
4897
4898	default:
4899		DSSWARN("unsupported DSS version\n");
4900		return OMAP_DSS_CHANNEL_LCD;
4901	}
4902}
4903
4904static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
 
4905{
4906	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4907	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4908	int i;
4909
4910	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4911		if (!dsi->vc[i].dssdev) {
4912			dsi->vc[i].dssdev = dssdev;
4913			*channel = i;
4914			return 0;
4915		}
4916	}
4917
4918	DSSERR("cannot get VC for display %s", dssdev->name);
4919	return -ENOSPC;
4920}
4921
4922static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4923{
4924	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4925	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4926
4927	if (vc_id < 0 || vc_id > 3) {
4928		DSSERR("VC ID out of range\n");
4929		return -EINVAL;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4930	}
4931
4932	if (channel < 0 || channel > 3) {
4933		DSSERR("Virtual Channel out of range\n");
4934		return -EINVAL;
4935	}
4936
4937	if (dsi->vc[channel].dssdev != dssdev) {
4938		DSSERR("Virtual Channel not allocated to display %s\n",
4939			dssdev->name);
4940		return -EINVAL;
4941	}
4942
4943	dsi->vc[channel].vc_id = vc_id;
 
 
 
 
4944
4945	return 0;
4946}
4947
4948static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
 
4949{
4950	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4951	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 
 
 
4952
4953	if ((channel >= 0 && channel <= 3) &&
4954		dsi->vc[channel].dssdev == dssdev) {
4955		dsi->vc[channel].dssdev = NULL;
4956		dsi->vc[channel].vc_id = 0;
4957	}
4958}
4959
 
 
 
 
 
 
4960
4961static int dsi_get_clocks(struct platform_device *dsidev)
4962{
4963	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4964	struct clk *clk;
4965
4966	clk = devm_clk_get(&dsidev->dev, "fck");
4967	if (IS_ERR(clk)) {
4968		DSSERR("can't get fck\n");
4969		return PTR_ERR(clk);
4970	}
4971
4972	dsi->dss_clk = clk;
4973
4974	return 0;
4975}
4976
4977static int dsi_connect(struct omap_dss_device *dssdev,
4978		struct omap_dss_device *dst)
4979{
4980	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4981	enum omap_channel dispc_channel = dssdev->dispc_channel;
4982	int r;
4983
4984	r = dsi_regulator_init(dsidev);
4985	if (r)
4986		return r;
4987
4988	r = dss_mgr_connect(dispc_channel, dssdev);
4989	if (r)
4990		return r;
 
4991
4992	r = omapdss_output_set_device(dssdev, dst);
4993	if (r) {
4994		DSSERR("failed to connect output to new device: %s\n",
4995				dssdev->name);
4996		dss_mgr_disconnect(dispc_channel, dssdev);
4997		return r;
4998	}
4999
5000	return 0;
5001}
5002
5003static void dsi_disconnect(struct omap_dss_device *dssdev,
5004		struct omap_dss_device *dst)
5005{
5006	enum omap_channel dispc_channel = dssdev->dispc_channel;
 
 
5007
5008	WARN_ON(dst != dssdev->dst);
 
 
 
 
 
5009
5010	if (dst != dssdev->dst)
5011		return;
 
 
 
5012
5013	omapdss_output_unset_device(dssdev);
 
 
5014
5015	dss_mgr_disconnect(dispc_channel, dssdev);
5016}
 
 
5017
5018static const struct omapdss_dsi_ops dsi_ops = {
5019	.connect = dsi_connect,
5020	.disconnect = dsi_disconnect,
5021
5022	.bus_lock = dsi_bus_lock,
5023	.bus_unlock = dsi_bus_unlock,
 
 
 
 
5024
5025	.enable = dsi_display_enable,
5026	.disable = dsi_display_disable,
5027
5028	.enable_hs = dsi_vc_enable_hs,
5029
5030	.configure_pins = dsi_configure_pins,
5031	.set_config = dsi_set_config,
 
 
 
 
 
 
 
5032
5033	.enable_video_output = dsi_enable_video_output,
5034	.disable_video_output = dsi_disable_video_output,
5035
5036	.update = dsi_update,
5037
5038	.enable_te = dsi_enable_te,
 
5039
5040	.request_vc = dsi_request_vc,
5041	.set_vc_id = dsi_set_vc_id,
5042	.release_vc = dsi_release_vc,
 
 
 
 
 
 
5043
5044	.dcs_write = dsi_vc_dcs_write,
5045	.dcs_write_nosync = dsi_vc_dcs_write_nosync,
5046	.dcs_read = dsi_vc_dcs_read,
 
 
5047
5048	.gen_write = dsi_vc_generic_write,
5049	.gen_write_nosync = dsi_vc_generic_write_nosync,
5050	.gen_read = dsi_vc_generic_read,
 
5051
5052	.bta_sync = dsi_vc_send_bta_sync,
 
 
 
5053
5054	.set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5055};
5056
5057static void dsi_init_output(struct platform_device *dsidev)
5058{
5059	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5060	struct omap_dss_device *out = &dsi->output;
 
 
5061
5062	out->dev = &dsidev->dev;
5063	out->id = dsi->module_id == 0 ?
5064			OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5065
5066	out->output_type = OMAP_DISPLAY_TYPE_DSI;
5067	out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5068	out->dispc_channel = dsi_get_channel(dsi->module_id);
5069	out->ops.dsi = &dsi_ops;
5070	out->owner = THIS_MODULE;
5071
5072	omapdss_register_output(out);
5073}
 
 
5074
5075static void dsi_uninit_output(struct platform_device *dsidev)
5076{
5077	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5078	struct omap_dss_device *out = &dsi->output;
 
 
5079
5080	omapdss_unregister_output(out);
5081}
5082
5083static int dsi_probe_of(struct platform_device *pdev)
 
5084{
5085	struct device_node *node = pdev->dev.of_node;
5086	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5087	struct property *prop;
5088	u32 lane_arr[10];
5089	int len, num_pins;
5090	int r, i;
5091	struct device_node *ep;
5092	struct omap_dsi_pin_config pin_cfg;
5093
5094	ep = omapdss_of_get_first_endpoint(node);
5095	if (!ep)
5096		return 0;
5097
5098	prop = of_find_property(ep, "lanes", &len);
5099	if (prop == NULL) {
5100		dev_err(&pdev->dev, "failed to find lane data\n");
5101		r = -EINVAL;
5102		goto err;
5103	}
5104
5105	num_pins = len / sizeof(u32);
5106
5107	if (num_pins < 4 || num_pins % 2 != 0 ||
5108		num_pins > dsi->num_lanes_supported * 2) {
5109		dev_err(&pdev->dev, "bad number of lanes\n");
5110		r = -EINVAL;
5111		goto err;
5112	}
5113
5114	r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5115	if (r) {
5116		dev_err(&pdev->dev, "failed to read lane data\n");
5117		goto err;
5118	}
5119
5120	pin_cfg.num_pins = num_pins;
5121	for (i = 0; i < num_pins; ++i)
5122		pin_cfg.pins[i] = (int)lane_arr[i];
5123
5124	r = dsi_configure_pins(&dsi->output, &pin_cfg);
5125	if (r) {
5126		dev_err(&pdev->dev, "failed to configure pins");
5127		goto err;
5128	}
5129
5130	of_node_put(ep);
5131
 
 
5132	return 0;
5133
5134err:
5135	of_node_put(ep);
5136	return r;
5137}
5138
 
 
 
 
 
 
 
 
 
 
5139static const struct dss_pll_ops dsi_pll_ops = {
5140	.enable = dsi_pll_enable,
5141	.disable = dsi_pll_disable,
5142	.set_config = dss_pll_write_config_type_a,
5143};
5144
5145static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
5146	.type = DSS_PLL_TYPE_A,
5147
5148	.n_max = (1 << 7) - 1,
5149	.m_max = (1 << 11) - 1,
5150	.mX_max = (1 << 4) - 1,
5151	.fint_min = 750000,
5152	.fint_max = 2100000,
5153	.clkdco_low = 1000000000,
5154	.clkdco_max = 1800000000,
5155
5156	.n_msb = 7,
5157	.n_lsb = 1,
5158	.m_msb = 18,
5159	.m_lsb = 8,
5160
5161	.mX_msb[0] = 22,
5162	.mX_lsb[0] = 19,
5163	.mX_msb[1] = 26,
5164	.mX_lsb[1] = 23,
5165
5166	.has_stopmode = true,
5167	.has_freqsel = true,
5168	.has_selfreqdco = false,
5169	.has_refsel = false,
5170};
5171
5172static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
5173	.type = DSS_PLL_TYPE_A,
5174
5175	.n_max = (1 << 8) - 1,
5176	.m_max = (1 << 12) - 1,
5177	.mX_max = (1 << 5) - 1,
5178	.fint_min = 500000,
5179	.fint_max = 2500000,
5180	.clkdco_low = 1000000000,
5181	.clkdco_max = 1800000000,
5182
5183	.n_msb = 8,
5184	.n_lsb = 1,
5185	.m_msb = 20,
5186	.m_lsb = 9,
5187
5188	.mX_msb[0] = 25,
5189	.mX_lsb[0] = 21,
5190	.mX_msb[1] = 30,
5191	.mX_lsb[1] = 26,
5192
5193	.has_stopmode = true,
5194	.has_freqsel = false,
5195	.has_selfreqdco = false,
5196	.has_refsel = false,
5197};
5198
5199static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
5200	.type = DSS_PLL_TYPE_A,
5201
5202	.n_max = (1 << 8) - 1,
5203	.m_max = (1 << 12) - 1,
5204	.mX_max = (1 << 5) - 1,
5205	.fint_min = 150000,
5206	.fint_max = 52000000,
5207	.clkdco_low = 1000000000,
5208	.clkdco_max = 1800000000,
5209
5210	.n_msb = 8,
5211	.n_lsb = 1,
5212	.m_msb = 20,
5213	.m_lsb = 9,
5214
5215	.mX_msb[0] = 25,
5216	.mX_lsb[0] = 21,
5217	.mX_msb[1] = 30,
5218	.mX_lsb[1] = 26,
5219
5220	.has_stopmode = true,
5221	.has_freqsel = false,
5222	.has_selfreqdco = true,
5223	.has_refsel = true,
5224};
5225
5226static int dsi_init_pll_data(struct platform_device *dsidev)
5227{
5228	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5229	struct dss_pll *pll = &dsi->pll;
5230	struct clk *clk;
5231	int r;
5232
5233	clk = devm_clk_get(&dsidev->dev, "sys_clk");
5234	if (IS_ERR(clk)) {
5235		DSSERR("can't get sys_clk\n");
5236		return PTR_ERR(clk);
5237	}
5238
5239	pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5240	pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5241	pll->clkin = clk;
5242	pll->base = dsi->pll_base;
 
 
5243
5244	switch (omapdss_get_version()) {
5245	case OMAPDSS_VER_OMAP34xx_ES1:
5246	case OMAPDSS_VER_OMAP34xx_ES3:
5247	case OMAPDSS_VER_OMAP3630:
5248	case OMAPDSS_VER_AM35xx:
5249		pll->hw = &dss_omap3_dsi_pll_hw;
5250		break;
5251
5252	case OMAPDSS_VER_OMAP4430_ES1:
5253	case OMAPDSS_VER_OMAP4430_ES2:
5254	case OMAPDSS_VER_OMAP4:
5255		pll->hw = &dss_omap4_dsi_pll_hw;
5256		break;
5257
5258	case OMAPDSS_VER_OMAP5:
5259		pll->hw = &dss_omap5_dsi_pll_hw;
5260		break;
5261
5262	default:
5263		return -ENODEV;
5264	}
 
 
 
 
5265
5266	pll->ops = &dsi_pll_ops;
 
 
5267
5268	r = dss_pll_register(pll);
5269	if (r)
5270		return r;
5271
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
5272	return 0;
5273}
5274
5275/* DSI1 HW IP initialisation */
5276static int dsi_bind(struct device *dev, struct device *master, void *data)
5277{
5278	struct platform_device *dsidev = to_platform_device(dev);
5279	u32 rev;
5280	int r, i;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
5281	struct dsi_data *dsi;
5282	struct resource *dsi_mem;
5283	struct resource *res;
5284	struct resource temp_res;
 
5285
5286	dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5287	if (!dsi)
5288		return -ENOMEM;
5289
5290	dsi->pdev = dsidev;
5291	dev_set_drvdata(&dsidev->dev, dsi);
5292
5293	spin_lock_init(&dsi->irq_lock);
5294	spin_lock_init(&dsi->errors_lock);
5295	dsi->errors = 0;
5296
5297#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5298	spin_lock_init(&dsi->irq_stats_lock);
5299	dsi->irq_stats.last_reset = jiffies;
5300#endif
5301
5302	mutex_init(&dsi->lock);
5303	sema_init(&dsi->bus_lock, 1);
5304
5305	INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5306			     dsi_framedone_timeout_work_callback);
5307
 
 
5308#ifdef DSI_CATCH_MISSING_TE
5309	init_timer(&dsi->te_timer);
5310	dsi->te_timer.function = dsi_te_timeout;
5311	dsi->te_timer.data = 0;
5312#endif
5313
5314	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
5315	if (!res) {
5316		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5317		if (!res) {
5318			DSSERR("can't get IORESOURCE_MEM DSI\n");
5319			return -EINVAL;
5320		}
5321
5322		temp_res.start = res->start;
5323		temp_res.end = temp_res.start + DSI_PROTO_SZ - 1;
5324		res = &temp_res;
5325	}
5326
5327	dsi_mem = res;
5328
5329	dsi->proto_base = devm_ioremap(&dsidev->dev, res->start,
5330		resource_size(res));
5331	if (!dsi->proto_base) {
5332		DSSERR("can't ioremap DSI protocol engine\n");
5333		return -ENOMEM;
5334	}
5335
5336	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
5337	if (!res) {
5338		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5339		if (!res) {
5340			DSSERR("can't get IORESOURCE_MEM DSI\n");
5341			return -EINVAL;
5342		}
5343
5344		temp_res.start = res->start + DSI_PHY_OFFSET;
5345		temp_res.end = temp_res.start + DSI_PHY_SZ - 1;
5346		res = &temp_res;
5347	}
5348
5349	dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
5350		resource_size(res));
5351	if (!dsi->phy_base) {
5352		DSSERR("can't ioremap DSI PHY\n");
5353		return -ENOMEM;
5354	}
5355
5356	res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
5357	if (!res) {
5358		res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5359		if (!res) {
5360			DSSERR("can't get IORESOURCE_MEM DSI\n");
5361			return -EINVAL;
5362		}
5363
5364		temp_res.start = res->start + DSI_PLL_OFFSET;
5365		temp_res.end = temp_res.start + DSI_PLL_SZ - 1;
5366		res = &temp_res;
5367	}
5368
5369	dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5370		resource_size(res));
5371	if (!dsi->pll_base) {
5372		DSSERR("can't ioremap DSI PLL\n");
5373		return -ENOMEM;
5374	}
5375
5376	dsi->irq = platform_get_irq(dsi->pdev, 0);
5377	if (dsi->irq < 0) {
5378		DSSERR("platform_get_irq failed\n");
5379		return -ENODEV;
5380	}
5381
5382	r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5383			     IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5384	if (r < 0) {
5385		DSSERR("request_irq failed\n");
5386		return r;
5387	}
5388
5389	if (dsidev->dev.of_node) {
5390		const struct of_device_id *match;
5391		const struct dsi_module_id_data *d;
5392
5393		match = of_match_node(dsi_of_match, dsidev->dev.of_node);
5394		if (!match) {
5395			DSSERR("unsupported DSI module\n");
5396			return -ENODEV;
5397		}
 
 
 
 
 
 
 
 
 
 
 
 
5398
5399		d = match->data;
5400
5401		while (d->address != 0 && d->address != dsi_mem->start)
5402			d++;
 
5403
5404		if (d->address == 0) {
5405			DSSERR("unsupported DSI module\n");
 
 
 
 
 
 
5406			return -ENODEV;
5407		}
5408
5409		dsi->module_id = d->id;
5410	} else {
5411		dsi->module_id = dsidev->id;
5412	}
5413
5414	/* DSI VCs initialization */
5415	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5416		dsi->vc[i].source = DSI_VC_SOURCE_L4;
5417		dsi->vc[i].dssdev = NULL;
5418		dsi->vc[i].vc_id = 0;
5419	}
5420
5421	r = dsi_get_clocks(dsidev);
5422	if (r)
5423		return r;
5424
5425	dsi_init_pll_data(dsidev);
5426
5427	pm_runtime_enable(&dsidev->dev);
5428
5429	r = dsi_runtime_get(dsidev);
5430	if (r)
5431		goto err_runtime_get;
5432
5433	rev = dsi_read_reg(dsidev, DSI_REVISION);
5434	dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5435	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5436
5437	/* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5438	 * of data to 3 by default */
5439	if (dss_has_feature(FEAT_DSI_GNQ))
 
5440		/* NB_DATA_LANES */
5441		dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5442	else
 
5443		dsi->num_lanes_supported = 3;
 
5444
5445	dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5446
5447	dsi_init_output(dsidev);
5448
5449	if (dsidev->dev.of_node) {
5450		r = dsi_probe_of(dsidev);
5451		if (r) {
5452			DSSERR("Invalid DSI DT data\n");
5453			goto err_probe_of;
5454		}
5455
5456		r = of_platform_populate(dsidev->dev.of_node, NULL, NULL,
5457			&dsidev->dev);
5458		if (r)
5459			DSSERR("Failed to populate DSI child devices: %d\n", r);
5460	}
5461
5462	dsi_runtime_put(dsidev);
 
 
 
 
5463
5464	if (dsi->module_id == 0)
5465		dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5466	else if (dsi->module_id == 1)
5467		dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5468
5469#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5470	if (dsi->module_id == 0)
5471		dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5472	else if (dsi->module_id == 1)
5473		dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5474#endif
5475
5476	return 0;
5477
5478err_probe_of:
5479	dsi_uninit_output(dsidev);
5480	dsi_runtime_put(dsidev);
5481
5482err_runtime_get:
5483	pm_runtime_disable(&dsidev->dev);
5484	return r;
5485}
5486
5487static void dsi_unbind(struct device *dev, struct device *master, void *data)
5488{
5489	struct platform_device *dsidev = to_platform_device(dev);
5490	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5491
5492	of_platform_depopulate(&dsidev->dev);
5493
5494	WARN_ON(dsi->scp_clk_refcount > 0);
5495
5496	dss_pll_unregister(&dsi->pll);
5497
5498	dsi_uninit_output(dsidev);
5499
5500	pm_runtime_disable(&dsidev->dev);
5501
5502	if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5503		regulator_disable(dsi->vdds_dsi_reg);
5504		dsi->vdds_dsi_enabled = false;
5505	}
5506}
5507
5508static const struct component_ops dsi_component_ops = {
5509	.bind	= dsi_bind,
5510	.unbind	= dsi_unbind,
5511};
5512
5513static int dsi_probe(struct platform_device *pdev)
5514{
5515	return component_add(&pdev->dev, &dsi_component_ops);
5516}
5517
5518static int dsi_remove(struct platform_device *pdev)
5519{
5520	component_del(&pdev->dev, &dsi_component_ops);
5521	return 0;
5522}
5523
5524static int dsi_runtime_suspend(struct device *dev)
5525{
5526	struct platform_device *pdev = to_platform_device(dev);
5527	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5528
5529	dsi->is_enabled = false;
5530	/* ensure the irq handler sees the is_enabled value */
5531	smp_wmb();
5532	/* wait for current handler to finish before turning the DSI off */
5533	synchronize_irq(dsi->irq);
5534
5535	dispc_runtime_put();
5536
5537	return 0;
5538}
5539
5540static int dsi_runtime_resume(struct device *dev)
5541{
5542	struct platform_device *pdev = to_platform_device(dev);
5543	struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5544	int r;
5545
5546	r = dispc_runtime_get();
5547	if (r)
5548		return r;
5549
5550	dsi->is_enabled = true;
5551	/* ensure the irq handler sees the is_enabled value */
5552	smp_wmb();
5553
5554	return 0;
5555}
5556
5557static const struct dev_pm_ops dsi_pm_ops = {
5558	.runtime_suspend = dsi_runtime_suspend,
5559	.runtime_resume = dsi_runtime_resume,
 
5560};
5561
5562static const struct dsi_module_id_data dsi_of_data_omap3[] = {
5563	{ .address = 0x4804fc00, .id = 0, },
5564	{ },
5565};
5566
5567static const struct dsi_module_id_data dsi_of_data_omap4[] = {
5568	{ .address = 0x58004000, .id = 0, },
5569	{ .address = 0x58005000, .id = 1, },
5570	{ },
5571};
5572
5573static const struct dsi_module_id_data dsi_of_data_omap5[] = {
5574	{ .address = 0x58004000, .id = 0, },
5575	{ .address = 0x58009000, .id = 1, },
5576	{ },
5577};
5578
5579static const struct of_device_id dsi_of_match[] = {
5580	{ .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, },
5581	{ .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, },
5582	{ .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, },
5583	{},
5584};
5585
5586static struct platform_driver omap_dsihw_driver = {
5587	.probe		= dsi_probe,
5588	.remove		= dsi_remove,
5589	.driver         = {
5590		.name   = "omapdss_dsi",
5591		.pm	= &dsi_pm_ops,
5592		.of_match_table = dsi_of_match,
5593		.suppress_bind_attrs = true,
5594	},
5595};
5596
5597int __init dsi_init_platform_driver(void)
5598{
5599	return platform_driver_register(&omap_dsihw_driver);
5600}
5601
5602void dsi_uninit_platform_driver(void)
5603{
5604	platform_driver_unregister(&omap_dsihw_driver);
5605}