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1/* drivers/gpu/drm/exynos/exynos7_drm_decon.c
2 *
3 * Copyright (C) 2014 Samsung Electronics Co.Ltd
4 * Authors:
5 * Akshu Agarwal <akshua@gmail.com>
6 * Ajay Kumar <ajaykumar.rs@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14#include <drm/drmP.h>
15#include <drm/exynos_drm.h>
16
17#include <linux/clk.h>
18#include <linux/component.h>
19#include <linux/kernel.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25
26#include <video/of_display_timing.h>
27#include <video/of_videomode.h>
28#include <video/exynos7_decon.h>
29
30#include "exynos_drm_crtc.h"
31#include "exynos_drm_plane.h"
32#include "exynos_drm_drv.h"
33#include "exynos_drm_fb.h"
34#include "exynos_drm_iommu.h"
35
36/*
37 * DECON stands for Display and Enhancement controller.
38 */
39
40#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
41
42#define WINDOWS_NR 2
43
44struct decon_context {
45 struct device *dev;
46 struct drm_device *drm_dev;
47 struct exynos_drm_crtc *crtc;
48 struct exynos_drm_plane planes[WINDOWS_NR];
49 struct exynos_drm_plane_config configs[WINDOWS_NR];
50 struct clk *pclk;
51 struct clk *aclk;
52 struct clk *eclk;
53 struct clk *vclk;
54 void __iomem *regs;
55 unsigned long irq_flags;
56 bool i80_if;
57 bool suspended;
58 int pipe;
59 wait_queue_head_t wait_vsync_queue;
60 atomic_t wait_vsync_event;
61
62 struct drm_encoder *encoder;
63};
64
65static const struct of_device_id decon_driver_dt_match[] = {
66 {.compatible = "samsung,exynos7-decon"},
67 {},
68};
69MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
70
71static const uint32_t decon_formats[] = {
72 DRM_FORMAT_RGB565,
73 DRM_FORMAT_XRGB8888,
74 DRM_FORMAT_XBGR8888,
75 DRM_FORMAT_RGBX8888,
76 DRM_FORMAT_BGRX8888,
77 DRM_FORMAT_ARGB8888,
78 DRM_FORMAT_ABGR8888,
79 DRM_FORMAT_RGBA8888,
80 DRM_FORMAT_BGRA8888,
81};
82
83static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
84 DRM_PLANE_TYPE_PRIMARY,
85 DRM_PLANE_TYPE_CURSOR,
86};
87
88static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
89{
90 struct decon_context *ctx = crtc->ctx;
91
92 if (ctx->suspended)
93 return;
94
95 atomic_set(&ctx->wait_vsync_event, 1);
96
97 /*
98 * wait for DECON to signal VSYNC interrupt or return after
99 * timeout which is set to 50ms (refresh rate of 20).
100 */
101 if (!wait_event_timeout(ctx->wait_vsync_queue,
102 !atomic_read(&ctx->wait_vsync_event),
103 HZ/20))
104 DRM_DEBUG_KMS("vblank wait timed out.\n");
105}
106
107static void decon_clear_channels(struct exynos_drm_crtc *crtc)
108{
109 struct decon_context *ctx = crtc->ctx;
110 unsigned int win, ch_enabled = 0;
111
112 DRM_DEBUG_KMS("%s\n", __FILE__);
113
114 /* Check if any channel is enabled. */
115 for (win = 0; win < WINDOWS_NR; win++) {
116 u32 val = readl(ctx->regs + WINCON(win));
117
118 if (val & WINCONx_ENWIN) {
119 val &= ~WINCONx_ENWIN;
120 writel(val, ctx->regs + WINCON(win));
121 ch_enabled = 1;
122 }
123 }
124
125 /* Wait for vsync, as disable channel takes effect at next vsync */
126 if (ch_enabled)
127 decon_wait_for_vblank(ctx->crtc);
128}
129
130static int decon_ctx_initialize(struct decon_context *ctx,
131 struct drm_device *drm_dev)
132{
133 struct exynos_drm_private *priv = drm_dev->dev_private;
134 int ret;
135
136 ctx->drm_dev = drm_dev;
137 ctx->pipe = priv->pipe++;
138
139 decon_clear_channels(ctx->crtc);
140
141 ret = drm_iommu_attach_device(drm_dev, ctx->dev);
142 if (ret)
143 priv->pipe--;
144
145 return ret;
146}
147
148static void decon_ctx_remove(struct decon_context *ctx)
149{
150 /* detach this sub driver from iommu mapping if supported. */
151 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
152}
153
154static u32 decon_calc_clkdiv(struct decon_context *ctx,
155 const struct drm_display_mode *mode)
156{
157 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
158 u32 clkdiv;
159
160 /* Find the clock divider value that gets us closest to ideal_clk */
161 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
162
163 return (clkdiv < 0x100) ? clkdiv : 0xff;
164}
165
166static void decon_commit(struct exynos_drm_crtc *crtc)
167{
168 struct decon_context *ctx = crtc->ctx;
169 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
170 u32 val, clkdiv;
171
172 if (ctx->suspended)
173 return;
174
175 /* nothing to do if we haven't set the mode yet */
176 if (mode->htotal == 0 || mode->vtotal == 0)
177 return;
178
179 if (!ctx->i80_if) {
180 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
181 /* setup vertical timing values. */
182 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
183 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
184 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
185
186 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
187 writel(val, ctx->regs + VIDTCON0);
188
189 val = VIDTCON1_VSPW(vsync_len - 1);
190 writel(val, ctx->regs + VIDTCON1);
191
192 /* setup horizontal timing values. */
193 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
194 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
195 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
196
197 /* setup horizontal timing values. */
198 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
199 writel(val, ctx->regs + VIDTCON2);
200
201 val = VIDTCON3_HSPW(hsync_len - 1);
202 writel(val, ctx->regs + VIDTCON3);
203 }
204
205 /* setup horizontal and vertical display size. */
206 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
207 VIDTCON4_HOZVAL(mode->hdisplay - 1);
208 writel(val, ctx->regs + VIDTCON4);
209
210 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
211
212 /*
213 * fields of register with prefix '_F' would be updated
214 * at vsync(same as dma start)
215 */
216 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
217 writel(val, ctx->regs + VIDCON0);
218
219 clkdiv = decon_calc_clkdiv(ctx, mode);
220 if (clkdiv > 1) {
221 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
222 writel(val, ctx->regs + VCLKCON1);
223 writel(val, ctx->regs + VCLKCON2);
224 }
225
226 val = readl(ctx->regs + DECON_UPDATE);
227 val |= DECON_UPDATE_STANDALONE_F;
228 writel(val, ctx->regs + DECON_UPDATE);
229}
230
231static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
232{
233 struct decon_context *ctx = crtc->ctx;
234 u32 val;
235
236 if (ctx->suspended)
237 return -EPERM;
238
239 if (!test_and_set_bit(0, &ctx->irq_flags)) {
240 val = readl(ctx->regs + VIDINTCON0);
241
242 val |= VIDINTCON0_INT_ENABLE;
243
244 if (!ctx->i80_if) {
245 val |= VIDINTCON0_INT_FRAME;
246 val &= ~VIDINTCON0_FRAMESEL0_MASK;
247 val |= VIDINTCON0_FRAMESEL0_VSYNC;
248 }
249
250 writel(val, ctx->regs + VIDINTCON0);
251 }
252
253 return 0;
254}
255
256static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
257{
258 struct decon_context *ctx = crtc->ctx;
259 u32 val;
260
261 if (ctx->suspended)
262 return;
263
264 if (test_and_clear_bit(0, &ctx->irq_flags)) {
265 val = readl(ctx->regs + VIDINTCON0);
266
267 val &= ~VIDINTCON0_INT_ENABLE;
268 if (!ctx->i80_if)
269 val &= ~VIDINTCON0_INT_FRAME;
270
271 writel(val, ctx->regs + VIDINTCON0);
272 }
273}
274
275static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
276 struct drm_framebuffer *fb)
277{
278 unsigned long val;
279 int padding;
280
281 val = readl(ctx->regs + WINCON(win));
282 val &= ~WINCONx_BPPMODE_MASK;
283
284 switch (fb->pixel_format) {
285 case DRM_FORMAT_RGB565:
286 val |= WINCONx_BPPMODE_16BPP_565;
287 val |= WINCONx_BURSTLEN_16WORD;
288 break;
289 case DRM_FORMAT_XRGB8888:
290 val |= WINCONx_BPPMODE_24BPP_xRGB;
291 val |= WINCONx_BURSTLEN_16WORD;
292 break;
293 case DRM_FORMAT_XBGR8888:
294 val |= WINCONx_BPPMODE_24BPP_xBGR;
295 val |= WINCONx_BURSTLEN_16WORD;
296 break;
297 case DRM_FORMAT_RGBX8888:
298 val |= WINCONx_BPPMODE_24BPP_RGBx;
299 val |= WINCONx_BURSTLEN_16WORD;
300 break;
301 case DRM_FORMAT_BGRX8888:
302 val |= WINCONx_BPPMODE_24BPP_BGRx;
303 val |= WINCONx_BURSTLEN_16WORD;
304 break;
305 case DRM_FORMAT_ARGB8888:
306 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
307 WINCONx_ALPHA_SEL;
308 val |= WINCONx_BURSTLEN_16WORD;
309 break;
310 case DRM_FORMAT_ABGR8888:
311 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
312 WINCONx_ALPHA_SEL;
313 val |= WINCONx_BURSTLEN_16WORD;
314 break;
315 case DRM_FORMAT_RGBA8888:
316 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
317 WINCONx_ALPHA_SEL;
318 val |= WINCONx_BURSTLEN_16WORD;
319 break;
320 case DRM_FORMAT_BGRA8888:
321 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
322 WINCONx_ALPHA_SEL;
323 val |= WINCONx_BURSTLEN_16WORD;
324 break;
325 default:
326 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
327
328 val |= WINCONx_BPPMODE_24BPP_xRGB;
329 val |= WINCONx_BURSTLEN_16WORD;
330 break;
331 }
332
333 DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel);
334
335 /*
336 * In case of exynos, setting dma-burst to 16Word causes permanent
337 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
338 * switching which is based on plane size is not recommended as
339 * plane size varies a lot towards the end of the screen and rapid
340 * movement causes unstable DMA which results into iommu crash/tear.
341 */
342
343 padding = (fb->pitches[0] / (fb->bits_per_pixel >> 3)) - fb->width;
344 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
345 val &= ~WINCONx_BURSTLEN_MASK;
346 val |= WINCONx_BURSTLEN_8WORD;
347 }
348
349 writel(val, ctx->regs + WINCON(win));
350}
351
352static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
353{
354 unsigned int keycon0 = 0, keycon1 = 0;
355
356 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
357 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
358
359 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
360
361 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
362 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
363}
364
365/**
366 * shadow_protect_win() - disable updating values from shadow registers at vsync
367 *
368 * @win: window to protect registers for
369 * @protect: 1 to protect (disable updates)
370 */
371static void decon_shadow_protect_win(struct decon_context *ctx,
372 unsigned int win, bool protect)
373{
374 u32 bits, val;
375
376 bits = SHADOWCON_WINx_PROTECT(win);
377
378 val = readl(ctx->regs + SHADOWCON);
379 if (protect)
380 val |= bits;
381 else
382 val &= ~bits;
383 writel(val, ctx->regs + SHADOWCON);
384}
385
386static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
387{
388 struct decon_context *ctx = crtc->ctx;
389 int i;
390
391 if (ctx->suspended)
392 return;
393
394 for (i = 0; i < WINDOWS_NR; i++)
395 decon_shadow_protect_win(ctx, i, true);
396}
397
398static void decon_update_plane(struct exynos_drm_crtc *crtc,
399 struct exynos_drm_plane *plane)
400{
401 struct exynos_drm_plane_state *state =
402 to_exynos_plane_state(plane->base.state);
403 struct decon_context *ctx = crtc->ctx;
404 struct drm_framebuffer *fb = state->base.fb;
405 int padding;
406 unsigned long val, alpha;
407 unsigned int last_x;
408 unsigned int last_y;
409 unsigned int win = plane->index;
410 unsigned int bpp = fb->bits_per_pixel >> 3;
411 unsigned int pitch = fb->pitches[0];
412
413 if (ctx->suspended)
414 return;
415
416 /*
417 * SHADOWCON/PRTCON register is used for enabling timing.
418 *
419 * for example, once only width value of a register is set,
420 * if the dma is started then decon hardware could malfunction so
421 * with protect window setting, the register fields with prefix '_F'
422 * wouldn't be updated at vsync also but updated once unprotect window
423 * is set.
424 */
425
426 /* buffer start address */
427 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
428 writel(val, ctx->regs + VIDW_BUF_START(win));
429
430 padding = (pitch / bpp) - fb->width;
431
432 /* buffer size */
433 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
434 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
435
436 /* offset from the start of the buffer to read */
437 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
438 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
439
440 DRM_DEBUG_KMS("start addr = 0x%lx\n",
441 (unsigned long)val);
442 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
443 state->crtc.w, state->crtc.h);
444
445 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
446 VIDOSDxA_TOPLEFT_Y(state->crtc.y);
447 writel(val, ctx->regs + VIDOSD_A(win));
448
449 last_x = state->crtc.x + state->crtc.w;
450 if (last_x)
451 last_x--;
452 last_y = state->crtc.y + state->crtc.h;
453 if (last_y)
454 last_y--;
455
456 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
457
458 writel(val, ctx->regs + VIDOSD_B(win));
459
460 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
461 state->crtc.x, state->crtc.y, last_x, last_y);
462
463 /* OSD alpha */
464 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
465 VIDOSDxC_ALPHA0_G_F(0x0) |
466 VIDOSDxC_ALPHA0_B_F(0x0);
467
468 writel(alpha, ctx->regs + VIDOSD_C(win));
469
470 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
471 VIDOSDxD_ALPHA1_G_F(0xff) |
472 VIDOSDxD_ALPHA1_B_F(0xff);
473
474 writel(alpha, ctx->regs + VIDOSD_D(win));
475
476 decon_win_set_pixfmt(ctx, win, fb);
477
478 /* hardware window 0 doesn't support color key. */
479 if (win != 0)
480 decon_win_set_colkey(ctx, win);
481
482 /* wincon */
483 val = readl(ctx->regs + WINCON(win));
484 val |= WINCONx_TRIPLE_BUF_MODE;
485 val |= WINCONx_ENWIN;
486 writel(val, ctx->regs + WINCON(win));
487
488 /* Enable DMA channel and unprotect windows */
489 decon_shadow_protect_win(ctx, win, false);
490
491 val = readl(ctx->regs + DECON_UPDATE);
492 val |= DECON_UPDATE_STANDALONE_F;
493 writel(val, ctx->regs + DECON_UPDATE);
494}
495
496static void decon_disable_plane(struct exynos_drm_crtc *crtc,
497 struct exynos_drm_plane *plane)
498{
499 struct decon_context *ctx = crtc->ctx;
500 unsigned int win = plane->index;
501 u32 val;
502
503 if (ctx->suspended)
504 return;
505
506 /* protect windows */
507 decon_shadow_protect_win(ctx, win, true);
508
509 /* wincon */
510 val = readl(ctx->regs + WINCON(win));
511 val &= ~WINCONx_ENWIN;
512 writel(val, ctx->regs + WINCON(win));
513
514 val = readl(ctx->regs + DECON_UPDATE);
515 val |= DECON_UPDATE_STANDALONE_F;
516 writel(val, ctx->regs + DECON_UPDATE);
517}
518
519static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
520{
521 struct decon_context *ctx = crtc->ctx;
522 int i;
523
524 if (ctx->suspended)
525 return;
526
527 for (i = 0; i < WINDOWS_NR; i++)
528 decon_shadow_protect_win(ctx, i, false);
529}
530
531static void decon_init(struct decon_context *ctx)
532{
533 u32 val;
534
535 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
536
537 val = VIDOUTCON0_DISP_IF_0_ON;
538 if (!ctx->i80_if)
539 val |= VIDOUTCON0_RGBIF;
540 writel(val, ctx->regs + VIDOUTCON0);
541
542 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
543
544 if (!ctx->i80_if)
545 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
546}
547
548static void decon_enable(struct exynos_drm_crtc *crtc)
549{
550 struct decon_context *ctx = crtc->ctx;
551
552 if (!ctx->suspended)
553 return;
554
555 pm_runtime_get_sync(ctx->dev);
556
557 decon_init(ctx);
558
559 /* if vblank was enabled status, enable it again. */
560 if (test_and_clear_bit(0, &ctx->irq_flags))
561 decon_enable_vblank(ctx->crtc);
562
563 decon_commit(ctx->crtc);
564
565 ctx->suspended = false;
566}
567
568static void decon_disable(struct exynos_drm_crtc *crtc)
569{
570 struct decon_context *ctx = crtc->ctx;
571 int i;
572
573 if (ctx->suspended)
574 return;
575
576 /*
577 * We need to make sure that all windows are disabled before we
578 * suspend that connector. Otherwise we might try to scan from
579 * a destroyed buffer later.
580 */
581 for (i = 0; i < WINDOWS_NR; i++)
582 decon_disable_plane(crtc, &ctx->planes[i]);
583
584 pm_runtime_put_sync(ctx->dev);
585
586 ctx->suspended = true;
587}
588
589static const struct exynos_drm_crtc_ops decon_crtc_ops = {
590 .enable = decon_enable,
591 .disable = decon_disable,
592 .commit = decon_commit,
593 .enable_vblank = decon_enable_vblank,
594 .disable_vblank = decon_disable_vblank,
595 .atomic_begin = decon_atomic_begin,
596 .update_plane = decon_update_plane,
597 .disable_plane = decon_disable_plane,
598 .atomic_flush = decon_atomic_flush,
599};
600
601
602static irqreturn_t decon_irq_handler(int irq, void *dev_id)
603{
604 struct decon_context *ctx = (struct decon_context *)dev_id;
605 u32 val, clear_bit;
606
607 val = readl(ctx->regs + VIDINTCON1);
608
609 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
610 if (val & clear_bit)
611 writel(clear_bit, ctx->regs + VIDINTCON1);
612
613 /* check the crtc is detached already from encoder */
614 if (ctx->pipe < 0 || !ctx->drm_dev)
615 goto out;
616
617 if (!ctx->i80_if) {
618 drm_crtc_handle_vblank(&ctx->crtc->base);
619
620 /* set wait vsync event to zero and wake up queue. */
621 if (atomic_read(&ctx->wait_vsync_event)) {
622 atomic_set(&ctx->wait_vsync_event, 0);
623 wake_up(&ctx->wait_vsync_queue);
624 }
625 }
626out:
627 return IRQ_HANDLED;
628}
629
630static int decon_bind(struct device *dev, struct device *master, void *data)
631{
632 struct decon_context *ctx = dev_get_drvdata(dev);
633 struct drm_device *drm_dev = data;
634 struct exynos_drm_plane *exynos_plane;
635 unsigned int i;
636 int ret;
637
638 ret = decon_ctx_initialize(ctx, drm_dev);
639 if (ret) {
640 DRM_ERROR("decon_ctx_initialize failed.\n");
641 return ret;
642 }
643
644 for (i = 0; i < WINDOWS_NR; i++) {
645 ctx->configs[i].pixel_formats = decon_formats;
646 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
647 ctx->configs[i].zpos = i;
648 ctx->configs[i].type = decon_win_types[i];
649
650 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
651 1 << ctx->pipe, &ctx->configs[i]);
652 if (ret)
653 return ret;
654 }
655
656 exynos_plane = &ctx->planes[DEFAULT_WIN];
657 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
658 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
659 &decon_crtc_ops, ctx);
660 if (IS_ERR(ctx->crtc)) {
661 decon_ctx_remove(ctx);
662 return PTR_ERR(ctx->crtc);
663 }
664
665 if (ctx->encoder)
666 exynos_dpi_bind(drm_dev, ctx->encoder);
667
668 return 0;
669
670}
671
672static void decon_unbind(struct device *dev, struct device *master,
673 void *data)
674{
675 struct decon_context *ctx = dev_get_drvdata(dev);
676
677 decon_disable(ctx->crtc);
678
679 if (ctx->encoder)
680 exynos_dpi_remove(ctx->encoder);
681
682 decon_ctx_remove(ctx);
683}
684
685static const struct component_ops decon_component_ops = {
686 .bind = decon_bind,
687 .unbind = decon_unbind,
688};
689
690static int decon_probe(struct platform_device *pdev)
691{
692 struct device *dev = &pdev->dev;
693 struct decon_context *ctx;
694 struct device_node *i80_if_timings;
695 struct resource *res;
696 int ret;
697
698 if (!dev->of_node)
699 return -ENODEV;
700
701 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
702 if (!ctx)
703 return -ENOMEM;
704
705 ctx->dev = dev;
706 ctx->suspended = true;
707
708 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
709 if (i80_if_timings)
710 ctx->i80_if = true;
711 of_node_put(i80_if_timings);
712
713 ctx->regs = of_iomap(dev->of_node, 0);
714 if (!ctx->regs)
715 return -ENOMEM;
716
717 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
718 if (IS_ERR(ctx->pclk)) {
719 dev_err(dev, "failed to get bus clock pclk\n");
720 ret = PTR_ERR(ctx->pclk);
721 goto err_iounmap;
722 }
723
724 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
725 if (IS_ERR(ctx->aclk)) {
726 dev_err(dev, "failed to get bus clock aclk\n");
727 ret = PTR_ERR(ctx->aclk);
728 goto err_iounmap;
729 }
730
731 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
732 if (IS_ERR(ctx->eclk)) {
733 dev_err(dev, "failed to get eclock\n");
734 ret = PTR_ERR(ctx->eclk);
735 goto err_iounmap;
736 }
737
738 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
739 if (IS_ERR(ctx->vclk)) {
740 dev_err(dev, "failed to get vclock\n");
741 ret = PTR_ERR(ctx->vclk);
742 goto err_iounmap;
743 }
744
745 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
746 ctx->i80_if ? "lcd_sys" : "vsync");
747 if (!res) {
748 dev_err(dev, "irq request failed.\n");
749 ret = -ENXIO;
750 goto err_iounmap;
751 }
752
753 ret = devm_request_irq(dev, res->start, decon_irq_handler,
754 0, "drm_decon", ctx);
755 if (ret) {
756 dev_err(dev, "irq request failed.\n");
757 goto err_iounmap;
758 }
759
760 init_waitqueue_head(&ctx->wait_vsync_queue);
761 atomic_set(&ctx->wait_vsync_event, 0);
762
763 platform_set_drvdata(pdev, ctx);
764
765 ctx->encoder = exynos_dpi_probe(dev);
766 if (IS_ERR(ctx->encoder)) {
767 ret = PTR_ERR(ctx->encoder);
768 goto err_iounmap;
769 }
770
771 pm_runtime_enable(dev);
772
773 ret = component_add(dev, &decon_component_ops);
774 if (ret)
775 goto err_disable_pm_runtime;
776
777 return ret;
778
779err_disable_pm_runtime:
780 pm_runtime_disable(dev);
781
782err_iounmap:
783 iounmap(ctx->regs);
784
785 return ret;
786}
787
788static int decon_remove(struct platform_device *pdev)
789{
790 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
791
792 pm_runtime_disable(&pdev->dev);
793
794 iounmap(ctx->regs);
795
796 component_del(&pdev->dev, &decon_component_ops);
797
798 return 0;
799}
800
801#ifdef CONFIG_PM
802static int exynos7_decon_suspend(struct device *dev)
803{
804 struct decon_context *ctx = dev_get_drvdata(dev);
805
806 clk_disable_unprepare(ctx->vclk);
807 clk_disable_unprepare(ctx->eclk);
808 clk_disable_unprepare(ctx->aclk);
809 clk_disable_unprepare(ctx->pclk);
810
811 return 0;
812}
813
814static int exynos7_decon_resume(struct device *dev)
815{
816 struct decon_context *ctx = dev_get_drvdata(dev);
817 int ret;
818
819 ret = clk_prepare_enable(ctx->pclk);
820 if (ret < 0) {
821 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
822 return ret;
823 }
824
825 ret = clk_prepare_enable(ctx->aclk);
826 if (ret < 0) {
827 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
828 return ret;
829 }
830
831 ret = clk_prepare_enable(ctx->eclk);
832 if (ret < 0) {
833 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
834 return ret;
835 }
836
837 ret = clk_prepare_enable(ctx->vclk);
838 if (ret < 0) {
839 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
840 return ret;
841 }
842
843 return 0;
844}
845#endif
846
847static const struct dev_pm_ops exynos7_decon_pm_ops = {
848 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
849 NULL)
850};
851
852struct platform_driver decon_driver = {
853 .probe = decon_probe,
854 .remove = decon_remove,
855 .driver = {
856 .name = "exynos-decon",
857 .pm = &exynos7_decon_pm_ops,
858 .of_match_table = decon_driver_dt_match,
859 },
860};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* drivers/gpu/drm/exynos/exynos7_drm_decon.c
3 *
4 * Copyright (C) 2014 Samsung Electronics Co.Ltd
5 * Authors:
6 * Akshu Agarwal <akshua@gmail.com>
7 * Ajay Kumar <ajaykumar.rs@samsung.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/component.h>
12#include <linux/kernel.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18
19#include <video/of_display_timing.h>
20#include <video/of_videomode.h>
21
22#include <drm/drm_fourcc.h>
23#include <drm/drm_vblank.h>
24#include <drm/exynos_drm.h>
25
26#include "exynos_drm_crtc.h"
27#include "exynos_drm_drv.h"
28#include "exynos_drm_fb.h"
29#include "exynos_drm_plane.h"
30#include "regs-decon7.h"
31
32/*
33 * DECON stands for Display and Enhancement controller.
34 */
35
36#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
37
38#define WINDOWS_NR 2
39
40struct decon_context {
41 struct device *dev;
42 struct drm_device *drm_dev;
43 void *dma_priv;
44 struct exynos_drm_crtc *crtc;
45 struct exynos_drm_plane planes[WINDOWS_NR];
46 struct exynos_drm_plane_config configs[WINDOWS_NR];
47 struct clk *pclk;
48 struct clk *aclk;
49 struct clk *eclk;
50 struct clk *vclk;
51 void __iomem *regs;
52 unsigned long irq_flags;
53 bool i80_if;
54 bool suspended;
55 wait_queue_head_t wait_vsync_queue;
56 atomic_t wait_vsync_event;
57
58 struct drm_encoder *encoder;
59};
60
61static const struct of_device_id decon_driver_dt_match[] = {
62 {.compatible = "samsung,exynos7-decon"},
63 {},
64};
65MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
66
67static const uint32_t decon_formats[] = {
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_RGBX8888,
72 DRM_FORMAT_BGRX8888,
73 DRM_FORMAT_ARGB8888,
74 DRM_FORMAT_ABGR8888,
75 DRM_FORMAT_RGBA8888,
76 DRM_FORMAT_BGRA8888,
77};
78
79static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
80 DRM_PLANE_TYPE_PRIMARY,
81 DRM_PLANE_TYPE_CURSOR,
82};
83
84static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
85{
86 struct decon_context *ctx = crtc->ctx;
87
88 if (ctx->suspended)
89 return;
90
91 atomic_set(&ctx->wait_vsync_event, 1);
92
93 /*
94 * wait for DECON to signal VSYNC interrupt or return after
95 * timeout which is set to 50ms (refresh rate of 20).
96 */
97 if (!wait_event_timeout(ctx->wait_vsync_queue,
98 !atomic_read(&ctx->wait_vsync_event),
99 HZ/20))
100 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
101}
102
103static void decon_clear_channels(struct exynos_drm_crtc *crtc)
104{
105 struct decon_context *ctx = crtc->ctx;
106 unsigned int win, ch_enabled = 0;
107
108 /* Check if any channel is enabled. */
109 for (win = 0; win < WINDOWS_NR; win++) {
110 u32 val = readl(ctx->regs + WINCON(win));
111
112 if (val & WINCONx_ENWIN) {
113 val &= ~WINCONx_ENWIN;
114 writel(val, ctx->regs + WINCON(win));
115 ch_enabled = 1;
116 }
117 }
118
119 /* Wait for vsync, as disable channel takes effect at next vsync */
120 if (ch_enabled)
121 decon_wait_for_vblank(ctx->crtc);
122}
123
124static int decon_ctx_initialize(struct decon_context *ctx,
125 struct drm_device *drm_dev)
126{
127 ctx->drm_dev = drm_dev;
128
129 decon_clear_channels(ctx->crtc);
130
131 return exynos_drm_register_dma(drm_dev, ctx->dev, &ctx->dma_priv);
132}
133
134static void decon_ctx_remove(struct decon_context *ctx)
135{
136 /* detach this sub driver from iommu mapping if supported. */
137 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
138}
139
140static u32 decon_calc_clkdiv(struct decon_context *ctx,
141 const struct drm_display_mode *mode)
142{
143 unsigned long ideal_clk = mode->clock;
144 u32 clkdiv;
145
146 /* Find the clock divider value that gets us closest to ideal_clk */
147 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
148
149 return (clkdiv < 0x100) ? clkdiv : 0xff;
150}
151
152static void decon_commit(struct exynos_drm_crtc *crtc)
153{
154 struct decon_context *ctx = crtc->ctx;
155 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
156 u32 val, clkdiv;
157
158 if (ctx->suspended)
159 return;
160
161 /* nothing to do if we haven't set the mode yet */
162 if (mode->htotal == 0 || mode->vtotal == 0)
163 return;
164
165 if (!ctx->i80_if) {
166 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
167 /* setup vertical timing values. */
168 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
169 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
170 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
171
172 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
173 writel(val, ctx->regs + VIDTCON0);
174
175 val = VIDTCON1_VSPW(vsync_len - 1);
176 writel(val, ctx->regs + VIDTCON1);
177
178 /* setup horizontal timing values. */
179 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
180 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
181 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
182
183 /* setup horizontal timing values. */
184 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
185 writel(val, ctx->regs + VIDTCON2);
186
187 val = VIDTCON3_HSPW(hsync_len - 1);
188 writel(val, ctx->regs + VIDTCON3);
189 }
190
191 /* setup horizontal and vertical display size. */
192 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
193 VIDTCON4_HOZVAL(mode->hdisplay - 1);
194 writel(val, ctx->regs + VIDTCON4);
195
196 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
197
198 /*
199 * fields of register with prefix '_F' would be updated
200 * at vsync(same as dma start)
201 */
202 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
203 writel(val, ctx->regs + VIDCON0);
204
205 clkdiv = decon_calc_clkdiv(ctx, mode);
206 if (clkdiv > 1) {
207 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
208 writel(val, ctx->regs + VCLKCON1);
209 writel(val, ctx->regs + VCLKCON2);
210 }
211
212 val = readl(ctx->regs + DECON_UPDATE);
213 val |= DECON_UPDATE_STANDALONE_F;
214 writel(val, ctx->regs + DECON_UPDATE);
215}
216
217static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
218{
219 struct decon_context *ctx = crtc->ctx;
220 u32 val;
221
222 if (ctx->suspended)
223 return -EPERM;
224
225 if (!test_and_set_bit(0, &ctx->irq_flags)) {
226 val = readl(ctx->regs + VIDINTCON0);
227
228 val |= VIDINTCON0_INT_ENABLE;
229
230 if (!ctx->i80_if) {
231 val |= VIDINTCON0_INT_FRAME;
232 val &= ~VIDINTCON0_FRAMESEL0_MASK;
233 val |= VIDINTCON0_FRAMESEL0_VSYNC;
234 }
235
236 writel(val, ctx->regs + VIDINTCON0);
237 }
238
239 return 0;
240}
241
242static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
243{
244 struct decon_context *ctx = crtc->ctx;
245 u32 val;
246
247 if (ctx->suspended)
248 return;
249
250 if (test_and_clear_bit(0, &ctx->irq_flags)) {
251 val = readl(ctx->regs + VIDINTCON0);
252
253 val &= ~VIDINTCON0_INT_ENABLE;
254 if (!ctx->i80_if)
255 val &= ~VIDINTCON0_INT_FRAME;
256
257 writel(val, ctx->regs + VIDINTCON0);
258 }
259}
260
261static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
262 struct drm_framebuffer *fb)
263{
264 unsigned long val;
265 int padding;
266
267 val = readl(ctx->regs + WINCON(win));
268 val &= ~WINCONx_BPPMODE_MASK;
269
270 switch (fb->format->format) {
271 case DRM_FORMAT_RGB565:
272 val |= WINCONx_BPPMODE_16BPP_565;
273 val |= WINCONx_BURSTLEN_16WORD;
274 break;
275 case DRM_FORMAT_XRGB8888:
276 val |= WINCONx_BPPMODE_24BPP_xRGB;
277 val |= WINCONx_BURSTLEN_16WORD;
278 break;
279 case DRM_FORMAT_XBGR8888:
280 val |= WINCONx_BPPMODE_24BPP_xBGR;
281 val |= WINCONx_BURSTLEN_16WORD;
282 break;
283 case DRM_FORMAT_RGBX8888:
284 val |= WINCONx_BPPMODE_24BPP_RGBx;
285 val |= WINCONx_BURSTLEN_16WORD;
286 break;
287 case DRM_FORMAT_BGRX8888:
288 val |= WINCONx_BPPMODE_24BPP_BGRx;
289 val |= WINCONx_BURSTLEN_16WORD;
290 break;
291 case DRM_FORMAT_ARGB8888:
292 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
293 WINCONx_ALPHA_SEL;
294 val |= WINCONx_BURSTLEN_16WORD;
295 break;
296 case DRM_FORMAT_ABGR8888:
297 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
298 WINCONx_ALPHA_SEL;
299 val |= WINCONx_BURSTLEN_16WORD;
300 break;
301 case DRM_FORMAT_RGBA8888:
302 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
303 WINCONx_ALPHA_SEL;
304 val |= WINCONx_BURSTLEN_16WORD;
305 break;
306 case DRM_FORMAT_BGRA8888:
307 default:
308 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
309 WINCONx_ALPHA_SEL;
310 val |= WINCONx_BURSTLEN_16WORD;
311 break;
312 }
313
314 DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %d\n", fb->format->cpp[0]);
315
316 /*
317 * In case of exynos, setting dma-burst to 16Word causes permanent
318 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
319 * switching which is based on plane size is not recommended as
320 * plane size varies a lot towards the end of the screen and rapid
321 * movement causes unstable DMA which results into iommu crash/tear.
322 */
323
324 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width;
325 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
326 val &= ~WINCONx_BURSTLEN_MASK;
327 val |= WINCONx_BURSTLEN_8WORD;
328 }
329
330 writel(val, ctx->regs + WINCON(win));
331}
332
333static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
334{
335 unsigned int keycon0 = 0, keycon1 = 0;
336
337 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
338 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
339
340 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
341
342 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
343 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
344}
345
346/**
347 * decon_shadow_protect_win() - disable updating values from shadow registers at vsync
348 *
349 * @ctx: display and enhancement controller context
350 * @win: window to protect registers for
351 * @protect: 1 to protect (disable updates)
352 */
353static void decon_shadow_protect_win(struct decon_context *ctx,
354 unsigned int win, bool protect)
355{
356 u32 bits, val;
357
358 bits = SHADOWCON_WINx_PROTECT(win);
359
360 val = readl(ctx->regs + SHADOWCON);
361 if (protect)
362 val |= bits;
363 else
364 val &= ~bits;
365 writel(val, ctx->regs + SHADOWCON);
366}
367
368static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
369{
370 struct decon_context *ctx = crtc->ctx;
371 int i;
372
373 if (ctx->suspended)
374 return;
375
376 for (i = 0; i < WINDOWS_NR; i++)
377 decon_shadow_protect_win(ctx, i, true);
378}
379
380static void decon_update_plane(struct exynos_drm_crtc *crtc,
381 struct exynos_drm_plane *plane)
382{
383 struct exynos_drm_plane_state *state =
384 to_exynos_plane_state(plane->base.state);
385 struct decon_context *ctx = crtc->ctx;
386 struct drm_framebuffer *fb = state->base.fb;
387 int padding;
388 unsigned long val, alpha;
389 unsigned int last_x;
390 unsigned int last_y;
391 unsigned int win = plane->index;
392 unsigned int cpp = fb->format->cpp[0];
393 unsigned int pitch = fb->pitches[0];
394
395 if (ctx->suspended)
396 return;
397
398 /*
399 * SHADOWCON/PRTCON register is used for enabling timing.
400 *
401 * for example, once only width value of a register is set,
402 * if the dma is started then decon hardware could malfunction so
403 * with protect window setting, the register fields with prefix '_F'
404 * wouldn't be updated at vsync also but updated once unprotect window
405 * is set.
406 */
407
408 /* buffer start address */
409 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
410 writel(val, ctx->regs + VIDW_BUF_START(win));
411
412 padding = (pitch / cpp) - fb->width;
413
414 /* buffer size */
415 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
416 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
417
418 /* offset from the start of the buffer to read */
419 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
420 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
421
422 DRM_DEV_DEBUG_KMS(ctx->dev, "start addr = 0x%lx\n",
423 (unsigned long)val);
424 DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
425 state->crtc.w, state->crtc.h);
426
427 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
428 VIDOSDxA_TOPLEFT_Y(state->crtc.y);
429 writel(val, ctx->regs + VIDOSD_A(win));
430
431 last_x = state->crtc.x + state->crtc.w;
432 if (last_x)
433 last_x--;
434 last_y = state->crtc.y + state->crtc.h;
435 if (last_y)
436 last_y--;
437
438 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
439
440 writel(val, ctx->regs + VIDOSD_B(win));
441
442 DRM_DEV_DEBUG_KMS(ctx->dev, "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
443 state->crtc.x, state->crtc.y, last_x, last_y);
444
445 /* OSD alpha */
446 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
447 VIDOSDxC_ALPHA0_G_F(0x0) |
448 VIDOSDxC_ALPHA0_B_F(0x0);
449
450 writel(alpha, ctx->regs + VIDOSD_C(win));
451
452 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
453 VIDOSDxD_ALPHA1_G_F(0xff) |
454 VIDOSDxD_ALPHA1_B_F(0xff);
455
456 writel(alpha, ctx->regs + VIDOSD_D(win));
457
458 decon_win_set_pixfmt(ctx, win, fb);
459
460 /* hardware window 0 doesn't support color key. */
461 if (win != 0)
462 decon_win_set_colkey(ctx, win);
463
464 /* wincon */
465 val = readl(ctx->regs + WINCON(win));
466 val |= WINCONx_TRIPLE_BUF_MODE;
467 val |= WINCONx_ENWIN;
468 writel(val, ctx->regs + WINCON(win));
469
470 /* Enable DMA channel and unprotect windows */
471 decon_shadow_protect_win(ctx, win, false);
472
473 val = readl(ctx->regs + DECON_UPDATE);
474 val |= DECON_UPDATE_STANDALONE_F;
475 writel(val, ctx->regs + DECON_UPDATE);
476}
477
478static void decon_disable_plane(struct exynos_drm_crtc *crtc,
479 struct exynos_drm_plane *plane)
480{
481 struct decon_context *ctx = crtc->ctx;
482 unsigned int win = plane->index;
483 u32 val;
484
485 if (ctx->suspended)
486 return;
487
488 /* protect windows */
489 decon_shadow_protect_win(ctx, win, true);
490
491 /* wincon */
492 val = readl(ctx->regs + WINCON(win));
493 val &= ~WINCONx_ENWIN;
494 writel(val, ctx->regs + WINCON(win));
495
496 val = readl(ctx->regs + DECON_UPDATE);
497 val |= DECON_UPDATE_STANDALONE_F;
498 writel(val, ctx->regs + DECON_UPDATE);
499}
500
501static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
502{
503 struct decon_context *ctx = crtc->ctx;
504 int i;
505
506 if (ctx->suspended)
507 return;
508
509 for (i = 0; i < WINDOWS_NR; i++)
510 decon_shadow_protect_win(ctx, i, false);
511 exynos_crtc_handle_event(crtc);
512}
513
514static void decon_init(struct decon_context *ctx)
515{
516 u32 val;
517
518 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
519
520 val = VIDOUTCON0_DISP_IF_0_ON;
521 if (!ctx->i80_if)
522 val |= VIDOUTCON0_RGBIF;
523 writel(val, ctx->regs + VIDOUTCON0);
524
525 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
526
527 if (!ctx->i80_if)
528 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
529}
530
531static void decon_atomic_enable(struct exynos_drm_crtc *crtc)
532{
533 struct decon_context *ctx = crtc->ctx;
534 int ret;
535
536 if (!ctx->suspended)
537 return;
538
539 ret = pm_runtime_resume_and_get(ctx->dev);
540 if (ret < 0) {
541 DRM_DEV_ERROR(ctx->dev, "failed to enable DECON device.\n");
542 return;
543 }
544
545 decon_init(ctx);
546
547 /* if vblank was enabled status, enable it again. */
548 if (test_and_clear_bit(0, &ctx->irq_flags))
549 decon_enable_vblank(ctx->crtc);
550
551 decon_commit(ctx->crtc);
552
553 ctx->suspended = false;
554}
555
556static void decon_atomic_disable(struct exynos_drm_crtc *crtc)
557{
558 struct decon_context *ctx = crtc->ctx;
559 int i;
560
561 if (ctx->suspended)
562 return;
563
564 /*
565 * We need to make sure that all windows are disabled before we
566 * suspend that connector. Otherwise we might try to scan from
567 * a destroyed buffer later.
568 */
569 for (i = 0; i < WINDOWS_NR; i++)
570 decon_disable_plane(crtc, &ctx->planes[i]);
571
572 pm_runtime_put_sync(ctx->dev);
573
574 ctx->suspended = true;
575}
576
577static const struct exynos_drm_crtc_ops decon_crtc_ops = {
578 .atomic_enable = decon_atomic_enable,
579 .atomic_disable = decon_atomic_disable,
580 .enable_vblank = decon_enable_vblank,
581 .disable_vblank = decon_disable_vblank,
582 .atomic_begin = decon_atomic_begin,
583 .update_plane = decon_update_plane,
584 .disable_plane = decon_disable_plane,
585 .atomic_flush = decon_atomic_flush,
586};
587
588
589static irqreturn_t decon_irq_handler(int irq, void *dev_id)
590{
591 struct decon_context *ctx = (struct decon_context *)dev_id;
592 u32 val, clear_bit;
593
594 val = readl(ctx->regs + VIDINTCON1);
595
596 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
597 if (val & clear_bit)
598 writel(clear_bit, ctx->regs + VIDINTCON1);
599
600 /* check the crtc is detached already from encoder */
601 if (!ctx->drm_dev)
602 goto out;
603
604 if (!ctx->i80_if) {
605 drm_crtc_handle_vblank(&ctx->crtc->base);
606
607 /* set wait vsync event to zero and wake up queue. */
608 if (atomic_read(&ctx->wait_vsync_event)) {
609 atomic_set(&ctx->wait_vsync_event, 0);
610 wake_up(&ctx->wait_vsync_queue);
611 }
612 }
613out:
614 return IRQ_HANDLED;
615}
616
617static int decon_bind(struct device *dev, struct device *master, void *data)
618{
619 struct decon_context *ctx = dev_get_drvdata(dev);
620 struct drm_device *drm_dev = data;
621 struct exynos_drm_plane *exynos_plane;
622 unsigned int i;
623 int ret;
624
625 ret = decon_ctx_initialize(ctx, drm_dev);
626 if (ret) {
627 DRM_DEV_ERROR(dev, "decon_ctx_initialize failed.\n");
628 return ret;
629 }
630
631 for (i = 0; i < WINDOWS_NR; i++) {
632 ctx->configs[i].pixel_formats = decon_formats;
633 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
634 ctx->configs[i].zpos = i;
635 ctx->configs[i].type = decon_win_types[i];
636
637 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
638 &ctx->configs[i]);
639 if (ret)
640 return ret;
641 }
642
643 exynos_plane = &ctx->planes[DEFAULT_WIN];
644 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
645 EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx);
646 if (IS_ERR(ctx->crtc)) {
647 decon_ctx_remove(ctx);
648 return PTR_ERR(ctx->crtc);
649 }
650
651 if (ctx->encoder)
652 exynos_dpi_bind(drm_dev, ctx->encoder);
653
654 return 0;
655
656}
657
658static void decon_unbind(struct device *dev, struct device *master,
659 void *data)
660{
661 struct decon_context *ctx = dev_get_drvdata(dev);
662
663 decon_atomic_disable(ctx->crtc);
664
665 if (ctx->encoder)
666 exynos_dpi_remove(ctx->encoder);
667
668 decon_ctx_remove(ctx);
669}
670
671static const struct component_ops decon_component_ops = {
672 .bind = decon_bind,
673 .unbind = decon_unbind,
674};
675
676static int decon_probe(struct platform_device *pdev)
677{
678 struct device *dev = &pdev->dev;
679 struct decon_context *ctx;
680 struct device_node *i80_if_timings;
681 struct resource *res;
682 int ret;
683
684 if (!dev->of_node)
685 return -ENODEV;
686
687 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
688 if (!ctx)
689 return -ENOMEM;
690
691 ctx->dev = dev;
692 ctx->suspended = true;
693
694 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
695 if (i80_if_timings)
696 ctx->i80_if = true;
697 of_node_put(i80_if_timings);
698
699 ctx->regs = of_iomap(dev->of_node, 0);
700 if (!ctx->regs)
701 return -ENOMEM;
702
703 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
704 if (IS_ERR(ctx->pclk)) {
705 dev_err(dev, "failed to get bus clock pclk\n");
706 ret = PTR_ERR(ctx->pclk);
707 goto err_iounmap;
708 }
709
710 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
711 if (IS_ERR(ctx->aclk)) {
712 dev_err(dev, "failed to get bus clock aclk\n");
713 ret = PTR_ERR(ctx->aclk);
714 goto err_iounmap;
715 }
716
717 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
718 if (IS_ERR(ctx->eclk)) {
719 dev_err(dev, "failed to get eclock\n");
720 ret = PTR_ERR(ctx->eclk);
721 goto err_iounmap;
722 }
723
724 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
725 if (IS_ERR(ctx->vclk)) {
726 dev_err(dev, "failed to get vclock\n");
727 ret = PTR_ERR(ctx->vclk);
728 goto err_iounmap;
729 }
730
731 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
732 ctx->i80_if ? "lcd_sys" : "vsync");
733 if (!res) {
734 dev_err(dev, "irq request failed.\n");
735 ret = -ENXIO;
736 goto err_iounmap;
737 }
738
739 ret = devm_request_irq(dev, res->start, decon_irq_handler,
740 0, "drm_decon", ctx);
741 if (ret) {
742 dev_err(dev, "irq request failed.\n");
743 goto err_iounmap;
744 }
745
746 init_waitqueue_head(&ctx->wait_vsync_queue);
747 atomic_set(&ctx->wait_vsync_event, 0);
748
749 platform_set_drvdata(pdev, ctx);
750
751 ctx->encoder = exynos_dpi_probe(dev);
752 if (IS_ERR(ctx->encoder)) {
753 ret = PTR_ERR(ctx->encoder);
754 goto err_iounmap;
755 }
756
757 pm_runtime_enable(dev);
758
759 ret = component_add(dev, &decon_component_ops);
760 if (ret)
761 goto err_disable_pm_runtime;
762
763 return ret;
764
765err_disable_pm_runtime:
766 pm_runtime_disable(dev);
767
768err_iounmap:
769 iounmap(ctx->regs);
770
771 return ret;
772}
773
774static int decon_remove(struct platform_device *pdev)
775{
776 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
777
778 pm_runtime_disable(&pdev->dev);
779
780 iounmap(ctx->regs);
781
782 component_del(&pdev->dev, &decon_component_ops);
783
784 return 0;
785}
786
787#ifdef CONFIG_PM
788static int exynos7_decon_suspend(struct device *dev)
789{
790 struct decon_context *ctx = dev_get_drvdata(dev);
791
792 clk_disable_unprepare(ctx->vclk);
793 clk_disable_unprepare(ctx->eclk);
794 clk_disable_unprepare(ctx->aclk);
795 clk_disable_unprepare(ctx->pclk);
796
797 return 0;
798}
799
800static int exynos7_decon_resume(struct device *dev)
801{
802 struct decon_context *ctx = dev_get_drvdata(dev);
803 int ret;
804
805 ret = clk_prepare_enable(ctx->pclk);
806 if (ret < 0) {
807 DRM_DEV_ERROR(dev, "Failed to prepare_enable the pclk [%d]\n",
808 ret);
809 return ret;
810 }
811
812 ret = clk_prepare_enable(ctx->aclk);
813 if (ret < 0) {
814 DRM_DEV_ERROR(dev, "Failed to prepare_enable the aclk [%d]\n",
815 ret);
816 return ret;
817 }
818
819 ret = clk_prepare_enable(ctx->eclk);
820 if (ret < 0) {
821 DRM_DEV_ERROR(dev, "Failed to prepare_enable the eclk [%d]\n",
822 ret);
823 return ret;
824 }
825
826 ret = clk_prepare_enable(ctx->vclk);
827 if (ret < 0) {
828 DRM_DEV_ERROR(dev, "Failed to prepare_enable the vclk [%d]\n",
829 ret);
830 return ret;
831 }
832
833 return 0;
834}
835#endif
836
837static const struct dev_pm_ops exynos7_decon_pm_ops = {
838 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
839 NULL)
840 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
841 pm_runtime_force_resume)
842};
843
844struct platform_driver decon_driver = {
845 .probe = decon_probe,
846 .remove = decon_remove,
847 .driver = {
848 .name = "exynos-decon",
849 .pm = &exynos7_decon_pm_ops,
850 .of_match_table = decon_driver_dt_match,
851 },
852};