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1/*
2 * Library implementing the most common irq chip callback functions
3 *
4 * Copyright (C) 2011, Thomas Gleixner
5 */
6#include <linux/io.h>
7#include <linux/irq.h>
8#include <linux/slab.h>
9#include <linux/export.h>
10#include <linux/irqdomain.h>
11#include <linux/interrupt.h>
12#include <linux/kernel_stat.h>
13#include <linux/syscore_ops.h>
14
15#include "internals.h"
16
17static LIST_HEAD(gc_list);
18static DEFINE_RAW_SPINLOCK(gc_lock);
19
20/**
21 * irq_gc_noop - NOOP function
22 * @d: irq_data
23 */
24void irq_gc_noop(struct irq_data *d)
25{
26}
27
28/**
29 * irq_gc_mask_disable_reg - Mask chip via disable register
30 * @d: irq_data
31 *
32 * Chip has separate enable/disable registers instead of a single mask
33 * register.
34 */
35void irq_gc_mask_disable_reg(struct irq_data *d)
36{
37 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38 struct irq_chip_type *ct = irq_data_get_chip_type(d);
39 u32 mask = d->mask;
40
41 irq_gc_lock(gc);
42 irq_reg_writel(gc, mask, ct->regs.disable);
43 *ct->mask_cache &= ~mask;
44 irq_gc_unlock(gc);
45}
46
47/**
48 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
49 * @d: irq_data
50 *
51 * Chip has a single mask register. Values of this register are cached
52 * and protected by gc->lock
53 */
54void irq_gc_mask_set_bit(struct irq_data *d)
55{
56 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
57 struct irq_chip_type *ct = irq_data_get_chip_type(d);
58 u32 mask = d->mask;
59
60 irq_gc_lock(gc);
61 *ct->mask_cache |= mask;
62 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
63 irq_gc_unlock(gc);
64}
65EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
66
67/**
68 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
69 * @d: irq_data
70 *
71 * Chip has a single mask register. Values of this register are cached
72 * and protected by gc->lock
73 */
74void irq_gc_mask_clr_bit(struct irq_data *d)
75{
76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 struct irq_chip_type *ct = irq_data_get_chip_type(d);
78 u32 mask = d->mask;
79
80 irq_gc_lock(gc);
81 *ct->mask_cache &= ~mask;
82 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
83 irq_gc_unlock(gc);
84}
85EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
86
87/**
88 * irq_gc_unmask_enable_reg - Unmask chip via enable register
89 * @d: irq_data
90 *
91 * Chip has separate enable/disable registers instead of a single mask
92 * register.
93 */
94void irq_gc_unmask_enable_reg(struct irq_data *d)
95{
96 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
97 struct irq_chip_type *ct = irq_data_get_chip_type(d);
98 u32 mask = d->mask;
99
100 irq_gc_lock(gc);
101 irq_reg_writel(gc, mask, ct->regs.enable);
102 *ct->mask_cache |= mask;
103 irq_gc_unlock(gc);
104}
105
106/**
107 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
108 * @d: irq_data
109 */
110void irq_gc_ack_set_bit(struct irq_data *d)
111{
112 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
113 struct irq_chip_type *ct = irq_data_get_chip_type(d);
114 u32 mask = d->mask;
115
116 irq_gc_lock(gc);
117 irq_reg_writel(gc, mask, ct->regs.ack);
118 irq_gc_unlock(gc);
119}
120EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
121
122/**
123 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
124 * @d: irq_data
125 */
126void irq_gc_ack_clr_bit(struct irq_data *d)
127{
128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
129 struct irq_chip_type *ct = irq_data_get_chip_type(d);
130 u32 mask = ~d->mask;
131
132 irq_gc_lock(gc);
133 irq_reg_writel(gc, mask, ct->regs.ack);
134 irq_gc_unlock(gc);
135}
136
137/**
138 * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
139 * @d: irq_data
140 */
141void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
142{
143 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
144 struct irq_chip_type *ct = irq_data_get_chip_type(d);
145 u32 mask = d->mask;
146
147 irq_gc_lock(gc);
148 irq_reg_writel(gc, mask, ct->regs.mask);
149 irq_reg_writel(gc, mask, ct->regs.ack);
150 irq_gc_unlock(gc);
151}
152
153/**
154 * irq_gc_eoi - EOI interrupt
155 * @d: irq_data
156 */
157void irq_gc_eoi(struct irq_data *d)
158{
159 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
160 struct irq_chip_type *ct = irq_data_get_chip_type(d);
161 u32 mask = d->mask;
162
163 irq_gc_lock(gc);
164 irq_reg_writel(gc, mask, ct->regs.eoi);
165 irq_gc_unlock(gc);
166}
167
168/**
169 * irq_gc_set_wake - Set/clr wake bit for an interrupt
170 * @d: irq_data
171 * @on: Indicates whether the wake bit should be set or cleared
172 *
173 * For chips where the wake from suspend functionality is not
174 * configured in a separate register and the wakeup active state is
175 * just stored in a bitmask.
176 */
177int irq_gc_set_wake(struct irq_data *d, unsigned int on)
178{
179 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
180 u32 mask = d->mask;
181
182 if (!(mask & gc->wake_enabled))
183 return -EINVAL;
184
185 irq_gc_lock(gc);
186 if (on)
187 gc->wake_active |= mask;
188 else
189 gc->wake_active &= ~mask;
190 irq_gc_unlock(gc);
191 return 0;
192}
193
194static u32 irq_readl_be(void __iomem *addr)
195{
196 return ioread32be(addr);
197}
198
199static void irq_writel_be(u32 val, void __iomem *addr)
200{
201 iowrite32be(val, addr);
202}
203
204static void
205irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
206 int num_ct, unsigned int irq_base,
207 void __iomem *reg_base, irq_flow_handler_t handler)
208{
209 raw_spin_lock_init(&gc->lock);
210 gc->num_ct = num_ct;
211 gc->irq_base = irq_base;
212 gc->reg_base = reg_base;
213 gc->chip_types->chip.name = name;
214 gc->chip_types->handler = handler;
215}
216
217/**
218 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
219 * @name: Name of the irq chip
220 * @num_ct: Number of irq_chip_type instances associated with this
221 * @irq_base: Interrupt base nr for this chip
222 * @reg_base: Register base address (virtual)
223 * @handler: Default flow handler associated with this chip
224 *
225 * Returns an initialized irq_chip_generic structure. The chip defaults
226 * to the primary (index 0) irq_chip_type and @handler
227 */
228struct irq_chip_generic *
229irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
230 void __iomem *reg_base, irq_flow_handler_t handler)
231{
232 struct irq_chip_generic *gc;
233 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
234
235 gc = kzalloc(sz, GFP_KERNEL);
236 if (gc) {
237 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
238 handler);
239 }
240 return gc;
241}
242EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
243
244static void
245irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
246{
247 struct irq_chip_type *ct = gc->chip_types;
248 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
249 int i;
250
251 for (i = 0; i < gc->num_ct; i++) {
252 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
253 mskptr = &ct[i].mask_cache_priv;
254 mskreg = ct[i].regs.mask;
255 }
256 ct[i].mask_cache = mskptr;
257 if (flags & IRQ_GC_INIT_MASK_CACHE)
258 *mskptr = irq_reg_readl(gc, mskreg);
259 }
260}
261
262/**
263 * __irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
264 * @d: irq domain for which to allocate chips
265 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
266 * @num_ct: Number of irq_chip_type instances associated with this
267 * @name: Name of the irq chip
268 * @handler: Default flow handler associated with these chips
269 * @clr: IRQ_* bits to clear in the mapping function
270 * @set: IRQ_* bits to set in the mapping function
271 * @gcflags: Generic chip specific setup flags
272 */
273int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
274 int num_ct, const char *name,
275 irq_flow_handler_t handler,
276 unsigned int clr, unsigned int set,
277 enum irq_gc_flags gcflags)
278{
279 struct irq_domain_chip_generic *dgc;
280 struct irq_chip_generic *gc;
281 int numchips, sz, i;
282 unsigned long flags;
283 void *tmp;
284
285 if (d->gc)
286 return -EBUSY;
287
288 numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
289 if (!numchips)
290 return -EINVAL;
291
292 /* Allocate a pointer, generic chip and chiptypes for each chip */
293 sz = sizeof(*dgc) + numchips * sizeof(gc);
294 sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
295
296 tmp = dgc = kzalloc(sz, GFP_KERNEL);
297 if (!dgc)
298 return -ENOMEM;
299 dgc->irqs_per_chip = irqs_per_chip;
300 dgc->num_chips = numchips;
301 dgc->irq_flags_to_set = set;
302 dgc->irq_flags_to_clear = clr;
303 dgc->gc_flags = gcflags;
304 d->gc = dgc;
305
306 /* Calc pointer to the first generic chip */
307 tmp += sizeof(*dgc) + numchips * sizeof(gc);
308 for (i = 0; i < numchips; i++) {
309 /* Store the pointer to the generic chip */
310 dgc->gc[i] = gc = tmp;
311 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
312 NULL, handler);
313
314 gc->domain = d;
315 if (gcflags & IRQ_GC_BE_IO) {
316 gc->reg_readl = &irq_readl_be;
317 gc->reg_writel = &irq_writel_be;
318 }
319
320 raw_spin_lock_irqsave(&gc_lock, flags);
321 list_add_tail(&gc->list, &gc_list);
322 raw_spin_unlock_irqrestore(&gc_lock, flags);
323 /* Calc pointer to the next generic chip */
324 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
325 }
326 d->name = name;
327 return 0;
328}
329EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
330
331static struct irq_chip_generic *
332__irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
333{
334 struct irq_domain_chip_generic *dgc = d->gc;
335 int idx;
336
337 if (!dgc)
338 return ERR_PTR(-ENODEV);
339 idx = hw_irq / dgc->irqs_per_chip;
340 if (idx >= dgc->num_chips)
341 return ERR_PTR(-EINVAL);
342 return dgc->gc[idx];
343}
344
345/**
346 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
347 * @d: irq domain pointer
348 * @hw_irq: Hardware interrupt number
349 */
350struct irq_chip_generic *
351irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
352{
353 struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
354
355 return !IS_ERR(gc) ? gc : NULL;
356}
357EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
358
359/*
360 * Separate lockdep class for interrupt chip which can nest irq_desc
361 * lock.
362 */
363static struct lock_class_key irq_nested_lock_class;
364
365/*
366 * irq_map_generic_chip - Map a generic chip for an irq domain
367 */
368int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
369 irq_hw_number_t hw_irq)
370{
371 struct irq_data *data = irq_domain_get_irq_data(d, virq);
372 struct irq_domain_chip_generic *dgc = d->gc;
373 struct irq_chip_generic *gc;
374 struct irq_chip_type *ct;
375 struct irq_chip *chip;
376 unsigned long flags;
377 int idx;
378
379 gc = __irq_get_domain_generic_chip(d, hw_irq);
380 if (IS_ERR(gc))
381 return PTR_ERR(gc);
382
383 idx = hw_irq % dgc->irqs_per_chip;
384
385 if (test_bit(idx, &gc->unused))
386 return -ENOTSUPP;
387
388 if (test_bit(idx, &gc->installed))
389 return -EBUSY;
390
391 ct = gc->chip_types;
392 chip = &ct->chip;
393
394 /* We only init the cache for the first mapping of a generic chip */
395 if (!gc->installed) {
396 raw_spin_lock_irqsave(&gc->lock, flags);
397 irq_gc_init_mask_cache(gc, dgc->gc_flags);
398 raw_spin_unlock_irqrestore(&gc->lock, flags);
399 }
400
401 /* Mark the interrupt as installed */
402 set_bit(idx, &gc->installed);
403
404 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
405 irq_set_lockdep_class(virq, &irq_nested_lock_class);
406
407 if (chip->irq_calc_mask)
408 chip->irq_calc_mask(data);
409 else
410 data->mask = 1 << idx;
411
412 irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
413 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
414 return 0;
415}
416
417static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
418{
419 struct irq_data *data = irq_domain_get_irq_data(d, virq);
420 struct irq_domain_chip_generic *dgc = d->gc;
421 unsigned int hw_irq = data->hwirq;
422 struct irq_chip_generic *gc;
423 int irq_idx;
424
425 gc = irq_get_domain_generic_chip(d, hw_irq);
426 if (!gc)
427 return;
428
429 irq_idx = hw_irq % dgc->irqs_per_chip;
430
431 clear_bit(irq_idx, &gc->installed);
432 irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
433 NULL);
434
435}
436
437struct irq_domain_ops irq_generic_chip_ops = {
438 .map = irq_map_generic_chip,
439 .unmap = irq_unmap_generic_chip,
440 .xlate = irq_domain_xlate_onetwocell,
441};
442EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
443
444/**
445 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
446 * @gc: Generic irq chip holding all data
447 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
448 * @flags: Flags for initialization
449 * @clr: IRQ_* bits to clear
450 * @set: IRQ_* bits to set
451 *
452 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
453 * initializes all interrupts to the primary irq_chip_type and its
454 * associated handler.
455 */
456void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
457 enum irq_gc_flags flags, unsigned int clr,
458 unsigned int set)
459{
460 struct irq_chip_type *ct = gc->chip_types;
461 struct irq_chip *chip = &ct->chip;
462 unsigned int i;
463
464 raw_spin_lock(&gc_lock);
465 list_add_tail(&gc->list, &gc_list);
466 raw_spin_unlock(&gc_lock);
467
468 irq_gc_init_mask_cache(gc, flags);
469
470 for (i = gc->irq_base; msk; msk >>= 1, i++) {
471 if (!(msk & 0x01))
472 continue;
473
474 if (flags & IRQ_GC_INIT_NESTED_LOCK)
475 irq_set_lockdep_class(i, &irq_nested_lock_class);
476
477 if (!(flags & IRQ_GC_NO_MASK)) {
478 struct irq_data *d = irq_get_irq_data(i);
479
480 if (chip->irq_calc_mask)
481 chip->irq_calc_mask(d);
482 else
483 d->mask = 1 << (i - gc->irq_base);
484 }
485 irq_set_chip_and_handler(i, chip, ct->handler);
486 irq_set_chip_data(i, gc);
487 irq_modify_status(i, clr, set);
488 }
489 gc->irq_cnt = i - gc->irq_base;
490}
491EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
492
493/**
494 * irq_setup_alt_chip - Switch to alternative chip
495 * @d: irq_data for this interrupt
496 * @type: Flow type to be initialized
497 *
498 * Only to be called from chip->irq_set_type() callbacks.
499 */
500int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
501{
502 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
503 struct irq_chip_type *ct = gc->chip_types;
504 unsigned int i;
505
506 for (i = 0; i < gc->num_ct; i++, ct++) {
507 if (ct->type & type) {
508 d->chip = &ct->chip;
509 irq_data_to_desc(d)->handle_irq = ct->handler;
510 return 0;
511 }
512 }
513 return -EINVAL;
514}
515EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
516
517/**
518 * irq_remove_generic_chip - Remove a chip
519 * @gc: Generic irq chip holding all data
520 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
521 * @clr: IRQ_* bits to clear
522 * @set: IRQ_* bits to set
523 *
524 * Remove up to 32 interrupts starting from gc->irq_base.
525 */
526void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
527 unsigned int clr, unsigned int set)
528{
529 unsigned int i = gc->irq_base;
530
531 raw_spin_lock(&gc_lock);
532 list_del(&gc->list);
533 raw_spin_unlock(&gc_lock);
534
535 for (; msk; msk >>= 1, i++) {
536 if (!(msk & 0x01))
537 continue;
538
539 /* Remove handler first. That will mask the irq line */
540 irq_set_handler(i, NULL);
541 irq_set_chip(i, &no_irq_chip);
542 irq_set_chip_data(i, NULL);
543 irq_modify_status(i, clr, set);
544 }
545}
546EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
547
548static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
549{
550 unsigned int virq;
551
552 if (!gc->domain)
553 return irq_get_irq_data(gc->irq_base);
554
555 /*
556 * We don't know which of the irqs has been actually
557 * installed. Use the first one.
558 */
559 if (!gc->installed)
560 return NULL;
561
562 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
563 return virq ? irq_get_irq_data(virq) : NULL;
564}
565
566#ifdef CONFIG_PM
567static int irq_gc_suspend(void)
568{
569 struct irq_chip_generic *gc;
570
571 list_for_each_entry(gc, &gc_list, list) {
572 struct irq_chip_type *ct = gc->chip_types;
573
574 if (ct->chip.irq_suspend) {
575 struct irq_data *data = irq_gc_get_irq_data(gc);
576
577 if (data)
578 ct->chip.irq_suspend(data);
579 }
580
581 if (gc->suspend)
582 gc->suspend(gc);
583 }
584 return 0;
585}
586
587static void irq_gc_resume(void)
588{
589 struct irq_chip_generic *gc;
590
591 list_for_each_entry(gc, &gc_list, list) {
592 struct irq_chip_type *ct = gc->chip_types;
593
594 if (gc->resume)
595 gc->resume(gc);
596
597 if (ct->chip.irq_resume) {
598 struct irq_data *data = irq_gc_get_irq_data(gc);
599
600 if (data)
601 ct->chip.irq_resume(data);
602 }
603 }
604}
605#else
606#define irq_gc_suspend NULL
607#define irq_gc_resume NULL
608#endif
609
610static void irq_gc_shutdown(void)
611{
612 struct irq_chip_generic *gc;
613
614 list_for_each_entry(gc, &gc_list, list) {
615 struct irq_chip_type *ct = gc->chip_types;
616
617 if (ct->chip.irq_pm_shutdown) {
618 struct irq_data *data = irq_gc_get_irq_data(gc);
619
620 if (data)
621 ct->chip.irq_pm_shutdown(data);
622 }
623 }
624}
625
626static struct syscore_ops irq_gc_syscore_ops = {
627 .suspend = irq_gc_suspend,
628 .resume = irq_gc_resume,
629 .shutdown = irq_gc_shutdown,
630};
631
632static int __init irq_gc_init_ops(void)
633{
634 register_syscore_ops(&irq_gc_syscore_ops);
635 return 0;
636}
637device_initcall(irq_gc_init_ops);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Library implementing the most common irq chip callback functions
4 *
5 * Copyright (C) 2011, Thomas Gleixner
6 */
7#include <linux/io.h>
8#include <linux/irq.h>
9#include <linux/slab.h>
10#include <linux/export.h>
11#include <linux/irqdomain.h>
12#include <linux/interrupt.h>
13#include <linux/kernel_stat.h>
14#include <linux/syscore_ops.h>
15
16#include "internals.h"
17
18static LIST_HEAD(gc_list);
19static DEFINE_RAW_SPINLOCK(gc_lock);
20
21/**
22 * irq_gc_noop - NOOP function
23 * @d: irq_data
24 */
25void irq_gc_noop(struct irq_data *d)
26{
27}
28
29/**
30 * irq_gc_mask_disable_reg - Mask chip via disable register
31 * @d: irq_data
32 *
33 * Chip has separate enable/disable registers instead of a single mask
34 * register.
35 */
36void irq_gc_mask_disable_reg(struct irq_data *d)
37{
38 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
39 struct irq_chip_type *ct = irq_data_get_chip_type(d);
40 u32 mask = d->mask;
41
42 irq_gc_lock(gc);
43 irq_reg_writel(gc, mask, ct->regs.disable);
44 *ct->mask_cache &= ~mask;
45 irq_gc_unlock(gc);
46}
47
48/**
49 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
50 * @d: irq_data
51 *
52 * Chip has a single mask register. Values of this register are cached
53 * and protected by gc->lock
54 */
55void irq_gc_mask_set_bit(struct irq_data *d)
56{
57 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
58 struct irq_chip_type *ct = irq_data_get_chip_type(d);
59 u32 mask = d->mask;
60
61 irq_gc_lock(gc);
62 *ct->mask_cache |= mask;
63 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
64 irq_gc_unlock(gc);
65}
66EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
67
68/**
69 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
70 * @d: irq_data
71 *
72 * Chip has a single mask register. Values of this register are cached
73 * and protected by gc->lock
74 */
75void irq_gc_mask_clr_bit(struct irq_data *d)
76{
77 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
78 struct irq_chip_type *ct = irq_data_get_chip_type(d);
79 u32 mask = d->mask;
80
81 irq_gc_lock(gc);
82 *ct->mask_cache &= ~mask;
83 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
84 irq_gc_unlock(gc);
85}
86EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
87
88/**
89 * irq_gc_unmask_enable_reg - Unmask chip via enable register
90 * @d: irq_data
91 *
92 * Chip has separate enable/disable registers instead of a single mask
93 * register.
94 */
95void irq_gc_unmask_enable_reg(struct irq_data *d)
96{
97 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
98 struct irq_chip_type *ct = irq_data_get_chip_type(d);
99 u32 mask = d->mask;
100
101 irq_gc_lock(gc);
102 irq_reg_writel(gc, mask, ct->regs.enable);
103 *ct->mask_cache |= mask;
104 irq_gc_unlock(gc);
105}
106
107/**
108 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
109 * @d: irq_data
110 */
111void irq_gc_ack_set_bit(struct irq_data *d)
112{
113 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
114 struct irq_chip_type *ct = irq_data_get_chip_type(d);
115 u32 mask = d->mask;
116
117 irq_gc_lock(gc);
118 irq_reg_writel(gc, mask, ct->regs.ack);
119 irq_gc_unlock(gc);
120}
121EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
122
123/**
124 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
125 * @d: irq_data
126 */
127void irq_gc_ack_clr_bit(struct irq_data *d)
128{
129 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
130 struct irq_chip_type *ct = irq_data_get_chip_type(d);
131 u32 mask = ~d->mask;
132
133 irq_gc_lock(gc);
134 irq_reg_writel(gc, mask, ct->regs.ack);
135 irq_gc_unlock(gc);
136}
137
138/**
139 * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
140 * @d: irq_data
141 *
142 * This generic implementation of the irq_mask_ack method is for chips
143 * with separate enable/disable registers instead of a single mask
144 * register and where a pending interrupt is acknowledged by setting a
145 * bit.
146 *
147 * Note: This is the only permutation currently used. Similar generic
148 * functions should be added here if other permutations are required.
149 */
150void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
151{
152 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
153 struct irq_chip_type *ct = irq_data_get_chip_type(d);
154 u32 mask = d->mask;
155
156 irq_gc_lock(gc);
157 irq_reg_writel(gc, mask, ct->regs.disable);
158 *ct->mask_cache &= ~mask;
159 irq_reg_writel(gc, mask, ct->regs.ack);
160 irq_gc_unlock(gc);
161}
162
163/**
164 * irq_gc_eoi - EOI interrupt
165 * @d: irq_data
166 */
167void irq_gc_eoi(struct irq_data *d)
168{
169 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
170 struct irq_chip_type *ct = irq_data_get_chip_type(d);
171 u32 mask = d->mask;
172
173 irq_gc_lock(gc);
174 irq_reg_writel(gc, mask, ct->regs.eoi);
175 irq_gc_unlock(gc);
176}
177
178/**
179 * irq_gc_set_wake - Set/clr wake bit for an interrupt
180 * @d: irq_data
181 * @on: Indicates whether the wake bit should be set or cleared
182 *
183 * For chips where the wake from suspend functionality is not
184 * configured in a separate register and the wakeup active state is
185 * just stored in a bitmask.
186 */
187int irq_gc_set_wake(struct irq_data *d, unsigned int on)
188{
189 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
190 u32 mask = d->mask;
191
192 if (!(mask & gc->wake_enabled))
193 return -EINVAL;
194
195 irq_gc_lock(gc);
196 if (on)
197 gc->wake_active |= mask;
198 else
199 gc->wake_active &= ~mask;
200 irq_gc_unlock(gc);
201 return 0;
202}
203EXPORT_SYMBOL_GPL(irq_gc_set_wake);
204
205static u32 irq_readl_be(void __iomem *addr)
206{
207 return ioread32be(addr);
208}
209
210static void irq_writel_be(u32 val, void __iomem *addr)
211{
212 iowrite32be(val, addr);
213}
214
215void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
216 int num_ct, unsigned int irq_base,
217 void __iomem *reg_base, irq_flow_handler_t handler)
218{
219 raw_spin_lock_init(&gc->lock);
220 gc->num_ct = num_ct;
221 gc->irq_base = irq_base;
222 gc->reg_base = reg_base;
223 gc->chip_types->chip.name = name;
224 gc->chip_types->handler = handler;
225}
226
227/**
228 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
229 * @name: Name of the irq chip
230 * @num_ct: Number of irq_chip_type instances associated with this
231 * @irq_base: Interrupt base nr for this chip
232 * @reg_base: Register base address (virtual)
233 * @handler: Default flow handler associated with this chip
234 *
235 * Returns an initialized irq_chip_generic structure. The chip defaults
236 * to the primary (index 0) irq_chip_type and @handler
237 */
238struct irq_chip_generic *
239irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
240 void __iomem *reg_base, irq_flow_handler_t handler)
241{
242 struct irq_chip_generic *gc;
243 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
244
245 gc = kzalloc(sz, GFP_KERNEL);
246 if (gc) {
247 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
248 handler);
249 }
250 return gc;
251}
252EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
253
254static void
255irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
256{
257 struct irq_chip_type *ct = gc->chip_types;
258 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
259 int i;
260
261 for (i = 0; i < gc->num_ct; i++) {
262 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
263 mskptr = &ct[i].mask_cache_priv;
264 mskreg = ct[i].regs.mask;
265 }
266 ct[i].mask_cache = mskptr;
267 if (flags & IRQ_GC_INIT_MASK_CACHE)
268 *mskptr = irq_reg_readl(gc, mskreg);
269 }
270}
271
272/**
273 * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
274 * @d: irq domain for which to allocate chips
275 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
276 * @num_ct: Number of irq_chip_type instances associated with this
277 * @name: Name of the irq chip
278 * @handler: Default flow handler associated with these chips
279 * @clr: IRQ_* bits to clear in the mapping function
280 * @set: IRQ_* bits to set in the mapping function
281 * @gcflags: Generic chip specific setup flags
282 */
283int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
284 int num_ct, const char *name,
285 irq_flow_handler_t handler,
286 unsigned int clr, unsigned int set,
287 enum irq_gc_flags gcflags)
288{
289 struct irq_domain_chip_generic *dgc;
290 struct irq_chip_generic *gc;
291 int numchips, sz, i;
292 unsigned long flags;
293 void *tmp;
294
295 if (d->gc)
296 return -EBUSY;
297
298 numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
299 if (!numchips)
300 return -EINVAL;
301
302 /* Allocate a pointer, generic chip and chiptypes for each chip */
303 sz = sizeof(*dgc) + numchips * sizeof(gc);
304 sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
305
306 tmp = dgc = kzalloc(sz, GFP_KERNEL);
307 if (!dgc)
308 return -ENOMEM;
309 dgc->irqs_per_chip = irqs_per_chip;
310 dgc->num_chips = numchips;
311 dgc->irq_flags_to_set = set;
312 dgc->irq_flags_to_clear = clr;
313 dgc->gc_flags = gcflags;
314 d->gc = dgc;
315
316 /* Calc pointer to the first generic chip */
317 tmp += sizeof(*dgc) + numchips * sizeof(gc);
318 for (i = 0; i < numchips; i++) {
319 /* Store the pointer to the generic chip */
320 dgc->gc[i] = gc = tmp;
321 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
322 NULL, handler);
323
324 gc->domain = d;
325 if (gcflags & IRQ_GC_BE_IO) {
326 gc->reg_readl = &irq_readl_be;
327 gc->reg_writel = &irq_writel_be;
328 }
329
330 raw_spin_lock_irqsave(&gc_lock, flags);
331 list_add_tail(&gc->list, &gc_list);
332 raw_spin_unlock_irqrestore(&gc_lock, flags);
333 /* Calc pointer to the next generic chip */
334 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
335 }
336 return 0;
337}
338EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
339
340static struct irq_chip_generic *
341__irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
342{
343 struct irq_domain_chip_generic *dgc = d->gc;
344 int idx;
345
346 if (!dgc)
347 return ERR_PTR(-ENODEV);
348 idx = hw_irq / dgc->irqs_per_chip;
349 if (idx >= dgc->num_chips)
350 return ERR_PTR(-EINVAL);
351 return dgc->gc[idx];
352}
353
354/**
355 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
356 * @d: irq domain pointer
357 * @hw_irq: Hardware interrupt number
358 */
359struct irq_chip_generic *
360irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
361{
362 struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
363
364 return !IS_ERR(gc) ? gc : NULL;
365}
366EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
367
368/*
369 * Separate lockdep classes for interrupt chip which can nest irq_desc
370 * lock and request mutex.
371 */
372static struct lock_class_key irq_nested_lock_class;
373static struct lock_class_key irq_nested_request_class;
374
375/*
376 * irq_map_generic_chip - Map a generic chip for an irq domain
377 */
378int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
379 irq_hw_number_t hw_irq)
380{
381 struct irq_data *data = irq_domain_get_irq_data(d, virq);
382 struct irq_domain_chip_generic *dgc = d->gc;
383 struct irq_chip_generic *gc;
384 struct irq_chip_type *ct;
385 struct irq_chip *chip;
386 unsigned long flags;
387 int idx;
388
389 gc = __irq_get_domain_generic_chip(d, hw_irq);
390 if (IS_ERR(gc))
391 return PTR_ERR(gc);
392
393 idx = hw_irq % dgc->irqs_per_chip;
394
395 if (test_bit(idx, &gc->unused))
396 return -ENOTSUPP;
397
398 if (test_bit(idx, &gc->installed))
399 return -EBUSY;
400
401 ct = gc->chip_types;
402 chip = &ct->chip;
403
404 /* We only init the cache for the first mapping of a generic chip */
405 if (!gc->installed) {
406 raw_spin_lock_irqsave(&gc->lock, flags);
407 irq_gc_init_mask_cache(gc, dgc->gc_flags);
408 raw_spin_unlock_irqrestore(&gc->lock, flags);
409 }
410
411 /* Mark the interrupt as installed */
412 set_bit(idx, &gc->installed);
413
414 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
415 irq_set_lockdep_class(virq, &irq_nested_lock_class,
416 &irq_nested_request_class);
417
418 if (chip->irq_calc_mask)
419 chip->irq_calc_mask(data);
420 else
421 data->mask = 1 << idx;
422
423 irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
424 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
425 return 0;
426}
427
428static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
429{
430 struct irq_data *data = irq_domain_get_irq_data(d, virq);
431 struct irq_domain_chip_generic *dgc = d->gc;
432 unsigned int hw_irq = data->hwirq;
433 struct irq_chip_generic *gc;
434 int irq_idx;
435
436 gc = irq_get_domain_generic_chip(d, hw_irq);
437 if (!gc)
438 return;
439
440 irq_idx = hw_irq % dgc->irqs_per_chip;
441
442 clear_bit(irq_idx, &gc->installed);
443 irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
444 NULL);
445
446}
447
448struct irq_domain_ops irq_generic_chip_ops = {
449 .map = irq_map_generic_chip,
450 .unmap = irq_unmap_generic_chip,
451 .xlate = irq_domain_xlate_onetwocell,
452};
453EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
454
455/**
456 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
457 * @gc: Generic irq chip holding all data
458 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
459 * @flags: Flags for initialization
460 * @clr: IRQ_* bits to clear
461 * @set: IRQ_* bits to set
462 *
463 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
464 * initializes all interrupts to the primary irq_chip_type and its
465 * associated handler.
466 */
467void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
468 enum irq_gc_flags flags, unsigned int clr,
469 unsigned int set)
470{
471 struct irq_chip_type *ct = gc->chip_types;
472 struct irq_chip *chip = &ct->chip;
473 unsigned int i;
474
475 raw_spin_lock(&gc_lock);
476 list_add_tail(&gc->list, &gc_list);
477 raw_spin_unlock(&gc_lock);
478
479 irq_gc_init_mask_cache(gc, flags);
480
481 for (i = gc->irq_base; msk; msk >>= 1, i++) {
482 if (!(msk & 0x01))
483 continue;
484
485 if (flags & IRQ_GC_INIT_NESTED_LOCK)
486 irq_set_lockdep_class(i, &irq_nested_lock_class,
487 &irq_nested_request_class);
488
489 if (!(flags & IRQ_GC_NO_MASK)) {
490 struct irq_data *d = irq_get_irq_data(i);
491
492 if (chip->irq_calc_mask)
493 chip->irq_calc_mask(d);
494 else
495 d->mask = 1 << (i - gc->irq_base);
496 }
497 irq_set_chip_and_handler(i, chip, ct->handler);
498 irq_set_chip_data(i, gc);
499 irq_modify_status(i, clr, set);
500 }
501 gc->irq_cnt = i - gc->irq_base;
502}
503EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
504
505/**
506 * irq_setup_alt_chip - Switch to alternative chip
507 * @d: irq_data for this interrupt
508 * @type: Flow type to be initialized
509 *
510 * Only to be called from chip->irq_set_type() callbacks.
511 */
512int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
513{
514 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
515 struct irq_chip_type *ct = gc->chip_types;
516 unsigned int i;
517
518 for (i = 0; i < gc->num_ct; i++, ct++) {
519 if (ct->type & type) {
520 d->chip = &ct->chip;
521 irq_data_to_desc(d)->handle_irq = ct->handler;
522 return 0;
523 }
524 }
525 return -EINVAL;
526}
527EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
528
529/**
530 * irq_remove_generic_chip - Remove a chip
531 * @gc: Generic irq chip holding all data
532 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
533 * @clr: IRQ_* bits to clear
534 * @set: IRQ_* bits to set
535 *
536 * Remove up to 32 interrupts starting from gc->irq_base.
537 */
538void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
539 unsigned int clr, unsigned int set)
540{
541 unsigned int i = gc->irq_base;
542
543 raw_spin_lock(&gc_lock);
544 list_del(&gc->list);
545 raw_spin_unlock(&gc_lock);
546
547 for (; msk; msk >>= 1, i++) {
548 if (!(msk & 0x01))
549 continue;
550
551 /* Remove handler first. That will mask the irq line */
552 irq_set_handler(i, NULL);
553 irq_set_chip(i, &no_irq_chip);
554 irq_set_chip_data(i, NULL);
555 irq_modify_status(i, clr, set);
556 }
557}
558EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
559
560static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
561{
562 unsigned int virq;
563
564 if (!gc->domain)
565 return irq_get_irq_data(gc->irq_base);
566
567 /*
568 * We don't know which of the irqs has been actually
569 * installed. Use the first one.
570 */
571 if (!gc->installed)
572 return NULL;
573
574 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
575 return virq ? irq_get_irq_data(virq) : NULL;
576}
577
578#ifdef CONFIG_PM
579static int irq_gc_suspend(void)
580{
581 struct irq_chip_generic *gc;
582
583 list_for_each_entry(gc, &gc_list, list) {
584 struct irq_chip_type *ct = gc->chip_types;
585
586 if (ct->chip.irq_suspend) {
587 struct irq_data *data = irq_gc_get_irq_data(gc);
588
589 if (data)
590 ct->chip.irq_suspend(data);
591 }
592
593 if (gc->suspend)
594 gc->suspend(gc);
595 }
596 return 0;
597}
598
599static void irq_gc_resume(void)
600{
601 struct irq_chip_generic *gc;
602
603 list_for_each_entry(gc, &gc_list, list) {
604 struct irq_chip_type *ct = gc->chip_types;
605
606 if (gc->resume)
607 gc->resume(gc);
608
609 if (ct->chip.irq_resume) {
610 struct irq_data *data = irq_gc_get_irq_data(gc);
611
612 if (data)
613 ct->chip.irq_resume(data);
614 }
615 }
616}
617#else
618#define irq_gc_suspend NULL
619#define irq_gc_resume NULL
620#endif
621
622static void irq_gc_shutdown(void)
623{
624 struct irq_chip_generic *gc;
625
626 list_for_each_entry(gc, &gc_list, list) {
627 struct irq_chip_type *ct = gc->chip_types;
628
629 if (ct->chip.irq_pm_shutdown) {
630 struct irq_data *data = irq_gc_get_irq_data(gc);
631
632 if (data)
633 ct->chip.irq_pm_shutdown(data);
634 }
635 }
636}
637
638static struct syscore_ops irq_gc_syscore_ops = {
639 .suspend = irq_gc_suspend,
640 .resume = irq_gc_resume,
641 .shutdown = irq_gc_shutdown,
642};
643
644static int __init irq_gc_init_ops(void)
645{
646 register_syscore_ops(&irq_gc_syscore_ops);
647 return 0;
648}
649device_initcall(irq_gc_init_ops);