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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_ADMINQ_CMD_H_
28#define _I40E_ADMINQ_CMD_H_
29
30/* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
36#define I40E_FW_API_VERSION_MAJOR 0x0001
37#define I40E_FW_API_VERSION_MINOR 0x0005
38
39struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61};
62
63/* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68/* command flags and offsets*/
69#define I40E_AQ_FLAG_DD_SHIFT 0
70#define I40E_AQ_FLAG_CMP_SHIFT 1
71#define I40E_AQ_FLAG_ERR_SHIFT 2
72#define I40E_AQ_FLAG_VFE_SHIFT 3
73#define I40E_AQ_FLAG_LB_SHIFT 9
74#define I40E_AQ_FLAG_RD_SHIFT 10
75#define I40E_AQ_FLAG_VFC_SHIFT 11
76#define I40E_AQ_FLAG_BUF_SHIFT 12
77#define I40E_AQ_FLAG_SI_SHIFT 13
78#define I40E_AQ_FLAG_EI_SHIFT 14
79#define I40E_AQ_FLAG_FE_SHIFT 15
80
81#define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82#define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83#define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84#define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85#define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86#define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87#define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88#define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89#define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90#define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91#define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
92
93/* error codes */
94enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
118};
119
120/* Admin Queue command opcodes */
121enum i40e_admin_queue_opc {
122 /* aq commands */
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
127
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
131
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
134
135 /* LAA */
136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
138
139 /* PXE */
140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
141
142 /* internal switch commands */
143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
148 i40e_aqc_opc_set_switch_config = 0x0205,
149 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
150 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
151
152 i40e_aqc_opc_add_vsi = 0x0210,
153 i40e_aqc_opc_update_vsi_parameters = 0x0211,
154 i40e_aqc_opc_get_vsi_parameters = 0x0212,
155
156 i40e_aqc_opc_add_pv = 0x0220,
157 i40e_aqc_opc_update_pv_parameters = 0x0221,
158 i40e_aqc_opc_get_pv_parameters = 0x0222,
159
160 i40e_aqc_opc_add_veb = 0x0230,
161 i40e_aqc_opc_update_veb_parameters = 0x0231,
162 i40e_aqc_opc_get_veb_parameters = 0x0232,
163
164 i40e_aqc_opc_delete_element = 0x0243,
165
166 i40e_aqc_opc_add_macvlan = 0x0250,
167 i40e_aqc_opc_remove_macvlan = 0x0251,
168 i40e_aqc_opc_add_vlan = 0x0252,
169 i40e_aqc_opc_remove_vlan = 0x0253,
170 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
171 i40e_aqc_opc_add_tag = 0x0255,
172 i40e_aqc_opc_remove_tag = 0x0256,
173 i40e_aqc_opc_add_multicast_etag = 0x0257,
174 i40e_aqc_opc_remove_multicast_etag = 0x0258,
175 i40e_aqc_opc_update_tag = 0x0259,
176 i40e_aqc_opc_add_control_packet_filter = 0x025A,
177 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
178 i40e_aqc_opc_add_cloud_filters = 0x025C,
179 i40e_aqc_opc_remove_cloud_filters = 0x025D,
180
181 i40e_aqc_opc_add_mirror_rule = 0x0260,
182 i40e_aqc_opc_delete_mirror_rule = 0x0261,
183
184 /* DCB commands */
185 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
186 i40e_aqc_opc_dcb_updated = 0x0302,
187
188 /* TX scheduler */
189 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
190 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
191 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
192 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
193 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
194 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
195
196 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
197 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
198 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
199 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
200 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
201 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
202 i40e_aqc_opc_query_port_ets_config = 0x0419,
203 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
204 i40e_aqc_opc_suspend_port_tx = 0x041B,
205 i40e_aqc_opc_resume_port_tx = 0x041C,
206 i40e_aqc_opc_configure_partition_bw = 0x041D,
207 /* hmc */
208 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
209 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
210
211 /* phy commands*/
212 i40e_aqc_opc_get_phy_abilities = 0x0600,
213 i40e_aqc_opc_set_phy_config = 0x0601,
214 i40e_aqc_opc_set_mac_config = 0x0603,
215 i40e_aqc_opc_set_link_restart_an = 0x0605,
216 i40e_aqc_opc_get_link_status = 0x0607,
217 i40e_aqc_opc_set_phy_int_mask = 0x0613,
218 i40e_aqc_opc_get_local_advt_reg = 0x0614,
219 i40e_aqc_opc_set_local_advt_reg = 0x0615,
220 i40e_aqc_opc_get_partner_advt = 0x0616,
221 i40e_aqc_opc_set_lb_modes = 0x0618,
222 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
223 i40e_aqc_opc_set_phy_debug = 0x0622,
224 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
225 i40e_aqc_opc_run_phy_activity = 0x0626,
226
227 /* NVM commands */
228 i40e_aqc_opc_nvm_read = 0x0701,
229 i40e_aqc_opc_nvm_erase = 0x0702,
230 i40e_aqc_opc_nvm_update = 0x0703,
231 i40e_aqc_opc_nvm_config_read = 0x0704,
232 i40e_aqc_opc_nvm_config_write = 0x0705,
233 i40e_aqc_opc_oem_post_update = 0x0720,
234 i40e_aqc_opc_thermal_sensor = 0x0721,
235
236 /* virtualization commands */
237 i40e_aqc_opc_send_msg_to_pf = 0x0801,
238 i40e_aqc_opc_send_msg_to_vf = 0x0802,
239 i40e_aqc_opc_send_msg_to_peer = 0x0803,
240
241 /* alternate structure */
242 i40e_aqc_opc_alternate_write = 0x0900,
243 i40e_aqc_opc_alternate_write_indirect = 0x0901,
244 i40e_aqc_opc_alternate_read = 0x0902,
245 i40e_aqc_opc_alternate_read_indirect = 0x0903,
246 i40e_aqc_opc_alternate_write_done = 0x0904,
247 i40e_aqc_opc_alternate_set_mode = 0x0905,
248 i40e_aqc_opc_alternate_clear_port = 0x0906,
249
250 /* LLDP commands */
251 i40e_aqc_opc_lldp_get_mib = 0x0A00,
252 i40e_aqc_opc_lldp_update_mib = 0x0A01,
253 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
254 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
255 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
256 i40e_aqc_opc_lldp_stop = 0x0A05,
257 i40e_aqc_opc_lldp_start = 0x0A06,
258 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
259 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
260 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
261
262 /* Tunnel commands */
263 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
264 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
265 i40e_aqc_opc_set_rss_key = 0x0B02,
266 i40e_aqc_opc_set_rss_lut = 0x0B03,
267 i40e_aqc_opc_get_rss_key = 0x0B04,
268 i40e_aqc_opc_get_rss_lut = 0x0B05,
269
270 /* Async Events */
271 i40e_aqc_opc_event_lan_overflow = 0x1001,
272
273 /* OEM commands */
274 i40e_aqc_opc_oem_parameter_change = 0xFE00,
275 i40e_aqc_opc_oem_device_status_change = 0xFE01,
276 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
277 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
278
279 /* debug commands */
280 i40e_aqc_opc_debug_read_reg = 0xFF03,
281 i40e_aqc_opc_debug_write_reg = 0xFF04,
282 i40e_aqc_opc_debug_modify_reg = 0xFF07,
283 i40e_aqc_opc_debug_dump_internals = 0xFF08,
284};
285
286/* command structures and indirect data structures */
287
288/* Structure naming conventions:
289 * - no suffix for direct command descriptor structures
290 * - _data for indirect sent data
291 * - _resp for indirect return data (data which is both will use _data)
292 * - _completion for direct return data
293 * - _element_ for repeated elements (may also be _data or _resp)
294 *
295 * Command structures are expected to overlay the params.raw member of the basic
296 * descriptor, and as such cannot exceed 16 bytes in length.
297 */
298
299/* This macro is used to generate a compilation error if a structure
300 * is not exactly the correct length. It gives a divide by zero error if the
301 * structure is not of the correct size, otherwise it creates an enum that is
302 * never used.
303 */
304#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
305 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
306
307/* This macro is used extensively to ensure that command structures are 16
308 * bytes in length as they have to map to the raw array of that size.
309 */
310#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
311
312/* internal (0x00XX) commands */
313
314/* Get version (direct 0x0001) */
315struct i40e_aqc_get_version {
316 __le32 rom_ver;
317 __le32 fw_build;
318 __le16 fw_major;
319 __le16 fw_minor;
320 __le16 api_major;
321 __le16 api_minor;
322};
323
324I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
325
326/* Send driver version (indirect 0x0002) */
327struct i40e_aqc_driver_version {
328 u8 driver_major_ver;
329 u8 driver_minor_ver;
330 u8 driver_build_ver;
331 u8 driver_subbuild_ver;
332 u8 reserved[4];
333 __le32 address_high;
334 __le32 address_low;
335};
336
337I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
338
339/* Queue Shutdown (direct 0x0003) */
340struct i40e_aqc_queue_shutdown {
341 __le32 driver_unloading;
342#define I40E_AQ_DRIVER_UNLOADING 0x1
343 u8 reserved[12];
344};
345
346I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
347
348/* Set PF context (0x0004, direct) */
349struct i40e_aqc_set_pf_context {
350 u8 pf_id;
351 u8 reserved[15];
352};
353
354I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
355
356/* Request resource ownership (direct 0x0008)
357 * Release resource ownership (direct 0x0009)
358 */
359#define I40E_AQ_RESOURCE_NVM 1
360#define I40E_AQ_RESOURCE_SDP 2
361#define I40E_AQ_RESOURCE_ACCESS_READ 1
362#define I40E_AQ_RESOURCE_ACCESS_WRITE 2
363#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
364#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
365
366struct i40e_aqc_request_resource {
367 __le16 resource_id;
368 __le16 access_type;
369 __le32 timeout;
370 __le32 resource_number;
371 u8 reserved[4];
372};
373
374I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
375
376/* Get function capabilities (indirect 0x000A)
377 * Get device capabilities (indirect 0x000B)
378 */
379struct i40e_aqc_list_capabilites {
380 u8 command_flags;
381#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
382 u8 pf_index;
383 u8 reserved[2];
384 __le32 count;
385 __le32 addr_high;
386 __le32 addr_low;
387};
388
389I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
390
391struct i40e_aqc_list_capabilities_element_resp {
392 __le16 id;
393 u8 major_rev;
394 u8 minor_rev;
395 __le32 number;
396 __le32 logical_id;
397 __le32 phys_id;
398 u8 reserved[16];
399};
400
401/* list of caps */
402
403#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
404#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
405#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
406#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
407#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
408#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
409#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
410#define I40E_AQ_CAP_ID_SRIOV 0x0012
411#define I40E_AQ_CAP_ID_VF 0x0013
412#define I40E_AQ_CAP_ID_VMDQ 0x0014
413#define I40E_AQ_CAP_ID_8021QBG 0x0015
414#define I40E_AQ_CAP_ID_8021QBR 0x0016
415#define I40E_AQ_CAP_ID_VSI 0x0017
416#define I40E_AQ_CAP_ID_DCB 0x0018
417#define I40E_AQ_CAP_ID_FCOE 0x0021
418#define I40E_AQ_CAP_ID_ISCSI 0x0022
419#define I40E_AQ_CAP_ID_RSS 0x0040
420#define I40E_AQ_CAP_ID_RXQ 0x0041
421#define I40E_AQ_CAP_ID_TXQ 0x0042
422#define I40E_AQ_CAP_ID_MSIX 0x0043
423#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
424#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
425#define I40E_AQ_CAP_ID_1588 0x0046
426#define I40E_AQ_CAP_ID_IWARP 0x0051
427#define I40E_AQ_CAP_ID_LED 0x0061
428#define I40E_AQ_CAP_ID_SDP 0x0062
429#define I40E_AQ_CAP_ID_MDIO 0x0063
430#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
431#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
432#define I40E_AQ_CAP_ID_FLEX10 0x00F1
433#define I40E_AQ_CAP_ID_CEM 0x00F2
434
435/* Set CPPM Configuration (direct 0x0103) */
436struct i40e_aqc_cppm_configuration {
437 __le16 command_flags;
438#define I40E_AQ_CPPM_EN_LTRC 0x0800
439#define I40E_AQ_CPPM_EN_DMCTH 0x1000
440#define I40E_AQ_CPPM_EN_DMCTLX 0x2000
441#define I40E_AQ_CPPM_EN_HPTC 0x4000
442#define I40E_AQ_CPPM_EN_DMARC 0x8000
443 __le16 ttlx;
444 __le32 dmacr;
445 __le16 dmcth;
446 u8 hptc;
447 u8 reserved;
448 __le32 pfltrc;
449};
450
451I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
452
453/* Set ARP Proxy command / response (indirect 0x0104) */
454struct i40e_aqc_arp_proxy_data {
455 __le16 command_flags;
456#define I40E_AQ_ARP_INIT_IPV4 0x0800
457#define I40E_AQ_ARP_UNSUP_CTL 0x1000
458#define I40E_AQ_ARP_ENA 0x2000
459#define I40E_AQ_ARP_ADD_IPV4 0x4000
460#define I40E_AQ_ARP_DEL_IPV4 0x8000
461 __le16 table_id;
462 __le32 enabled_offloads;
463#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
464#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
465 __le32 ip_addr;
466 u8 mac_addr[6];
467 u8 reserved[2];
468};
469
470I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
471
472/* Set NS Proxy Table Entry Command (indirect 0x0105) */
473struct i40e_aqc_ns_proxy_data {
474 __le16 table_idx_mac_addr_0;
475 __le16 table_idx_mac_addr_1;
476 __le16 table_idx_ipv6_0;
477 __le16 table_idx_ipv6_1;
478 __le16 control;
479#define I40E_AQ_NS_PROXY_ADD_0 0x0001
480#define I40E_AQ_NS_PROXY_DEL_0 0x0002
481#define I40E_AQ_NS_PROXY_ADD_1 0x0004
482#define I40E_AQ_NS_PROXY_DEL_1 0x0008
483#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
484#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
485#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
486#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
487#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
488#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
489#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
490#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
491#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
492 u8 mac_addr_0[6];
493 u8 mac_addr_1[6];
494 u8 local_mac_addr[6];
495 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
496 u8 ipv6_addr_1[16];
497};
498
499I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
500
501/* Manage LAA Command (0x0106) - obsolete */
502struct i40e_aqc_mng_laa {
503 __le16 command_flags;
504#define I40E_AQ_LAA_FLAG_WR 0x8000
505 u8 reserved[2];
506 __le32 sal;
507 __le16 sah;
508 u8 reserved2[6];
509};
510
511I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
512
513/* Manage MAC Address Read Command (indirect 0x0107) */
514struct i40e_aqc_mac_address_read {
515 __le16 command_flags;
516#define I40E_AQC_LAN_ADDR_VALID 0x10
517#define I40E_AQC_SAN_ADDR_VALID 0x20
518#define I40E_AQC_PORT_ADDR_VALID 0x40
519#define I40E_AQC_WOL_ADDR_VALID 0x80
520#define I40E_AQC_MC_MAG_EN_VALID 0x100
521#define I40E_AQC_ADDR_VALID_MASK 0x1F0
522 u8 reserved[6];
523 __le32 addr_high;
524 __le32 addr_low;
525};
526
527I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
528
529struct i40e_aqc_mac_address_read_data {
530 u8 pf_lan_mac[6];
531 u8 pf_san_mac[6];
532 u8 port_mac[6];
533 u8 pf_wol_mac[6];
534};
535
536I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
537
538/* Manage MAC Address Write Command (0x0108) */
539struct i40e_aqc_mac_address_write {
540 __le16 command_flags;
541#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
542#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
543#define I40E_AQC_WRITE_TYPE_PORT 0x8000
544#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
545#define I40E_AQC_WRITE_TYPE_MASK 0xC000
546
547 __le16 mac_sah;
548 __le32 mac_sal;
549 u8 reserved[8];
550};
551
552I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
553
554/* PXE commands (0x011x) */
555
556/* Clear PXE Command and response (direct 0x0110) */
557struct i40e_aqc_clear_pxe {
558 u8 rx_cnt;
559 u8 reserved[15];
560};
561
562I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
563
564/* Switch configuration commands (0x02xx) */
565
566/* Used by many indirect commands that only pass an seid and a buffer in the
567 * command
568 */
569struct i40e_aqc_switch_seid {
570 __le16 seid;
571 u8 reserved[6];
572 __le32 addr_high;
573 __le32 addr_low;
574};
575
576I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
577
578/* Get Switch Configuration command (indirect 0x0200)
579 * uses i40e_aqc_switch_seid for the descriptor
580 */
581struct i40e_aqc_get_switch_config_header_resp {
582 __le16 num_reported;
583 __le16 num_total;
584 u8 reserved[12];
585};
586
587I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
588
589struct i40e_aqc_switch_config_element_resp {
590 u8 element_type;
591#define I40E_AQ_SW_ELEM_TYPE_MAC 1
592#define I40E_AQ_SW_ELEM_TYPE_PF 2
593#define I40E_AQ_SW_ELEM_TYPE_VF 3
594#define I40E_AQ_SW_ELEM_TYPE_EMP 4
595#define I40E_AQ_SW_ELEM_TYPE_BMC 5
596#define I40E_AQ_SW_ELEM_TYPE_PV 16
597#define I40E_AQ_SW_ELEM_TYPE_VEB 17
598#define I40E_AQ_SW_ELEM_TYPE_PA 18
599#define I40E_AQ_SW_ELEM_TYPE_VSI 19
600 u8 revision;
601#define I40E_AQ_SW_ELEM_REV_1 1
602 __le16 seid;
603 __le16 uplink_seid;
604 __le16 downlink_seid;
605 u8 reserved[3];
606 u8 connection_type;
607#define I40E_AQ_CONN_TYPE_REGULAR 0x1
608#define I40E_AQ_CONN_TYPE_DEFAULT 0x2
609#define I40E_AQ_CONN_TYPE_CASCADED 0x3
610 __le16 scheduler_id;
611 __le16 element_info;
612};
613
614I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
615
616/* Get Switch Configuration (indirect 0x0200)
617 * an array of elements are returned in the response buffer
618 * the first in the array is the header, remainder are elements
619 */
620struct i40e_aqc_get_switch_config_resp {
621 struct i40e_aqc_get_switch_config_header_resp header;
622 struct i40e_aqc_switch_config_element_resp element[1];
623};
624
625I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
626
627/* Add Statistics (direct 0x0201)
628 * Remove Statistics (direct 0x0202)
629 */
630struct i40e_aqc_add_remove_statistics {
631 __le16 seid;
632 __le16 vlan;
633 __le16 stat_index;
634 u8 reserved[10];
635};
636
637I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
638
639/* Set Port Parameters command (direct 0x0203) */
640struct i40e_aqc_set_port_parameters {
641 __le16 command_flags;
642#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
643#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
644#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
645 __le16 bad_frame_vsi;
646 __le16 default_seid; /* reserved for command */
647 u8 reserved[10];
648};
649
650I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
651
652/* Get Switch Resource Allocation (indirect 0x0204) */
653struct i40e_aqc_get_switch_resource_alloc {
654 u8 num_entries; /* reserved for command */
655 u8 reserved[7];
656 __le32 addr_high;
657 __le32 addr_low;
658};
659
660I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
661
662/* expect an array of these structs in the response buffer */
663struct i40e_aqc_switch_resource_alloc_element_resp {
664 u8 resource_type;
665#define I40E_AQ_RESOURCE_TYPE_VEB 0x0
666#define I40E_AQ_RESOURCE_TYPE_VSI 0x1
667#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
668#define I40E_AQ_RESOURCE_TYPE_STAG 0x3
669#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
670#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
671#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
672#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
673#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
674#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
675#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
676#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
677#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
678#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
679#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
680#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
681#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
682#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
683#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
684 u8 reserved1;
685 __le16 guaranteed;
686 __le16 total;
687 __le16 used;
688 __le16 total_unalloced;
689 u8 reserved2[6];
690};
691
692I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
693
694/* Set Switch Configuration (direct 0x0205) */
695struct i40e_aqc_set_switch_config {
696 __le16 flags;
697#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
698#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
699 __le16 valid_flags;
700 u8 reserved[12];
701};
702
703I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
704
705/* Read Receive control registers (direct 0x0206)
706 * Write Receive control registers (direct 0x0207)
707 * used for accessing Rx control registers that can be
708 * slow and need special handling when under high Rx load
709 */
710struct i40e_aqc_rx_ctl_reg_read_write {
711 __le32 reserved1;
712 __le32 address;
713 __le32 reserved2;
714 __le32 value;
715};
716
717I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
718
719/* Add VSI (indirect 0x0210)
720 * this indirect command uses struct i40e_aqc_vsi_properties_data
721 * as the indirect buffer (128 bytes)
722 *
723 * Update VSI (indirect 0x211)
724 * uses the same data structure as Add VSI
725 *
726 * Get VSI (indirect 0x0212)
727 * uses the same completion and data structure as Add VSI
728 */
729struct i40e_aqc_add_get_update_vsi {
730 __le16 uplink_seid;
731 u8 connection_type;
732#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
733#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
734#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
735 u8 reserved1;
736 u8 vf_id;
737 u8 reserved2;
738 __le16 vsi_flags;
739#define I40E_AQ_VSI_TYPE_SHIFT 0x0
740#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
741#define I40E_AQ_VSI_TYPE_VF 0x0
742#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
743#define I40E_AQ_VSI_TYPE_PF 0x2
744#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
745#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
746 __le32 addr_high;
747 __le32 addr_low;
748};
749
750I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
751
752struct i40e_aqc_add_get_update_vsi_completion {
753 __le16 seid;
754 __le16 vsi_number;
755 __le16 vsi_used;
756 __le16 vsi_free;
757 __le32 addr_high;
758 __le32 addr_low;
759};
760
761I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
762
763struct i40e_aqc_vsi_properties_data {
764 /* first 96 byte are written by SW */
765 __le16 valid_sections;
766#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
767#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
768#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
769#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
770#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
771#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
772#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
773#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
774#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
775#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
776 /* switch section */
777 __le16 switch_id; /* 12bit id combined with flags below */
778#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
779#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
780#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
781#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
782#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
783 u8 sw_reserved[2];
784 /* security section */
785 u8 sec_flags;
786#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
787#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
788#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
789 u8 sec_reserved;
790 /* VLAN section */
791 __le16 pvid; /* VLANS include priority bits */
792 __le16 fcoe_pvid;
793 u8 port_vlan_flags;
794#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
795#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
796 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
797#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
798#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
799#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
800#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
801#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
802#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
803 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
804#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
805#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
806#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
807#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
808 u8 pvlan_reserved[3];
809 /* ingress egress up sections */
810 __le32 ingress_table; /* bitmap, 3 bits per up */
811#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
812#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
813 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
814#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
815#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
816 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
817#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
818#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
819 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
820#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
821#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
822 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
823#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
824#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
825 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
826#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
827#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
828 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
829#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
830#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
831 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
832#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
833#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
834 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
835 __le32 egress_table; /* same defines as for ingress table */
836 /* cascaded PV section */
837 __le16 cas_pv_tag;
838 u8 cas_pv_flags;
839#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
840#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
841 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
842#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
843#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
844#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
845#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
846#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
847#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
848 u8 cas_pv_reserved;
849 /* queue mapping section */
850 __le16 mapping_flags;
851#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
852#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
853 __le16 queue_mapping[16];
854#define I40E_AQ_VSI_QUEUE_SHIFT 0x0
855#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
856 __le16 tc_mapping[8];
857#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
858#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
859 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
860#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
861#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
862 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
863 /* queueing option section */
864 u8 queueing_opt_flags;
865#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
866#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
867#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
868#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
869#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
870#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
871 u8 queueing_opt_reserved[3];
872 /* scheduler section */
873 u8 up_enable_bits;
874 u8 sched_reserved;
875 /* outer up section */
876 __le32 outer_up_table; /* same structure and defines as ingress tbl */
877 u8 cmd_reserved[8];
878 /* last 32 bytes are written by FW */
879 __le16 qs_handle[8];
880#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
881 __le16 stat_counter_idx;
882 __le16 sched_id;
883 u8 resp_reserved[12];
884};
885
886I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
887
888/* Add Port Virtualizer (direct 0x0220)
889 * also used for update PV (direct 0x0221) but only flags are used
890 * (IS_CTRL_PORT only works on add PV)
891 */
892struct i40e_aqc_add_update_pv {
893 __le16 command_flags;
894#define I40E_AQC_PV_FLAG_PV_TYPE 0x1
895#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
896#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
897#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
898 __le16 uplink_seid;
899 __le16 connected_seid;
900 u8 reserved[10];
901};
902
903I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
904
905struct i40e_aqc_add_update_pv_completion {
906 /* reserved for update; for add also encodes error if rc == ENOSPC */
907 __le16 pv_seid;
908#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
909#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
910#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
911#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
912 u8 reserved[14];
913};
914
915I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
916
917/* Get PV Params (direct 0x0222)
918 * uses i40e_aqc_switch_seid for the descriptor
919 */
920
921struct i40e_aqc_get_pv_params_completion {
922 __le16 seid;
923 __le16 default_stag;
924 __le16 pv_flags; /* same flags as add_pv */
925#define I40E_AQC_GET_PV_PV_TYPE 0x1
926#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
927#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
928 u8 reserved[8];
929 __le16 default_port_seid;
930};
931
932I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
933
934/* Add VEB (direct 0x0230) */
935struct i40e_aqc_add_veb {
936 __le16 uplink_seid;
937 __le16 downlink_seid;
938 __le16 veb_flags;
939#define I40E_AQC_ADD_VEB_FLOATING 0x1
940#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
941#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
942 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
943#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
944#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
945#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
946#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
947 u8 enable_tcs;
948 u8 reserved[9];
949};
950
951I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
952
953struct i40e_aqc_add_veb_completion {
954 u8 reserved[6];
955 __le16 switch_seid;
956 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
957 __le16 veb_seid;
958#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
959#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
960#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
961#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
962 __le16 statistic_index;
963 __le16 vebs_used;
964 __le16 vebs_free;
965};
966
967I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
968
969/* Get VEB Parameters (direct 0x0232)
970 * uses i40e_aqc_switch_seid for the descriptor
971 */
972struct i40e_aqc_get_veb_parameters_completion {
973 __le16 seid;
974 __le16 switch_id;
975 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
976 __le16 statistic_index;
977 __le16 vebs_used;
978 __le16 vebs_free;
979 u8 reserved[4];
980};
981
982I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
983
984/* Delete Element (direct 0x0243)
985 * uses the generic i40e_aqc_switch_seid
986 */
987
988/* Add MAC-VLAN (indirect 0x0250) */
989
990/* used for the command for most vlan commands */
991struct i40e_aqc_macvlan {
992 __le16 num_addresses;
993 __le16 seid[3];
994#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
995#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
996 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
997#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
998 __le32 addr_high;
999 __le32 addr_low;
1000};
1001
1002I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1003
1004/* indirect data for command and response */
1005struct i40e_aqc_add_macvlan_element_data {
1006 u8 mac_addr[6];
1007 __le16 vlan_tag;
1008 __le16 flags;
1009#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1010#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1011#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1012#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1013#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1014 __le16 queue_number;
1015#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1016#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1017 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1018 /* response section */
1019 u8 match_method;
1020#define I40E_AQC_MM_PERFECT_MATCH 0x01
1021#define I40E_AQC_MM_HASH_MATCH 0x02
1022#define I40E_AQC_MM_ERR_NO_RES 0xFF
1023 u8 reserved1[3];
1024};
1025
1026struct i40e_aqc_add_remove_macvlan_completion {
1027 __le16 perfect_mac_used;
1028 __le16 perfect_mac_free;
1029 __le16 unicast_hash_free;
1030 __le16 multicast_hash_free;
1031 __le32 addr_high;
1032 __le32 addr_low;
1033};
1034
1035I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1036
1037/* Remove MAC-VLAN (indirect 0x0251)
1038 * uses i40e_aqc_macvlan for the descriptor
1039 * data points to an array of num_addresses of elements
1040 */
1041
1042struct i40e_aqc_remove_macvlan_element_data {
1043 u8 mac_addr[6];
1044 __le16 vlan_tag;
1045 u8 flags;
1046#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1047#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1048#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1049#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1050 u8 reserved[3];
1051 /* reply section */
1052 u8 error_code;
1053#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1054#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1055 u8 reply_reserved[3];
1056};
1057
1058/* Add VLAN (indirect 0x0252)
1059 * Remove VLAN (indirect 0x0253)
1060 * use the generic i40e_aqc_macvlan for the command
1061 */
1062struct i40e_aqc_add_remove_vlan_element_data {
1063 __le16 vlan_tag;
1064 u8 vlan_flags;
1065/* flags for add VLAN */
1066#define I40E_AQC_ADD_VLAN_LOCAL 0x1
1067#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1068#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1069#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1070#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1071#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1072#define I40E_AQC_VLAN_PTYPE_SHIFT 3
1073#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1074#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1075#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1076#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1077#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1078/* flags for remove VLAN */
1079#define I40E_AQC_REMOVE_VLAN_ALL 0x1
1080 u8 reserved;
1081 u8 result;
1082/* flags for add VLAN */
1083#define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1084#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1085#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1086/* flags for remove VLAN */
1087#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1088#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1089 u8 reserved1[3];
1090};
1091
1092struct i40e_aqc_add_remove_vlan_completion {
1093 u8 reserved[4];
1094 __le16 vlans_used;
1095 __le16 vlans_free;
1096 __le32 addr_high;
1097 __le32 addr_low;
1098};
1099
1100/* Set VSI Promiscuous Modes (direct 0x0254) */
1101struct i40e_aqc_set_vsi_promiscuous_modes {
1102 __le16 promiscuous_flags;
1103 __le16 valid_flags;
1104/* flags used for both fields above */
1105#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1106#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1107#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1108#define I40E_AQC_SET_VSI_DEFAULT 0x08
1109#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1110#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1111 __le16 seid;
1112#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1113 __le16 vlan_tag;
1114#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1115#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1116 u8 reserved[8];
1117};
1118
1119I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1120
1121/* Add S/E-tag command (direct 0x0255)
1122 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1123 */
1124struct i40e_aqc_add_tag {
1125 __le16 flags;
1126#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1127 __le16 seid;
1128#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1129#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1130 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1131 __le16 tag;
1132 __le16 queue_number;
1133 u8 reserved[8];
1134};
1135
1136I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1137
1138struct i40e_aqc_add_remove_tag_completion {
1139 u8 reserved[12];
1140 __le16 tags_used;
1141 __le16 tags_free;
1142};
1143
1144I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1145
1146/* Remove S/E-tag command (direct 0x0256)
1147 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1148 */
1149struct i40e_aqc_remove_tag {
1150 __le16 seid;
1151#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1152#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1153 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1154 __le16 tag;
1155 u8 reserved[12];
1156};
1157
1158I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1159
1160/* Add multicast E-Tag (direct 0x0257)
1161 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1162 * and no external data
1163 */
1164struct i40e_aqc_add_remove_mcast_etag {
1165 __le16 pv_seid;
1166 __le16 etag;
1167 u8 num_unicast_etags;
1168 u8 reserved[3];
1169 __le32 addr_high; /* address of array of 2-byte s-tags */
1170 __le32 addr_low;
1171};
1172
1173I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1174
1175struct i40e_aqc_add_remove_mcast_etag_completion {
1176 u8 reserved[4];
1177 __le16 mcast_etags_used;
1178 __le16 mcast_etags_free;
1179 __le32 addr_high;
1180 __le32 addr_low;
1181
1182};
1183
1184I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1185
1186/* Update S/E-Tag (direct 0x0259) */
1187struct i40e_aqc_update_tag {
1188 __le16 seid;
1189#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1190#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1191 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1192 __le16 old_tag;
1193 __le16 new_tag;
1194 u8 reserved[10];
1195};
1196
1197I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1198
1199struct i40e_aqc_update_tag_completion {
1200 u8 reserved[12];
1201 __le16 tags_used;
1202 __le16 tags_free;
1203};
1204
1205I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1206
1207/* Add Control Packet filter (direct 0x025A)
1208 * Remove Control Packet filter (direct 0x025B)
1209 * uses the i40e_aqc_add_oveb_cloud,
1210 * and the generic direct completion structure
1211 */
1212struct i40e_aqc_add_remove_control_packet_filter {
1213 u8 mac[6];
1214 __le16 etype;
1215 __le16 flags;
1216#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1217#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1218#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1219#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1220#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1221 __le16 seid;
1222#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1223#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1224 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1225 __le16 queue;
1226 u8 reserved[2];
1227};
1228
1229I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1230
1231struct i40e_aqc_add_remove_control_packet_filter_completion {
1232 __le16 mac_etype_used;
1233 __le16 etype_used;
1234 __le16 mac_etype_free;
1235 __le16 etype_free;
1236 u8 reserved[8];
1237};
1238
1239I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1240
1241/* Add Cloud filters (indirect 0x025C)
1242 * Remove Cloud filters (indirect 0x025D)
1243 * uses the i40e_aqc_add_remove_cloud_filters,
1244 * and the generic indirect completion structure
1245 */
1246struct i40e_aqc_add_remove_cloud_filters {
1247 u8 num_filters;
1248 u8 reserved;
1249 __le16 seid;
1250#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1251#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1252 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1253 u8 reserved2[4];
1254 __le32 addr_high;
1255 __le32 addr_low;
1256};
1257
1258I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1259
1260struct i40e_aqc_add_remove_cloud_filters_element_data {
1261 u8 outer_mac[6];
1262 u8 inner_mac[6];
1263 __le16 inner_vlan;
1264 union {
1265 struct {
1266 u8 reserved[12];
1267 u8 data[4];
1268 } v4;
1269 struct {
1270 u8 data[16];
1271 } v6;
1272 } ipaddr;
1273 __le16 flags;
1274#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1275#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1276 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1277/* 0x0000 reserved */
1278#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1279/* 0x0002 reserved */
1280#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1281#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1282/* 0x0005 reserved */
1283#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1284/* 0x0007 reserved */
1285/* 0x0008 reserved */
1286#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1287#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1288#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1289#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1290
1291#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1292#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1293#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1294#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1295#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1296
1297#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1298#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1299#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1300#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1301#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1302#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1303#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1304#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1305
1306#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1307#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1308#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1309
1310 __le32 tenant_id;
1311 u8 reserved[4];
1312 __le16 queue_number;
1313#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1314#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1315 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1316 u8 reserved2[14];
1317 /* response section */
1318 u8 allocation_result;
1319#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1320#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1321 u8 response_reserved[7];
1322};
1323
1324struct i40e_aqc_remove_cloud_filters_completion {
1325 __le16 perfect_ovlan_used;
1326 __le16 perfect_ovlan_free;
1327 __le16 vlan_used;
1328 __le16 vlan_free;
1329 __le32 addr_high;
1330 __le32 addr_low;
1331};
1332
1333I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1334
1335/* Add Mirror Rule (indirect or direct 0x0260)
1336 * Delete Mirror Rule (indirect or direct 0x0261)
1337 * note: some rule types (4,5) do not use an external buffer.
1338 * take care to set the flags correctly.
1339 */
1340struct i40e_aqc_add_delete_mirror_rule {
1341 __le16 seid;
1342 __le16 rule_type;
1343#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1344#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1345 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1346#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1347#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1348#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1349#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1350#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1351 __le16 num_entries;
1352 __le16 destination; /* VSI for add, rule id for delete */
1353 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1354 __le32 addr_low;
1355};
1356
1357I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1358
1359struct i40e_aqc_add_delete_mirror_rule_completion {
1360 u8 reserved[2];
1361 __le16 rule_id; /* only used on add */
1362 __le16 mirror_rules_used;
1363 __le16 mirror_rules_free;
1364 __le32 addr_high;
1365 __le32 addr_low;
1366};
1367
1368I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1369
1370/* DCB 0x03xx*/
1371
1372/* PFC Ignore (direct 0x0301)
1373 * the command and response use the same descriptor structure
1374 */
1375struct i40e_aqc_pfc_ignore {
1376 u8 tc_bitmap;
1377 u8 command_flags; /* unused on response */
1378#define I40E_AQC_PFC_IGNORE_SET 0x80
1379#define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1380 u8 reserved[14];
1381};
1382
1383I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1384
1385/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1386 * with no parameters
1387 */
1388
1389/* TX scheduler 0x04xx */
1390
1391/* Almost all the indirect commands use
1392 * this generic struct to pass the SEID in param0
1393 */
1394struct i40e_aqc_tx_sched_ind {
1395 __le16 vsi_seid;
1396 u8 reserved[6];
1397 __le32 addr_high;
1398 __le32 addr_low;
1399};
1400
1401I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1402
1403/* Several commands respond with a set of queue set handles */
1404struct i40e_aqc_qs_handles_resp {
1405 __le16 qs_handles[8];
1406};
1407
1408/* Configure VSI BW limits (direct 0x0400) */
1409struct i40e_aqc_configure_vsi_bw_limit {
1410 __le16 vsi_seid;
1411 u8 reserved[2];
1412 __le16 credit;
1413 u8 reserved1[2];
1414 u8 max_credit; /* 0-3, limit = 2^max */
1415 u8 reserved2[7];
1416};
1417
1418I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1419
1420/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1421 * responds with i40e_aqc_qs_handles_resp
1422 */
1423struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1424 u8 tc_valid_bits;
1425 u8 reserved[15];
1426 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1427
1428 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1429 __le16 tc_bw_max[2];
1430 u8 reserved1[28];
1431};
1432
1433I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1434
1435/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1436 * responds with i40e_aqc_qs_handles_resp
1437 */
1438struct i40e_aqc_configure_vsi_tc_bw_data {
1439 u8 tc_valid_bits;
1440 u8 reserved[3];
1441 u8 tc_bw_credits[8];
1442 u8 reserved1[4];
1443 __le16 qs_handles[8];
1444};
1445
1446I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1447
1448/* Query vsi bw configuration (indirect 0x0408) */
1449struct i40e_aqc_query_vsi_bw_config_resp {
1450 u8 tc_valid_bits;
1451 u8 tc_suspended_bits;
1452 u8 reserved[14];
1453 __le16 qs_handles[8];
1454 u8 reserved1[4];
1455 __le16 port_bw_limit;
1456 u8 reserved2[2];
1457 u8 max_bw; /* 0-3, limit = 2^max */
1458 u8 reserved3[23];
1459};
1460
1461I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1462
1463/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1464struct i40e_aqc_query_vsi_ets_sla_config_resp {
1465 u8 tc_valid_bits;
1466 u8 reserved[3];
1467 u8 share_credits[8];
1468 __le16 credits[8];
1469
1470 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1471 __le16 tc_bw_max[2];
1472};
1473
1474I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1475
1476/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1477struct i40e_aqc_configure_switching_comp_bw_limit {
1478 __le16 seid;
1479 u8 reserved[2];
1480 __le16 credit;
1481 u8 reserved1[2];
1482 u8 max_bw; /* 0-3, limit = 2^max */
1483 u8 reserved2[7];
1484};
1485
1486I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1487
1488/* Enable Physical Port ETS (indirect 0x0413)
1489 * Modify Physical Port ETS (indirect 0x0414)
1490 * Disable Physical Port ETS (indirect 0x0415)
1491 */
1492struct i40e_aqc_configure_switching_comp_ets_data {
1493 u8 reserved[4];
1494 u8 tc_valid_bits;
1495 u8 seepage;
1496#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1497 u8 tc_strict_priority_flags;
1498 u8 reserved1[17];
1499 u8 tc_bw_share_credits[8];
1500 u8 reserved2[96];
1501};
1502
1503I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1504
1505/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1506struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1507 u8 tc_valid_bits;
1508 u8 reserved[15];
1509 __le16 tc_bw_credit[8];
1510
1511 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1512 __le16 tc_bw_max[2];
1513 u8 reserved1[28];
1514};
1515
1516I40E_CHECK_STRUCT_LEN(0x40,
1517 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1518
1519/* Configure Switching Component Bandwidth Allocation per Tc
1520 * (indirect 0x0417)
1521 */
1522struct i40e_aqc_configure_switching_comp_bw_config_data {
1523 u8 tc_valid_bits;
1524 u8 reserved[2];
1525 u8 absolute_credits; /* bool */
1526 u8 tc_bw_share_credits[8];
1527 u8 reserved1[20];
1528};
1529
1530I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1531
1532/* Query Switching Component Configuration (indirect 0x0418) */
1533struct i40e_aqc_query_switching_comp_ets_config_resp {
1534 u8 tc_valid_bits;
1535 u8 reserved[35];
1536 __le16 port_bw_limit;
1537 u8 reserved1[2];
1538 u8 tc_bw_max; /* 0-3, limit = 2^max */
1539 u8 reserved2[23];
1540};
1541
1542I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1543
1544/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1545struct i40e_aqc_query_port_ets_config_resp {
1546 u8 reserved[4];
1547 u8 tc_valid_bits;
1548 u8 reserved1;
1549 u8 tc_strict_priority_bits;
1550 u8 reserved2;
1551 u8 tc_bw_share_credits[8];
1552 __le16 tc_bw_limits[8];
1553
1554 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1555 __le16 tc_bw_max[2];
1556 u8 reserved3[32];
1557};
1558
1559I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1560
1561/* Query Switching Component Bandwidth Allocation per Traffic Type
1562 * (indirect 0x041A)
1563 */
1564struct i40e_aqc_query_switching_comp_bw_config_resp {
1565 u8 tc_valid_bits;
1566 u8 reserved[2];
1567 u8 absolute_credits_enable; /* bool */
1568 u8 tc_bw_share_credits[8];
1569 __le16 tc_bw_limits[8];
1570
1571 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1572 __le16 tc_bw_max[2];
1573};
1574
1575I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1576
1577/* Suspend/resume port TX traffic
1578 * (direct 0x041B and 0x041C) uses the generic SEID struct
1579 */
1580
1581/* Configure partition BW
1582 * (indirect 0x041D)
1583 */
1584struct i40e_aqc_configure_partition_bw_data {
1585 __le16 pf_valid_bits;
1586 u8 min_bw[16]; /* guaranteed bandwidth */
1587 u8 max_bw[16]; /* bandwidth limit */
1588};
1589
1590I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1591
1592/* Get and set the active HMC resource profile and status.
1593 * (direct 0x0500) and (direct 0x0501)
1594 */
1595struct i40e_aq_get_set_hmc_resource_profile {
1596 u8 pm_profile;
1597 u8 pe_vf_enabled;
1598 u8 reserved[14];
1599};
1600
1601I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1602
1603enum i40e_aq_hmc_profile {
1604 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1605 I40E_HMC_PROFILE_DEFAULT = 1,
1606 I40E_HMC_PROFILE_FAVOR_VF = 2,
1607 I40E_HMC_PROFILE_EQUAL = 3,
1608};
1609
1610/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1611
1612/* set in param0 for get phy abilities to report qualified modules */
1613#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1614#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1615
1616enum i40e_aq_phy_type {
1617 I40E_PHY_TYPE_SGMII = 0x0,
1618 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1619 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1620 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1621 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1622 I40E_PHY_TYPE_XAUI = 0x5,
1623 I40E_PHY_TYPE_XFI = 0x6,
1624 I40E_PHY_TYPE_SFI = 0x7,
1625 I40E_PHY_TYPE_XLAUI = 0x8,
1626 I40E_PHY_TYPE_XLPPI = 0x9,
1627 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1628 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1629 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1630 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1631 I40E_PHY_TYPE_100BASE_TX = 0x11,
1632 I40E_PHY_TYPE_1000BASE_T = 0x12,
1633 I40E_PHY_TYPE_10GBASE_T = 0x13,
1634 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1635 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1636 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1637 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1638 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1639 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1640 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1641 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1642 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1643 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1644 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1645 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1646 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1647 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1648 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1649 I40E_PHY_TYPE_MAX
1650};
1651
1652#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1653#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1654#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1655#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1656#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1657#define I40E_LINK_SPEED_25GB_SHIFT 0x6
1658
1659enum i40e_aq_link_speed {
1660 I40E_LINK_SPEED_UNKNOWN = 0,
1661 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1662 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1663 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1664 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1665 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1666 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1667};
1668
1669struct i40e_aqc_module_desc {
1670 u8 oui[3];
1671 u8 reserved1;
1672 u8 part_number[16];
1673 u8 revision[4];
1674 u8 reserved2[8];
1675};
1676
1677I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1678
1679struct i40e_aq_get_phy_abilities_resp {
1680 __le32 phy_type; /* bitmap using the above enum for offsets */
1681 u8 link_speed; /* bitmap using the above enum bit patterns */
1682 u8 abilities;
1683#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1684#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1685#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1686#define I40E_AQ_PHY_LINK_ENABLED 0x08
1687#define I40E_AQ_PHY_AN_ENABLED 0x10
1688#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1689#define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1690#define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1691 __le16 eee_capability;
1692#define I40E_AQ_EEE_100BASE_TX 0x0002
1693#define I40E_AQ_EEE_1000BASE_T 0x0004
1694#define I40E_AQ_EEE_10GBASE_T 0x0008
1695#define I40E_AQ_EEE_1000BASE_KX 0x0010
1696#define I40E_AQ_EEE_10GBASE_KX4 0x0020
1697#define I40E_AQ_EEE_10GBASE_KR 0x0040
1698 __le32 eeer_val;
1699 u8 d3_lpan;
1700#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1701 u8 phy_type_ext;
1702#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1703#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1704#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1705#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1706 u8 fec_cfg_curr_mod_ext_info;
1707#define I40E_AQ_ENABLE_FEC_KR 0x01
1708#define I40E_AQ_ENABLE_FEC_RS 0x02
1709#define I40E_AQ_REQUEST_FEC_KR 0x04
1710#define I40E_AQ_REQUEST_FEC_RS 0x08
1711#define I40E_AQ_ENABLE_FEC_AUTO 0x10
1712#define I40E_AQ_FEC
1713#define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
1714#define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
1715
1716 u8 ext_comp_code;
1717 u8 phy_id[4];
1718 u8 module_type[3];
1719 u8 qualified_module_count;
1720#define I40E_AQ_PHY_MAX_QMS 16
1721 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1722};
1723
1724I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1725
1726/* Set PHY Config (direct 0x0601) */
1727struct i40e_aq_set_phy_config { /* same bits as above in all */
1728 __le32 phy_type;
1729 u8 link_speed;
1730 u8 abilities;
1731/* bits 0-2 use the values from get_phy_abilities_resp */
1732#define I40E_AQ_PHY_ENABLE_LINK 0x08
1733#define I40E_AQ_PHY_ENABLE_AN 0x10
1734#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1735 __le16 eee_capability;
1736 __le32 eeer;
1737 u8 low_power_ctrl;
1738 u8 phy_type_ext;
1739#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1740#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1741#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1742#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1743 u8 fec_config;
1744#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1745#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1746#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1747#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1748#define I40E_AQ_SET_FEC_AUTO BIT(4)
1749#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1750#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1751 u8 reserved;
1752};
1753
1754I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1755
1756/* Set MAC Config command data structure (direct 0x0603) */
1757struct i40e_aq_set_mac_config {
1758 __le16 max_frame_size;
1759 u8 params;
1760#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1761#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1762#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1763#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1764#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1765#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1766#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1767#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1768#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1769#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1770#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1771#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1772#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1773#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1774 u8 tx_timer_priority; /* bitmap */
1775 __le16 tx_timer_value;
1776 __le16 fc_refresh_threshold;
1777 u8 reserved[8];
1778};
1779
1780I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1781
1782/* Restart Auto-Negotiation (direct 0x605) */
1783struct i40e_aqc_set_link_restart_an {
1784 u8 command;
1785#define I40E_AQ_PHY_RESTART_AN 0x02
1786#define I40E_AQ_PHY_LINK_ENABLE 0x04
1787 u8 reserved[15];
1788};
1789
1790I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1791
1792/* Get Link Status cmd & response data structure (direct 0x0607) */
1793struct i40e_aqc_get_link_status {
1794 __le16 command_flags; /* only field set on command */
1795#define I40E_AQ_LSE_MASK 0x3
1796#define I40E_AQ_LSE_NOP 0x0
1797#define I40E_AQ_LSE_DISABLE 0x2
1798#define I40E_AQ_LSE_ENABLE 0x3
1799/* only response uses this flag */
1800#define I40E_AQ_LSE_IS_ENABLED 0x1
1801 u8 phy_type; /* i40e_aq_phy_type */
1802 u8 link_speed; /* i40e_aq_link_speed */
1803 u8 link_info;
1804#define I40E_AQ_LINK_UP 0x01 /* obsolete */
1805#define I40E_AQ_LINK_UP_FUNCTION 0x01
1806#define I40E_AQ_LINK_FAULT 0x02
1807#define I40E_AQ_LINK_FAULT_TX 0x04
1808#define I40E_AQ_LINK_FAULT_RX 0x08
1809#define I40E_AQ_LINK_FAULT_REMOTE 0x10
1810#define I40E_AQ_LINK_UP_PORT 0x20
1811#define I40E_AQ_MEDIA_AVAILABLE 0x40
1812#define I40E_AQ_SIGNAL_DETECT 0x80
1813 u8 an_info;
1814#define I40E_AQ_AN_COMPLETED 0x01
1815#define I40E_AQ_LP_AN_ABILITY 0x02
1816#define I40E_AQ_PD_FAULT 0x04
1817#define I40E_AQ_FEC_EN 0x08
1818#define I40E_AQ_PHY_LOW_POWER 0x10
1819#define I40E_AQ_LINK_PAUSE_TX 0x20
1820#define I40E_AQ_LINK_PAUSE_RX 0x40
1821#define I40E_AQ_QUALIFIED_MODULE 0x80
1822 u8 ext_info;
1823#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1824#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1825#define I40E_AQ_LINK_TX_SHIFT 0x02
1826#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1827#define I40E_AQ_LINK_TX_ACTIVE 0x00
1828#define I40E_AQ_LINK_TX_DRAINED 0x01
1829#define I40E_AQ_LINK_TX_FLUSHED 0x03
1830#define I40E_AQ_LINK_FORCED_40G 0x10
1831/* 25G Error Codes */
1832#define I40E_AQ_25G_NO_ERR 0X00
1833#define I40E_AQ_25G_NOT_PRESENT 0X01
1834#define I40E_AQ_25G_NVM_CRC_ERR 0X02
1835#define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
1836#define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
1837#define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
1838 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1839 __le16 max_frame_size;
1840 u8 config;
1841#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1842#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1843#define I40E_AQ_CONFIG_CRC_ENA 0x04
1844#define I40E_AQ_CONFIG_PACING_MASK 0x78
1845 u8 external_power_ability;
1846#define I40E_AQ_LINK_POWER_CLASS_1 0x00
1847#define I40E_AQ_LINK_POWER_CLASS_2 0x01
1848#define I40E_AQ_LINK_POWER_CLASS_3 0x02
1849#define I40E_AQ_LINK_POWER_CLASS_4 0x03
1850 u8 reserved[4];
1851};
1852
1853I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1854
1855/* Set event mask command (direct 0x613) */
1856struct i40e_aqc_set_phy_int_mask {
1857 u8 reserved[8];
1858 __le16 event_mask;
1859#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1860#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1861#define I40E_AQ_EVENT_LINK_FAULT 0x0008
1862#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1863#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1864#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1865#define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1866#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1867#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1868 u8 reserved1[6];
1869};
1870
1871I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1872
1873/* Get Local AN advt register (direct 0x0614)
1874 * Set Local AN advt register (direct 0x0615)
1875 * Get Link Partner AN advt register (direct 0x0616)
1876 */
1877struct i40e_aqc_an_advt_reg {
1878 __le32 local_an_reg0;
1879 __le16 local_an_reg1;
1880 u8 reserved[10];
1881};
1882
1883I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1884
1885/* Set Loopback mode (0x0618) */
1886struct i40e_aqc_set_lb_mode {
1887 __le16 lb_mode;
1888#define I40E_AQ_LB_PHY_LOCAL 0x01
1889#define I40E_AQ_LB_PHY_REMOTE 0x02
1890#define I40E_AQ_LB_MAC_LOCAL 0x04
1891 u8 reserved[14];
1892};
1893
1894I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1895
1896/* Set PHY Debug command (0x0622) */
1897struct i40e_aqc_set_phy_debug {
1898 u8 command_flags;
1899#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1900#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1901#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1902 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1903#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1904#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1905#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1906/* Disable link manageability on a single port */
1907#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1908/* Disable link manageability on all ports */
1909#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1910 u8 reserved[15];
1911};
1912
1913I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1914
1915enum i40e_aq_phy_reg_type {
1916 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1917 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1918 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1919};
1920
1921/* Run PHY Activity (0x0626) */
1922struct i40e_aqc_run_phy_activity {
1923 __le16 activity_id;
1924 u8 flags;
1925 u8 reserved1;
1926 __le32 control;
1927 __le32 data;
1928 u8 reserved2[4];
1929};
1930
1931I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1932
1933/* NVM Read command (indirect 0x0701)
1934 * NVM Erase commands (direct 0x0702)
1935 * NVM Update commands (indirect 0x0703)
1936 */
1937struct i40e_aqc_nvm_update {
1938 u8 command_flags;
1939#define I40E_AQ_NVM_LAST_CMD 0x01
1940#define I40E_AQ_NVM_FLASH_ONLY 0x80
1941 u8 module_pointer;
1942 __le16 length;
1943 __le32 offset;
1944 __le32 addr_high;
1945 __le32 addr_low;
1946};
1947
1948I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1949
1950/* NVM Config Read (indirect 0x0704) */
1951struct i40e_aqc_nvm_config_read {
1952 __le16 cmd_flags;
1953#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1954#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1955#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1956 __le16 element_count;
1957 __le16 element_id; /* Feature/field ID */
1958 __le16 element_id_msw; /* MSWord of field ID */
1959 __le32 address_high;
1960 __le32 address_low;
1961};
1962
1963I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1964
1965/* NVM Config Write (indirect 0x0705) */
1966struct i40e_aqc_nvm_config_write {
1967 __le16 cmd_flags;
1968 __le16 element_count;
1969 u8 reserved[4];
1970 __le32 address_high;
1971 __le32 address_low;
1972};
1973
1974I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1975
1976/* Used for 0x0704 as well as for 0x0705 commands */
1977#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1978#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1979 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1980#define I40E_AQ_ANVM_FEATURE 0
1981#define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT)
1982struct i40e_aqc_nvm_config_data_feature {
1983 __le16 feature_id;
1984#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1985#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1986#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1987 __le16 feature_options;
1988 __le16 feature_selection;
1989};
1990
1991I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1992
1993struct i40e_aqc_nvm_config_data_immediate_field {
1994 __le32 field_id;
1995 __le32 field_value;
1996 __le16 field_options;
1997 __le16 reserved;
1998};
1999
2000I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2001
2002/* OEM Post Update (indirect 0x0720)
2003 * no command data struct used
2004 */
2005struct i40e_aqc_nvm_oem_post_update {
2006#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2007 u8 sel_data;
2008 u8 reserved[7];
2009};
2010
2011I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2012
2013struct i40e_aqc_nvm_oem_post_update_buffer {
2014 u8 str_len;
2015 u8 dev_addr;
2016 __le16 eeprom_addr;
2017 u8 data[36];
2018};
2019
2020I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2021
2022/* Thermal Sensor (indirect 0x0721)
2023 * read or set thermal sensor configs and values
2024 * takes a sensor and command specific data buffer, not detailed here
2025 */
2026struct i40e_aqc_thermal_sensor {
2027 u8 sensor_action;
2028#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2029#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2030#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2031 u8 reserved[7];
2032 __le32 addr_high;
2033 __le32 addr_low;
2034};
2035
2036I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2037
2038/* Send to PF command (indirect 0x0801) id is only used by PF
2039 * Send to VF command (indirect 0x0802) id is only used by PF
2040 * Send to Peer PF command (indirect 0x0803)
2041 */
2042struct i40e_aqc_pf_vf_message {
2043 __le32 id;
2044 u8 reserved[4];
2045 __le32 addr_high;
2046 __le32 addr_low;
2047};
2048
2049I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2050
2051/* Alternate structure */
2052
2053/* Direct write (direct 0x0900)
2054 * Direct read (direct 0x0902)
2055 */
2056struct i40e_aqc_alternate_write {
2057 __le32 address0;
2058 __le32 data0;
2059 __le32 address1;
2060 __le32 data1;
2061};
2062
2063I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2064
2065/* Indirect write (indirect 0x0901)
2066 * Indirect read (indirect 0x0903)
2067 */
2068
2069struct i40e_aqc_alternate_ind_write {
2070 __le32 address;
2071 __le32 length;
2072 __le32 addr_high;
2073 __le32 addr_low;
2074};
2075
2076I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2077
2078/* Done alternate write (direct 0x0904)
2079 * uses i40e_aq_desc
2080 */
2081struct i40e_aqc_alternate_write_done {
2082 __le16 cmd_flags;
2083#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2084#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2085#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2086#define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2087 u8 reserved[14];
2088};
2089
2090I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2091
2092/* Set OEM mode (direct 0x0905) */
2093struct i40e_aqc_alternate_set_mode {
2094 __le32 mode;
2095#define I40E_AQ_ALTERNATE_MODE_NONE 0
2096#define I40E_AQ_ALTERNATE_MODE_OEM 1
2097 u8 reserved[12];
2098};
2099
2100I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2101
2102/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2103
2104/* async events 0x10xx */
2105
2106/* Lan Queue Overflow Event (direct, 0x1001) */
2107struct i40e_aqc_lan_overflow {
2108 __le32 prtdcb_rupto;
2109 __le32 otx_ctl;
2110 u8 reserved[8];
2111};
2112
2113I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2114
2115/* Get LLDP MIB (indirect 0x0A00) */
2116struct i40e_aqc_lldp_get_mib {
2117 u8 type;
2118 u8 reserved1;
2119#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2120#define I40E_AQ_LLDP_MIB_LOCAL 0x0
2121#define I40E_AQ_LLDP_MIB_REMOTE 0x1
2122#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2123#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2124#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2125#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2126#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2127#define I40E_AQ_LLDP_TX_SHIFT 0x4
2128#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2129/* TX pause flags use I40E_AQ_LINK_TX_* above */
2130 __le16 local_len;
2131 __le16 remote_len;
2132 u8 reserved2[2];
2133 __le32 addr_high;
2134 __le32 addr_low;
2135};
2136
2137I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2138
2139/* Configure LLDP MIB Change Event (direct 0x0A01)
2140 * also used for the event (with type in the command field)
2141 */
2142struct i40e_aqc_lldp_update_mib {
2143 u8 command;
2144#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2145#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2146 u8 reserved[7];
2147 __le32 addr_high;
2148 __le32 addr_low;
2149};
2150
2151I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2152
2153/* Add LLDP TLV (indirect 0x0A02)
2154 * Delete LLDP TLV (indirect 0x0A04)
2155 */
2156struct i40e_aqc_lldp_add_tlv {
2157 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2158 u8 reserved1[1];
2159 __le16 len;
2160 u8 reserved2[4];
2161 __le32 addr_high;
2162 __le32 addr_low;
2163};
2164
2165I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2166
2167/* Update LLDP TLV (indirect 0x0A03) */
2168struct i40e_aqc_lldp_update_tlv {
2169 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2170 u8 reserved;
2171 __le16 old_len;
2172 __le16 new_offset;
2173 __le16 new_len;
2174 __le32 addr_high;
2175 __le32 addr_low;
2176};
2177
2178I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2179
2180/* Stop LLDP (direct 0x0A05) */
2181struct i40e_aqc_lldp_stop {
2182 u8 command;
2183#define I40E_AQ_LLDP_AGENT_STOP 0x0
2184#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2185 u8 reserved[15];
2186};
2187
2188I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2189
2190/* Start LLDP (direct 0x0A06) */
2191
2192struct i40e_aqc_lldp_start {
2193 u8 command;
2194#define I40E_AQ_LLDP_AGENT_START 0x1
2195 u8 reserved[15];
2196};
2197
2198I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2199
2200/* Get CEE DCBX Oper Config (0x0A07)
2201 * uses the generic descriptor struct
2202 * returns below as indirect response
2203 */
2204
2205#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2206#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2207#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2208#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2209#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2210#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2211
2212#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2213#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2214#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2215#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2216#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2217#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2218#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2219#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2220#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2221#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2222#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2223#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2224
2225/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2226 * word boundary layout issues, which the Linux compilers silently deal
2227 * with by adding padding, making the actual struct larger than designed.
2228 * However, the FW compiler for the NIC is less lenient and complains
2229 * about the struct. Hence, the struct defined here has an extra byte in
2230 * fields reserved3 and reserved4 to directly acknowledge that padding,
2231 * and the new length is used in the length check macro.
2232 */
2233struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2234 u8 reserved1;
2235 u8 oper_num_tc;
2236 u8 oper_prio_tc[4];
2237 u8 reserved2;
2238 u8 oper_tc_bw[8];
2239 u8 oper_pfc_en;
2240 u8 reserved3[2];
2241 __le16 oper_app_prio;
2242 u8 reserved4[2];
2243 __le16 tlv_status;
2244};
2245
2246I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2247
2248struct i40e_aqc_get_cee_dcb_cfg_resp {
2249 u8 oper_num_tc;
2250 u8 oper_prio_tc[4];
2251 u8 oper_tc_bw[8];
2252 u8 oper_pfc_en;
2253 __le16 oper_app_prio;
2254#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2255#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2256#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2257#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2258#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2259#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2260#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2261 __le32 tlv_status;
2262#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2263#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2264#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2265#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2266#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2267#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2268 u8 reserved[12];
2269};
2270
2271I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2272
2273/* Set Local LLDP MIB (indirect 0x0A08)
2274 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2275 */
2276struct i40e_aqc_lldp_set_local_mib {
2277#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2278#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2279#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2280#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2281#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \
2282 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2283#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2284 u8 type;
2285 u8 reserved0;
2286 __le16 length;
2287 u8 reserved1[4];
2288 __le32 address_high;
2289 __le32 address_low;
2290};
2291
2292I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2293
2294/* Stop/Start LLDP Agent (direct 0x0A09)
2295 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2296 */
2297struct i40e_aqc_lldp_stop_start_specific_agent {
2298#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2299#define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2300 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2301 u8 command;
2302 u8 reserved[15];
2303};
2304
2305I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2306
2307/* Add Udp Tunnel command and completion (direct 0x0B00) */
2308struct i40e_aqc_add_udp_tunnel {
2309 __le16 udp_port;
2310 u8 reserved0[3];
2311 u8 protocol_type;
2312#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2313#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2314#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2315#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2316 u8 reserved1[10];
2317};
2318
2319I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2320
2321struct i40e_aqc_add_udp_tunnel_completion {
2322 __le16 udp_port;
2323 u8 filter_entry_index;
2324 u8 multiple_pfs;
2325#define I40E_AQC_SINGLE_PF 0x0
2326#define I40E_AQC_MULTIPLE_PFS 0x1
2327 u8 total_filters;
2328 u8 reserved[11];
2329};
2330
2331I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2332
2333/* remove UDP Tunnel command (0x0B01) */
2334struct i40e_aqc_remove_udp_tunnel {
2335 u8 reserved[2];
2336 u8 index; /* 0 to 15 */
2337 u8 reserved2[13];
2338};
2339
2340I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2341
2342struct i40e_aqc_del_udp_tunnel_completion {
2343 __le16 udp_port;
2344 u8 index; /* 0 to 15 */
2345 u8 multiple_pfs;
2346 u8 total_filters_used;
2347 u8 reserved1[11];
2348};
2349
2350I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2351
2352struct i40e_aqc_get_set_rss_key {
2353#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2354#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2355#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2356 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2357 __le16 vsi_id;
2358 u8 reserved[6];
2359 __le32 addr_high;
2360 __le32 addr_low;
2361};
2362
2363I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2364
2365struct i40e_aqc_get_set_rss_key_data {
2366 u8 standard_rss_key[0x28];
2367 u8 extended_hash_key[0xc];
2368};
2369
2370I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2371
2372struct i40e_aqc_get_set_rss_lut {
2373#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2374#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2375#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2376 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2377 __le16 vsi_id;
2378#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2379#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2380
2381#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2382#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2383 __le16 flags;
2384 u8 reserved[4];
2385 __le32 addr_high;
2386 __le32 addr_low;
2387};
2388
2389I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2390
2391/* tunnel key structure 0x0B10 */
2392
2393struct i40e_aqc_tunnel_key_structure {
2394 u8 key1_off;
2395 u8 key2_off;
2396 u8 key1_len; /* 0 to 15 */
2397 u8 key2_len; /* 0 to 15 */
2398 u8 flags;
2399#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2400/* response flags */
2401#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2402#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2403#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2404 u8 network_key_index;
2405#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2406#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2407#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2408#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2409 u8 reserved[10];
2410};
2411
2412I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2413
2414/* OEM mode commands (direct 0xFE0x) */
2415struct i40e_aqc_oem_param_change {
2416 __le32 param_type;
2417#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2418#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2419#define I40E_AQ_OEM_PARAM_MAC 2
2420 __le32 param_value1;
2421 __le16 param_value2;
2422 u8 reserved[6];
2423};
2424
2425I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2426
2427struct i40e_aqc_oem_state_change {
2428 __le32 state;
2429#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2430#define I40E_AQ_OEM_STATE_LINK_UP 0x1
2431 u8 reserved[12];
2432};
2433
2434I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2435
2436/* Initialize OCSD (0xFE02, direct) */
2437struct i40e_aqc_opc_oem_ocsd_initialize {
2438 u8 type_status;
2439 u8 reserved1[3];
2440 __le32 ocsd_memory_block_addr_high;
2441 __le32 ocsd_memory_block_addr_low;
2442 __le32 requested_update_interval;
2443};
2444
2445I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2446
2447/* Initialize OCBB (0xFE03, direct) */
2448struct i40e_aqc_opc_oem_ocbb_initialize {
2449 u8 type_status;
2450 u8 reserved1[3];
2451 __le32 ocbb_memory_block_addr_high;
2452 __le32 ocbb_memory_block_addr_low;
2453 u8 reserved2[4];
2454};
2455
2456I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2457
2458/* debug commands */
2459
2460/* get device id (0xFF00) uses the generic structure */
2461
2462/* set test more (0xFF01, internal) */
2463
2464struct i40e_acq_set_test_mode {
2465 u8 mode;
2466#define I40E_AQ_TEST_PARTIAL 0
2467#define I40E_AQ_TEST_FULL 1
2468#define I40E_AQ_TEST_NVM 2
2469 u8 reserved[3];
2470 u8 command;
2471#define I40E_AQ_TEST_OPEN 0
2472#define I40E_AQ_TEST_CLOSE 1
2473#define I40E_AQ_TEST_INC 2
2474 u8 reserved2[3];
2475 __le32 address_high;
2476 __le32 address_low;
2477};
2478
2479I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2480
2481/* Debug Read Register command (0xFF03)
2482 * Debug Write Register command (0xFF04)
2483 */
2484struct i40e_aqc_debug_reg_read_write {
2485 __le32 reserved;
2486 __le32 address;
2487 __le32 value_high;
2488 __le32 value_low;
2489};
2490
2491I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2492
2493/* Scatter/gather Reg Read (indirect 0xFF05)
2494 * Scatter/gather Reg Write (indirect 0xFF06)
2495 */
2496
2497/* i40e_aq_desc is used for the command */
2498struct i40e_aqc_debug_reg_sg_element_data {
2499 __le32 address;
2500 __le32 value;
2501};
2502
2503/* Debug Modify register (direct 0xFF07) */
2504struct i40e_aqc_debug_modify_reg {
2505 __le32 address;
2506 __le32 value;
2507 __le32 clear_mask;
2508 __le32 set_mask;
2509};
2510
2511I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2512
2513/* dump internal data (0xFF08, indirect) */
2514
2515#define I40E_AQ_CLUSTER_ID_AUX 0
2516#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2517#define I40E_AQ_CLUSTER_ID_TXSCHED 2
2518#define I40E_AQ_CLUSTER_ID_HMC 3
2519#define I40E_AQ_CLUSTER_ID_MAC0 4
2520#define I40E_AQ_CLUSTER_ID_MAC1 5
2521#define I40E_AQ_CLUSTER_ID_MAC2 6
2522#define I40E_AQ_CLUSTER_ID_MAC3 7
2523#define I40E_AQ_CLUSTER_ID_DCB 8
2524#define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2525#define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2526#define I40E_AQ_CLUSTER_ID_ALTRAM 11
2527
2528struct i40e_aqc_debug_dump_internals {
2529 u8 cluster_id;
2530 u8 table_id;
2531 __le16 data_size;
2532 __le32 idx;
2533 __le32 address_high;
2534 __le32 address_low;
2535};
2536
2537I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2538
2539struct i40e_aqc_debug_modify_internals {
2540 u8 cluster_id;
2541 u8 cluster_specific_params[7];
2542 __le32 address_high;
2543 __le32 address_low;
2544};
2545
2546I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2547
2548#endif /* _I40E_ADMINQ_CMD_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4#ifndef _I40E_ADMINQ_CMD_H_
5#define _I40E_ADMINQ_CMD_H_
6
7/* This header file defines the i40e Admin Queue commands and is shared between
8 * i40e Firmware and Software.
9 *
10 * This file needs to comply with the Linux Kernel coding style.
11 */
12
13#define I40E_FW_API_VERSION_MAJOR 0x0001
14#define I40E_FW_API_VERSION_MINOR_X722 0x0009
15#define I40E_FW_API_VERSION_MINOR_X710 0x0009
16
17#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
18 I40E_FW_API_VERSION_MINOR_X710 : \
19 I40E_FW_API_VERSION_MINOR_X722)
20
21/* API version 1.7 implements additional link and PHY-specific APIs */
22#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
23/* API version 1.9 for X722 implements additional link and PHY-specific APIs */
24#define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
25/* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
26#define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
27/* API version 1.10 for X722 devices adds ability to request FEC encoding */
28#define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
29
30struct i40e_aq_desc {
31 __le16 flags;
32 __le16 opcode;
33 __le16 datalen;
34 __le16 retval;
35 __le32 cookie_high;
36 __le32 cookie_low;
37 union {
38 struct {
39 __le32 param0;
40 __le32 param1;
41 __le32 param2;
42 __le32 param3;
43 } internal;
44 struct {
45 __le32 param0;
46 __le32 param1;
47 __le32 addr_high;
48 __le32 addr_low;
49 } external;
50 u8 raw[16];
51 } params;
52};
53
54/* Flags sub-structure
55 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
56 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
57 */
58
59/* command flags and offsets*/
60#define I40E_AQ_FLAG_ERR_SHIFT 2
61#define I40E_AQ_FLAG_LB_SHIFT 9
62#define I40E_AQ_FLAG_RD_SHIFT 10
63#define I40E_AQ_FLAG_BUF_SHIFT 12
64#define I40E_AQ_FLAG_SI_SHIFT 13
65
66#define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
67#define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
68#define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
69#define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
70#define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
71
72/* error codes */
73enum i40e_admin_queue_err {
74 I40E_AQ_RC_OK = 0, /* success */
75 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
76 I40E_AQ_RC_ENOENT = 2, /* No such element */
77 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
78 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
79 I40E_AQ_RC_EIO = 5, /* I/O error */
80 I40E_AQ_RC_ENXIO = 6, /* No such resource */
81 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
82 I40E_AQ_RC_EAGAIN = 8, /* Try again */
83 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
84 I40E_AQ_RC_EACCES = 10, /* Permission denied */
85 I40E_AQ_RC_EFAULT = 11, /* Bad address */
86 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
87 I40E_AQ_RC_EEXIST = 13, /* object already exists */
88 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
89 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
90 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
91 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
92 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
93 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
94 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
95 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
96 I40E_AQ_RC_EFBIG = 22, /* File too large */
97};
98
99/* Admin Queue command opcodes */
100enum i40e_admin_queue_opc {
101 /* aq commands */
102 i40e_aqc_opc_get_version = 0x0001,
103 i40e_aqc_opc_driver_version = 0x0002,
104 i40e_aqc_opc_queue_shutdown = 0x0003,
105 i40e_aqc_opc_set_pf_context = 0x0004,
106
107 /* resource ownership */
108 i40e_aqc_opc_request_resource = 0x0008,
109 i40e_aqc_opc_release_resource = 0x0009,
110
111 i40e_aqc_opc_list_func_capabilities = 0x000A,
112 i40e_aqc_opc_list_dev_capabilities = 0x000B,
113
114 /* Proxy commands */
115 i40e_aqc_opc_set_proxy_config = 0x0104,
116 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
117
118 /* LAA */
119 i40e_aqc_opc_mac_address_read = 0x0107,
120 i40e_aqc_opc_mac_address_write = 0x0108,
121
122 /* PXE */
123 i40e_aqc_opc_clear_pxe_mode = 0x0110,
124
125 /* WoL commands */
126 i40e_aqc_opc_set_wol_filter = 0x0120,
127 i40e_aqc_opc_get_wake_reason = 0x0121,
128
129 /* internal switch commands */
130 i40e_aqc_opc_get_switch_config = 0x0200,
131 i40e_aqc_opc_add_statistics = 0x0201,
132 i40e_aqc_opc_remove_statistics = 0x0202,
133 i40e_aqc_opc_set_port_parameters = 0x0203,
134 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
135 i40e_aqc_opc_set_switch_config = 0x0205,
136 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
137 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
138
139 i40e_aqc_opc_add_vsi = 0x0210,
140 i40e_aqc_opc_update_vsi_parameters = 0x0211,
141 i40e_aqc_opc_get_vsi_parameters = 0x0212,
142
143 i40e_aqc_opc_add_pv = 0x0220,
144 i40e_aqc_opc_update_pv_parameters = 0x0221,
145 i40e_aqc_opc_get_pv_parameters = 0x0222,
146
147 i40e_aqc_opc_add_veb = 0x0230,
148 i40e_aqc_opc_update_veb_parameters = 0x0231,
149 i40e_aqc_opc_get_veb_parameters = 0x0232,
150
151 i40e_aqc_opc_delete_element = 0x0243,
152
153 i40e_aqc_opc_add_macvlan = 0x0250,
154 i40e_aqc_opc_remove_macvlan = 0x0251,
155 i40e_aqc_opc_add_vlan = 0x0252,
156 i40e_aqc_opc_remove_vlan = 0x0253,
157 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
158 i40e_aqc_opc_add_tag = 0x0255,
159 i40e_aqc_opc_remove_tag = 0x0256,
160 i40e_aqc_opc_add_multicast_etag = 0x0257,
161 i40e_aqc_opc_remove_multicast_etag = 0x0258,
162 i40e_aqc_opc_update_tag = 0x0259,
163 i40e_aqc_opc_add_control_packet_filter = 0x025A,
164 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
165 i40e_aqc_opc_add_cloud_filters = 0x025C,
166 i40e_aqc_opc_remove_cloud_filters = 0x025D,
167 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
168
169 i40e_aqc_opc_add_mirror_rule = 0x0260,
170 i40e_aqc_opc_delete_mirror_rule = 0x0261,
171
172 /* Dynamic Device Personalization */
173 i40e_aqc_opc_write_personalization_profile = 0x0270,
174 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
175
176 /* DCB commands */
177 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
178 i40e_aqc_opc_dcb_updated = 0x0302,
179 i40e_aqc_opc_set_dcb_parameters = 0x0303,
180
181 /* TX scheduler */
182 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
183 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
184 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
185 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
186 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
187 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
188
189 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
190 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
191 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
192 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
193 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
194 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
195 i40e_aqc_opc_query_port_ets_config = 0x0419,
196 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
197 i40e_aqc_opc_suspend_port_tx = 0x041B,
198 i40e_aqc_opc_resume_port_tx = 0x041C,
199 i40e_aqc_opc_configure_partition_bw = 0x041D,
200 /* hmc */
201 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
202 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
203
204 /* phy commands*/
205 i40e_aqc_opc_get_phy_abilities = 0x0600,
206 i40e_aqc_opc_set_phy_config = 0x0601,
207 i40e_aqc_opc_set_mac_config = 0x0603,
208 i40e_aqc_opc_set_link_restart_an = 0x0605,
209 i40e_aqc_opc_get_link_status = 0x0607,
210 i40e_aqc_opc_set_phy_int_mask = 0x0613,
211 i40e_aqc_opc_get_local_advt_reg = 0x0614,
212 i40e_aqc_opc_set_local_advt_reg = 0x0615,
213 i40e_aqc_opc_get_partner_advt = 0x0616,
214 i40e_aqc_opc_set_lb_modes = 0x0618,
215 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
216 i40e_aqc_opc_set_phy_debug = 0x0622,
217 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
218 i40e_aqc_opc_run_phy_activity = 0x0626,
219 i40e_aqc_opc_set_phy_register = 0x0628,
220 i40e_aqc_opc_get_phy_register = 0x0629,
221
222 /* NVM commands */
223 i40e_aqc_opc_nvm_read = 0x0701,
224 i40e_aqc_opc_nvm_erase = 0x0702,
225 i40e_aqc_opc_nvm_update = 0x0703,
226 i40e_aqc_opc_nvm_config_read = 0x0704,
227 i40e_aqc_opc_nvm_config_write = 0x0705,
228 i40e_aqc_opc_oem_post_update = 0x0720,
229 i40e_aqc_opc_thermal_sensor = 0x0721,
230
231 /* virtualization commands */
232 i40e_aqc_opc_send_msg_to_pf = 0x0801,
233 i40e_aqc_opc_send_msg_to_vf = 0x0802,
234 i40e_aqc_opc_send_msg_to_peer = 0x0803,
235
236 /* alternate structure */
237 i40e_aqc_opc_alternate_write = 0x0900,
238 i40e_aqc_opc_alternate_write_indirect = 0x0901,
239 i40e_aqc_opc_alternate_read = 0x0902,
240 i40e_aqc_opc_alternate_read_indirect = 0x0903,
241 i40e_aqc_opc_alternate_write_done = 0x0904,
242 i40e_aqc_opc_alternate_set_mode = 0x0905,
243 i40e_aqc_opc_alternate_clear_port = 0x0906,
244
245 /* LLDP commands */
246 i40e_aqc_opc_lldp_get_mib = 0x0A00,
247 i40e_aqc_opc_lldp_update_mib = 0x0A01,
248 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
249 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
250 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
251 i40e_aqc_opc_lldp_stop = 0x0A05,
252 i40e_aqc_opc_lldp_start = 0x0A06,
253 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
254 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
255 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
256 i40e_aqc_opc_lldp_restore = 0x0A0A,
257
258 /* Tunnel commands */
259 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
260 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
261 i40e_aqc_opc_set_rss_key = 0x0B02,
262 i40e_aqc_opc_set_rss_lut = 0x0B03,
263 i40e_aqc_opc_get_rss_key = 0x0B04,
264 i40e_aqc_opc_get_rss_lut = 0x0B05,
265
266 /* Async Events */
267 i40e_aqc_opc_event_lan_overflow = 0x1001,
268
269 /* OEM commands */
270 i40e_aqc_opc_oem_parameter_change = 0xFE00,
271 i40e_aqc_opc_oem_device_status_change = 0xFE01,
272 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
273 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
274
275 /* debug commands */
276 i40e_aqc_opc_debug_read_reg = 0xFF03,
277 i40e_aqc_opc_debug_write_reg = 0xFF04,
278 i40e_aqc_opc_debug_modify_reg = 0xFF07,
279 i40e_aqc_opc_debug_dump_internals = 0xFF08,
280};
281
282/* command structures and indirect data structures */
283
284/* Structure naming conventions:
285 * - no suffix for direct command descriptor structures
286 * - _data for indirect sent data
287 * - _resp for indirect return data (data which is both will use _data)
288 * - _completion for direct return data
289 * - _element_ for repeated elements (may also be _data or _resp)
290 *
291 * Command structures are expected to overlay the params.raw member of the basic
292 * descriptor, and as such cannot exceed 16 bytes in length.
293 */
294
295/* This macro is used to generate a compilation error if a structure
296 * is not exactly the correct length. It gives a divide by zero error if the
297 * structure is not of the correct size, otherwise it creates an enum that is
298 * never used.
299 */
300#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
301 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
302
303/* This macro is used extensively to ensure that command structures are 16
304 * bytes in length as they have to map to the raw array of that size.
305 */
306#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
307
308/* internal (0x00XX) commands */
309
310/* Get version (direct 0x0001) */
311struct i40e_aqc_get_version {
312 __le32 rom_ver;
313 __le32 fw_build;
314 __le16 fw_major;
315 __le16 fw_minor;
316 __le16 api_major;
317 __le16 api_minor;
318};
319
320I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
321
322/* Send driver version (indirect 0x0002) */
323struct i40e_aqc_driver_version {
324 u8 driver_major_ver;
325 u8 driver_minor_ver;
326 u8 driver_build_ver;
327 u8 driver_subbuild_ver;
328 u8 reserved[4];
329 __le32 address_high;
330 __le32 address_low;
331};
332
333I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
334
335/* Queue Shutdown (direct 0x0003) */
336struct i40e_aqc_queue_shutdown {
337 __le32 driver_unloading;
338#define I40E_AQ_DRIVER_UNLOADING 0x1
339 u8 reserved[12];
340};
341
342I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
343
344/* Set PF context (0x0004, direct) */
345struct i40e_aqc_set_pf_context {
346 u8 pf_id;
347 u8 reserved[15];
348};
349
350I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
351
352/* Request resource ownership (direct 0x0008)
353 * Release resource ownership (direct 0x0009)
354 */
355struct i40e_aqc_request_resource {
356 __le16 resource_id;
357 __le16 access_type;
358 __le32 timeout;
359 __le32 resource_number;
360 u8 reserved[4];
361};
362
363I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
364
365/* Get function capabilities (indirect 0x000A)
366 * Get device capabilities (indirect 0x000B)
367 */
368struct i40e_aqc_list_capabilites {
369 u8 command_flags;
370 u8 pf_index;
371 u8 reserved[2];
372 __le32 count;
373 __le32 addr_high;
374 __le32 addr_low;
375};
376
377I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
378
379struct i40e_aqc_list_capabilities_element_resp {
380 __le16 id;
381 u8 major_rev;
382 u8 minor_rev;
383 __le32 number;
384 __le32 logical_id;
385 __le32 phys_id;
386 u8 reserved[16];
387};
388
389/* list of caps */
390
391#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
392#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
393#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
394#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
395#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
396#define I40E_AQ_CAP_ID_SRIOV 0x0012
397#define I40E_AQ_CAP_ID_VF 0x0013
398#define I40E_AQ_CAP_ID_VMDQ 0x0014
399#define I40E_AQ_CAP_ID_8021QBG 0x0015
400#define I40E_AQ_CAP_ID_8021QBR 0x0016
401#define I40E_AQ_CAP_ID_VSI 0x0017
402#define I40E_AQ_CAP_ID_DCB 0x0018
403#define I40E_AQ_CAP_ID_FCOE 0x0021
404#define I40E_AQ_CAP_ID_ISCSI 0x0022
405#define I40E_AQ_CAP_ID_RSS 0x0040
406#define I40E_AQ_CAP_ID_RXQ 0x0041
407#define I40E_AQ_CAP_ID_TXQ 0x0042
408#define I40E_AQ_CAP_ID_MSIX 0x0043
409#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
410#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
411#define I40E_AQ_CAP_ID_1588 0x0046
412#define I40E_AQ_CAP_ID_IWARP 0x0051
413#define I40E_AQ_CAP_ID_LED 0x0061
414#define I40E_AQ_CAP_ID_SDP 0x0062
415#define I40E_AQ_CAP_ID_MDIO 0x0063
416#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
417#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
418#define I40E_AQ_CAP_ID_FLEX10 0x00F1
419#define I40E_AQ_CAP_ID_CEM 0x00F2
420
421/* Set CPPM Configuration (direct 0x0103) */
422struct i40e_aqc_cppm_configuration {
423 __le16 command_flags;
424 __le16 ttlx;
425 __le32 dmacr;
426 __le16 dmcth;
427 u8 hptc;
428 u8 reserved;
429 __le32 pfltrc;
430};
431
432I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
433
434/* Set ARP Proxy command / response (indirect 0x0104) */
435struct i40e_aqc_arp_proxy_data {
436 __le16 command_flags;
437 __le16 table_id;
438 __le32 enabled_offloads;
439 __le32 ip_addr;
440 u8 mac_addr[6];
441 u8 reserved[2];
442};
443
444I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
445
446/* Set NS Proxy Table Entry Command (indirect 0x0105) */
447struct i40e_aqc_ns_proxy_data {
448 __le16 table_idx_mac_addr_0;
449 __le16 table_idx_mac_addr_1;
450 __le16 table_idx_ipv6_0;
451 __le16 table_idx_ipv6_1;
452 __le16 control;
453 u8 mac_addr_0[6];
454 u8 mac_addr_1[6];
455 u8 local_mac_addr[6];
456 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
457 u8 ipv6_addr_1[16];
458};
459
460I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
461
462/* Manage LAA Command (0x0106) - obsolete */
463struct i40e_aqc_mng_laa {
464 __le16 command_flags;
465 u8 reserved[2];
466 __le32 sal;
467 __le16 sah;
468 u8 reserved2[6];
469};
470
471I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
472
473/* Manage MAC Address Read Command (indirect 0x0107) */
474struct i40e_aqc_mac_address_read {
475 __le16 command_flags;
476#define I40E_AQC_LAN_ADDR_VALID 0x10
477#define I40E_AQC_PORT_ADDR_VALID 0x40
478 u8 reserved[6];
479 __le32 addr_high;
480 __le32 addr_low;
481};
482
483I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
484
485struct i40e_aqc_mac_address_read_data {
486 u8 pf_lan_mac[6];
487 u8 pf_san_mac[6];
488 u8 port_mac[6];
489 u8 pf_wol_mac[6];
490};
491
492I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
493
494/* Manage MAC Address Write Command (0x0108) */
495struct i40e_aqc_mac_address_write {
496 __le16 command_flags;
497#define I40E_AQC_MC_MAG_EN 0x0100
498#define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
499#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
500#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
501#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
502
503 __le16 mac_sah;
504 __le32 mac_sal;
505 u8 reserved[8];
506};
507
508I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
509
510/* PXE commands (0x011x) */
511
512/* Clear PXE Command and response (direct 0x0110) */
513struct i40e_aqc_clear_pxe {
514 u8 rx_cnt;
515 u8 reserved[15];
516};
517
518I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
519
520/* Set WoL Filter (0x0120) */
521
522struct i40e_aqc_set_wol_filter {
523 __le16 filter_index;
524
525 __le16 cmd_flags;
526 __le16 valid_flags;
527 u8 reserved[2];
528 __le32 address_high;
529 __le32 address_low;
530};
531
532I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
533
534struct i40e_aqc_set_wol_filter_data {
535 u8 filter[128];
536 u8 mask[16];
537};
538
539I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
540
541/* Get Wake Reason (0x0121) */
542
543struct i40e_aqc_get_wake_reason_completion {
544 u8 reserved_1[2];
545 __le16 wake_reason;
546 u8 reserved_2[12];
547};
548
549I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
550
551/* Switch configuration commands (0x02xx) */
552
553/* Used by many indirect commands that only pass an seid and a buffer in the
554 * command
555 */
556struct i40e_aqc_switch_seid {
557 __le16 seid;
558 u8 reserved[6];
559 __le32 addr_high;
560 __le32 addr_low;
561};
562
563I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
564
565/* Get Switch Configuration command (indirect 0x0200)
566 * uses i40e_aqc_switch_seid for the descriptor
567 */
568struct i40e_aqc_get_switch_config_header_resp {
569 __le16 num_reported;
570 __le16 num_total;
571 u8 reserved[12];
572};
573
574I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
575
576struct i40e_aqc_switch_config_element_resp {
577 u8 element_type;
578 u8 revision;
579 __le16 seid;
580 __le16 uplink_seid;
581 __le16 downlink_seid;
582 u8 reserved[3];
583 u8 connection_type;
584 __le16 scheduler_id;
585 __le16 element_info;
586};
587
588I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
589
590/* Get Switch Configuration (indirect 0x0200)
591 * an array of elements are returned in the response buffer
592 * the first in the array is the header, remainder are elements
593 */
594struct i40e_aqc_get_switch_config_resp {
595 struct i40e_aqc_get_switch_config_header_resp header;
596 struct i40e_aqc_switch_config_element_resp element[1];
597};
598
599I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
600
601/* Add Statistics (direct 0x0201)
602 * Remove Statistics (direct 0x0202)
603 */
604struct i40e_aqc_add_remove_statistics {
605 __le16 seid;
606 __le16 vlan;
607 __le16 stat_index;
608 u8 reserved[10];
609};
610
611I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
612
613/* Set Port Parameters command (direct 0x0203) */
614struct i40e_aqc_set_port_parameters {
615 __le16 command_flags;
616 __le16 bad_frame_vsi;
617 __le16 default_seid; /* reserved for command */
618 u8 reserved[10];
619};
620
621I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
622
623/* Get Switch Resource Allocation (indirect 0x0204) */
624struct i40e_aqc_get_switch_resource_alloc {
625 u8 num_entries; /* reserved for command */
626 u8 reserved[7];
627 __le32 addr_high;
628 __le32 addr_low;
629};
630
631I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
632
633/* expect an array of these structs in the response buffer */
634struct i40e_aqc_switch_resource_alloc_element_resp {
635 u8 resource_type;
636 u8 reserved1;
637 __le16 guaranteed;
638 __le16 total;
639 __le16 used;
640 __le16 total_unalloced;
641 u8 reserved2[6];
642};
643
644I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
645
646/* Set Switch Configuration (direct 0x0205) */
647struct i40e_aqc_set_switch_config {
648 __le16 flags;
649/* flags used for both fields below */
650#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
651 __le16 valid_flags;
652 /* The ethertype in switch_tag is dropped on ingress and used
653 * internally by the switch. Set this to zero for the default
654 * of 0x88a8 (802.1ad). Should be zero for firmware API
655 * versions lower than 1.7.
656 */
657 __le16 switch_tag;
658 /* The ethertypes in first_tag and second_tag are used to
659 * match the outer and inner VLAN tags (respectively) when HW
660 * double VLAN tagging is enabled via the set port parameters
661 * AQ command. Otherwise these are both ignored. Set them to
662 * zero for their defaults of 0x8100 (802.1Q). Should be zero
663 * for firmware API versions lower than 1.7.
664 */
665 __le16 first_tag;
666 __le16 second_tag;
667 /* Next byte is split into following:
668 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
669 * Bit 6 : 0 : Destination Port, 1: source port
670 * Bit 5..4 : L4 type
671 * 0: rsvd
672 * 1: TCP
673 * 2: UDP
674 * 3: Both TCP and UDP
675 * Bits 3:0 Mode
676 * 0: default mode
677 * 1: L4 port only mode
678 * 2: non-tunneled mode
679 * 3: tunneled mode
680 */
681#define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
682
683
684#define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
685
686#define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
687 u8 mode;
688 u8 rsvd5[5];
689};
690
691I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
692
693/* Read Receive control registers (direct 0x0206)
694 * Write Receive control registers (direct 0x0207)
695 * used for accessing Rx control registers that can be
696 * slow and need special handling when under high Rx load
697 */
698struct i40e_aqc_rx_ctl_reg_read_write {
699 __le32 reserved1;
700 __le32 address;
701 __le32 reserved2;
702 __le32 value;
703};
704
705I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
706
707/* Add VSI (indirect 0x0210)
708 * this indirect command uses struct i40e_aqc_vsi_properties_data
709 * as the indirect buffer (128 bytes)
710 *
711 * Update VSI (indirect 0x211)
712 * uses the same data structure as Add VSI
713 *
714 * Get VSI (indirect 0x0212)
715 * uses the same completion and data structure as Add VSI
716 */
717struct i40e_aqc_add_get_update_vsi {
718 __le16 uplink_seid;
719 u8 connection_type;
720#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
721 u8 reserved1;
722 u8 vf_id;
723 u8 reserved2;
724 __le16 vsi_flags;
725#define I40E_AQ_VSI_TYPE_VF 0x0
726#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
727#define I40E_AQ_VSI_TYPE_PF 0x2
728 __le32 addr_high;
729 __le32 addr_low;
730};
731
732I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
733
734struct i40e_aqc_add_get_update_vsi_completion {
735 __le16 seid;
736 __le16 vsi_number;
737 __le16 vsi_used;
738 __le16 vsi_free;
739 __le32 addr_high;
740 __le32 addr_low;
741};
742
743I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
744
745struct i40e_aqc_vsi_properties_data {
746 /* first 96 byte are written by SW */
747 __le16 valid_sections;
748#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
749#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
750#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
751#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
752#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
753#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
754 /* switch section */
755 __le16 switch_id; /* 12bit id combined with flags below */
756#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
757#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
758#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
759#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
760 u8 sw_reserved[2];
761 /* security section */
762 u8 sec_flags;
763#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
764#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
765 u8 sec_reserved;
766 /* VLAN section */
767 __le16 pvid; /* VLANS include priority bits */
768 __le16 fcoe_pvid;
769 u8 port_vlan_flags;
770#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
771#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
772 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
773#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
774#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
775#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
776#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
777#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
778 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
779#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
780#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
781#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
782 u8 pvlan_reserved[3];
783 /* ingress egress up sections */
784 __le32 ingress_table; /* bitmap, 3 bits per up */
785 __le32 egress_table; /* same defines as for ingress table */
786 /* cascaded PV section */
787 __le16 cas_pv_tag;
788 u8 cas_pv_flags;
789 u8 cas_pv_reserved;
790 /* queue mapping section */
791 __le16 mapping_flags;
792#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
793#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
794 __le16 queue_mapping[16];
795 __le16 tc_mapping[8];
796#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
797#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
798 /* queueing option section */
799 u8 queueing_opt_flags;
800#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
801#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
802 u8 queueing_opt_reserved[3];
803 /* scheduler section */
804 u8 up_enable_bits;
805 u8 sched_reserved;
806 /* outer up section */
807 __le32 outer_up_table; /* same structure and defines as ingress tbl */
808 u8 cmd_reserved[8];
809 /* last 32 bytes are written by FW */
810 __le16 qs_handle[8];
811#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
812 __le16 stat_counter_idx;
813 __le16 sched_id;
814 u8 resp_reserved[12];
815};
816
817I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
818
819/* Add Port Virtualizer (direct 0x0220)
820 * also used for update PV (direct 0x0221) but only flags are used
821 * (IS_CTRL_PORT only works on add PV)
822 */
823struct i40e_aqc_add_update_pv {
824 __le16 command_flags;
825 __le16 uplink_seid;
826 __le16 connected_seid;
827 u8 reserved[10];
828};
829
830I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
831
832struct i40e_aqc_add_update_pv_completion {
833 /* reserved for update; for add also encodes error if rc == ENOSPC */
834 __le16 pv_seid;
835 u8 reserved[14];
836};
837
838I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
839
840/* Get PV Params (direct 0x0222)
841 * uses i40e_aqc_switch_seid for the descriptor
842 */
843
844struct i40e_aqc_get_pv_params_completion {
845 __le16 seid;
846 __le16 default_stag;
847 __le16 pv_flags; /* same flags as add_pv */
848 u8 reserved[8];
849 __le16 default_port_seid;
850};
851
852I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
853
854/* Add VEB (direct 0x0230) */
855struct i40e_aqc_add_veb {
856 __le16 uplink_seid;
857 __le16 downlink_seid;
858 __le16 veb_flags;
859#define I40E_AQC_ADD_VEB_FLOATING 0x1
860#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
861#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
862#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
863 u8 enable_tcs;
864 u8 reserved[9];
865};
866
867I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
868
869struct i40e_aqc_add_veb_completion {
870 u8 reserved[6];
871 __le16 switch_seid;
872 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
873 __le16 veb_seid;
874 __le16 statistic_index;
875 __le16 vebs_used;
876 __le16 vebs_free;
877};
878
879I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
880
881/* Get VEB Parameters (direct 0x0232)
882 * uses i40e_aqc_switch_seid for the descriptor
883 */
884struct i40e_aqc_get_veb_parameters_completion {
885 __le16 seid;
886 __le16 switch_id;
887 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
888 __le16 statistic_index;
889 __le16 vebs_used;
890 __le16 vebs_free;
891 u8 reserved[4];
892};
893
894I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
895
896/* Delete Element (direct 0x0243)
897 * uses the generic i40e_aqc_switch_seid
898 */
899
900/* Add MAC-VLAN (indirect 0x0250) */
901
902/* used for the command for most vlan commands */
903struct i40e_aqc_macvlan {
904 __le16 num_addresses;
905 __le16 seid[3];
906#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
907 __le32 addr_high;
908 __le32 addr_low;
909};
910
911I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
912
913/* indirect data for command and response */
914struct i40e_aqc_add_macvlan_element_data {
915 u8 mac_addr[6];
916 __le16 vlan_tag;
917 __le16 flags;
918#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
919#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
920#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
921 __le16 queue_number;
922 /* response section */
923 u8 match_method;
924#define I40E_AQC_MM_ERR_NO_RES 0xFF
925 u8 reserved1[3];
926};
927
928struct i40e_aqc_add_remove_macvlan_completion {
929 __le16 perfect_mac_used;
930 __le16 perfect_mac_free;
931 __le16 unicast_hash_free;
932 __le16 multicast_hash_free;
933 __le32 addr_high;
934 __le32 addr_low;
935};
936
937I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
938
939/* Remove MAC-VLAN (indirect 0x0251)
940 * uses i40e_aqc_macvlan for the descriptor
941 * data points to an array of num_addresses of elements
942 */
943
944struct i40e_aqc_remove_macvlan_element_data {
945 u8 mac_addr[6];
946 __le16 vlan_tag;
947 u8 flags;
948#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
949#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
950 u8 reserved[3];
951 /* reply section */
952 u8 error_code;
953 u8 reply_reserved[3];
954};
955
956/* Add VLAN (indirect 0x0252)
957 * Remove VLAN (indirect 0x0253)
958 * use the generic i40e_aqc_macvlan for the command
959 */
960struct i40e_aqc_add_remove_vlan_element_data {
961 __le16 vlan_tag;
962 u8 vlan_flags;
963 u8 reserved;
964 u8 result;
965 u8 reserved1[3];
966};
967
968struct i40e_aqc_add_remove_vlan_completion {
969 u8 reserved[4];
970 __le16 vlans_used;
971 __le16 vlans_free;
972 __le32 addr_high;
973 __le32 addr_low;
974};
975
976/* Set VSI Promiscuous Modes (direct 0x0254) */
977struct i40e_aqc_set_vsi_promiscuous_modes {
978 __le16 promiscuous_flags;
979 __le16 valid_flags;
980/* flags used for both fields above */
981#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
982#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
983#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
984#define I40E_AQC_SET_VSI_DEFAULT 0x08
985#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
986#define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000
987 __le16 seid;
988 __le16 vlan_tag;
989#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
990 u8 reserved[8];
991};
992
993I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
994
995/* Add S/E-tag command (direct 0x0255)
996 * Uses generic i40e_aqc_add_remove_tag_completion for completion
997 */
998struct i40e_aqc_add_tag {
999 __le16 flags;
1000 __le16 seid;
1001 __le16 tag;
1002 __le16 queue_number;
1003 u8 reserved[8];
1004};
1005
1006I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1007
1008struct i40e_aqc_add_remove_tag_completion {
1009 u8 reserved[12];
1010 __le16 tags_used;
1011 __le16 tags_free;
1012};
1013
1014I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1015
1016/* Remove S/E-tag command (direct 0x0256)
1017 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1018 */
1019struct i40e_aqc_remove_tag {
1020 __le16 seid;
1021 __le16 tag;
1022 u8 reserved[12];
1023};
1024
1025I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1026
1027/* Add multicast E-Tag (direct 0x0257)
1028 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1029 * and no external data
1030 */
1031struct i40e_aqc_add_remove_mcast_etag {
1032 __le16 pv_seid;
1033 __le16 etag;
1034 u8 num_unicast_etags;
1035 u8 reserved[3];
1036 __le32 addr_high; /* address of array of 2-byte s-tags */
1037 __le32 addr_low;
1038};
1039
1040I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1041
1042struct i40e_aqc_add_remove_mcast_etag_completion {
1043 u8 reserved[4];
1044 __le16 mcast_etags_used;
1045 __le16 mcast_etags_free;
1046 __le32 addr_high;
1047 __le32 addr_low;
1048
1049};
1050
1051I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1052
1053/* Update S/E-Tag (direct 0x0259) */
1054struct i40e_aqc_update_tag {
1055 __le16 seid;
1056 __le16 old_tag;
1057 __le16 new_tag;
1058 u8 reserved[10];
1059};
1060
1061I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1062
1063struct i40e_aqc_update_tag_completion {
1064 u8 reserved[12];
1065 __le16 tags_used;
1066 __le16 tags_free;
1067};
1068
1069I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1070
1071/* Add Control Packet filter (direct 0x025A)
1072 * Remove Control Packet filter (direct 0x025B)
1073 * uses the i40e_aqc_add_oveb_cloud,
1074 * and the generic direct completion structure
1075 */
1076struct i40e_aqc_add_remove_control_packet_filter {
1077 u8 mac[6];
1078 __le16 etype;
1079 __le16 flags;
1080#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1081#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1082#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1083#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1084 __le16 seid;
1085 __le16 queue;
1086 u8 reserved[2];
1087};
1088
1089I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1090
1091struct i40e_aqc_add_remove_control_packet_filter_completion {
1092 __le16 mac_etype_used;
1093 __le16 etype_used;
1094 __le16 mac_etype_free;
1095 __le16 etype_free;
1096 u8 reserved[8];
1097};
1098
1099I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1100
1101/* Add Cloud filters (indirect 0x025C)
1102 * Remove Cloud filters (indirect 0x025D)
1103 * uses the i40e_aqc_add_remove_cloud_filters,
1104 * and the generic indirect completion structure
1105 */
1106struct i40e_aqc_add_remove_cloud_filters {
1107 u8 num_filters;
1108 u8 reserved;
1109 __le16 seid;
1110 u8 big_buffer_flag;
1111#define I40E_AQC_ADD_CLOUD_CMD_BB 1
1112 u8 reserved2[3];
1113 __le32 addr_high;
1114 __le32 addr_low;
1115};
1116
1117I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1118
1119struct i40e_aqc_cloud_filters_element_data {
1120 u8 outer_mac[6];
1121 u8 inner_mac[6];
1122 __le16 inner_vlan;
1123 union {
1124 struct {
1125 u8 reserved[12];
1126 u8 data[4];
1127 } v4;
1128 struct {
1129 u8 data[16];
1130 } v6;
1131 struct {
1132 __le16 data[8];
1133 } raw_v6;
1134 } ipaddr;
1135 __le16 flags;
1136/* 0x0000 reserved */
1137/* 0x0001 reserved */
1138/* 0x0002 reserved */
1139#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1140#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1141/* 0x0005 reserved */
1142#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1143/* 0x0007 reserved */
1144/* 0x0008 reserved */
1145#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1146#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1147#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1148#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1149/* 0x000D reserved */
1150/* 0x000E reserved */
1151/* 0x000F reserved */
1152/* 0x0010 to 0x0017 is for custom filters */
1153#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1154#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1155#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1156
1157#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1158#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1159
1160#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1161#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1162#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1163
1164
1165 __le32 tenant_id;
1166 u8 reserved[4];
1167 __le16 queue_number;
1168 u8 reserved2[14];
1169 /* response section */
1170 u8 allocation_result;
1171 u8 response_reserved[7];
1172};
1173
1174I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1175
1176/* i40e_aqc_cloud_filters_element_bb is used when
1177 * I40E_AQC_CLOUD_CMD_BB flag is set.
1178 */
1179struct i40e_aqc_cloud_filters_element_bb {
1180 struct i40e_aqc_cloud_filters_element_data element;
1181 u16 general_fields[32];
1182#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1183};
1184
1185I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1186
1187struct i40e_aqc_remove_cloud_filters_completion {
1188 __le16 perfect_ovlan_used;
1189 __le16 perfect_ovlan_free;
1190 __le16 vlan_used;
1191 __le16 vlan_free;
1192 __le32 addr_high;
1193 __le32 addr_low;
1194};
1195
1196I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1197
1198/* Replace filter Command 0x025F
1199 * uses the i40e_aqc_replace_cloud_filters,
1200 * and the generic indirect completion structure
1201 */
1202struct i40e_filter_data {
1203 u8 filter_type;
1204 u8 input[3];
1205};
1206
1207I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1208
1209struct i40e_aqc_replace_cloud_filters_cmd {
1210 u8 valid_flags;
1211 u8 old_filter_type;
1212 u8 new_filter_type;
1213 u8 tr_bit;
1214 u8 reserved[4];
1215 __le32 addr_high;
1216 __le32 addr_low;
1217};
1218
1219I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1220
1221struct i40e_aqc_replace_cloud_filters_cmd_buf {
1222 u8 data[32];
1223 struct i40e_filter_data filters[8];
1224};
1225
1226I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1227
1228/* Add Mirror Rule (indirect or direct 0x0260)
1229 * Delete Mirror Rule (indirect or direct 0x0261)
1230 * note: some rule types (4,5) do not use an external buffer.
1231 * take care to set the flags correctly.
1232 */
1233struct i40e_aqc_add_delete_mirror_rule {
1234 __le16 seid;
1235 __le16 rule_type;
1236#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1237#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1238 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1239#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1240#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1241#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1242 __le16 num_entries;
1243 __le16 destination; /* VSI for add, rule id for delete */
1244 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1245 __le32 addr_low;
1246};
1247
1248I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1249
1250struct i40e_aqc_add_delete_mirror_rule_completion {
1251 u8 reserved[2];
1252 __le16 rule_id; /* only used on add */
1253 __le16 mirror_rules_used;
1254 __le16 mirror_rules_free;
1255 __le32 addr_high;
1256 __le32 addr_low;
1257};
1258
1259I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1260
1261/* Dynamic Device Personalization */
1262struct i40e_aqc_write_personalization_profile {
1263 u8 flags;
1264 u8 reserved[3];
1265 __le32 profile_track_id;
1266 __le32 addr_high;
1267 __le32 addr_low;
1268};
1269
1270I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1271
1272struct i40e_aqc_write_ddp_resp {
1273 __le32 error_offset;
1274 __le32 error_info;
1275 __le32 addr_high;
1276 __le32 addr_low;
1277};
1278
1279struct i40e_aqc_get_applied_profiles {
1280 u8 flags;
1281 u8 rsv[3];
1282 __le32 reserved;
1283 __le32 addr_high;
1284 __le32 addr_low;
1285};
1286
1287I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1288
1289/* DCB 0x03xx*/
1290
1291/* PFC Ignore (direct 0x0301)
1292 * the command and response use the same descriptor structure
1293 */
1294struct i40e_aqc_pfc_ignore {
1295 u8 tc_bitmap;
1296 u8 command_flags; /* unused on response */
1297 u8 reserved[14];
1298};
1299
1300I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1301
1302/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1303 * with no parameters
1304 */
1305
1306/* TX scheduler 0x04xx */
1307
1308/* Almost all the indirect commands use
1309 * this generic struct to pass the SEID in param0
1310 */
1311struct i40e_aqc_tx_sched_ind {
1312 __le16 vsi_seid;
1313 u8 reserved[6];
1314 __le32 addr_high;
1315 __le32 addr_low;
1316};
1317
1318I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1319
1320/* Several commands respond with a set of queue set handles */
1321struct i40e_aqc_qs_handles_resp {
1322 __le16 qs_handles[8];
1323};
1324
1325/* Configure VSI BW limits (direct 0x0400) */
1326struct i40e_aqc_configure_vsi_bw_limit {
1327 __le16 vsi_seid;
1328 u8 reserved[2];
1329 __le16 credit;
1330 u8 reserved1[2];
1331 u8 max_credit; /* 0-3, limit = 2^max */
1332 u8 reserved2[7];
1333};
1334
1335I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1336
1337/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1338 * responds with i40e_aqc_qs_handles_resp
1339 */
1340struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1341 u8 tc_valid_bits;
1342 u8 reserved[15];
1343 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1344
1345 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1346 __le16 tc_bw_max[2];
1347 u8 reserved1[28];
1348};
1349
1350I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1351
1352/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1353 * responds with i40e_aqc_qs_handles_resp
1354 */
1355struct i40e_aqc_configure_vsi_tc_bw_data {
1356 u8 tc_valid_bits;
1357 u8 reserved[3];
1358 u8 tc_bw_credits[8];
1359 u8 reserved1[4];
1360 __le16 qs_handles[8];
1361};
1362
1363I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1364
1365/* Query vsi bw configuration (indirect 0x0408) */
1366struct i40e_aqc_query_vsi_bw_config_resp {
1367 u8 tc_valid_bits;
1368 u8 tc_suspended_bits;
1369 u8 reserved[14];
1370 __le16 qs_handles[8];
1371 u8 reserved1[4];
1372 __le16 port_bw_limit;
1373 u8 reserved2[2];
1374 u8 max_bw; /* 0-3, limit = 2^max */
1375 u8 reserved3[23];
1376};
1377
1378I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1379
1380/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1381struct i40e_aqc_query_vsi_ets_sla_config_resp {
1382 u8 tc_valid_bits;
1383 u8 reserved[3];
1384 u8 share_credits[8];
1385 __le16 credits[8];
1386
1387 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1388 __le16 tc_bw_max[2];
1389};
1390
1391I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1392
1393/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1394struct i40e_aqc_configure_switching_comp_bw_limit {
1395 __le16 seid;
1396 u8 reserved[2];
1397 __le16 credit;
1398 u8 reserved1[2];
1399 u8 max_bw; /* 0-3, limit = 2^max */
1400 u8 reserved2[7];
1401};
1402
1403I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1404
1405/* Enable Physical Port ETS (indirect 0x0413)
1406 * Modify Physical Port ETS (indirect 0x0414)
1407 * Disable Physical Port ETS (indirect 0x0415)
1408 */
1409struct i40e_aqc_configure_switching_comp_ets_data {
1410 u8 reserved[4];
1411 u8 tc_valid_bits;
1412 u8 seepage;
1413 u8 tc_strict_priority_flags;
1414 u8 reserved1[17];
1415 u8 tc_bw_share_credits[8];
1416 u8 reserved2[96];
1417};
1418
1419I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1420
1421/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1422struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1423 u8 tc_valid_bits;
1424 u8 reserved[15];
1425 __le16 tc_bw_credit[8];
1426
1427 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1428 __le16 tc_bw_max[2];
1429 u8 reserved1[28];
1430};
1431
1432I40E_CHECK_STRUCT_LEN(0x40,
1433 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1434
1435/* Configure Switching Component Bandwidth Allocation per Tc
1436 * (indirect 0x0417)
1437 */
1438struct i40e_aqc_configure_switching_comp_bw_config_data {
1439 u8 tc_valid_bits;
1440 u8 reserved[2];
1441 u8 absolute_credits; /* bool */
1442 u8 tc_bw_share_credits[8];
1443 u8 reserved1[20];
1444};
1445
1446I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1447
1448/* Query Switching Component Configuration (indirect 0x0418) */
1449struct i40e_aqc_query_switching_comp_ets_config_resp {
1450 u8 tc_valid_bits;
1451 u8 reserved[35];
1452 __le16 port_bw_limit;
1453 u8 reserved1[2];
1454 u8 tc_bw_max; /* 0-3, limit = 2^max */
1455 u8 reserved2[23];
1456};
1457
1458I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1459
1460/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1461struct i40e_aqc_query_port_ets_config_resp {
1462 u8 reserved[4];
1463 u8 tc_valid_bits;
1464 u8 reserved1;
1465 u8 tc_strict_priority_bits;
1466 u8 reserved2;
1467 u8 tc_bw_share_credits[8];
1468 __le16 tc_bw_limits[8];
1469
1470 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1471 __le16 tc_bw_max[2];
1472 u8 reserved3[32];
1473};
1474
1475I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1476
1477/* Query Switching Component Bandwidth Allocation per Traffic Type
1478 * (indirect 0x041A)
1479 */
1480struct i40e_aqc_query_switching_comp_bw_config_resp {
1481 u8 tc_valid_bits;
1482 u8 reserved[2];
1483 u8 absolute_credits_enable; /* bool */
1484 u8 tc_bw_share_credits[8];
1485 __le16 tc_bw_limits[8];
1486
1487 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1488 __le16 tc_bw_max[2];
1489};
1490
1491I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1492
1493/* Suspend/resume port TX traffic
1494 * (direct 0x041B and 0x041C) uses the generic SEID struct
1495 */
1496
1497/* Configure partition BW
1498 * (indirect 0x041D)
1499 */
1500struct i40e_aqc_configure_partition_bw_data {
1501 __le16 pf_valid_bits;
1502 u8 min_bw[16]; /* guaranteed bandwidth */
1503 u8 max_bw[16]; /* bandwidth limit */
1504};
1505
1506I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1507
1508/* Get and set the active HMC resource profile and status.
1509 * (direct 0x0500) and (direct 0x0501)
1510 */
1511struct i40e_aq_get_set_hmc_resource_profile {
1512 u8 pm_profile;
1513 u8 pe_vf_enabled;
1514 u8 reserved[14];
1515};
1516
1517I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1518
1519enum i40e_aq_hmc_profile {
1520 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1521 I40E_HMC_PROFILE_DEFAULT = 1,
1522 I40E_HMC_PROFILE_FAVOR_VF = 2,
1523 I40E_HMC_PROFILE_EQUAL = 3,
1524};
1525
1526/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1527
1528/* set in param0 for get phy abilities to report qualified modules */
1529#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1530#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1531
1532enum i40e_aq_phy_type {
1533 I40E_PHY_TYPE_SGMII = 0x0,
1534 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1535 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1536 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1537 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1538 I40E_PHY_TYPE_XAUI = 0x5,
1539 I40E_PHY_TYPE_XFI = 0x6,
1540 I40E_PHY_TYPE_SFI = 0x7,
1541 I40E_PHY_TYPE_XLAUI = 0x8,
1542 I40E_PHY_TYPE_XLPPI = 0x9,
1543 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1544 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1545 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1546 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1547 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1548 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1549 I40E_PHY_TYPE_100BASE_TX = 0x11,
1550 I40E_PHY_TYPE_1000BASE_T = 0x12,
1551 I40E_PHY_TYPE_10GBASE_T = 0x13,
1552 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1553 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1554 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1555 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1556 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1557 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1558 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1559 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1560 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1561 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1562 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1563 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1564 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1565 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1566 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1567 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1568 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1569 I40E_PHY_TYPE_2_5GBASE_T = 0x26,
1570 I40E_PHY_TYPE_5GBASE_T = 0x27,
1571 I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS = 0x30,
1572 I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31,
1573 I40E_PHY_TYPE_MAX,
1574 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1575 I40E_PHY_TYPE_EMPTY = 0xFE,
1576 I40E_PHY_TYPE_DEFAULT = 0xFF,
1577};
1578
1579#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1580 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1581 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1582 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1583 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1584 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1585 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1586 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1587 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1588 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1589 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1590 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1591 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1592 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1593 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1594 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1595 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1596 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1597 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1598 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1599 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1600 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1601 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1602 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1603 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1604 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1605 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1606 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1607 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1608 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1609 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1610 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1611 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1612 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1613 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1614 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1615 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1616 BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1617
1618#define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
1619#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1620#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1621#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1622#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1623#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1624#define I40E_LINK_SPEED_25GB_SHIFT 0x6
1625#define I40E_LINK_SPEED_5GB_SHIFT 0x7
1626
1627enum i40e_aq_link_speed {
1628 I40E_LINK_SPEED_UNKNOWN = 0,
1629 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1630 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1631 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
1632 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT),
1633 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1634 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1635 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1636 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1637};
1638
1639struct i40e_aqc_module_desc {
1640 u8 oui[3];
1641 u8 reserved1;
1642 u8 part_number[16];
1643 u8 revision[4];
1644 u8 reserved2[8];
1645};
1646
1647I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1648
1649struct i40e_aq_get_phy_abilities_resp {
1650 __le32 phy_type; /* bitmap using the above enum for offsets */
1651 u8 link_speed; /* bitmap using the above enum bit patterns */
1652 u8 abilities;
1653#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1654#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1655 __le16 eee_capability;
1656 __le32 eeer_val;
1657 u8 d3_lpan;
1658 u8 phy_type_ext;
1659#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1660#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1661#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1662#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1663 u8 fec_cfg_curr_mod_ext_info;
1664#define I40E_AQ_REQUEST_FEC_KR 0x04
1665#define I40E_AQ_REQUEST_FEC_RS 0x08
1666#define I40E_AQ_ENABLE_FEC_AUTO 0x10
1667
1668 u8 ext_comp_code;
1669 u8 phy_id[4];
1670 u8 module_type[3];
1671 u8 qualified_module_count;
1672#define I40E_AQ_PHY_MAX_QMS 16
1673 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1674};
1675
1676I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1677
1678/* Set PHY Config (direct 0x0601) */
1679struct i40e_aq_set_phy_config { /* same bits as above in all */
1680 __le32 phy_type;
1681 u8 link_speed;
1682 u8 abilities;
1683/* bits 0-2 use the values from get_phy_abilities_resp */
1684#define I40E_AQ_PHY_ENABLE_LINK 0x08
1685#define I40E_AQ_PHY_ENABLE_AN 0x10
1686#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1687 __le16 eee_capability;
1688 __le32 eeer;
1689 u8 low_power_ctrl;
1690 u8 phy_type_ext;
1691#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1692#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1693#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1694#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1695 u8 fec_config;
1696#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1697#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1698#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1699#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1700#define I40E_AQ_SET_FEC_AUTO BIT(4)
1701#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1702#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1703 u8 reserved;
1704};
1705
1706I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1707
1708/* Set MAC Config command data structure (direct 0x0603) */
1709struct i40e_aq_set_mac_config {
1710 __le16 max_frame_size;
1711 u8 params;
1712 u8 tx_timer_priority; /* bitmap */
1713 __le16 tx_timer_value;
1714 __le16 fc_refresh_threshold;
1715 u8 reserved[8];
1716};
1717
1718I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1719
1720/* Restart Auto-Negotiation (direct 0x605) */
1721struct i40e_aqc_set_link_restart_an {
1722 u8 command;
1723#define I40E_AQ_PHY_RESTART_AN 0x02
1724#define I40E_AQ_PHY_LINK_ENABLE 0x04
1725 u8 reserved[15];
1726};
1727
1728I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1729
1730/* Get Link Status cmd & response data structure (direct 0x0607) */
1731struct i40e_aqc_get_link_status {
1732 __le16 command_flags; /* only field set on command */
1733#define I40E_AQ_LSE_DISABLE 0x2
1734#define I40E_AQ_LSE_ENABLE 0x3
1735/* only response uses this flag */
1736#define I40E_AQ_LSE_IS_ENABLED 0x1
1737 u8 phy_type; /* i40e_aq_phy_type */
1738 u8 link_speed; /* i40e_aq_link_speed */
1739 u8 link_info;
1740#define I40E_AQ_LINK_UP 0x01 /* obsolete */
1741#define I40E_AQ_MEDIA_AVAILABLE 0x40
1742 u8 an_info;
1743#define I40E_AQ_AN_COMPLETED 0x01
1744#define I40E_AQ_LINK_PAUSE_TX 0x20
1745#define I40E_AQ_LINK_PAUSE_RX 0x40
1746#define I40E_AQ_QUALIFIED_MODULE 0x80
1747 u8 ext_info;
1748 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1749/* Since firmware API 1.7 loopback field keeps power class info as well */
1750#define I40E_AQ_LOOPBACK_MASK 0x07
1751 __le16 max_frame_size;
1752 u8 config;
1753#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1754#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1755#define I40E_AQ_CONFIG_CRC_ENA 0x04
1756#define I40E_AQ_CONFIG_PACING_MASK 0x78
1757 union {
1758 struct {
1759 u8 power_desc;
1760 u8 reserved[4];
1761 };
1762 struct {
1763 u8 link_type[4];
1764 u8 link_type_ext;
1765 };
1766 };
1767};
1768
1769I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1770
1771/* Set event mask command (direct 0x613) */
1772struct i40e_aqc_set_phy_int_mask {
1773 u8 reserved[8];
1774 __le16 event_mask;
1775#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1776#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1777#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1778 u8 reserved1[6];
1779};
1780
1781I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1782
1783/* Get Local AN advt register (direct 0x0614)
1784 * Set Local AN advt register (direct 0x0615)
1785 * Get Link Partner AN advt register (direct 0x0616)
1786 */
1787struct i40e_aqc_an_advt_reg {
1788 __le32 local_an_reg0;
1789 __le16 local_an_reg1;
1790 u8 reserved[10];
1791};
1792
1793I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1794
1795/* Set Loopback mode (0x0618) */
1796struct i40e_aqc_set_lb_mode {
1797 __le16 lb_mode;
1798#define I40E_AQ_LB_PHY_LOCAL 0x01
1799#define I40E_AQ_LB_PHY_REMOTE 0x02
1800#define I40E_AQ_LB_MAC_LOCAL 0x04
1801 u8 reserved[14];
1802};
1803
1804I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1805
1806/* Set PHY Debug command (0x0622) */
1807struct i40e_aqc_set_phy_debug {
1808 u8 command_flags;
1809/* Disable link manageability on a single port */
1810#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1811/* Disable link manageability on all ports */
1812#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1813 u8 reserved[15];
1814};
1815
1816I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1817
1818enum i40e_aq_phy_reg_type {
1819 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1820 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1821 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1822};
1823
1824/* Run PHY Activity (0x0626) */
1825struct i40e_aqc_run_phy_activity {
1826 __le16 activity_id;
1827 u8 flags;
1828 u8 reserved1;
1829 __le32 control;
1830 __le32 data;
1831 u8 reserved2[4];
1832};
1833
1834I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1835
1836/* Set PHY Register command (0x0628) */
1837/* Get PHY Register command (0x0629) */
1838struct i40e_aqc_phy_register_access {
1839 u8 phy_interface;
1840#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
1841#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
1842 u8 dev_address;
1843 u8 cmd_flags;
1844#define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01
1845#define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02
1846#define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2
1847#define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \
1848 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT)
1849 u8 reserved1;
1850 __le32 reg_address;
1851 __le32 reg_value;
1852 u8 reserved2[4];
1853};
1854
1855I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
1856
1857/* NVM Read command (indirect 0x0701)
1858 * NVM Erase commands (direct 0x0702)
1859 * NVM Update commands (indirect 0x0703)
1860 */
1861struct i40e_aqc_nvm_update {
1862 u8 command_flags;
1863#define I40E_AQ_NVM_LAST_CMD 0x01
1864#define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
1865#define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
1866#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
1867#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
1868#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
1869 u8 module_pointer;
1870 __le16 length;
1871 __le32 offset;
1872 __le32 addr_high;
1873 __le32 addr_low;
1874};
1875
1876I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1877
1878/* NVM Config Read (indirect 0x0704) */
1879struct i40e_aqc_nvm_config_read {
1880 __le16 cmd_flags;
1881 __le16 element_count;
1882 __le16 element_id; /* Feature/field ID */
1883 __le16 element_id_msw; /* MSWord of field ID */
1884 __le32 address_high;
1885 __le32 address_low;
1886};
1887
1888I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1889
1890/* NVM Config Write (indirect 0x0705) */
1891struct i40e_aqc_nvm_config_write {
1892 __le16 cmd_flags;
1893 __le16 element_count;
1894 u8 reserved[4];
1895 __le32 address_high;
1896 __le32 address_low;
1897};
1898
1899I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1900
1901/* Used for 0x0704 as well as for 0x0705 commands */
1902struct i40e_aqc_nvm_config_data_feature {
1903 __le16 feature_id;
1904 __le16 feature_options;
1905 __le16 feature_selection;
1906};
1907
1908I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1909
1910struct i40e_aqc_nvm_config_data_immediate_field {
1911 __le32 field_id;
1912 __le32 field_value;
1913 __le16 field_options;
1914 __le16 reserved;
1915};
1916
1917I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1918
1919/* OEM Post Update (indirect 0x0720)
1920 * no command data struct used
1921 */
1922struct i40e_aqc_nvm_oem_post_update {
1923 u8 sel_data;
1924 u8 reserved[7];
1925};
1926
1927I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1928
1929struct i40e_aqc_nvm_oem_post_update_buffer {
1930 u8 str_len;
1931 u8 dev_addr;
1932 __le16 eeprom_addr;
1933 u8 data[36];
1934};
1935
1936I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1937
1938/* Thermal Sensor (indirect 0x0721)
1939 * read or set thermal sensor configs and values
1940 * takes a sensor and command specific data buffer, not detailed here
1941 */
1942struct i40e_aqc_thermal_sensor {
1943 u8 sensor_action;
1944 u8 reserved[7];
1945 __le32 addr_high;
1946 __le32 addr_low;
1947};
1948
1949I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1950
1951/* Send to PF command (indirect 0x0801) id is only used by PF
1952 * Send to VF command (indirect 0x0802) id is only used by PF
1953 * Send to Peer PF command (indirect 0x0803)
1954 */
1955struct i40e_aqc_pf_vf_message {
1956 __le32 id;
1957 u8 reserved[4];
1958 __le32 addr_high;
1959 __le32 addr_low;
1960};
1961
1962I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1963
1964/* Alternate structure */
1965
1966/* Direct write (direct 0x0900)
1967 * Direct read (direct 0x0902)
1968 */
1969struct i40e_aqc_alternate_write {
1970 __le32 address0;
1971 __le32 data0;
1972 __le32 address1;
1973 __le32 data1;
1974};
1975
1976I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1977
1978/* Indirect write (indirect 0x0901)
1979 * Indirect read (indirect 0x0903)
1980 */
1981
1982struct i40e_aqc_alternate_ind_write {
1983 __le32 address;
1984 __le32 length;
1985 __le32 addr_high;
1986 __le32 addr_low;
1987};
1988
1989I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1990
1991/* Done alternate write (direct 0x0904)
1992 * uses i40e_aq_desc
1993 */
1994struct i40e_aqc_alternate_write_done {
1995 __le16 cmd_flags;
1996 u8 reserved[14];
1997};
1998
1999I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2000
2001/* Set OEM mode (direct 0x0905) */
2002struct i40e_aqc_alternate_set_mode {
2003 __le32 mode;
2004 u8 reserved[12];
2005};
2006
2007I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2008
2009/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2010
2011/* async events 0x10xx */
2012
2013/* Lan Queue Overflow Event (direct, 0x1001) */
2014struct i40e_aqc_lan_overflow {
2015 __le32 prtdcb_rupto;
2016 __le32 otx_ctl;
2017 u8 reserved[8];
2018};
2019
2020I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2021
2022/* Get LLDP MIB (indirect 0x0A00) */
2023struct i40e_aqc_lldp_get_mib {
2024 u8 type;
2025 u8 reserved1;
2026#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2027#define I40E_AQ_LLDP_MIB_LOCAL 0x0
2028#define I40E_AQ_LLDP_MIB_REMOTE 0x1
2029#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2030#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2031#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2032/* TX pause flags use I40E_AQ_LINK_TX_* above */
2033 __le16 local_len;
2034 __le16 remote_len;
2035 u8 reserved2[2];
2036 __le32 addr_high;
2037 __le32 addr_low;
2038};
2039
2040I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2041
2042/* Configure LLDP MIB Change Event (direct 0x0A01)
2043 * also used for the event (with type in the command field)
2044 */
2045struct i40e_aqc_lldp_update_mib {
2046 u8 command;
2047#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2048 u8 reserved[7];
2049 __le32 addr_high;
2050 __le32 addr_low;
2051};
2052
2053I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2054
2055/* Add LLDP TLV (indirect 0x0A02)
2056 * Delete LLDP TLV (indirect 0x0A04)
2057 */
2058struct i40e_aqc_lldp_add_tlv {
2059 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2060 u8 reserved1[1];
2061 __le16 len;
2062 u8 reserved2[4];
2063 __le32 addr_high;
2064 __le32 addr_low;
2065};
2066
2067I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2068
2069/* Update LLDP TLV (indirect 0x0A03) */
2070struct i40e_aqc_lldp_update_tlv {
2071 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2072 u8 reserved;
2073 __le16 old_len;
2074 __le16 new_offset;
2075 __le16 new_len;
2076 __le32 addr_high;
2077 __le32 addr_low;
2078};
2079
2080I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2081
2082/* Stop LLDP (direct 0x0A05) */
2083struct i40e_aqc_lldp_stop {
2084 u8 command;
2085#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2086#define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2
2087 u8 reserved[15];
2088};
2089
2090I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2091
2092/* Start LLDP (direct 0x0A06) */
2093struct i40e_aqc_lldp_start {
2094 u8 command;
2095#define I40E_AQ_LLDP_AGENT_START 0x1
2096#define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2
2097 u8 reserved[15];
2098};
2099
2100I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2101
2102/* Set DCB (direct 0x0303) */
2103struct i40e_aqc_set_dcb_parameters {
2104 u8 command;
2105#define I40E_AQ_DCB_SET_AGENT 0x1
2106#define I40E_DCB_VALID 0x1
2107 u8 valid_flags;
2108 u8 reserved[14];
2109};
2110
2111I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2112
2113/* Get CEE DCBX Oper Config (0x0A07)
2114 * uses the generic descriptor struct
2115 * returns below as indirect response
2116 */
2117
2118#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2119#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2120#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2121#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2122#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2123#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2124
2125#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2126#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2127#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2128#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2129#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2130#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2131#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2132#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2133#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2134#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2135#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2136#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2137
2138/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2139 * word boundary layout issues, which the Linux compilers silently deal
2140 * with by adding padding, making the actual struct larger than designed.
2141 * However, the FW compiler for the NIC is less lenient and complains
2142 * about the struct. Hence, the struct defined here has an extra byte in
2143 * fields reserved3 and reserved4 to directly acknowledge that padding,
2144 * and the new length is used in the length check macro.
2145 */
2146struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2147 u8 reserved1;
2148 u8 oper_num_tc;
2149 u8 oper_prio_tc[4];
2150 u8 reserved2;
2151 u8 oper_tc_bw[8];
2152 u8 oper_pfc_en;
2153 u8 reserved3[2];
2154 __le16 oper_app_prio;
2155 u8 reserved4[2];
2156 __le16 tlv_status;
2157};
2158
2159I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2160
2161struct i40e_aqc_get_cee_dcb_cfg_resp {
2162 u8 oper_num_tc;
2163 u8 oper_prio_tc[4];
2164 u8 oper_tc_bw[8];
2165 u8 oper_pfc_en;
2166 __le16 oper_app_prio;
2167#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2168#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2169#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2170#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2171#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2172#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2173#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2174 __le32 tlv_status;
2175#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2176#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2177#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2178#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2179#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2180#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2181 u8 reserved[12];
2182};
2183
2184I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2185
2186/* Set Local LLDP MIB (indirect 0x0A08)
2187 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2188 */
2189struct i40e_aqc_lldp_set_local_mib {
2190#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2191#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2192 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2193#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2194#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2195#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2196 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2197#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2198 u8 type;
2199 u8 reserved0;
2200 __le16 length;
2201 u8 reserved1[4];
2202 __le32 address_high;
2203 __le32 address_low;
2204};
2205
2206I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2207
2208/* Stop/Start LLDP Agent (direct 0x0A09)
2209 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2210 */
2211struct i40e_aqc_lldp_stop_start_specific_agent {
2212 u8 command;
2213 u8 reserved[15];
2214};
2215
2216I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2217
2218/* Restore LLDP Agent factory settings (direct 0x0A0A) */
2219struct i40e_aqc_lldp_restore {
2220 u8 command;
2221#define I40E_AQ_LLDP_AGENT_RESTORE 0x1
2222 u8 reserved[15];
2223};
2224
2225I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore);
2226
2227/* Add Udp Tunnel command and completion (direct 0x0B00) */
2228struct i40e_aqc_add_udp_tunnel {
2229 __le16 udp_port;
2230 u8 reserved0[3];
2231 u8 protocol_type;
2232#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2233#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2234 u8 reserved1[10];
2235};
2236
2237I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2238
2239struct i40e_aqc_add_udp_tunnel_completion {
2240 __le16 udp_port;
2241 u8 filter_entry_index;
2242 u8 multiple_pfs;
2243 u8 total_filters;
2244 u8 reserved[11];
2245};
2246
2247I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2248
2249/* remove UDP Tunnel command (0x0B01) */
2250struct i40e_aqc_remove_udp_tunnel {
2251 u8 reserved[2];
2252 u8 index; /* 0 to 15 */
2253 u8 reserved2[13];
2254};
2255
2256I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2257
2258struct i40e_aqc_del_udp_tunnel_completion {
2259 __le16 udp_port;
2260 u8 index; /* 0 to 15 */
2261 u8 multiple_pfs;
2262 u8 total_filters_used;
2263 u8 reserved1[11];
2264};
2265
2266I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2267
2268struct i40e_aqc_get_set_rss_key {
2269#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2270#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2271#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2272 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2273 __le16 vsi_id;
2274 u8 reserved[6];
2275 __le32 addr_high;
2276 __le32 addr_low;
2277};
2278
2279I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2280
2281struct i40e_aqc_get_set_rss_key_data {
2282 u8 standard_rss_key[0x28];
2283 u8 extended_hash_key[0xc];
2284};
2285
2286I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2287
2288struct i40e_aqc_get_set_rss_lut {
2289#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2290#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2291#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2292 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2293 __le16 vsi_id;
2294#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2295#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2296
2297#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2298#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2299 __le16 flags;
2300 u8 reserved[4];
2301 __le32 addr_high;
2302 __le32 addr_low;
2303};
2304
2305I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2306
2307/* tunnel key structure 0x0B10 */
2308
2309struct i40e_aqc_tunnel_key_structure {
2310 u8 key1_off;
2311 u8 key2_off;
2312 u8 key1_len; /* 0 to 15 */
2313 u8 key2_len; /* 0 to 15 */
2314 u8 flags;
2315 u8 network_key_index;
2316 u8 reserved[10];
2317};
2318
2319I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2320
2321/* OEM mode commands (direct 0xFE0x) */
2322struct i40e_aqc_oem_param_change {
2323 __le32 param_type;
2324 __le32 param_value1;
2325 __le16 param_value2;
2326 u8 reserved[6];
2327};
2328
2329I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2330
2331struct i40e_aqc_oem_state_change {
2332 __le32 state;
2333 u8 reserved[12];
2334};
2335
2336I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2337
2338/* Initialize OCSD (0xFE02, direct) */
2339struct i40e_aqc_opc_oem_ocsd_initialize {
2340 u8 type_status;
2341 u8 reserved1[3];
2342 __le32 ocsd_memory_block_addr_high;
2343 __le32 ocsd_memory_block_addr_low;
2344 __le32 requested_update_interval;
2345};
2346
2347I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2348
2349/* Initialize OCBB (0xFE03, direct) */
2350struct i40e_aqc_opc_oem_ocbb_initialize {
2351 u8 type_status;
2352 u8 reserved1[3];
2353 __le32 ocbb_memory_block_addr_high;
2354 __le32 ocbb_memory_block_addr_low;
2355 u8 reserved2[4];
2356};
2357
2358I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2359
2360/* debug commands */
2361
2362/* get device id (0xFF00) uses the generic structure */
2363
2364/* set test more (0xFF01, internal) */
2365
2366struct i40e_acq_set_test_mode {
2367 u8 mode;
2368 u8 reserved[3];
2369 u8 command;
2370 u8 reserved2[3];
2371 __le32 address_high;
2372 __le32 address_low;
2373};
2374
2375I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2376
2377/* Debug Read Register command (0xFF03)
2378 * Debug Write Register command (0xFF04)
2379 */
2380struct i40e_aqc_debug_reg_read_write {
2381 __le32 reserved;
2382 __le32 address;
2383 __le32 value_high;
2384 __le32 value_low;
2385};
2386
2387I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2388
2389/* Scatter/gather Reg Read (indirect 0xFF05)
2390 * Scatter/gather Reg Write (indirect 0xFF06)
2391 */
2392
2393/* i40e_aq_desc is used for the command */
2394struct i40e_aqc_debug_reg_sg_element_data {
2395 __le32 address;
2396 __le32 value;
2397};
2398
2399/* Debug Modify register (direct 0xFF07) */
2400struct i40e_aqc_debug_modify_reg {
2401 __le32 address;
2402 __le32 value;
2403 __le32 clear_mask;
2404 __le32 set_mask;
2405};
2406
2407I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2408
2409/* dump internal data (0xFF08, indirect) */
2410struct i40e_aqc_debug_dump_internals {
2411 u8 cluster_id;
2412 u8 table_id;
2413 __le16 data_size;
2414 __le32 idx;
2415 __le32 address_high;
2416 __le32 address_low;
2417};
2418
2419I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2420
2421struct i40e_aqc_debug_modify_internals {
2422 u8 cluster_id;
2423 u8 cluster_specific_params[7];
2424 __le32 address_high;
2425 __le32 address_low;
2426};
2427
2428I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2429
2430#endif /* _I40E_ADMINQ_CMD_H_ */