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1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/sched.h>
5#include <linux/init.h>
6#include <linux/export.h>
7#include <linux/timer.h>
8#include <linux/acpi_pmtmr.h>
9#include <linux/cpufreq.h>
10#include <linux/delay.h>
11#include <linux/clocksource.h>
12#include <linux/percpu.h>
13#include <linux/timex.h>
14#include <linux/static_key.h>
15
16#include <asm/hpet.h>
17#include <asm/timer.h>
18#include <asm/vgtod.h>
19#include <asm/time.h>
20#include <asm/delay.h>
21#include <asm/hypervisor.h>
22#include <asm/nmi.h>
23#include <asm/x86_init.h>
24#include <asm/geode.h>
25#include <asm/apic.h>
26#include <asm/intel-family.h>
27
28unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
29EXPORT_SYMBOL(cpu_khz);
30
31unsigned int __read_mostly tsc_khz;
32EXPORT_SYMBOL(tsc_khz);
33
34/*
35 * TSC can be unstable due to cpufreq or due to unsynced TSCs
36 */
37static int __read_mostly tsc_unstable;
38
39/* native_sched_clock() is called before tsc_init(), so
40 we must start with the TSC soft disabled to prevent
41 erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */
42static int __read_mostly tsc_disabled = -1;
43
44static DEFINE_STATIC_KEY_FALSE(__use_tsc);
45
46int tsc_clocksource_reliable;
47
48static u32 art_to_tsc_numerator;
49static u32 art_to_tsc_denominator;
50static u64 art_to_tsc_offset;
51struct clocksource *art_related_clocksource;
52
53/*
54 * Use a ring-buffer like data structure, where a writer advances the head by
55 * writing a new data entry and a reader advances the tail when it observes a
56 * new entry.
57 *
58 * Writers are made to wait on readers until there's space to write a new
59 * entry.
60 *
61 * This means that we can always use an {offset, mul} pair to compute a ns
62 * value that is 'roughly' in the right direction, even if we're writing a new
63 * {offset, mul} pair during the clock read.
64 *
65 * The down-side is that we can no longer guarantee strict monotonicity anymore
66 * (assuming the TSC was that to begin with), because while we compute the
67 * intersection point of the two clock slopes and make sure the time is
68 * continuous at the point of switching; we can no longer guarantee a reader is
69 * strictly before or after the switch point.
70 *
71 * It does mean a reader no longer needs to disable IRQs in order to avoid
72 * CPU-Freq updates messing with his times, and similarly an NMI reader will
73 * no longer run the risk of hitting half-written state.
74 */
75
76struct cyc2ns {
77 struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */
78 struct cyc2ns_data *head; /* 48 + 8 = 56 */
79 struct cyc2ns_data *tail; /* 56 + 8 = 64 */
80}; /* exactly fits one cacheline */
81
82static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
83
84struct cyc2ns_data *cyc2ns_read_begin(void)
85{
86 struct cyc2ns_data *head;
87
88 preempt_disable();
89
90 head = this_cpu_read(cyc2ns.head);
91 /*
92 * Ensure we observe the entry when we observe the pointer to it.
93 * matches the wmb from cyc2ns_write_end().
94 */
95 smp_read_barrier_depends();
96 head->__count++;
97 barrier();
98
99 return head;
100}
101
102void cyc2ns_read_end(struct cyc2ns_data *head)
103{
104 barrier();
105 /*
106 * If we're the outer most nested read; update the tail pointer
107 * when we're done. This notifies possible pending writers
108 * that we've observed the head pointer and that the other
109 * entry is now free.
110 */
111 if (!--head->__count) {
112 /*
113 * x86-TSO does not reorder writes with older reads;
114 * therefore once this write becomes visible to another
115 * cpu, we must be finished reading the cyc2ns_data.
116 *
117 * matches with cyc2ns_write_begin().
118 */
119 this_cpu_write(cyc2ns.tail, head);
120 }
121 preempt_enable();
122}
123
124/*
125 * Begin writing a new @data entry for @cpu.
126 *
127 * Assumes some sort of write side lock; currently 'provided' by the assumption
128 * that cpufreq will call its notifiers sequentially.
129 */
130static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
131{
132 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
133 struct cyc2ns_data *data = c2n->data;
134
135 if (data == c2n->head)
136 data++;
137
138 /* XXX send an IPI to @cpu in order to guarantee a read? */
139
140 /*
141 * When we observe the tail write from cyc2ns_read_end(),
142 * the cpu must be done with that entry and its safe
143 * to start writing to it.
144 */
145 while (c2n->tail == data)
146 cpu_relax();
147
148 return data;
149}
150
151static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
152{
153 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
154
155 /*
156 * Ensure the @data writes are visible before we publish the
157 * entry. Matches the data-depencency in cyc2ns_read_begin().
158 */
159 smp_wmb();
160
161 ACCESS_ONCE(c2n->head) = data;
162}
163
164/*
165 * Accelerators for sched_clock()
166 * convert from cycles(64bits) => nanoseconds (64bits)
167 * basic equation:
168 * ns = cycles / (freq / ns_per_sec)
169 * ns = cycles * (ns_per_sec / freq)
170 * ns = cycles * (10^9 / (cpu_khz * 10^3))
171 * ns = cycles * (10^6 / cpu_khz)
172 *
173 * Then we use scaling math (suggested by george@mvista.com) to get:
174 * ns = cycles * (10^6 * SC / cpu_khz) / SC
175 * ns = cycles * cyc2ns_scale / SC
176 *
177 * And since SC is a constant power of two, we can convert the div
178 * into a shift. The larger SC is, the more accurate the conversion, but
179 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
180 * (64-bit result) can be used.
181 *
182 * We can use khz divisor instead of mhz to keep a better precision.
183 * (mathieu.desnoyers@polymtl.ca)
184 *
185 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
186 */
187
188static void cyc2ns_data_init(struct cyc2ns_data *data)
189{
190 data->cyc2ns_mul = 0;
191 data->cyc2ns_shift = 0;
192 data->cyc2ns_offset = 0;
193 data->__count = 0;
194}
195
196static void cyc2ns_init(int cpu)
197{
198 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
199
200 cyc2ns_data_init(&c2n->data[0]);
201 cyc2ns_data_init(&c2n->data[1]);
202
203 c2n->head = c2n->data;
204 c2n->tail = c2n->data;
205}
206
207static inline unsigned long long cycles_2_ns(unsigned long long cyc)
208{
209 struct cyc2ns_data *data, *tail;
210 unsigned long long ns;
211
212 /*
213 * See cyc2ns_read_*() for details; replicated in order to avoid
214 * an extra few instructions that came with the abstraction.
215 * Notable, it allows us to only do the __count and tail update
216 * dance when its actually needed.
217 */
218
219 preempt_disable_notrace();
220 data = this_cpu_read(cyc2ns.head);
221 tail = this_cpu_read(cyc2ns.tail);
222
223 if (likely(data == tail)) {
224 ns = data->cyc2ns_offset;
225 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
226 } else {
227 data->__count++;
228
229 barrier();
230
231 ns = data->cyc2ns_offset;
232 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
233
234 barrier();
235
236 if (!--data->__count)
237 this_cpu_write(cyc2ns.tail, data);
238 }
239 preempt_enable_notrace();
240
241 return ns;
242}
243
244static void set_cyc2ns_scale(unsigned long khz, int cpu)
245{
246 unsigned long long tsc_now, ns_now;
247 struct cyc2ns_data *data;
248 unsigned long flags;
249
250 local_irq_save(flags);
251 sched_clock_idle_sleep_event();
252
253 if (!khz)
254 goto done;
255
256 data = cyc2ns_write_begin(cpu);
257
258 tsc_now = rdtsc();
259 ns_now = cycles_2_ns(tsc_now);
260
261 /*
262 * Compute a new multiplier as per the above comment and ensure our
263 * time function is continuous; see the comment near struct
264 * cyc2ns_data.
265 */
266 clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, khz,
267 NSEC_PER_MSEC, 0);
268
269 /*
270 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
271 * not expected to be greater than 31 due to the original published
272 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
273 * value) - refer perf_event_mmap_page documentation in perf_event.h.
274 */
275 if (data->cyc2ns_shift == 32) {
276 data->cyc2ns_shift = 31;
277 data->cyc2ns_mul >>= 1;
278 }
279
280 data->cyc2ns_offset = ns_now -
281 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, data->cyc2ns_shift);
282
283 cyc2ns_write_end(cpu, data);
284
285done:
286 sched_clock_idle_wakeup_event(0);
287 local_irq_restore(flags);
288}
289/*
290 * Scheduler clock - returns current time in nanosec units.
291 */
292u64 native_sched_clock(void)
293{
294 if (static_branch_likely(&__use_tsc)) {
295 u64 tsc_now = rdtsc();
296
297 /* return the value in ns */
298 return cycles_2_ns(tsc_now);
299 }
300
301 /*
302 * Fall back to jiffies if there's no TSC available:
303 * ( But note that we still use it if the TSC is marked
304 * unstable. We do this because unlike Time Of Day,
305 * the scheduler clock tolerates small errors and it's
306 * very important for it to be as fast as the platform
307 * can achieve it. )
308 */
309
310 /* No locking but a rare wrong value is not a big deal: */
311 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
312}
313
314/*
315 * Generate a sched_clock if you already have a TSC value.
316 */
317u64 native_sched_clock_from_tsc(u64 tsc)
318{
319 return cycles_2_ns(tsc);
320}
321
322/* We need to define a real function for sched_clock, to override the
323 weak default version */
324#ifdef CONFIG_PARAVIRT
325unsigned long long sched_clock(void)
326{
327 return paravirt_sched_clock();
328}
329#else
330unsigned long long
331sched_clock(void) __attribute__((alias("native_sched_clock")));
332#endif
333
334int check_tsc_unstable(void)
335{
336 return tsc_unstable;
337}
338EXPORT_SYMBOL_GPL(check_tsc_unstable);
339
340#ifdef CONFIG_X86_TSC
341int __init notsc_setup(char *str)
342{
343 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
344 tsc_disabled = 1;
345 return 1;
346}
347#else
348/*
349 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
350 * in cpu/common.c
351 */
352int __init notsc_setup(char *str)
353{
354 setup_clear_cpu_cap(X86_FEATURE_TSC);
355 return 1;
356}
357#endif
358
359__setup("notsc", notsc_setup);
360
361static int no_sched_irq_time;
362
363static int __init tsc_setup(char *str)
364{
365 if (!strcmp(str, "reliable"))
366 tsc_clocksource_reliable = 1;
367 if (!strncmp(str, "noirqtime", 9))
368 no_sched_irq_time = 1;
369 return 1;
370}
371
372__setup("tsc=", tsc_setup);
373
374#define MAX_RETRIES 5
375#define SMI_TRESHOLD 50000
376
377/*
378 * Read TSC and the reference counters. Take care of SMI disturbance
379 */
380static u64 tsc_read_refs(u64 *p, int hpet)
381{
382 u64 t1, t2;
383 int i;
384
385 for (i = 0; i < MAX_RETRIES; i++) {
386 t1 = get_cycles();
387 if (hpet)
388 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
389 else
390 *p = acpi_pm_read_early();
391 t2 = get_cycles();
392 if ((t2 - t1) < SMI_TRESHOLD)
393 return t2;
394 }
395 return ULLONG_MAX;
396}
397
398/*
399 * Calculate the TSC frequency from HPET reference
400 */
401static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
402{
403 u64 tmp;
404
405 if (hpet2 < hpet1)
406 hpet2 += 0x100000000ULL;
407 hpet2 -= hpet1;
408 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
409 do_div(tmp, 1000000);
410 do_div(deltatsc, tmp);
411
412 return (unsigned long) deltatsc;
413}
414
415/*
416 * Calculate the TSC frequency from PMTimer reference
417 */
418static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
419{
420 u64 tmp;
421
422 if (!pm1 && !pm2)
423 return ULONG_MAX;
424
425 if (pm2 < pm1)
426 pm2 += (u64)ACPI_PM_OVRRUN;
427 pm2 -= pm1;
428 tmp = pm2 * 1000000000LL;
429 do_div(tmp, PMTMR_TICKS_PER_SEC);
430 do_div(deltatsc, tmp);
431
432 return (unsigned long) deltatsc;
433}
434
435#define CAL_MS 10
436#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
437#define CAL_PIT_LOOPS 1000
438
439#define CAL2_MS 50
440#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
441#define CAL2_PIT_LOOPS 5000
442
443
444/*
445 * Try to calibrate the TSC against the Programmable
446 * Interrupt Timer and return the frequency of the TSC
447 * in kHz.
448 *
449 * Return ULONG_MAX on failure to calibrate.
450 */
451static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
452{
453 u64 tsc, t1, t2, delta;
454 unsigned long tscmin, tscmax;
455 int pitcnt;
456
457 /* Set the Gate high, disable speaker */
458 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
459
460 /*
461 * Setup CTC channel 2* for mode 0, (interrupt on terminal
462 * count mode), binary count. Set the latch register to 50ms
463 * (LSB then MSB) to begin countdown.
464 */
465 outb(0xb0, 0x43);
466 outb(latch & 0xff, 0x42);
467 outb(latch >> 8, 0x42);
468
469 tsc = t1 = t2 = get_cycles();
470
471 pitcnt = 0;
472 tscmax = 0;
473 tscmin = ULONG_MAX;
474 while ((inb(0x61) & 0x20) == 0) {
475 t2 = get_cycles();
476 delta = t2 - tsc;
477 tsc = t2;
478 if ((unsigned long) delta < tscmin)
479 tscmin = (unsigned int) delta;
480 if ((unsigned long) delta > tscmax)
481 tscmax = (unsigned int) delta;
482 pitcnt++;
483 }
484
485 /*
486 * Sanity checks:
487 *
488 * If we were not able to read the PIT more than loopmin
489 * times, then we have been hit by a massive SMI
490 *
491 * If the maximum is 10 times larger than the minimum,
492 * then we got hit by an SMI as well.
493 */
494 if (pitcnt < loopmin || tscmax > 10 * tscmin)
495 return ULONG_MAX;
496
497 /* Calculate the PIT value */
498 delta = t2 - t1;
499 do_div(delta, ms);
500 return delta;
501}
502
503/*
504 * This reads the current MSB of the PIT counter, and
505 * checks if we are running on sufficiently fast and
506 * non-virtualized hardware.
507 *
508 * Our expectations are:
509 *
510 * - the PIT is running at roughly 1.19MHz
511 *
512 * - each IO is going to take about 1us on real hardware,
513 * but we allow it to be much faster (by a factor of 10) or
514 * _slightly_ slower (ie we allow up to a 2us read+counter
515 * update - anything else implies a unacceptably slow CPU
516 * or PIT for the fast calibration to work.
517 *
518 * - with 256 PIT ticks to read the value, we have 214us to
519 * see the same MSB (and overhead like doing a single TSC
520 * read per MSB value etc).
521 *
522 * - We're doing 2 reads per loop (LSB, MSB), and we expect
523 * them each to take about a microsecond on real hardware.
524 * So we expect a count value of around 100. But we'll be
525 * generous, and accept anything over 50.
526 *
527 * - if the PIT is stuck, and we see *many* more reads, we
528 * return early (and the next caller of pit_expect_msb()
529 * then consider it a failure when they don't see the
530 * next expected value).
531 *
532 * These expectations mean that we know that we have seen the
533 * transition from one expected value to another with a fairly
534 * high accuracy, and we didn't miss any events. We can thus
535 * use the TSC value at the transitions to calculate a pretty
536 * good value for the TSC frequencty.
537 */
538static inline int pit_verify_msb(unsigned char val)
539{
540 /* Ignore LSB */
541 inb(0x42);
542 return inb(0x42) == val;
543}
544
545static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
546{
547 int count;
548 u64 tsc = 0, prev_tsc = 0;
549
550 for (count = 0; count < 50000; count++) {
551 if (!pit_verify_msb(val))
552 break;
553 prev_tsc = tsc;
554 tsc = get_cycles();
555 }
556 *deltap = get_cycles() - prev_tsc;
557 *tscp = tsc;
558
559 /*
560 * We require _some_ success, but the quality control
561 * will be based on the error terms on the TSC values.
562 */
563 return count > 5;
564}
565
566/*
567 * How many MSB values do we want to see? We aim for
568 * a maximum error rate of 500ppm (in practice the
569 * real error is much smaller), but refuse to spend
570 * more than 50ms on it.
571 */
572#define MAX_QUICK_PIT_MS 50
573#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
574
575static unsigned long quick_pit_calibrate(void)
576{
577 int i;
578 u64 tsc, delta;
579 unsigned long d1, d2;
580
581 /* Set the Gate high, disable speaker */
582 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
583
584 /*
585 * Counter 2, mode 0 (one-shot), binary count
586 *
587 * NOTE! Mode 2 decrements by two (and then the
588 * output is flipped each time, giving the same
589 * final output frequency as a decrement-by-one),
590 * so mode 0 is much better when looking at the
591 * individual counts.
592 */
593 outb(0xb0, 0x43);
594
595 /* Start at 0xffff */
596 outb(0xff, 0x42);
597 outb(0xff, 0x42);
598
599 /*
600 * The PIT starts counting at the next edge, so we
601 * need to delay for a microsecond. The easiest way
602 * to do that is to just read back the 16-bit counter
603 * once from the PIT.
604 */
605 pit_verify_msb(0);
606
607 if (pit_expect_msb(0xff, &tsc, &d1)) {
608 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
609 if (!pit_expect_msb(0xff-i, &delta, &d2))
610 break;
611
612 delta -= tsc;
613
614 /*
615 * Extrapolate the error and fail fast if the error will
616 * never be below 500 ppm.
617 */
618 if (i == 1 &&
619 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
620 return 0;
621
622 /*
623 * Iterate until the error is less than 500 ppm
624 */
625 if (d1+d2 >= delta >> 11)
626 continue;
627
628 /*
629 * Check the PIT one more time to verify that
630 * all TSC reads were stable wrt the PIT.
631 *
632 * This also guarantees serialization of the
633 * last cycle read ('d2') in pit_expect_msb.
634 */
635 if (!pit_verify_msb(0xfe - i))
636 break;
637 goto success;
638 }
639 }
640 pr_info("Fast TSC calibration failed\n");
641 return 0;
642
643success:
644 /*
645 * Ok, if we get here, then we've seen the
646 * MSB of the PIT decrement 'i' times, and the
647 * error has shrunk to less than 500 ppm.
648 *
649 * As a result, we can depend on there not being
650 * any odd delays anywhere, and the TSC reads are
651 * reliable (within the error).
652 *
653 * kHz = ticks / time-in-seconds / 1000;
654 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
655 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
656 */
657 delta *= PIT_TICK_RATE;
658 do_div(delta, i*256*1000);
659 pr_info("Fast TSC calibration using PIT\n");
660 return delta;
661}
662
663/**
664 * native_calibrate_tsc
665 * Determine TSC frequency via CPUID, else return 0.
666 */
667unsigned long native_calibrate_tsc(void)
668{
669 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
670 unsigned int crystal_khz;
671
672 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
673 return 0;
674
675 if (boot_cpu_data.cpuid_level < 0x15)
676 return 0;
677
678 eax_denominator = ebx_numerator = ecx_hz = edx = 0;
679
680 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
681 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
682
683 if (ebx_numerator == 0 || eax_denominator == 0)
684 return 0;
685
686 crystal_khz = ecx_hz / 1000;
687
688 if (crystal_khz == 0) {
689 switch (boot_cpu_data.x86_model) {
690 case INTEL_FAM6_SKYLAKE_MOBILE:
691 case INTEL_FAM6_SKYLAKE_DESKTOP:
692 case INTEL_FAM6_KABYLAKE_MOBILE:
693 case INTEL_FAM6_KABYLAKE_DESKTOP:
694 crystal_khz = 24000; /* 24.0 MHz */
695 break;
696 case INTEL_FAM6_SKYLAKE_X:
697 case INTEL_FAM6_ATOM_DENVERTON:
698 crystal_khz = 25000; /* 25.0 MHz */
699 break;
700 case INTEL_FAM6_ATOM_GOLDMONT:
701 crystal_khz = 19200; /* 19.2 MHz */
702 break;
703 }
704 }
705
706 /*
707 * TSC frequency determined by CPUID is a "hardware reported"
708 * frequency and is the most accurate one so far we have. This
709 * is considered a known frequency.
710 */
711 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
712
713 /*
714 * For Atom SoCs TSC is the only reliable clocksource.
715 * Mark TSC reliable so no watchdog on it.
716 */
717 if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
718 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
719
720 return crystal_khz * ebx_numerator / eax_denominator;
721}
722
723static unsigned long cpu_khz_from_cpuid(void)
724{
725 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
726
727 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
728 return 0;
729
730 if (boot_cpu_data.cpuid_level < 0x16)
731 return 0;
732
733 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
734
735 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
736
737 return eax_base_mhz * 1000;
738}
739
740/**
741 * native_calibrate_cpu - calibrate the cpu on boot
742 */
743unsigned long native_calibrate_cpu(void)
744{
745 u64 tsc1, tsc2, delta, ref1, ref2;
746 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
747 unsigned long flags, latch, ms, fast_calibrate;
748 int hpet = is_hpet_enabled(), i, loopmin;
749
750 fast_calibrate = cpu_khz_from_cpuid();
751 if (fast_calibrate)
752 return fast_calibrate;
753
754 fast_calibrate = cpu_khz_from_msr();
755 if (fast_calibrate)
756 return fast_calibrate;
757
758 local_irq_save(flags);
759 fast_calibrate = quick_pit_calibrate();
760 local_irq_restore(flags);
761 if (fast_calibrate)
762 return fast_calibrate;
763
764 /*
765 * Run 5 calibration loops to get the lowest frequency value
766 * (the best estimate). We use two different calibration modes
767 * here:
768 *
769 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
770 * load a timeout of 50ms. We read the time right after we
771 * started the timer and wait until the PIT count down reaches
772 * zero. In each wait loop iteration we read the TSC and check
773 * the delta to the previous read. We keep track of the min
774 * and max values of that delta. The delta is mostly defined
775 * by the IO time of the PIT access, so we can detect when a
776 * SMI/SMM disturbance happened between the two reads. If the
777 * maximum time is significantly larger than the minimum time,
778 * then we discard the result and have another try.
779 *
780 * 2) Reference counter. If available we use the HPET or the
781 * PMTIMER as a reference to check the sanity of that value.
782 * We use separate TSC readouts and check inside of the
783 * reference read for a SMI/SMM disturbance. We dicard
784 * disturbed values here as well. We do that around the PIT
785 * calibration delay loop as we have to wait for a certain
786 * amount of time anyway.
787 */
788
789 /* Preset PIT loop values */
790 latch = CAL_LATCH;
791 ms = CAL_MS;
792 loopmin = CAL_PIT_LOOPS;
793
794 for (i = 0; i < 3; i++) {
795 unsigned long tsc_pit_khz;
796
797 /*
798 * Read the start value and the reference count of
799 * hpet/pmtimer when available. Then do the PIT
800 * calibration, which will take at least 50ms, and
801 * read the end value.
802 */
803 local_irq_save(flags);
804 tsc1 = tsc_read_refs(&ref1, hpet);
805 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
806 tsc2 = tsc_read_refs(&ref2, hpet);
807 local_irq_restore(flags);
808
809 /* Pick the lowest PIT TSC calibration so far */
810 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
811
812 /* hpet or pmtimer available ? */
813 if (ref1 == ref2)
814 continue;
815
816 /* Check, whether the sampling was disturbed by an SMI */
817 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
818 continue;
819
820 tsc2 = (tsc2 - tsc1) * 1000000LL;
821 if (hpet)
822 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
823 else
824 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
825
826 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
827
828 /* Check the reference deviation */
829 delta = ((u64) tsc_pit_min) * 100;
830 do_div(delta, tsc_ref_min);
831
832 /*
833 * If both calibration results are inside a 10% window
834 * then we can be sure, that the calibration
835 * succeeded. We break out of the loop right away. We
836 * use the reference value, as it is more precise.
837 */
838 if (delta >= 90 && delta <= 110) {
839 pr_info("PIT calibration matches %s. %d loops\n",
840 hpet ? "HPET" : "PMTIMER", i + 1);
841 return tsc_ref_min;
842 }
843
844 /*
845 * Check whether PIT failed more than once. This
846 * happens in virtualized environments. We need to
847 * give the virtual PC a slightly longer timeframe for
848 * the HPET/PMTIMER to make the result precise.
849 */
850 if (i == 1 && tsc_pit_min == ULONG_MAX) {
851 latch = CAL2_LATCH;
852 ms = CAL2_MS;
853 loopmin = CAL2_PIT_LOOPS;
854 }
855 }
856
857 /*
858 * Now check the results.
859 */
860 if (tsc_pit_min == ULONG_MAX) {
861 /* PIT gave no useful value */
862 pr_warn("Unable to calibrate against PIT\n");
863
864 /* We don't have an alternative source, disable TSC */
865 if (!hpet && !ref1 && !ref2) {
866 pr_notice("No reference (HPET/PMTIMER) available\n");
867 return 0;
868 }
869
870 /* The alternative source failed as well, disable TSC */
871 if (tsc_ref_min == ULONG_MAX) {
872 pr_warn("HPET/PMTIMER calibration failed\n");
873 return 0;
874 }
875
876 /* Use the alternative source */
877 pr_info("using %s reference calibration\n",
878 hpet ? "HPET" : "PMTIMER");
879
880 return tsc_ref_min;
881 }
882
883 /* We don't have an alternative source, use the PIT calibration value */
884 if (!hpet && !ref1 && !ref2) {
885 pr_info("Using PIT calibration value\n");
886 return tsc_pit_min;
887 }
888
889 /* The alternative source failed, use the PIT calibration value */
890 if (tsc_ref_min == ULONG_MAX) {
891 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
892 return tsc_pit_min;
893 }
894
895 /*
896 * The calibration values differ too much. In doubt, we use
897 * the PIT value as we know that there are PMTIMERs around
898 * running at double speed. At least we let the user know:
899 */
900 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
901 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
902 pr_info("Using PIT calibration value\n");
903 return tsc_pit_min;
904}
905
906int recalibrate_cpu_khz(void)
907{
908#ifndef CONFIG_SMP
909 unsigned long cpu_khz_old = cpu_khz;
910
911 if (!boot_cpu_has(X86_FEATURE_TSC))
912 return -ENODEV;
913
914 cpu_khz = x86_platform.calibrate_cpu();
915 tsc_khz = x86_platform.calibrate_tsc();
916 if (tsc_khz == 0)
917 tsc_khz = cpu_khz;
918 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
919 cpu_khz = tsc_khz;
920 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
921 cpu_khz_old, cpu_khz);
922
923 return 0;
924#else
925 return -ENODEV;
926#endif
927}
928
929EXPORT_SYMBOL(recalibrate_cpu_khz);
930
931
932static unsigned long long cyc2ns_suspend;
933
934void tsc_save_sched_clock_state(void)
935{
936 if (!sched_clock_stable())
937 return;
938
939 cyc2ns_suspend = sched_clock();
940}
941
942/*
943 * Even on processors with invariant TSC, TSC gets reset in some the
944 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
945 * arbitrary value (still sync'd across cpu's) during resume from such sleep
946 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
947 * that sched_clock() continues from the point where it was left off during
948 * suspend.
949 */
950void tsc_restore_sched_clock_state(void)
951{
952 unsigned long long offset;
953 unsigned long flags;
954 int cpu;
955
956 if (!sched_clock_stable())
957 return;
958
959 local_irq_save(flags);
960
961 /*
962 * We're coming out of suspend, there's no concurrency yet; don't
963 * bother being nice about the RCU stuff, just write to both
964 * data fields.
965 */
966
967 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
968 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
969
970 offset = cyc2ns_suspend - sched_clock();
971
972 for_each_possible_cpu(cpu) {
973 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
974 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
975 }
976
977 local_irq_restore(flags);
978}
979
980#ifdef CONFIG_CPU_FREQ
981
982/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
983 * changes.
984 *
985 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
986 * not that important because current Opteron setups do not support
987 * scaling on SMP anyroads.
988 *
989 * Should fix up last_tsc too. Currently gettimeofday in the
990 * first tick after the change will be slightly wrong.
991 */
992
993static unsigned int ref_freq;
994static unsigned long loops_per_jiffy_ref;
995static unsigned long tsc_khz_ref;
996
997static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
998 void *data)
999{
1000 struct cpufreq_freqs *freq = data;
1001 unsigned long *lpj;
1002
1003 lpj = &boot_cpu_data.loops_per_jiffy;
1004#ifdef CONFIG_SMP
1005 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
1006 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
1007#endif
1008
1009 if (!ref_freq) {
1010 ref_freq = freq->old;
1011 loops_per_jiffy_ref = *lpj;
1012 tsc_khz_ref = tsc_khz;
1013 }
1014 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
1015 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
1016 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
1017
1018 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
1019 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
1020 mark_tsc_unstable("cpufreq changes");
1021
1022 set_cyc2ns_scale(tsc_khz, freq->cpu);
1023 }
1024
1025 return 0;
1026}
1027
1028static struct notifier_block time_cpufreq_notifier_block = {
1029 .notifier_call = time_cpufreq_notifier
1030};
1031
1032static int __init cpufreq_register_tsc_scaling(void)
1033{
1034 if (!boot_cpu_has(X86_FEATURE_TSC))
1035 return 0;
1036 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1037 return 0;
1038 cpufreq_register_notifier(&time_cpufreq_notifier_block,
1039 CPUFREQ_TRANSITION_NOTIFIER);
1040 return 0;
1041}
1042
1043core_initcall(cpufreq_register_tsc_scaling);
1044
1045#endif /* CONFIG_CPU_FREQ */
1046
1047#define ART_CPUID_LEAF (0x15)
1048#define ART_MIN_DENOMINATOR (1)
1049
1050
1051/*
1052 * If ART is present detect the numerator:denominator to convert to TSC
1053 */
1054static void detect_art(void)
1055{
1056 unsigned int unused[2];
1057
1058 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
1059 return;
1060
1061 /* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */
1062 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
1063 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
1064 !boot_cpu_has(X86_FEATURE_TSC_ADJUST))
1065 return;
1066
1067 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
1068 &art_to_tsc_numerator, unused, unused+1);
1069
1070 if (art_to_tsc_denominator < ART_MIN_DENOMINATOR)
1071 return;
1072
1073 rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset);
1074
1075 /* Make this sticky over multiple CPU init calls */
1076 setup_force_cpu_cap(X86_FEATURE_ART);
1077}
1078
1079
1080/* clocksource code */
1081
1082static struct clocksource clocksource_tsc;
1083
1084static void tsc_resume(struct clocksource *cs)
1085{
1086 tsc_verify_tsc_adjust(true);
1087}
1088
1089/*
1090 * We used to compare the TSC to the cycle_last value in the clocksource
1091 * structure to avoid a nasty time-warp. This can be observed in a
1092 * very small window right after one CPU updated cycle_last under
1093 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1094 * is smaller than the cycle_last reference value due to a TSC which
1095 * is slighty behind. This delta is nowhere else observable, but in
1096 * that case it results in a forward time jump in the range of hours
1097 * due to the unsigned delta calculation of the time keeping core
1098 * code, which is necessary to support wrapping clocksources like pm
1099 * timer.
1100 *
1101 * This sanity check is now done in the core timekeeping code.
1102 * checking the result of read_tsc() - cycle_last for being negative.
1103 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1104 */
1105static u64 read_tsc(struct clocksource *cs)
1106{
1107 return (u64)rdtsc_ordered();
1108}
1109
1110/*
1111 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1112 */
1113static struct clocksource clocksource_tsc = {
1114 .name = "tsc",
1115 .rating = 300,
1116 .read = read_tsc,
1117 .mask = CLOCKSOURCE_MASK(64),
1118 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1119 CLOCK_SOURCE_MUST_VERIFY,
1120 .archdata = { .vclock_mode = VCLOCK_TSC },
1121 .resume = tsc_resume,
1122};
1123
1124void mark_tsc_unstable(char *reason)
1125{
1126 if (!tsc_unstable) {
1127 tsc_unstable = 1;
1128 clear_sched_clock_stable();
1129 disable_sched_clock_irqtime();
1130 pr_info("Marking TSC unstable due to %s\n", reason);
1131 /* Change only the rating, when not registered */
1132 if (clocksource_tsc.mult)
1133 clocksource_mark_unstable(&clocksource_tsc);
1134 else {
1135 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
1136 clocksource_tsc.rating = 0;
1137 }
1138 }
1139}
1140
1141EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1142
1143static void __init check_system_tsc_reliable(void)
1144{
1145#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1146 if (is_geode_lx()) {
1147 /* RTSC counts during suspend */
1148#define RTSC_SUSP 0x100
1149 unsigned long res_low, res_high;
1150
1151 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1152 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1153 if (res_low & RTSC_SUSP)
1154 tsc_clocksource_reliable = 1;
1155 }
1156#endif
1157 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1158 tsc_clocksource_reliable = 1;
1159}
1160
1161/*
1162 * Make an educated guess if the TSC is trustworthy and synchronized
1163 * over all CPUs.
1164 */
1165int unsynchronized_tsc(void)
1166{
1167 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
1168 return 1;
1169
1170#ifdef CONFIG_SMP
1171 if (apic_is_clustered_box())
1172 return 1;
1173#endif
1174
1175 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1176 return 0;
1177
1178 if (tsc_clocksource_reliable)
1179 return 0;
1180 /*
1181 * Intel systems are normally all synchronized.
1182 * Exceptions must mark TSC as unstable:
1183 */
1184 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1185 /* assume multi socket systems are not synchronized: */
1186 if (num_possible_cpus() > 1)
1187 return 1;
1188 }
1189
1190 return 0;
1191}
1192
1193/*
1194 * Convert ART to TSC given numerator/denominator found in detect_art()
1195 */
1196struct system_counterval_t convert_art_to_tsc(u64 art)
1197{
1198 u64 tmp, res, rem;
1199
1200 rem = do_div(art, art_to_tsc_denominator);
1201
1202 res = art * art_to_tsc_numerator;
1203 tmp = rem * art_to_tsc_numerator;
1204
1205 do_div(tmp, art_to_tsc_denominator);
1206 res += tmp + art_to_tsc_offset;
1207
1208 return (struct system_counterval_t) {.cs = art_related_clocksource,
1209 .cycles = res};
1210}
1211EXPORT_SYMBOL(convert_art_to_tsc);
1212
1213static void tsc_refine_calibration_work(struct work_struct *work);
1214static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1215/**
1216 * tsc_refine_calibration_work - Further refine tsc freq calibration
1217 * @work - ignored.
1218 *
1219 * This functions uses delayed work over a period of a
1220 * second to further refine the TSC freq value. Since this is
1221 * timer based, instead of loop based, we don't block the boot
1222 * process while this longer calibration is done.
1223 *
1224 * If there are any calibration anomalies (too many SMIs, etc),
1225 * or the refined calibration is off by 1% of the fast early
1226 * calibration, we throw out the new calibration and use the
1227 * early calibration.
1228 */
1229static void tsc_refine_calibration_work(struct work_struct *work)
1230{
1231 static u64 tsc_start = -1, ref_start;
1232 static int hpet;
1233 u64 tsc_stop, ref_stop, delta;
1234 unsigned long freq;
1235
1236 /* Don't bother refining TSC on unstable systems */
1237 if (check_tsc_unstable())
1238 goto out;
1239
1240 /*
1241 * Since the work is started early in boot, we may be
1242 * delayed the first time we expire. So set the workqueue
1243 * again once we know timers are working.
1244 */
1245 if (tsc_start == -1) {
1246 /*
1247 * Only set hpet once, to avoid mixing hardware
1248 * if the hpet becomes enabled later.
1249 */
1250 hpet = is_hpet_enabled();
1251 schedule_delayed_work(&tsc_irqwork, HZ);
1252 tsc_start = tsc_read_refs(&ref_start, hpet);
1253 return;
1254 }
1255
1256 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1257
1258 /* hpet or pmtimer available ? */
1259 if (ref_start == ref_stop)
1260 goto out;
1261
1262 /* Check, whether the sampling was disturbed by an SMI */
1263 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1264 goto out;
1265
1266 delta = tsc_stop - tsc_start;
1267 delta *= 1000000LL;
1268 if (hpet)
1269 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1270 else
1271 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1272
1273 /* Make sure we're within 1% */
1274 if (abs(tsc_khz - freq) > tsc_khz/100)
1275 goto out;
1276
1277 tsc_khz = freq;
1278 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1279 (unsigned long)tsc_khz / 1000,
1280 (unsigned long)tsc_khz % 1000);
1281
1282 /* Inform the TSC deadline clockevent devices about the recalibration */
1283 lapic_update_tsc_freq();
1284
1285out:
1286 if (boot_cpu_has(X86_FEATURE_ART))
1287 art_related_clocksource = &clocksource_tsc;
1288 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1289}
1290
1291
1292static int __init init_tsc_clocksource(void)
1293{
1294 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz)
1295 return 0;
1296
1297 if (tsc_clocksource_reliable)
1298 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1299 /* lower the rating if we already know its unstable: */
1300 if (check_tsc_unstable()) {
1301 clocksource_tsc.rating = 0;
1302 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1303 }
1304
1305 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1306 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1307
1308 /*
1309 * When TSC frequency is known (retrieved via MSR or CPUID), we skip
1310 * the refined calibration and directly register it as a clocksource.
1311 */
1312 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
1313 if (boot_cpu_has(X86_FEATURE_ART))
1314 art_related_clocksource = &clocksource_tsc;
1315 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1316 return 0;
1317 }
1318
1319 schedule_delayed_work(&tsc_irqwork, 0);
1320 return 0;
1321}
1322/*
1323 * We use device_initcall here, to ensure we run after the hpet
1324 * is fully initialized, which may occur at fs_initcall time.
1325 */
1326device_initcall(init_tsc_clocksource);
1327
1328void __init tsc_init(void)
1329{
1330 u64 lpj;
1331 int cpu;
1332
1333 if (!boot_cpu_has(X86_FEATURE_TSC)) {
1334 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1335 return;
1336 }
1337
1338 cpu_khz = x86_platform.calibrate_cpu();
1339 tsc_khz = x86_platform.calibrate_tsc();
1340
1341 /*
1342 * Trust non-zero tsc_khz as authorative,
1343 * and use it to sanity check cpu_khz,
1344 * which will be off if system timer is off.
1345 */
1346 if (tsc_khz == 0)
1347 tsc_khz = cpu_khz;
1348 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
1349 cpu_khz = tsc_khz;
1350
1351 if (!tsc_khz) {
1352 mark_tsc_unstable("could not calculate TSC khz");
1353 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1354 return;
1355 }
1356
1357 pr_info("Detected %lu.%03lu MHz processor\n",
1358 (unsigned long)cpu_khz / 1000,
1359 (unsigned long)cpu_khz % 1000);
1360
1361 /* Sanitize TSC ADJUST before cyc2ns gets initialized */
1362 tsc_store_and_check_tsc_adjust(true);
1363
1364 /*
1365 * Secondary CPUs do not run through tsc_init(), so set up
1366 * all the scale factors for all CPUs, assuming the same
1367 * speed as the bootup CPU. (cpufreq notifiers will fix this
1368 * up if their speed diverges)
1369 */
1370 for_each_possible_cpu(cpu) {
1371 cyc2ns_init(cpu);
1372 set_cyc2ns_scale(tsc_khz, cpu);
1373 }
1374
1375 if (tsc_disabled > 0)
1376 return;
1377
1378 /* now allow native_sched_clock() to use rdtsc */
1379
1380 tsc_disabled = 0;
1381 static_branch_enable(&__use_tsc);
1382
1383 if (!no_sched_irq_time)
1384 enable_sched_clock_irqtime();
1385
1386 lpj = ((u64)tsc_khz * 1000);
1387 do_div(lpj, HZ);
1388 lpj_fine = lpj;
1389
1390 use_tsc_delay();
1391
1392 if (unsynchronized_tsc())
1393 mark_tsc_unstable("TSCs unsynchronized");
1394
1395 check_system_tsc_reliable();
1396
1397 detect_art();
1398}
1399
1400#ifdef CONFIG_SMP
1401/*
1402 * If we have a constant TSC and are using the TSC for the delay loop,
1403 * we can skip clock calibration if another cpu in the same socket has already
1404 * been calibrated. This assumes that CONSTANT_TSC applies to all
1405 * cpus in the socket - this should be a safe assumption.
1406 */
1407unsigned long calibrate_delay_is_known(void)
1408{
1409 int sibling, cpu = smp_processor_id();
1410 struct cpumask *mask = topology_core_cpumask(cpu);
1411
1412 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1413 return 0;
1414
1415 if (!mask)
1416 return 0;
1417
1418 sibling = cpumask_any_but(mask, cpu);
1419 if (sibling < nr_cpu_ids)
1420 return cpu_data(sibling).loops_per_jiffy;
1421 return 0;
1422}
1423#endif
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/sched.h>
5#include <linux/init.h>
6#include <linux/module.h>
7#include <linux/timer.h>
8#include <linux/acpi_pmtmr.h>
9#include <linux/cpufreq.h>
10#include <linux/delay.h>
11#include <linux/clocksource.h>
12#include <linux/percpu.h>
13#include <linux/timex.h>
14#include <linux/static_key.h>
15
16#include <asm/hpet.h>
17#include <asm/timer.h>
18#include <asm/vgtod.h>
19#include <asm/time.h>
20#include <asm/delay.h>
21#include <asm/hypervisor.h>
22#include <asm/nmi.h>
23#include <asm/x86_init.h>
24#include <asm/geode.h>
25
26unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
27EXPORT_SYMBOL(cpu_khz);
28
29unsigned int __read_mostly tsc_khz;
30EXPORT_SYMBOL(tsc_khz);
31
32/*
33 * TSC can be unstable due to cpufreq or due to unsynced TSCs
34 */
35static int __read_mostly tsc_unstable;
36
37/* native_sched_clock() is called before tsc_init(), so
38 we must start with the TSC soft disabled to prevent
39 erroneous rdtsc usage on !cpu_has_tsc processors */
40static int __read_mostly tsc_disabled = -1;
41
42static DEFINE_STATIC_KEY_FALSE(__use_tsc);
43
44int tsc_clocksource_reliable;
45
46static u32 art_to_tsc_numerator;
47static u32 art_to_tsc_denominator;
48static u64 art_to_tsc_offset;
49struct clocksource *art_related_clocksource;
50
51/*
52 * Use a ring-buffer like data structure, where a writer advances the head by
53 * writing a new data entry and a reader advances the tail when it observes a
54 * new entry.
55 *
56 * Writers are made to wait on readers until there's space to write a new
57 * entry.
58 *
59 * This means that we can always use an {offset, mul} pair to compute a ns
60 * value that is 'roughly' in the right direction, even if we're writing a new
61 * {offset, mul} pair during the clock read.
62 *
63 * The down-side is that we can no longer guarantee strict monotonicity anymore
64 * (assuming the TSC was that to begin with), because while we compute the
65 * intersection point of the two clock slopes and make sure the time is
66 * continuous at the point of switching; we can no longer guarantee a reader is
67 * strictly before or after the switch point.
68 *
69 * It does mean a reader no longer needs to disable IRQs in order to avoid
70 * CPU-Freq updates messing with his times, and similarly an NMI reader will
71 * no longer run the risk of hitting half-written state.
72 */
73
74struct cyc2ns {
75 struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */
76 struct cyc2ns_data *head; /* 48 + 8 = 56 */
77 struct cyc2ns_data *tail; /* 56 + 8 = 64 */
78}; /* exactly fits one cacheline */
79
80static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
81
82struct cyc2ns_data *cyc2ns_read_begin(void)
83{
84 struct cyc2ns_data *head;
85
86 preempt_disable();
87
88 head = this_cpu_read(cyc2ns.head);
89 /*
90 * Ensure we observe the entry when we observe the pointer to it.
91 * matches the wmb from cyc2ns_write_end().
92 */
93 smp_read_barrier_depends();
94 head->__count++;
95 barrier();
96
97 return head;
98}
99
100void cyc2ns_read_end(struct cyc2ns_data *head)
101{
102 barrier();
103 /*
104 * If we're the outer most nested read; update the tail pointer
105 * when we're done. This notifies possible pending writers
106 * that we've observed the head pointer and that the other
107 * entry is now free.
108 */
109 if (!--head->__count) {
110 /*
111 * x86-TSO does not reorder writes with older reads;
112 * therefore once this write becomes visible to another
113 * cpu, we must be finished reading the cyc2ns_data.
114 *
115 * matches with cyc2ns_write_begin().
116 */
117 this_cpu_write(cyc2ns.tail, head);
118 }
119 preempt_enable();
120}
121
122/*
123 * Begin writing a new @data entry for @cpu.
124 *
125 * Assumes some sort of write side lock; currently 'provided' by the assumption
126 * that cpufreq will call its notifiers sequentially.
127 */
128static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
129{
130 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
131 struct cyc2ns_data *data = c2n->data;
132
133 if (data == c2n->head)
134 data++;
135
136 /* XXX send an IPI to @cpu in order to guarantee a read? */
137
138 /*
139 * When we observe the tail write from cyc2ns_read_end(),
140 * the cpu must be done with that entry and its safe
141 * to start writing to it.
142 */
143 while (c2n->tail == data)
144 cpu_relax();
145
146 return data;
147}
148
149static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
150{
151 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
152
153 /*
154 * Ensure the @data writes are visible before we publish the
155 * entry. Matches the data-depencency in cyc2ns_read_begin().
156 */
157 smp_wmb();
158
159 ACCESS_ONCE(c2n->head) = data;
160}
161
162/*
163 * Accelerators for sched_clock()
164 * convert from cycles(64bits) => nanoseconds (64bits)
165 * basic equation:
166 * ns = cycles / (freq / ns_per_sec)
167 * ns = cycles * (ns_per_sec / freq)
168 * ns = cycles * (10^9 / (cpu_khz * 10^3))
169 * ns = cycles * (10^6 / cpu_khz)
170 *
171 * Then we use scaling math (suggested by george@mvista.com) to get:
172 * ns = cycles * (10^6 * SC / cpu_khz) / SC
173 * ns = cycles * cyc2ns_scale / SC
174 *
175 * And since SC is a constant power of two, we can convert the div
176 * into a shift. The larger SC is, the more accurate the conversion, but
177 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
178 * (64-bit result) can be used.
179 *
180 * We can use khz divisor instead of mhz to keep a better precision.
181 * (mathieu.desnoyers@polymtl.ca)
182 *
183 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
184 */
185
186static void cyc2ns_data_init(struct cyc2ns_data *data)
187{
188 data->cyc2ns_mul = 0;
189 data->cyc2ns_shift = 0;
190 data->cyc2ns_offset = 0;
191 data->__count = 0;
192}
193
194static void cyc2ns_init(int cpu)
195{
196 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
197
198 cyc2ns_data_init(&c2n->data[0]);
199 cyc2ns_data_init(&c2n->data[1]);
200
201 c2n->head = c2n->data;
202 c2n->tail = c2n->data;
203}
204
205static inline unsigned long long cycles_2_ns(unsigned long long cyc)
206{
207 struct cyc2ns_data *data, *tail;
208 unsigned long long ns;
209
210 /*
211 * See cyc2ns_read_*() for details; replicated in order to avoid
212 * an extra few instructions that came with the abstraction.
213 * Notable, it allows us to only do the __count and tail update
214 * dance when its actually needed.
215 */
216
217 preempt_disable_notrace();
218 data = this_cpu_read(cyc2ns.head);
219 tail = this_cpu_read(cyc2ns.tail);
220
221 if (likely(data == tail)) {
222 ns = data->cyc2ns_offset;
223 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
224 } else {
225 data->__count++;
226
227 barrier();
228
229 ns = data->cyc2ns_offset;
230 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
231
232 barrier();
233
234 if (!--data->__count)
235 this_cpu_write(cyc2ns.tail, data);
236 }
237 preempt_enable_notrace();
238
239 return ns;
240}
241
242static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
243{
244 unsigned long long tsc_now, ns_now;
245 struct cyc2ns_data *data;
246 unsigned long flags;
247
248 local_irq_save(flags);
249 sched_clock_idle_sleep_event();
250
251 if (!cpu_khz)
252 goto done;
253
254 data = cyc2ns_write_begin(cpu);
255
256 tsc_now = rdtsc();
257 ns_now = cycles_2_ns(tsc_now);
258
259 /*
260 * Compute a new multiplier as per the above comment and ensure our
261 * time function is continuous; see the comment near struct
262 * cyc2ns_data.
263 */
264 clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, cpu_khz,
265 NSEC_PER_MSEC, 0);
266
267 /*
268 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
269 * not expected to be greater than 31 due to the original published
270 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
271 * value) - refer perf_event_mmap_page documentation in perf_event.h.
272 */
273 if (data->cyc2ns_shift == 32) {
274 data->cyc2ns_shift = 31;
275 data->cyc2ns_mul >>= 1;
276 }
277
278 data->cyc2ns_offset = ns_now -
279 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, data->cyc2ns_shift);
280
281 cyc2ns_write_end(cpu, data);
282
283done:
284 sched_clock_idle_wakeup_event(0);
285 local_irq_restore(flags);
286}
287/*
288 * Scheduler clock - returns current time in nanosec units.
289 */
290u64 native_sched_clock(void)
291{
292 if (static_branch_likely(&__use_tsc)) {
293 u64 tsc_now = rdtsc();
294
295 /* return the value in ns */
296 return cycles_2_ns(tsc_now);
297 }
298
299 /*
300 * Fall back to jiffies if there's no TSC available:
301 * ( But note that we still use it if the TSC is marked
302 * unstable. We do this because unlike Time Of Day,
303 * the scheduler clock tolerates small errors and it's
304 * very important for it to be as fast as the platform
305 * can achieve it. )
306 */
307
308 /* No locking but a rare wrong value is not a big deal: */
309 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
310}
311
312/*
313 * Generate a sched_clock if you already have a TSC value.
314 */
315u64 native_sched_clock_from_tsc(u64 tsc)
316{
317 return cycles_2_ns(tsc);
318}
319
320/* We need to define a real function for sched_clock, to override the
321 weak default version */
322#ifdef CONFIG_PARAVIRT
323unsigned long long sched_clock(void)
324{
325 return paravirt_sched_clock();
326}
327#else
328unsigned long long
329sched_clock(void) __attribute__((alias("native_sched_clock")));
330#endif
331
332int check_tsc_unstable(void)
333{
334 return tsc_unstable;
335}
336EXPORT_SYMBOL_GPL(check_tsc_unstable);
337
338int check_tsc_disabled(void)
339{
340 return tsc_disabled;
341}
342EXPORT_SYMBOL_GPL(check_tsc_disabled);
343
344#ifdef CONFIG_X86_TSC
345int __init notsc_setup(char *str)
346{
347 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
348 tsc_disabled = 1;
349 return 1;
350}
351#else
352/*
353 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
354 * in cpu/common.c
355 */
356int __init notsc_setup(char *str)
357{
358 setup_clear_cpu_cap(X86_FEATURE_TSC);
359 return 1;
360}
361#endif
362
363__setup("notsc", notsc_setup);
364
365static int no_sched_irq_time;
366
367static int __init tsc_setup(char *str)
368{
369 if (!strcmp(str, "reliable"))
370 tsc_clocksource_reliable = 1;
371 if (!strncmp(str, "noirqtime", 9))
372 no_sched_irq_time = 1;
373 return 1;
374}
375
376__setup("tsc=", tsc_setup);
377
378#define MAX_RETRIES 5
379#define SMI_TRESHOLD 50000
380
381/*
382 * Read TSC and the reference counters. Take care of SMI disturbance
383 */
384static u64 tsc_read_refs(u64 *p, int hpet)
385{
386 u64 t1, t2;
387 int i;
388
389 for (i = 0; i < MAX_RETRIES; i++) {
390 t1 = get_cycles();
391 if (hpet)
392 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
393 else
394 *p = acpi_pm_read_early();
395 t2 = get_cycles();
396 if ((t2 - t1) < SMI_TRESHOLD)
397 return t2;
398 }
399 return ULLONG_MAX;
400}
401
402/*
403 * Calculate the TSC frequency from HPET reference
404 */
405static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
406{
407 u64 tmp;
408
409 if (hpet2 < hpet1)
410 hpet2 += 0x100000000ULL;
411 hpet2 -= hpet1;
412 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
413 do_div(tmp, 1000000);
414 do_div(deltatsc, tmp);
415
416 return (unsigned long) deltatsc;
417}
418
419/*
420 * Calculate the TSC frequency from PMTimer reference
421 */
422static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
423{
424 u64 tmp;
425
426 if (!pm1 && !pm2)
427 return ULONG_MAX;
428
429 if (pm2 < pm1)
430 pm2 += (u64)ACPI_PM_OVRRUN;
431 pm2 -= pm1;
432 tmp = pm2 * 1000000000LL;
433 do_div(tmp, PMTMR_TICKS_PER_SEC);
434 do_div(deltatsc, tmp);
435
436 return (unsigned long) deltatsc;
437}
438
439#define CAL_MS 10
440#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
441#define CAL_PIT_LOOPS 1000
442
443#define CAL2_MS 50
444#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
445#define CAL2_PIT_LOOPS 5000
446
447
448/*
449 * Try to calibrate the TSC against the Programmable
450 * Interrupt Timer and return the frequency of the TSC
451 * in kHz.
452 *
453 * Return ULONG_MAX on failure to calibrate.
454 */
455static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
456{
457 u64 tsc, t1, t2, delta;
458 unsigned long tscmin, tscmax;
459 int pitcnt;
460
461 /* Set the Gate high, disable speaker */
462 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
463
464 /*
465 * Setup CTC channel 2* for mode 0, (interrupt on terminal
466 * count mode), binary count. Set the latch register to 50ms
467 * (LSB then MSB) to begin countdown.
468 */
469 outb(0xb0, 0x43);
470 outb(latch & 0xff, 0x42);
471 outb(latch >> 8, 0x42);
472
473 tsc = t1 = t2 = get_cycles();
474
475 pitcnt = 0;
476 tscmax = 0;
477 tscmin = ULONG_MAX;
478 while ((inb(0x61) & 0x20) == 0) {
479 t2 = get_cycles();
480 delta = t2 - tsc;
481 tsc = t2;
482 if ((unsigned long) delta < tscmin)
483 tscmin = (unsigned int) delta;
484 if ((unsigned long) delta > tscmax)
485 tscmax = (unsigned int) delta;
486 pitcnt++;
487 }
488
489 /*
490 * Sanity checks:
491 *
492 * If we were not able to read the PIT more than loopmin
493 * times, then we have been hit by a massive SMI
494 *
495 * If the maximum is 10 times larger than the minimum,
496 * then we got hit by an SMI as well.
497 */
498 if (pitcnt < loopmin || tscmax > 10 * tscmin)
499 return ULONG_MAX;
500
501 /* Calculate the PIT value */
502 delta = t2 - t1;
503 do_div(delta, ms);
504 return delta;
505}
506
507/*
508 * This reads the current MSB of the PIT counter, and
509 * checks if we are running on sufficiently fast and
510 * non-virtualized hardware.
511 *
512 * Our expectations are:
513 *
514 * - the PIT is running at roughly 1.19MHz
515 *
516 * - each IO is going to take about 1us on real hardware,
517 * but we allow it to be much faster (by a factor of 10) or
518 * _slightly_ slower (ie we allow up to a 2us read+counter
519 * update - anything else implies a unacceptably slow CPU
520 * or PIT for the fast calibration to work.
521 *
522 * - with 256 PIT ticks to read the value, we have 214us to
523 * see the same MSB (and overhead like doing a single TSC
524 * read per MSB value etc).
525 *
526 * - We're doing 2 reads per loop (LSB, MSB), and we expect
527 * them each to take about a microsecond on real hardware.
528 * So we expect a count value of around 100. But we'll be
529 * generous, and accept anything over 50.
530 *
531 * - if the PIT is stuck, and we see *many* more reads, we
532 * return early (and the next caller of pit_expect_msb()
533 * then consider it a failure when they don't see the
534 * next expected value).
535 *
536 * These expectations mean that we know that we have seen the
537 * transition from one expected value to another with a fairly
538 * high accuracy, and we didn't miss any events. We can thus
539 * use the TSC value at the transitions to calculate a pretty
540 * good value for the TSC frequencty.
541 */
542static inline int pit_verify_msb(unsigned char val)
543{
544 /* Ignore LSB */
545 inb(0x42);
546 return inb(0x42) == val;
547}
548
549static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
550{
551 int count;
552 u64 tsc = 0, prev_tsc = 0;
553
554 for (count = 0; count < 50000; count++) {
555 if (!pit_verify_msb(val))
556 break;
557 prev_tsc = tsc;
558 tsc = get_cycles();
559 }
560 *deltap = get_cycles() - prev_tsc;
561 *tscp = tsc;
562
563 /*
564 * We require _some_ success, but the quality control
565 * will be based on the error terms on the TSC values.
566 */
567 return count > 5;
568}
569
570/*
571 * How many MSB values do we want to see? We aim for
572 * a maximum error rate of 500ppm (in practice the
573 * real error is much smaller), but refuse to spend
574 * more than 50ms on it.
575 */
576#define MAX_QUICK_PIT_MS 50
577#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
578
579static unsigned long quick_pit_calibrate(void)
580{
581 int i;
582 u64 tsc, delta;
583 unsigned long d1, d2;
584
585 /* Set the Gate high, disable speaker */
586 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
587
588 /*
589 * Counter 2, mode 0 (one-shot), binary count
590 *
591 * NOTE! Mode 2 decrements by two (and then the
592 * output is flipped each time, giving the same
593 * final output frequency as a decrement-by-one),
594 * so mode 0 is much better when looking at the
595 * individual counts.
596 */
597 outb(0xb0, 0x43);
598
599 /* Start at 0xffff */
600 outb(0xff, 0x42);
601 outb(0xff, 0x42);
602
603 /*
604 * The PIT starts counting at the next edge, so we
605 * need to delay for a microsecond. The easiest way
606 * to do that is to just read back the 16-bit counter
607 * once from the PIT.
608 */
609 pit_verify_msb(0);
610
611 if (pit_expect_msb(0xff, &tsc, &d1)) {
612 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
613 if (!pit_expect_msb(0xff-i, &delta, &d2))
614 break;
615
616 delta -= tsc;
617
618 /*
619 * Extrapolate the error and fail fast if the error will
620 * never be below 500 ppm.
621 */
622 if (i == 1 &&
623 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
624 return 0;
625
626 /*
627 * Iterate until the error is less than 500 ppm
628 */
629 if (d1+d2 >= delta >> 11)
630 continue;
631
632 /*
633 * Check the PIT one more time to verify that
634 * all TSC reads were stable wrt the PIT.
635 *
636 * This also guarantees serialization of the
637 * last cycle read ('d2') in pit_expect_msb.
638 */
639 if (!pit_verify_msb(0xfe - i))
640 break;
641 goto success;
642 }
643 }
644 pr_info("Fast TSC calibration failed\n");
645 return 0;
646
647success:
648 /*
649 * Ok, if we get here, then we've seen the
650 * MSB of the PIT decrement 'i' times, and the
651 * error has shrunk to less than 500 ppm.
652 *
653 * As a result, we can depend on there not being
654 * any odd delays anywhere, and the TSC reads are
655 * reliable (within the error).
656 *
657 * kHz = ticks / time-in-seconds / 1000;
658 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
659 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
660 */
661 delta *= PIT_TICK_RATE;
662 do_div(delta, i*256*1000);
663 pr_info("Fast TSC calibration using PIT\n");
664 return delta;
665}
666
667/**
668 * native_calibrate_tsc - calibrate the tsc on boot
669 */
670unsigned long native_calibrate_tsc(void)
671{
672 u64 tsc1, tsc2, delta, ref1, ref2;
673 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
674 unsigned long flags, latch, ms, fast_calibrate;
675 int hpet = is_hpet_enabled(), i, loopmin;
676
677 /* Calibrate TSC using MSR for Intel Atom SoCs */
678 local_irq_save(flags);
679 fast_calibrate = try_msr_calibrate_tsc();
680 local_irq_restore(flags);
681 if (fast_calibrate)
682 return fast_calibrate;
683
684 local_irq_save(flags);
685 fast_calibrate = quick_pit_calibrate();
686 local_irq_restore(flags);
687 if (fast_calibrate)
688 return fast_calibrate;
689
690 /*
691 * Run 5 calibration loops to get the lowest frequency value
692 * (the best estimate). We use two different calibration modes
693 * here:
694 *
695 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
696 * load a timeout of 50ms. We read the time right after we
697 * started the timer and wait until the PIT count down reaches
698 * zero. In each wait loop iteration we read the TSC and check
699 * the delta to the previous read. We keep track of the min
700 * and max values of that delta. The delta is mostly defined
701 * by the IO time of the PIT access, so we can detect when a
702 * SMI/SMM disturbance happened between the two reads. If the
703 * maximum time is significantly larger than the minimum time,
704 * then we discard the result and have another try.
705 *
706 * 2) Reference counter. If available we use the HPET or the
707 * PMTIMER as a reference to check the sanity of that value.
708 * We use separate TSC readouts and check inside of the
709 * reference read for a SMI/SMM disturbance. We dicard
710 * disturbed values here as well. We do that around the PIT
711 * calibration delay loop as we have to wait for a certain
712 * amount of time anyway.
713 */
714
715 /* Preset PIT loop values */
716 latch = CAL_LATCH;
717 ms = CAL_MS;
718 loopmin = CAL_PIT_LOOPS;
719
720 for (i = 0; i < 3; i++) {
721 unsigned long tsc_pit_khz;
722
723 /*
724 * Read the start value and the reference count of
725 * hpet/pmtimer when available. Then do the PIT
726 * calibration, which will take at least 50ms, and
727 * read the end value.
728 */
729 local_irq_save(flags);
730 tsc1 = tsc_read_refs(&ref1, hpet);
731 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
732 tsc2 = tsc_read_refs(&ref2, hpet);
733 local_irq_restore(flags);
734
735 /* Pick the lowest PIT TSC calibration so far */
736 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
737
738 /* hpet or pmtimer available ? */
739 if (ref1 == ref2)
740 continue;
741
742 /* Check, whether the sampling was disturbed by an SMI */
743 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
744 continue;
745
746 tsc2 = (tsc2 - tsc1) * 1000000LL;
747 if (hpet)
748 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
749 else
750 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
751
752 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
753
754 /* Check the reference deviation */
755 delta = ((u64) tsc_pit_min) * 100;
756 do_div(delta, tsc_ref_min);
757
758 /*
759 * If both calibration results are inside a 10% window
760 * then we can be sure, that the calibration
761 * succeeded. We break out of the loop right away. We
762 * use the reference value, as it is more precise.
763 */
764 if (delta >= 90 && delta <= 110) {
765 pr_info("PIT calibration matches %s. %d loops\n",
766 hpet ? "HPET" : "PMTIMER", i + 1);
767 return tsc_ref_min;
768 }
769
770 /*
771 * Check whether PIT failed more than once. This
772 * happens in virtualized environments. We need to
773 * give the virtual PC a slightly longer timeframe for
774 * the HPET/PMTIMER to make the result precise.
775 */
776 if (i == 1 && tsc_pit_min == ULONG_MAX) {
777 latch = CAL2_LATCH;
778 ms = CAL2_MS;
779 loopmin = CAL2_PIT_LOOPS;
780 }
781 }
782
783 /*
784 * Now check the results.
785 */
786 if (tsc_pit_min == ULONG_MAX) {
787 /* PIT gave no useful value */
788 pr_warn("Unable to calibrate against PIT\n");
789
790 /* We don't have an alternative source, disable TSC */
791 if (!hpet && !ref1 && !ref2) {
792 pr_notice("No reference (HPET/PMTIMER) available\n");
793 return 0;
794 }
795
796 /* The alternative source failed as well, disable TSC */
797 if (tsc_ref_min == ULONG_MAX) {
798 pr_warn("HPET/PMTIMER calibration failed\n");
799 return 0;
800 }
801
802 /* Use the alternative source */
803 pr_info("using %s reference calibration\n",
804 hpet ? "HPET" : "PMTIMER");
805
806 return tsc_ref_min;
807 }
808
809 /* We don't have an alternative source, use the PIT calibration value */
810 if (!hpet && !ref1 && !ref2) {
811 pr_info("Using PIT calibration value\n");
812 return tsc_pit_min;
813 }
814
815 /* The alternative source failed, use the PIT calibration value */
816 if (tsc_ref_min == ULONG_MAX) {
817 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
818 return tsc_pit_min;
819 }
820
821 /*
822 * The calibration values differ too much. In doubt, we use
823 * the PIT value as we know that there are PMTIMERs around
824 * running at double speed. At least we let the user know:
825 */
826 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
827 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
828 pr_info("Using PIT calibration value\n");
829 return tsc_pit_min;
830}
831
832int recalibrate_cpu_khz(void)
833{
834#ifndef CONFIG_SMP
835 unsigned long cpu_khz_old = cpu_khz;
836
837 if (cpu_has_tsc) {
838 tsc_khz = x86_platform.calibrate_tsc();
839 cpu_khz = tsc_khz;
840 cpu_data(0).loops_per_jiffy =
841 cpufreq_scale(cpu_data(0).loops_per_jiffy,
842 cpu_khz_old, cpu_khz);
843 return 0;
844 } else
845 return -ENODEV;
846#else
847 return -ENODEV;
848#endif
849}
850
851EXPORT_SYMBOL(recalibrate_cpu_khz);
852
853
854static unsigned long long cyc2ns_suspend;
855
856void tsc_save_sched_clock_state(void)
857{
858 if (!sched_clock_stable())
859 return;
860
861 cyc2ns_suspend = sched_clock();
862}
863
864/*
865 * Even on processors with invariant TSC, TSC gets reset in some the
866 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
867 * arbitrary value (still sync'd across cpu's) during resume from such sleep
868 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
869 * that sched_clock() continues from the point where it was left off during
870 * suspend.
871 */
872void tsc_restore_sched_clock_state(void)
873{
874 unsigned long long offset;
875 unsigned long flags;
876 int cpu;
877
878 if (!sched_clock_stable())
879 return;
880
881 local_irq_save(flags);
882
883 /*
884 * We're coming out of suspend, there's no concurrency yet; don't
885 * bother being nice about the RCU stuff, just write to both
886 * data fields.
887 */
888
889 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
890 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
891
892 offset = cyc2ns_suspend - sched_clock();
893
894 for_each_possible_cpu(cpu) {
895 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
896 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
897 }
898
899 local_irq_restore(flags);
900}
901
902#ifdef CONFIG_CPU_FREQ
903
904/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
905 * changes.
906 *
907 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
908 * not that important because current Opteron setups do not support
909 * scaling on SMP anyroads.
910 *
911 * Should fix up last_tsc too. Currently gettimeofday in the
912 * first tick after the change will be slightly wrong.
913 */
914
915static unsigned int ref_freq;
916static unsigned long loops_per_jiffy_ref;
917static unsigned long tsc_khz_ref;
918
919static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
920 void *data)
921{
922 struct cpufreq_freqs *freq = data;
923 unsigned long *lpj;
924
925 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
926 return 0;
927
928 lpj = &boot_cpu_data.loops_per_jiffy;
929#ifdef CONFIG_SMP
930 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
931 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
932#endif
933
934 if (!ref_freq) {
935 ref_freq = freq->old;
936 loops_per_jiffy_ref = *lpj;
937 tsc_khz_ref = tsc_khz;
938 }
939 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
940 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
941 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
942
943 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
944 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
945 mark_tsc_unstable("cpufreq changes");
946
947 set_cyc2ns_scale(tsc_khz, freq->cpu);
948 }
949
950 return 0;
951}
952
953static struct notifier_block time_cpufreq_notifier_block = {
954 .notifier_call = time_cpufreq_notifier
955};
956
957static int __init cpufreq_tsc(void)
958{
959 if (!cpu_has_tsc)
960 return 0;
961 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
962 return 0;
963 cpufreq_register_notifier(&time_cpufreq_notifier_block,
964 CPUFREQ_TRANSITION_NOTIFIER);
965 return 0;
966}
967
968core_initcall(cpufreq_tsc);
969
970#endif /* CONFIG_CPU_FREQ */
971
972#define ART_CPUID_LEAF (0x15)
973#define ART_MIN_DENOMINATOR (1)
974
975
976/*
977 * If ART is present detect the numerator:denominator to convert to TSC
978 */
979static void detect_art(void)
980{
981 unsigned int unused[2];
982
983 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
984 return;
985
986 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
987 &art_to_tsc_numerator, unused, unused+1);
988
989 /* Don't enable ART in a VM, non-stop TSC required */
990 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
991 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
992 art_to_tsc_denominator < ART_MIN_DENOMINATOR)
993 return;
994
995 if (rdmsrl_safe(MSR_IA32_TSC_ADJUST, &art_to_tsc_offset))
996 return;
997
998 /* Make this sticky over multiple CPU init calls */
999 setup_force_cpu_cap(X86_FEATURE_ART);
1000}
1001
1002
1003/* clocksource code */
1004
1005static struct clocksource clocksource_tsc;
1006
1007/*
1008 * We used to compare the TSC to the cycle_last value in the clocksource
1009 * structure to avoid a nasty time-warp. This can be observed in a
1010 * very small window right after one CPU updated cycle_last under
1011 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1012 * is smaller than the cycle_last reference value due to a TSC which
1013 * is slighty behind. This delta is nowhere else observable, but in
1014 * that case it results in a forward time jump in the range of hours
1015 * due to the unsigned delta calculation of the time keeping core
1016 * code, which is necessary to support wrapping clocksources like pm
1017 * timer.
1018 *
1019 * This sanity check is now done in the core timekeeping code.
1020 * checking the result of read_tsc() - cycle_last for being negative.
1021 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1022 */
1023static cycle_t read_tsc(struct clocksource *cs)
1024{
1025 return (cycle_t)rdtsc_ordered();
1026}
1027
1028/*
1029 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1030 */
1031static struct clocksource clocksource_tsc = {
1032 .name = "tsc",
1033 .rating = 300,
1034 .read = read_tsc,
1035 .mask = CLOCKSOURCE_MASK(64),
1036 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1037 CLOCK_SOURCE_MUST_VERIFY,
1038 .archdata = { .vclock_mode = VCLOCK_TSC },
1039};
1040
1041void mark_tsc_unstable(char *reason)
1042{
1043 if (!tsc_unstable) {
1044 tsc_unstable = 1;
1045 clear_sched_clock_stable();
1046 disable_sched_clock_irqtime();
1047 pr_info("Marking TSC unstable due to %s\n", reason);
1048 /* Change only the rating, when not registered */
1049 if (clocksource_tsc.mult)
1050 clocksource_mark_unstable(&clocksource_tsc);
1051 else {
1052 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
1053 clocksource_tsc.rating = 0;
1054 }
1055 }
1056}
1057
1058EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1059
1060static void __init check_system_tsc_reliable(void)
1061{
1062#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1063 if (is_geode_lx()) {
1064 /* RTSC counts during suspend */
1065#define RTSC_SUSP 0x100
1066 unsigned long res_low, res_high;
1067
1068 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1069 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1070 if (res_low & RTSC_SUSP)
1071 tsc_clocksource_reliable = 1;
1072 }
1073#endif
1074 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1075 tsc_clocksource_reliable = 1;
1076}
1077
1078/*
1079 * Make an educated guess if the TSC is trustworthy and synchronized
1080 * over all CPUs.
1081 */
1082int unsynchronized_tsc(void)
1083{
1084 if (!cpu_has_tsc || tsc_unstable)
1085 return 1;
1086
1087#ifdef CONFIG_SMP
1088 if (apic_is_clustered_box())
1089 return 1;
1090#endif
1091
1092 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1093 return 0;
1094
1095 if (tsc_clocksource_reliable)
1096 return 0;
1097 /*
1098 * Intel systems are normally all synchronized.
1099 * Exceptions must mark TSC as unstable:
1100 */
1101 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1102 /* assume multi socket systems are not synchronized: */
1103 if (num_possible_cpus() > 1)
1104 return 1;
1105 }
1106
1107 return 0;
1108}
1109
1110/*
1111 * Convert ART to TSC given numerator/denominator found in detect_art()
1112 */
1113struct system_counterval_t convert_art_to_tsc(cycle_t art)
1114{
1115 u64 tmp, res, rem;
1116
1117 rem = do_div(art, art_to_tsc_denominator);
1118
1119 res = art * art_to_tsc_numerator;
1120 tmp = rem * art_to_tsc_numerator;
1121
1122 do_div(tmp, art_to_tsc_denominator);
1123 res += tmp + art_to_tsc_offset;
1124
1125 return (struct system_counterval_t) {.cs = art_related_clocksource,
1126 .cycles = res};
1127}
1128EXPORT_SYMBOL(convert_art_to_tsc);
1129
1130static void tsc_refine_calibration_work(struct work_struct *work);
1131static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1132/**
1133 * tsc_refine_calibration_work - Further refine tsc freq calibration
1134 * @work - ignored.
1135 *
1136 * This functions uses delayed work over a period of a
1137 * second to further refine the TSC freq value. Since this is
1138 * timer based, instead of loop based, we don't block the boot
1139 * process while this longer calibration is done.
1140 *
1141 * If there are any calibration anomalies (too many SMIs, etc),
1142 * or the refined calibration is off by 1% of the fast early
1143 * calibration, we throw out the new calibration and use the
1144 * early calibration.
1145 */
1146static void tsc_refine_calibration_work(struct work_struct *work)
1147{
1148 static u64 tsc_start = -1, ref_start;
1149 static int hpet;
1150 u64 tsc_stop, ref_stop, delta;
1151 unsigned long freq;
1152
1153 /* Don't bother refining TSC on unstable systems */
1154 if (check_tsc_unstable())
1155 goto out;
1156
1157 /*
1158 * Since the work is started early in boot, we may be
1159 * delayed the first time we expire. So set the workqueue
1160 * again once we know timers are working.
1161 */
1162 if (tsc_start == -1) {
1163 /*
1164 * Only set hpet once, to avoid mixing hardware
1165 * if the hpet becomes enabled later.
1166 */
1167 hpet = is_hpet_enabled();
1168 schedule_delayed_work(&tsc_irqwork, HZ);
1169 tsc_start = tsc_read_refs(&ref_start, hpet);
1170 return;
1171 }
1172
1173 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1174
1175 /* hpet or pmtimer available ? */
1176 if (ref_start == ref_stop)
1177 goto out;
1178
1179 /* Check, whether the sampling was disturbed by an SMI */
1180 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1181 goto out;
1182
1183 delta = tsc_stop - tsc_start;
1184 delta *= 1000000LL;
1185 if (hpet)
1186 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1187 else
1188 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1189
1190 /* Make sure we're within 1% */
1191 if (abs(tsc_khz - freq) > tsc_khz/100)
1192 goto out;
1193
1194 tsc_khz = freq;
1195 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1196 (unsigned long)tsc_khz / 1000,
1197 (unsigned long)tsc_khz % 1000);
1198
1199out:
1200 if (boot_cpu_has(X86_FEATURE_ART))
1201 art_related_clocksource = &clocksource_tsc;
1202 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1203}
1204
1205
1206static int __init init_tsc_clocksource(void)
1207{
1208 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
1209 return 0;
1210
1211 if (tsc_clocksource_reliable)
1212 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1213 /* lower the rating if we already know its unstable: */
1214 if (check_tsc_unstable()) {
1215 clocksource_tsc.rating = 0;
1216 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1217 }
1218
1219 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1220 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1221
1222 /*
1223 * Trust the results of the earlier calibration on systems
1224 * exporting a reliable TSC.
1225 */
1226 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
1227 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1228 return 0;
1229 }
1230
1231 schedule_delayed_work(&tsc_irqwork, 0);
1232 return 0;
1233}
1234/*
1235 * We use device_initcall here, to ensure we run after the hpet
1236 * is fully initialized, which may occur at fs_initcall time.
1237 */
1238device_initcall(init_tsc_clocksource);
1239
1240void __init tsc_init(void)
1241{
1242 u64 lpj;
1243 int cpu;
1244
1245 if (!cpu_has_tsc) {
1246 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1247 return;
1248 }
1249
1250 tsc_khz = x86_platform.calibrate_tsc();
1251 cpu_khz = tsc_khz;
1252
1253 if (!tsc_khz) {
1254 mark_tsc_unstable("could not calculate TSC khz");
1255 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1256 return;
1257 }
1258
1259 pr_info("Detected %lu.%03lu MHz processor\n",
1260 (unsigned long)cpu_khz / 1000,
1261 (unsigned long)cpu_khz % 1000);
1262
1263 /*
1264 * Secondary CPUs do not run through tsc_init(), so set up
1265 * all the scale factors for all CPUs, assuming the same
1266 * speed as the bootup CPU. (cpufreq notifiers will fix this
1267 * up if their speed diverges)
1268 */
1269 for_each_possible_cpu(cpu) {
1270 cyc2ns_init(cpu);
1271 set_cyc2ns_scale(cpu_khz, cpu);
1272 }
1273
1274 if (tsc_disabled > 0)
1275 return;
1276
1277 /* now allow native_sched_clock() to use rdtsc */
1278
1279 tsc_disabled = 0;
1280 static_branch_enable(&__use_tsc);
1281
1282 if (!no_sched_irq_time)
1283 enable_sched_clock_irqtime();
1284
1285 lpj = ((u64)tsc_khz * 1000);
1286 do_div(lpj, HZ);
1287 lpj_fine = lpj;
1288
1289 use_tsc_delay();
1290
1291 if (unsynchronized_tsc())
1292 mark_tsc_unstable("TSCs unsynchronized");
1293
1294 check_system_tsc_reliable();
1295
1296 detect_art();
1297}
1298
1299#ifdef CONFIG_SMP
1300/*
1301 * If we have a constant TSC and are using the TSC for the delay loop,
1302 * we can skip clock calibration if another cpu in the same socket has already
1303 * been calibrated. This assumes that CONSTANT_TSC applies to all
1304 * cpus in the socket - this should be a safe assumption.
1305 */
1306unsigned long calibrate_delay_is_known(void)
1307{
1308 int sibling, cpu = smp_processor_id();
1309 struct cpumask *mask = topology_core_cpumask(cpu);
1310
1311 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1312 return 0;
1313
1314 if (!mask)
1315 return 0;
1316
1317 sibling = cpumask_any_but(mask, cpu);
1318 if (sibling < nr_cpu_ids)
1319 return cpu_data(sibling).loops_per_jiffy;
1320 return 0;
1321}
1322#endif