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1#include <linux/clocksource.h>
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/export.h>
5#include <linux/delay.h>
6#include <linux/errno.h>
7#include <linux/i8253.h>
8#include <linux/slab.h>
9#include <linux/hpet.h>
10#include <linux/init.h>
11#include <linux/cpu.h>
12#include <linux/pm.h>
13#include <linux/io.h>
14
15#include <asm/cpufeature.h>
16#include <asm/irqdomain.h>
17#include <asm/fixmap.h>
18#include <asm/hpet.h>
19#include <asm/time.h>
20
21#define HPET_MASK CLOCKSOURCE_MASK(32)
22
23/* FSEC = 10^-15
24 NSEC = 10^-9 */
25#define FSEC_PER_NSEC 1000000L
26
27#define HPET_DEV_USED_BIT 2
28#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
29#define HPET_DEV_VALID 0x8
30#define HPET_DEV_FSB_CAP 0x1000
31#define HPET_DEV_PERI_CAP 0x2000
32
33#define HPET_MIN_CYCLES 128
34#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
35
36/*
37 * HPET address is set in acpi/boot.c, when an ACPI entry exists
38 */
39unsigned long hpet_address;
40u8 hpet_blockid; /* OS timer block num */
41bool hpet_msi_disable;
42
43#ifdef CONFIG_PCI_MSI
44static unsigned int hpet_num_timers;
45#endif
46static void __iomem *hpet_virt_address;
47
48struct hpet_dev {
49 struct clock_event_device evt;
50 unsigned int num;
51 int cpu;
52 unsigned int irq;
53 unsigned int flags;
54 char name[10];
55};
56
57static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
58{
59 return container_of(evtdev, struct hpet_dev, evt);
60}
61
62inline unsigned int hpet_readl(unsigned int a)
63{
64 return readl(hpet_virt_address + a);
65}
66
67static inline void hpet_writel(unsigned int d, unsigned int a)
68{
69 writel(d, hpet_virt_address + a);
70}
71
72#ifdef CONFIG_X86_64
73#include <asm/pgtable.h>
74#endif
75
76static inline void hpet_set_mapping(void)
77{
78 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
79}
80
81static inline void hpet_clear_mapping(void)
82{
83 iounmap(hpet_virt_address);
84 hpet_virt_address = NULL;
85}
86
87/*
88 * HPET command line enable / disable
89 */
90bool boot_hpet_disable;
91bool hpet_force_user;
92static bool hpet_verbose;
93
94static int __init hpet_setup(char *str)
95{
96 while (str) {
97 char *next = strchr(str, ',');
98
99 if (next)
100 *next++ = 0;
101 if (!strncmp("disable", str, 7))
102 boot_hpet_disable = true;
103 if (!strncmp("force", str, 5))
104 hpet_force_user = true;
105 if (!strncmp("verbose", str, 7))
106 hpet_verbose = true;
107 str = next;
108 }
109 return 1;
110}
111__setup("hpet=", hpet_setup);
112
113static int __init disable_hpet(char *str)
114{
115 boot_hpet_disable = true;
116 return 1;
117}
118__setup("nohpet", disable_hpet);
119
120static inline int is_hpet_capable(void)
121{
122 return !boot_hpet_disable && hpet_address;
123}
124
125/*
126 * HPET timer interrupt enable / disable
127 */
128static bool hpet_legacy_int_enabled;
129
130/**
131 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
132 */
133int is_hpet_enabled(void)
134{
135 return is_hpet_capable() && hpet_legacy_int_enabled;
136}
137EXPORT_SYMBOL_GPL(is_hpet_enabled);
138
139static void _hpet_print_config(const char *function, int line)
140{
141 u32 i, timers, l, h;
142 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
143 l = hpet_readl(HPET_ID);
144 h = hpet_readl(HPET_PERIOD);
145 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
146 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
147 l = hpet_readl(HPET_CFG);
148 h = hpet_readl(HPET_STATUS);
149 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
150 l = hpet_readl(HPET_COUNTER);
151 h = hpet_readl(HPET_COUNTER+4);
152 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
153
154 for (i = 0; i < timers; i++) {
155 l = hpet_readl(HPET_Tn_CFG(i));
156 h = hpet_readl(HPET_Tn_CFG(i)+4);
157 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
158 i, l, h);
159 l = hpet_readl(HPET_Tn_CMP(i));
160 h = hpet_readl(HPET_Tn_CMP(i)+4);
161 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
162 i, l, h);
163 l = hpet_readl(HPET_Tn_ROUTE(i));
164 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
165 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
166 i, l, h);
167 }
168}
169
170#define hpet_print_config() \
171do { \
172 if (hpet_verbose) \
173 _hpet_print_config(__func__, __LINE__); \
174} while (0)
175
176/*
177 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
178 * timer 0 and timer 1 in case of RTC emulation.
179 */
180#ifdef CONFIG_HPET
181
182static void hpet_reserve_msi_timers(struct hpet_data *hd);
183
184static void hpet_reserve_platform_timers(unsigned int id)
185{
186 struct hpet __iomem *hpet = hpet_virt_address;
187 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
188 unsigned int nrtimers, i;
189 struct hpet_data hd;
190
191 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
192
193 memset(&hd, 0, sizeof(hd));
194 hd.hd_phys_address = hpet_address;
195 hd.hd_address = hpet;
196 hd.hd_nirqs = nrtimers;
197 hpet_reserve_timer(&hd, 0);
198
199#ifdef CONFIG_HPET_EMULATE_RTC
200 hpet_reserve_timer(&hd, 1);
201#endif
202
203 /*
204 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
205 * is wrong for i8259!) not the output IRQ. Many BIOS writers
206 * don't bother configuring *any* comparator interrupts.
207 */
208 hd.hd_irq[0] = HPET_LEGACY_8254;
209 hd.hd_irq[1] = HPET_LEGACY_RTC;
210
211 for (i = 2; i < nrtimers; timer++, i++) {
212 hd.hd_irq[i] = (readl(&timer->hpet_config) &
213 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
214 }
215
216 hpet_reserve_msi_timers(&hd);
217
218 hpet_alloc(&hd);
219
220}
221#else
222static void hpet_reserve_platform_timers(unsigned int id) { }
223#endif
224
225/*
226 * Common hpet info
227 */
228static unsigned long hpet_freq;
229
230static struct clock_event_device hpet_clockevent;
231
232static void hpet_stop_counter(void)
233{
234 u32 cfg = hpet_readl(HPET_CFG);
235 cfg &= ~HPET_CFG_ENABLE;
236 hpet_writel(cfg, HPET_CFG);
237}
238
239static void hpet_reset_counter(void)
240{
241 hpet_writel(0, HPET_COUNTER);
242 hpet_writel(0, HPET_COUNTER + 4);
243}
244
245static void hpet_start_counter(void)
246{
247 unsigned int cfg = hpet_readl(HPET_CFG);
248 cfg |= HPET_CFG_ENABLE;
249 hpet_writel(cfg, HPET_CFG);
250}
251
252static void hpet_restart_counter(void)
253{
254 hpet_stop_counter();
255 hpet_reset_counter();
256 hpet_start_counter();
257}
258
259static void hpet_resume_device(void)
260{
261 force_hpet_resume();
262}
263
264static void hpet_resume_counter(struct clocksource *cs)
265{
266 hpet_resume_device();
267 hpet_restart_counter();
268}
269
270static void hpet_enable_legacy_int(void)
271{
272 unsigned int cfg = hpet_readl(HPET_CFG);
273
274 cfg |= HPET_CFG_LEGACY;
275 hpet_writel(cfg, HPET_CFG);
276 hpet_legacy_int_enabled = true;
277}
278
279static void hpet_legacy_clockevent_register(void)
280{
281 /* Start HPET legacy interrupts */
282 hpet_enable_legacy_int();
283
284 /*
285 * Start hpet with the boot cpu mask and make it
286 * global after the IO_APIC has been initialized.
287 */
288 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
289 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
290 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
291 global_clock_event = &hpet_clockevent;
292 printk(KERN_DEBUG "hpet clockevent registered\n");
293}
294
295static int hpet_set_periodic(struct clock_event_device *evt, int timer)
296{
297 unsigned int cfg, cmp, now;
298 uint64_t delta;
299
300 hpet_stop_counter();
301 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
302 delta >>= evt->shift;
303 now = hpet_readl(HPET_COUNTER);
304 cmp = now + (unsigned int)delta;
305 cfg = hpet_readl(HPET_Tn_CFG(timer));
306 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
307 HPET_TN_32BIT;
308 hpet_writel(cfg, HPET_Tn_CFG(timer));
309 hpet_writel(cmp, HPET_Tn_CMP(timer));
310 udelay(1);
311 /*
312 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
313 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
314 * bit is automatically cleared after the first write.
315 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
316 * Publication # 24674)
317 */
318 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
319 hpet_start_counter();
320 hpet_print_config();
321
322 return 0;
323}
324
325static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
326{
327 unsigned int cfg;
328
329 cfg = hpet_readl(HPET_Tn_CFG(timer));
330 cfg &= ~HPET_TN_PERIODIC;
331 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
332 hpet_writel(cfg, HPET_Tn_CFG(timer));
333
334 return 0;
335}
336
337static int hpet_shutdown(struct clock_event_device *evt, int timer)
338{
339 unsigned int cfg;
340
341 cfg = hpet_readl(HPET_Tn_CFG(timer));
342 cfg &= ~HPET_TN_ENABLE;
343 hpet_writel(cfg, HPET_Tn_CFG(timer));
344
345 return 0;
346}
347
348static int hpet_resume(struct clock_event_device *evt, int timer)
349{
350 if (!timer) {
351 hpet_enable_legacy_int();
352 } else {
353 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
354
355 irq_domain_deactivate_irq(irq_get_irq_data(hdev->irq));
356 irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
357 disable_irq(hdev->irq);
358 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
359 enable_irq(hdev->irq);
360 }
361 hpet_print_config();
362
363 return 0;
364}
365
366static int hpet_next_event(unsigned long delta,
367 struct clock_event_device *evt, int timer)
368{
369 u32 cnt;
370 s32 res;
371
372 cnt = hpet_readl(HPET_COUNTER);
373 cnt += (u32) delta;
374 hpet_writel(cnt, HPET_Tn_CMP(timer));
375
376 /*
377 * HPETs are a complete disaster. The compare register is
378 * based on a equal comparison and neither provides a less
379 * than or equal functionality (which would require to take
380 * the wraparound into account) nor a simple count down event
381 * mode. Further the write to the comparator register is
382 * delayed internally up to two HPET clock cycles in certain
383 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
384 * longer delays. We worked around that by reading back the
385 * compare register, but that required another workaround for
386 * ICH9,10 chips where the first readout after write can
387 * return the old stale value. We already had a minimum
388 * programming delta of 5us enforced, but a NMI or SMI hitting
389 * between the counter readout and the comparator write can
390 * move us behind that point easily. Now instead of reading
391 * the compare register back several times, we make the ETIME
392 * decision based on the following: Return ETIME if the
393 * counter value after the write is less than HPET_MIN_CYCLES
394 * away from the event or if the counter is already ahead of
395 * the event. The minimum programming delta for the generic
396 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
397 */
398 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
399
400 return res < HPET_MIN_CYCLES ? -ETIME : 0;
401}
402
403static int hpet_legacy_shutdown(struct clock_event_device *evt)
404{
405 return hpet_shutdown(evt, 0);
406}
407
408static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
409{
410 return hpet_set_oneshot(evt, 0);
411}
412
413static int hpet_legacy_set_periodic(struct clock_event_device *evt)
414{
415 return hpet_set_periodic(evt, 0);
416}
417
418static int hpet_legacy_resume(struct clock_event_device *evt)
419{
420 return hpet_resume(evt, 0);
421}
422
423static int hpet_legacy_next_event(unsigned long delta,
424 struct clock_event_device *evt)
425{
426 return hpet_next_event(delta, evt, 0);
427}
428
429/*
430 * The hpet clock event device
431 */
432static struct clock_event_device hpet_clockevent = {
433 .name = "hpet",
434 .features = CLOCK_EVT_FEAT_PERIODIC |
435 CLOCK_EVT_FEAT_ONESHOT,
436 .set_state_periodic = hpet_legacy_set_periodic,
437 .set_state_oneshot = hpet_legacy_set_oneshot,
438 .set_state_shutdown = hpet_legacy_shutdown,
439 .tick_resume = hpet_legacy_resume,
440 .set_next_event = hpet_legacy_next_event,
441 .irq = 0,
442 .rating = 50,
443};
444
445/*
446 * HPET MSI Support
447 */
448#ifdef CONFIG_PCI_MSI
449
450static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
451static struct hpet_dev *hpet_devs;
452static struct irq_domain *hpet_domain;
453
454void hpet_msi_unmask(struct irq_data *data)
455{
456 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
457 unsigned int cfg;
458
459 /* unmask it */
460 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
461 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
462 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
463}
464
465void hpet_msi_mask(struct irq_data *data)
466{
467 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
468 unsigned int cfg;
469
470 /* mask it */
471 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
472 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
473 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
474}
475
476void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
477{
478 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
479 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
480}
481
482void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
483{
484 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
485 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
486 msg->address_hi = 0;
487}
488
489static int hpet_msi_shutdown(struct clock_event_device *evt)
490{
491 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
492
493 return hpet_shutdown(evt, hdev->num);
494}
495
496static int hpet_msi_set_oneshot(struct clock_event_device *evt)
497{
498 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
499
500 return hpet_set_oneshot(evt, hdev->num);
501}
502
503static int hpet_msi_set_periodic(struct clock_event_device *evt)
504{
505 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
506
507 return hpet_set_periodic(evt, hdev->num);
508}
509
510static int hpet_msi_resume(struct clock_event_device *evt)
511{
512 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
513
514 return hpet_resume(evt, hdev->num);
515}
516
517static int hpet_msi_next_event(unsigned long delta,
518 struct clock_event_device *evt)
519{
520 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
521 return hpet_next_event(delta, evt, hdev->num);
522}
523
524static irqreturn_t hpet_interrupt_handler(int irq, void *data)
525{
526 struct hpet_dev *dev = (struct hpet_dev *)data;
527 struct clock_event_device *hevt = &dev->evt;
528
529 if (!hevt->event_handler) {
530 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
531 dev->num);
532 return IRQ_HANDLED;
533 }
534
535 hevt->event_handler(hevt);
536 return IRQ_HANDLED;
537}
538
539static int hpet_setup_irq(struct hpet_dev *dev)
540{
541
542 if (request_irq(dev->irq, hpet_interrupt_handler,
543 IRQF_TIMER | IRQF_NOBALANCING,
544 dev->name, dev))
545 return -1;
546
547 disable_irq(dev->irq);
548 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
549 enable_irq(dev->irq);
550
551 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
552 dev->name, dev->irq);
553
554 return 0;
555}
556
557/* This should be called in specific @cpu */
558static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
559{
560 struct clock_event_device *evt = &hdev->evt;
561
562 WARN_ON(cpu != smp_processor_id());
563 if (!(hdev->flags & HPET_DEV_VALID))
564 return;
565
566 hdev->cpu = cpu;
567 per_cpu(cpu_hpet_dev, cpu) = hdev;
568 evt->name = hdev->name;
569 hpet_setup_irq(hdev);
570 evt->irq = hdev->irq;
571
572 evt->rating = 110;
573 evt->features = CLOCK_EVT_FEAT_ONESHOT;
574 if (hdev->flags & HPET_DEV_PERI_CAP) {
575 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
576 evt->set_state_periodic = hpet_msi_set_periodic;
577 }
578
579 evt->set_state_shutdown = hpet_msi_shutdown;
580 evt->set_state_oneshot = hpet_msi_set_oneshot;
581 evt->tick_resume = hpet_msi_resume;
582 evt->set_next_event = hpet_msi_next_event;
583 evt->cpumask = cpumask_of(hdev->cpu);
584
585 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
586 0x7FFFFFFF);
587}
588
589#ifdef CONFIG_HPET
590/* Reserve at least one timer for userspace (/dev/hpet) */
591#define RESERVE_TIMERS 1
592#else
593#define RESERVE_TIMERS 0
594#endif
595
596static void hpet_msi_capability_lookup(unsigned int start_timer)
597{
598 unsigned int id;
599 unsigned int num_timers;
600 unsigned int num_timers_used = 0;
601 int i, irq;
602
603 if (hpet_msi_disable)
604 return;
605
606 if (boot_cpu_has(X86_FEATURE_ARAT))
607 return;
608 id = hpet_readl(HPET_ID);
609
610 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
611 num_timers++; /* Value read out starts from 0 */
612 hpet_print_config();
613
614 hpet_domain = hpet_create_irq_domain(hpet_blockid);
615 if (!hpet_domain)
616 return;
617
618 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
619 if (!hpet_devs)
620 return;
621
622 hpet_num_timers = num_timers;
623
624 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
625 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
626 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
627
628 /* Only consider HPET timer with MSI support */
629 if (!(cfg & HPET_TN_FSB_CAP))
630 continue;
631
632 hdev->flags = 0;
633 if (cfg & HPET_TN_PERIODIC_CAP)
634 hdev->flags |= HPET_DEV_PERI_CAP;
635 sprintf(hdev->name, "hpet%d", i);
636 hdev->num = i;
637
638 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
639 if (irq <= 0)
640 continue;
641
642 hdev->irq = irq;
643 hdev->flags |= HPET_DEV_FSB_CAP;
644 hdev->flags |= HPET_DEV_VALID;
645 num_timers_used++;
646 if (num_timers_used == num_possible_cpus())
647 break;
648 }
649
650 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
651 num_timers, num_timers_used);
652}
653
654#ifdef CONFIG_HPET
655static void hpet_reserve_msi_timers(struct hpet_data *hd)
656{
657 int i;
658
659 if (!hpet_devs)
660 return;
661
662 for (i = 0; i < hpet_num_timers; i++) {
663 struct hpet_dev *hdev = &hpet_devs[i];
664
665 if (!(hdev->flags & HPET_DEV_VALID))
666 continue;
667
668 hd->hd_irq[hdev->num] = hdev->irq;
669 hpet_reserve_timer(hd, hdev->num);
670 }
671}
672#endif
673
674static struct hpet_dev *hpet_get_unused_timer(void)
675{
676 int i;
677
678 if (!hpet_devs)
679 return NULL;
680
681 for (i = 0; i < hpet_num_timers; i++) {
682 struct hpet_dev *hdev = &hpet_devs[i];
683
684 if (!(hdev->flags & HPET_DEV_VALID))
685 continue;
686 if (test_and_set_bit(HPET_DEV_USED_BIT,
687 (unsigned long *)&hdev->flags))
688 continue;
689 return hdev;
690 }
691 return NULL;
692}
693
694struct hpet_work_struct {
695 struct delayed_work work;
696 struct completion complete;
697};
698
699static void hpet_work(struct work_struct *w)
700{
701 struct hpet_dev *hdev;
702 int cpu = smp_processor_id();
703 struct hpet_work_struct *hpet_work;
704
705 hpet_work = container_of(w, struct hpet_work_struct, work.work);
706
707 hdev = hpet_get_unused_timer();
708 if (hdev)
709 init_one_hpet_msi_clockevent(hdev, cpu);
710
711 complete(&hpet_work->complete);
712}
713
714static int hpet_cpuhp_online(unsigned int cpu)
715{
716 struct hpet_work_struct work;
717
718 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
719 init_completion(&work.complete);
720 /* FIXME: add schedule_work_on() */
721 schedule_delayed_work_on(cpu, &work.work, 0);
722 wait_for_completion(&work.complete);
723 destroy_delayed_work_on_stack(&work.work);
724 return 0;
725}
726
727static int hpet_cpuhp_dead(unsigned int cpu)
728{
729 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
730
731 if (!hdev)
732 return 0;
733 free_irq(hdev->irq, hdev);
734 hdev->flags &= ~HPET_DEV_USED;
735 per_cpu(cpu_hpet_dev, cpu) = NULL;
736 return 0;
737}
738#else
739
740static void hpet_msi_capability_lookup(unsigned int start_timer)
741{
742 return;
743}
744
745#ifdef CONFIG_HPET
746static void hpet_reserve_msi_timers(struct hpet_data *hd)
747{
748 return;
749}
750#endif
751
752#define hpet_cpuhp_online NULL
753#define hpet_cpuhp_dead NULL
754
755#endif
756
757/*
758 * Clock source related code
759 */
760#if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
761/*
762 * Reading the HPET counter is a very slow operation. If a large number of
763 * CPUs are trying to access the HPET counter simultaneously, it can cause
764 * massive delay and slow down system performance dramatically. This may
765 * happen when HPET is the default clock source instead of TSC. For a
766 * really large system with hundreds of CPUs, the slowdown may be so
767 * severe that it may actually crash the system because of a NMI watchdog
768 * soft lockup, for example.
769 *
770 * If multiple CPUs are trying to access the HPET counter at the same time,
771 * we don't actually need to read the counter multiple times. Instead, the
772 * other CPUs can use the counter value read by the first CPU in the group.
773 *
774 * This special feature is only enabled on x86-64 systems. It is unlikely
775 * that 32-bit x86 systems will have enough CPUs to require this feature
776 * with its associated locking overhead. And we also need 64-bit atomic
777 * read.
778 *
779 * The lock and the hpet value are stored together and can be read in a
780 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
781 * is 32 bits in size.
782 */
783union hpet_lock {
784 struct {
785 arch_spinlock_t lock;
786 u32 value;
787 };
788 u64 lockval;
789};
790
791static union hpet_lock hpet __cacheline_aligned = {
792 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
793};
794
795static u64 read_hpet(struct clocksource *cs)
796{
797 unsigned long flags;
798 union hpet_lock old, new;
799
800 BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
801
802 /*
803 * Read HPET directly if in NMI.
804 */
805 if (in_nmi())
806 return (u64)hpet_readl(HPET_COUNTER);
807
808 /*
809 * Read the current state of the lock and HPET value atomically.
810 */
811 old.lockval = READ_ONCE(hpet.lockval);
812
813 if (arch_spin_is_locked(&old.lock))
814 goto contended;
815
816 local_irq_save(flags);
817 if (arch_spin_trylock(&hpet.lock)) {
818 new.value = hpet_readl(HPET_COUNTER);
819 /*
820 * Use WRITE_ONCE() to prevent store tearing.
821 */
822 WRITE_ONCE(hpet.value, new.value);
823 arch_spin_unlock(&hpet.lock);
824 local_irq_restore(flags);
825 return (u64)new.value;
826 }
827 local_irq_restore(flags);
828
829contended:
830 /*
831 * Contended case
832 * --------------
833 * Wait until the HPET value change or the lock is free to indicate
834 * its value is up-to-date.
835 *
836 * It is possible that old.value has already contained the latest
837 * HPET value while the lock holder was in the process of releasing
838 * the lock. Checking for lock state change will enable us to return
839 * the value immediately instead of waiting for the next HPET reader
840 * to come along.
841 */
842 do {
843 cpu_relax();
844 new.lockval = READ_ONCE(hpet.lockval);
845 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
846
847 return (u64)new.value;
848}
849#else
850/*
851 * For UP or 32-bit.
852 */
853static u64 read_hpet(struct clocksource *cs)
854{
855 return (u64)hpet_readl(HPET_COUNTER);
856}
857#endif
858
859static struct clocksource clocksource_hpet = {
860 .name = "hpet",
861 .rating = 250,
862 .read = read_hpet,
863 .mask = HPET_MASK,
864 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
865 .resume = hpet_resume_counter,
866};
867
868static int hpet_clocksource_register(void)
869{
870 u64 start, now;
871 u64 t1;
872
873 /* Start the counter */
874 hpet_restart_counter();
875
876 /* Verify whether hpet counter works */
877 t1 = hpet_readl(HPET_COUNTER);
878 start = rdtsc();
879
880 /*
881 * We don't know the TSC frequency yet, but waiting for
882 * 200000 TSC cycles is safe:
883 * 4 GHz == 50us
884 * 1 GHz == 200us
885 */
886 do {
887 rep_nop();
888 now = rdtsc();
889 } while ((now - start) < 200000UL);
890
891 if (t1 == hpet_readl(HPET_COUNTER)) {
892 printk(KERN_WARNING
893 "HPET counter not counting. HPET disabled\n");
894 return -ENODEV;
895 }
896
897 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
898 return 0;
899}
900
901static u32 *hpet_boot_cfg;
902
903/**
904 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
905 */
906int __init hpet_enable(void)
907{
908 u32 hpet_period, cfg, id;
909 u64 freq;
910 unsigned int i, last;
911
912 if (!is_hpet_capable())
913 return 0;
914
915 hpet_set_mapping();
916
917 /*
918 * Read the period and check for a sane value:
919 */
920 hpet_period = hpet_readl(HPET_PERIOD);
921
922 /*
923 * AMD SB700 based systems with spread spectrum enabled use a
924 * SMM based HPET emulation to provide proper frequency
925 * setting. The SMM code is initialized with the first HPET
926 * register access and takes some time to complete. During
927 * this time the config register reads 0xffffffff. We check
928 * for max. 1000 loops whether the config register reads a non
929 * 0xffffffff value to make sure that HPET is up and running
930 * before we go further. A counting loop is safe, as the HPET
931 * access takes thousands of CPU cycles. On non SB700 based
932 * machines this check is only done once and has no side
933 * effects.
934 */
935 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
936 if (i == 1000) {
937 printk(KERN_WARNING
938 "HPET config register value = 0xFFFFFFFF. "
939 "Disabling HPET\n");
940 goto out_nohpet;
941 }
942 }
943
944 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
945 goto out_nohpet;
946
947 /*
948 * The period is a femto seconds value. Convert it to a
949 * frequency.
950 */
951 freq = FSEC_PER_SEC;
952 do_div(freq, hpet_period);
953 hpet_freq = freq;
954
955 /*
956 * Read the HPET ID register to retrieve the IRQ routing
957 * information and the number of channels
958 */
959 id = hpet_readl(HPET_ID);
960 hpet_print_config();
961
962 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
963
964#ifdef CONFIG_HPET_EMULATE_RTC
965 /*
966 * The legacy routing mode needs at least two channels, tick timer
967 * and the rtc emulation channel.
968 */
969 if (!last)
970 goto out_nohpet;
971#endif
972
973 cfg = hpet_readl(HPET_CFG);
974 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
975 GFP_KERNEL);
976 if (hpet_boot_cfg)
977 *hpet_boot_cfg = cfg;
978 else
979 pr_warn("HPET initial state will not be saved\n");
980 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
981 hpet_writel(cfg, HPET_CFG);
982 if (cfg)
983 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
984 cfg);
985
986 for (i = 0; i <= last; ++i) {
987 cfg = hpet_readl(HPET_Tn_CFG(i));
988 if (hpet_boot_cfg)
989 hpet_boot_cfg[i + 1] = cfg;
990 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
991 hpet_writel(cfg, HPET_Tn_CFG(i));
992 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
993 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
994 | HPET_TN_FSB | HPET_TN_FSB_CAP);
995 if (cfg)
996 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
997 cfg, i);
998 }
999 hpet_print_config();
1000
1001 if (hpet_clocksource_register())
1002 goto out_nohpet;
1003
1004 if (id & HPET_ID_LEGSUP) {
1005 hpet_legacy_clockevent_register();
1006 return 1;
1007 }
1008 return 0;
1009
1010out_nohpet:
1011 hpet_clear_mapping();
1012 hpet_address = 0;
1013 return 0;
1014}
1015
1016/*
1017 * Needs to be late, as the reserve_timer code calls kalloc !
1018 *
1019 * Not a problem on i386 as hpet_enable is called from late_time_init,
1020 * but on x86_64 it is necessary !
1021 */
1022static __init int hpet_late_init(void)
1023{
1024 int ret;
1025
1026 if (boot_hpet_disable)
1027 return -ENODEV;
1028
1029 if (!hpet_address) {
1030 if (!force_hpet_address)
1031 return -ENODEV;
1032
1033 hpet_address = force_hpet_address;
1034 hpet_enable();
1035 }
1036
1037 if (!hpet_virt_address)
1038 return -ENODEV;
1039
1040 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
1041 hpet_msi_capability_lookup(2);
1042 else
1043 hpet_msi_capability_lookup(0);
1044
1045 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
1046 hpet_print_config();
1047
1048 if (hpet_msi_disable)
1049 return 0;
1050
1051 if (boot_cpu_has(X86_FEATURE_ARAT))
1052 return 0;
1053
1054 /* This notifier should be called after workqueue is ready */
1055 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online",
1056 hpet_cpuhp_online, NULL);
1057 if (ret)
1058 return ret;
1059 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL,
1060 hpet_cpuhp_dead);
1061 if (ret)
1062 goto err_cpuhp;
1063 return 0;
1064
1065err_cpuhp:
1066 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
1067 return ret;
1068}
1069fs_initcall(hpet_late_init);
1070
1071void hpet_disable(void)
1072{
1073 if (is_hpet_capable() && hpet_virt_address) {
1074 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
1075
1076 if (hpet_boot_cfg)
1077 cfg = *hpet_boot_cfg;
1078 else if (hpet_legacy_int_enabled) {
1079 cfg &= ~HPET_CFG_LEGACY;
1080 hpet_legacy_int_enabled = false;
1081 }
1082 cfg &= ~HPET_CFG_ENABLE;
1083 hpet_writel(cfg, HPET_CFG);
1084
1085 if (!hpet_boot_cfg)
1086 return;
1087
1088 id = hpet_readl(HPET_ID);
1089 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
1090
1091 for (id = 0; id <= last; ++id)
1092 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1093
1094 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1095 hpet_writel(*hpet_boot_cfg, HPET_CFG);
1096 }
1097}
1098
1099#ifdef CONFIG_HPET_EMULATE_RTC
1100
1101/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1102 * is enabled, we support RTC interrupt functionality in software.
1103 * RTC has 3 kinds of interrupts:
1104 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1105 * is updated
1106 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1107 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1108 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1109 * (1) and (2) above are implemented using polling at a frequency of
1110 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1111 * overhead. (DEFAULT_RTC_INT_FREQ)
1112 * For (3), we use interrupts at 64Hz or user specified periodic
1113 * frequency, whichever is higher.
1114 */
1115#include <linux/mc146818rtc.h>
1116#include <linux/rtc.h>
1117
1118#define DEFAULT_RTC_INT_FREQ 64
1119#define DEFAULT_RTC_SHIFT 6
1120#define RTC_NUM_INTS 1
1121
1122static unsigned long hpet_rtc_flags;
1123static int hpet_prev_update_sec;
1124static struct rtc_time hpet_alarm_time;
1125static unsigned long hpet_pie_count;
1126static u32 hpet_t1_cmp;
1127static u32 hpet_default_delta;
1128static u32 hpet_pie_delta;
1129static unsigned long hpet_pie_limit;
1130
1131static rtc_irq_handler irq_handler;
1132
1133/*
1134 * Check that the hpet counter c1 is ahead of the c2
1135 */
1136static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1137{
1138 return (s32)(c2 - c1) < 0;
1139}
1140
1141/*
1142 * Registers a IRQ handler.
1143 */
1144int hpet_register_irq_handler(rtc_irq_handler handler)
1145{
1146 if (!is_hpet_enabled())
1147 return -ENODEV;
1148 if (irq_handler)
1149 return -EBUSY;
1150
1151 irq_handler = handler;
1152
1153 return 0;
1154}
1155EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1156
1157/*
1158 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1159 * and does cleanup.
1160 */
1161void hpet_unregister_irq_handler(rtc_irq_handler handler)
1162{
1163 if (!is_hpet_enabled())
1164 return;
1165
1166 irq_handler = NULL;
1167 hpet_rtc_flags = 0;
1168}
1169EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1170
1171/*
1172 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1173 * is not supported by all HPET implementations for timer 1.
1174 *
1175 * hpet_rtc_timer_init() is called when the rtc is initialized.
1176 */
1177int hpet_rtc_timer_init(void)
1178{
1179 unsigned int cfg, cnt, delta;
1180 unsigned long flags;
1181
1182 if (!is_hpet_enabled())
1183 return 0;
1184
1185 if (!hpet_default_delta) {
1186 uint64_t clc;
1187
1188 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1189 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1190 hpet_default_delta = clc;
1191 }
1192
1193 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1194 delta = hpet_default_delta;
1195 else
1196 delta = hpet_pie_delta;
1197
1198 local_irq_save(flags);
1199
1200 cnt = delta + hpet_readl(HPET_COUNTER);
1201 hpet_writel(cnt, HPET_T1_CMP);
1202 hpet_t1_cmp = cnt;
1203
1204 cfg = hpet_readl(HPET_T1_CFG);
1205 cfg &= ~HPET_TN_PERIODIC;
1206 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1207 hpet_writel(cfg, HPET_T1_CFG);
1208
1209 local_irq_restore(flags);
1210
1211 return 1;
1212}
1213EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1214
1215static void hpet_disable_rtc_channel(void)
1216{
1217 u32 cfg = hpet_readl(HPET_T1_CFG);
1218 cfg &= ~HPET_TN_ENABLE;
1219 hpet_writel(cfg, HPET_T1_CFG);
1220}
1221
1222/*
1223 * The functions below are called from rtc driver.
1224 * Return 0 if HPET is not being used.
1225 * Otherwise do the necessary changes and return 1.
1226 */
1227int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1228{
1229 if (!is_hpet_enabled())
1230 return 0;
1231
1232 hpet_rtc_flags &= ~bit_mask;
1233 if (unlikely(!hpet_rtc_flags))
1234 hpet_disable_rtc_channel();
1235
1236 return 1;
1237}
1238EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1239
1240int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1241{
1242 unsigned long oldbits = hpet_rtc_flags;
1243
1244 if (!is_hpet_enabled())
1245 return 0;
1246
1247 hpet_rtc_flags |= bit_mask;
1248
1249 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1250 hpet_prev_update_sec = -1;
1251
1252 if (!oldbits)
1253 hpet_rtc_timer_init();
1254
1255 return 1;
1256}
1257EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1258
1259int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1260 unsigned char sec)
1261{
1262 if (!is_hpet_enabled())
1263 return 0;
1264
1265 hpet_alarm_time.tm_hour = hrs;
1266 hpet_alarm_time.tm_min = min;
1267 hpet_alarm_time.tm_sec = sec;
1268
1269 return 1;
1270}
1271EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1272
1273int hpet_set_periodic_freq(unsigned long freq)
1274{
1275 uint64_t clc;
1276
1277 if (!is_hpet_enabled())
1278 return 0;
1279
1280 if (freq <= DEFAULT_RTC_INT_FREQ)
1281 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1282 else {
1283 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1284 do_div(clc, freq);
1285 clc >>= hpet_clockevent.shift;
1286 hpet_pie_delta = clc;
1287 hpet_pie_limit = 0;
1288 }
1289 return 1;
1290}
1291EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1292
1293int hpet_rtc_dropped_irq(void)
1294{
1295 return is_hpet_enabled();
1296}
1297EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1298
1299static void hpet_rtc_timer_reinit(void)
1300{
1301 unsigned int delta;
1302 int lost_ints = -1;
1303
1304 if (unlikely(!hpet_rtc_flags))
1305 hpet_disable_rtc_channel();
1306
1307 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1308 delta = hpet_default_delta;
1309 else
1310 delta = hpet_pie_delta;
1311
1312 /*
1313 * Increment the comparator value until we are ahead of the
1314 * current count.
1315 */
1316 do {
1317 hpet_t1_cmp += delta;
1318 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1319 lost_ints++;
1320 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1321
1322 if (lost_ints) {
1323 if (hpet_rtc_flags & RTC_PIE)
1324 hpet_pie_count += lost_ints;
1325 if (printk_ratelimit())
1326 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1327 lost_ints);
1328 }
1329}
1330
1331irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1332{
1333 struct rtc_time curr_time;
1334 unsigned long rtc_int_flag = 0;
1335
1336 hpet_rtc_timer_reinit();
1337 memset(&curr_time, 0, sizeof(struct rtc_time));
1338
1339 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1340 mc146818_get_time(&curr_time);
1341
1342 if (hpet_rtc_flags & RTC_UIE &&
1343 curr_time.tm_sec != hpet_prev_update_sec) {
1344 if (hpet_prev_update_sec >= 0)
1345 rtc_int_flag = RTC_UF;
1346 hpet_prev_update_sec = curr_time.tm_sec;
1347 }
1348
1349 if (hpet_rtc_flags & RTC_PIE &&
1350 ++hpet_pie_count >= hpet_pie_limit) {
1351 rtc_int_flag |= RTC_PF;
1352 hpet_pie_count = 0;
1353 }
1354
1355 if (hpet_rtc_flags & RTC_AIE &&
1356 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1357 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1358 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1359 rtc_int_flag |= RTC_AF;
1360
1361 if (rtc_int_flag) {
1362 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1363 if (irq_handler)
1364 irq_handler(rtc_int_flag, dev_id);
1365 }
1366 return IRQ_HANDLED;
1367}
1368EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1369#endif
1#include <linux/clocksource.h>
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/export.h>
5#include <linux/delay.h>
6#include <linux/errno.h>
7#include <linux/i8253.h>
8#include <linux/slab.h>
9#include <linux/hpet.h>
10#include <linux/init.h>
11#include <linux/cpu.h>
12#include <linux/pm.h>
13#include <linux/io.h>
14
15#include <asm/cpufeature.h>
16#include <asm/irqdomain.h>
17#include <asm/fixmap.h>
18#include <asm/hpet.h>
19#include <asm/time.h>
20
21#define HPET_MASK CLOCKSOURCE_MASK(32)
22
23/* FSEC = 10^-15
24 NSEC = 10^-9 */
25#define FSEC_PER_NSEC 1000000L
26
27#define HPET_DEV_USED_BIT 2
28#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
29#define HPET_DEV_VALID 0x8
30#define HPET_DEV_FSB_CAP 0x1000
31#define HPET_DEV_PERI_CAP 0x2000
32
33#define HPET_MIN_CYCLES 128
34#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
35
36/*
37 * HPET address is set in acpi/boot.c, when an ACPI entry exists
38 */
39unsigned long hpet_address;
40u8 hpet_blockid; /* OS timer block num */
41bool hpet_msi_disable;
42
43#ifdef CONFIG_PCI_MSI
44static unsigned int hpet_num_timers;
45#endif
46static void __iomem *hpet_virt_address;
47
48struct hpet_dev {
49 struct clock_event_device evt;
50 unsigned int num;
51 int cpu;
52 unsigned int irq;
53 unsigned int flags;
54 char name[10];
55};
56
57inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
58{
59 return container_of(evtdev, struct hpet_dev, evt);
60}
61
62inline unsigned int hpet_readl(unsigned int a)
63{
64 return readl(hpet_virt_address + a);
65}
66
67static inline void hpet_writel(unsigned int d, unsigned int a)
68{
69 writel(d, hpet_virt_address + a);
70}
71
72#ifdef CONFIG_X86_64
73#include <asm/pgtable.h>
74#endif
75
76static inline void hpet_set_mapping(void)
77{
78 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
79}
80
81static inline void hpet_clear_mapping(void)
82{
83 iounmap(hpet_virt_address);
84 hpet_virt_address = NULL;
85}
86
87/*
88 * HPET command line enable / disable
89 */
90bool boot_hpet_disable;
91bool hpet_force_user;
92static bool hpet_verbose;
93
94static int __init hpet_setup(char *str)
95{
96 while (str) {
97 char *next = strchr(str, ',');
98
99 if (next)
100 *next++ = 0;
101 if (!strncmp("disable", str, 7))
102 boot_hpet_disable = true;
103 if (!strncmp("force", str, 5))
104 hpet_force_user = true;
105 if (!strncmp("verbose", str, 7))
106 hpet_verbose = true;
107 str = next;
108 }
109 return 1;
110}
111__setup("hpet=", hpet_setup);
112
113static int __init disable_hpet(char *str)
114{
115 boot_hpet_disable = true;
116 return 1;
117}
118__setup("nohpet", disable_hpet);
119
120static inline int is_hpet_capable(void)
121{
122 return !boot_hpet_disable && hpet_address;
123}
124
125/*
126 * HPET timer interrupt enable / disable
127 */
128static bool hpet_legacy_int_enabled;
129
130/**
131 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
132 */
133int is_hpet_enabled(void)
134{
135 return is_hpet_capable() && hpet_legacy_int_enabled;
136}
137EXPORT_SYMBOL_GPL(is_hpet_enabled);
138
139static void _hpet_print_config(const char *function, int line)
140{
141 u32 i, timers, l, h;
142 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
143 l = hpet_readl(HPET_ID);
144 h = hpet_readl(HPET_PERIOD);
145 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
146 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
147 l = hpet_readl(HPET_CFG);
148 h = hpet_readl(HPET_STATUS);
149 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
150 l = hpet_readl(HPET_COUNTER);
151 h = hpet_readl(HPET_COUNTER+4);
152 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
153
154 for (i = 0; i < timers; i++) {
155 l = hpet_readl(HPET_Tn_CFG(i));
156 h = hpet_readl(HPET_Tn_CFG(i)+4);
157 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
158 i, l, h);
159 l = hpet_readl(HPET_Tn_CMP(i));
160 h = hpet_readl(HPET_Tn_CMP(i)+4);
161 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
162 i, l, h);
163 l = hpet_readl(HPET_Tn_ROUTE(i));
164 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
165 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
166 i, l, h);
167 }
168}
169
170#define hpet_print_config() \
171do { \
172 if (hpet_verbose) \
173 _hpet_print_config(__func__, __LINE__); \
174} while (0)
175
176/*
177 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
178 * timer 0 and timer 1 in case of RTC emulation.
179 */
180#ifdef CONFIG_HPET
181
182static void hpet_reserve_msi_timers(struct hpet_data *hd);
183
184static void hpet_reserve_platform_timers(unsigned int id)
185{
186 struct hpet __iomem *hpet = hpet_virt_address;
187 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
188 unsigned int nrtimers, i;
189 struct hpet_data hd;
190
191 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
192
193 memset(&hd, 0, sizeof(hd));
194 hd.hd_phys_address = hpet_address;
195 hd.hd_address = hpet;
196 hd.hd_nirqs = nrtimers;
197 hpet_reserve_timer(&hd, 0);
198
199#ifdef CONFIG_HPET_EMULATE_RTC
200 hpet_reserve_timer(&hd, 1);
201#endif
202
203 /*
204 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
205 * is wrong for i8259!) not the output IRQ. Many BIOS writers
206 * don't bother configuring *any* comparator interrupts.
207 */
208 hd.hd_irq[0] = HPET_LEGACY_8254;
209 hd.hd_irq[1] = HPET_LEGACY_RTC;
210
211 for (i = 2; i < nrtimers; timer++, i++) {
212 hd.hd_irq[i] = (readl(&timer->hpet_config) &
213 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
214 }
215
216 hpet_reserve_msi_timers(&hd);
217
218 hpet_alloc(&hd);
219
220}
221#else
222static void hpet_reserve_platform_timers(unsigned int id) { }
223#endif
224
225/*
226 * Common hpet info
227 */
228static unsigned long hpet_freq;
229
230static struct clock_event_device hpet_clockevent;
231
232static void hpet_stop_counter(void)
233{
234 u32 cfg = hpet_readl(HPET_CFG);
235 cfg &= ~HPET_CFG_ENABLE;
236 hpet_writel(cfg, HPET_CFG);
237}
238
239static void hpet_reset_counter(void)
240{
241 hpet_writel(0, HPET_COUNTER);
242 hpet_writel(0, HPET_COUNTER + 4);
243}
244
245static void hpet_start_counter(void)
246{
247 unsigned int cfg = hpet_readl(HPET_CFG);
248 cfg |= HPET_CFG_ENABLE;
249 hpet_writel(cfg, HPET_CFG);
250}
251
252static void hpet_restart_counter(void)
253{
254 hpet_stop_counter();
255 hpet_reset_counter();
256 hpet_start_counter();
257}
258
259static void hpet_resume_device(void)
260{
261 force_hpet_resume();
262}
263
264static void hpet_resume_counter(struct clocksource *cs)
265{
266 hpet_resume_device();
267 hpet_restart_counter();
268}
269
270static void hpet_enable_legacy_int(void)
271{
272 unsigned int cfg = hpet_readl(HPET_CFG);
273
274 cfg |= HPET_CFG_LEGACY;
275 hpet_writel(cfg, HPET_CFG);
276 hpet_legacy_int_enabled = true;
277}
278
279static void hpet_legacy_clockevent_register(void)
280{
281 /* Start HPET legacy interrupts */
282 hpet_enable_legacy_int();
283
284 /*
285 * Start hpet with the boot cpu mask and make it
286 * global after the IO_APIC has been initialized.
287 */
288 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
289 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
290 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
291 global_clock_event = &hpet_clockevent;
292 printk(KERN_DEBUG "hpet clockevent registered\n");
293}
294
295static int hpet_set_periodic(struct clock_event_device *evt, int timer)
296{
297 unsigned int cfg, cmp, now;
298 uint64_t delta;
299
300 hpet_stop_counter();
301 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
302 delta >>= evt->shift;
303 now = hpet_readl(HPET_COUNTER);
304 cmp = now + (unsigned int)delta;
305 cfg = hpet_readl(HPET_Tn_CFG(timer));
306 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
307 HPET_TN_32BIT;
308 hpet_writel(cfg, HPET_Tn_CFG(timer));
309 hpet_writel(cmp, HPET_Tn_CMP(timer));
310 udelay(1);
311 /*
312 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
313 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
314 * bit is automatically cleared after the first write.
315 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
316 * Publication # 24674)
317 */
318 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
319 hpet_start_counter();
320 hpet_print_config();
321
322 return 0;
323}
324
325static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
326{
327 unsigned int cfg;
328
329 cfg = hpet_readl(HPET_Tn_CFG(timer));
330 cfg &= ~HPET_TN_PERIODIC;
331 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
332 hpet_writel(cfg, HPET_Tn_CFG(timer));
333
334 return 0;
335}
336
337static int hpet_shutdown(struct clock_event_device *evt, int timer)
338{
339 unsigned int cfg;
340
341 cfg = hpet_readl(HPET_Tn_CFG(timer));
342 cfg &= ~HPET_TN_ENABLE;
343 hpet_writel(cfg, HPET_Tn_CFG(timer));
344
345 return 0;
346}
347
348static int hpet_resume(struct clock_event_device *evt, int timer)
349{
350 if (!timer) {
351 hpet_enable_legacy_int();
352 } else {
353 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
354
355 irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
356 disable_irq(hdev->irq);
357 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
358 enable_irq(hdev->irq);
359 }
360 hpet_print_config();
361
362 return 0;
363}
364
365static int hpet_next_event(unsigned long delta,
366 struct clock_event_device *evt, int timer)
367{
368 u32 cnt;
369 s32 res;
370
371 cnt = hpet_readl(HPET_COUNTER);
372 cnt += (u32) delta;
373 hpet_writel(cnt, HPET_Tn_CMP(timer));
374
375 /*
376 * HPETs are a complete disaster. The compare register is
377 * based on a equal comparison and neither provides a less
378 * than or equal functionality (which would require to take
379 * the wraparound into account) nor a simple count down event
380 * mode. Further the write to the comparator register is
381 * delayed internally up to two HPET clock cycles in certain
382 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
383 * longer delays. We worked around that by reading back the
384 * compare register, but that required another workaround for
385 * ICH9,10 chips where the first readout after write can
386 * return the old stale value. We already had a minimum
387 * programming delta of 5us enforced, but a NMI or SMI hitting
388 * between the counter readout and the comparator write can
389 * move us behind that point easily. Now instead of reading
390 * the compare register back several times, we make the ETIME
391 * decision based on the following: Return ETIME if the
392 * counter value after the write is less than HPET_MIN_CYCLES
393 * away from the event or if the counter is already ahead of
394 * the event. The minimum programming delta for the generic
395 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
396 */
397 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
398
399 return res < HPET_MIN_CYCLES ? -ETIME : 0;
400}
401
402static int hpet_legacy_shutdown(struct clock_event_device *evt)
403{
404 return hpet_shutdown(evt, 0);
405}
406
407static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
408{
409 return hpet_set_oneshot(evt, 0);
410}
411
412static int hpet_legacy_set_periodic(struct clock_event_device *evt)
413{
414 return hpet_set_periodic(evt, 0);
415}
416
417static int hpet_legacy_resume(struct clock_event_device *evt)
418{
419 return hpet_resume(evt, 0);
420}
421
422static int hpet_legacy_next_event(unsigned long delta,
423 struct clock_event_device *evt)
424{
425 return hpet_next_event(delta, evt, 0);
426}
427
428/*
429 * The hpet clock event device
430 */
431static struct clock_event_device hpet_clockevent = {
432 .name = "hpet",
433 .features = CLOCK_EVT_FEAT_PERIODIC |
434 CLOCK_EVT_FEAT_ONESHOT,
435 .set_state_periodic = hpet_legacy_set_periodic,
436 .set_state_oneshot = hpet_legacy_set_oneshot,
437 .set_state_shutdown = hpet_legacy_shutdown,
438 .tick_resume = hpet_legacy_resume,
439 .set_next_event = hpet_legacy_next_event,
440 .irq = 0,
441 .rating = 50,
442};
443
444/*
445 * HPET MSI Support
446 */
447#ifdef CONFIG_PCI_MSI
448
449static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
450static struct hpet_dev *hpet_devs;
451static struct irq_domain *hpet_domain;
452
453void hpet_msi_unmask(struct irq_data *data)
454{
455 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
456 unsigned int cfg;
457
458 /* unmask it */
459 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
460 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
461 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
462}
463
464void hpet_msi_mask(struct irq_data *data)
465{
466 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
467 unsigned int cfg;
468
469 /* mask it */
470 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
471 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
472 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
473}
474
475void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
476{
477 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
478 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
479}
480
481void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
482{
483 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
484 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
485 msg->address_hi = 0;
486}
487
488static int hpet_msi_shutdown(struct clock_event_device *evt)
489{
490 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
491
492 return hpet_shutdown(evt, hdev->num);
493}
494
495static int hpet_msi_set_oneshot(struct clock_event_device *evt)
496{
497 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
498
499 return hpet_set_oneshot(evt, hdev->num);
500}
501
502static int hpet_msi_set_periodic(struct clock_event_device *evt)
503{
504 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
505
506 return hpet_set_periodic(evt, hdev->num);
507}
508
509static int hpet_msi_resume(struct clock_event_device *evt)
510{
511 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
512
513 return hpet_resume(evt, hdev->num);
514}
515
516static int hpet_msi_next_event(unsigned long delta,
517 struct clock_event_device *evt)
518{
519 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
520 return hpet_next_event(delta, evt, hdev->num);
521}
522
523static irqreturn_t hpet_interrupt_handler(int irq, void *data)
524{
525 struct hpet_dev *dev = (struct hpet_dev *)data;
526 struct clock_event_device *hevt = &dev->evt;
527
528 if (!hevt->event_handler) {
529 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
530 dev->num);
531 return IRQ_HANDLED;
532 }
533
534 hevt->event_handler(hevt);
535 return IRQ_HANDLED;
536}
537
538static int hpet_setup_irq(struct hpet_dev *dev)
539{
540
541 if (request_irq(dev->irq, hpet_interrupt_handler,
542 IRQF_TIMER | IRQF_NOBALANCING,
543 dev->name, dev))
544 return -1;
545
546 disable_irq(dev->irq);
547 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
548 enable_irq(dev->irq);
549
550 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
551 dev->name, dev->irq);
552
553 return 0;
554}
555
556/* This should be called in specific @cpu */
557static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
558{
559 struct clock_event_device *evt = &hdev->evt;
560
561 WARN_ON(cpu != smp_processor_id());
562 if (!(hdev->flags & HPET_DEV_VALID))
563 return;
564
565 hdev->cpu = cpu;
566 per_cpu(cpu_hpet_dev, cpu) = hdev;
567 evt->name = hdev->name;
568 hpet_setup_irq(hdev);
569 evt->irq = hdev->irq;
570
571 evt->rating = 110;
572 evt->features = CLOCK_EVT_FEAT_ONESHOT;
573 if (hdev->flags & HPET_DEV_PERI_CAP) {
574 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
575 evt->set_state_periodic = hpet_msi_set_periodic;
576 }
577
578 evt->set_state_shutdown = hpet_msi_shutdown;
579 evt->set_state_oneshot = hpet_msi_set_oneshot;
580 evt->tick_resume = hpet_msi_resume;
581 evt->set_next_event = hpet_msi_next_event;
582 evt->cpumask = cpumask_of(hdev->cpu);
583
584 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
585 0x7FFFFFFF);
586}
587
588#ifdef CONFIG_HPET
589/* Reserve at least one timer for userspace (/dev/hpet) */
590#define RESERVE_TIMERS 1
591#else
592#define RESERVE_TIMERS 0
593#endif
594
595static void hpet_msi_capability_lookup(unsigned int start_timer)
596{
597 unsigned int id;
598 unsigned int num_timers;
599 unsigned int num_timers_used = 0;
600 int i, irq;
601
602 if (hpet_msi_disable)
603 return;
604
605 if (boot_cpu_has(X86_FEATURE_ARAT))
606 return;
607 id = hpet_readl(HPET_ID);
608
609 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
610 num_timers++; /* Value read out starts from 0 */
611 hpet_print_config();
612
613 hpet_domain = hpet_create_irq_domain(hpet_blockid);
614 if (!hpet_domain)
615 return;
616
617 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
618 if (!hpet_devs)
619 return;
620
621 hpet_num_timers = num_timers;
622
623 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
624 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
625 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
626
627 /* Only consider HPET timer with MSI support */
628 if (!(cfg & HPET_TN_FSB_CAP))
629 continue;
630
631 hdev->flags = 0;
632 if (cfg & HPET_TN_PERIODIC_CAP)
633 hdev->flags |= HPET_DEV_PERI_CAP;
634 sprintf(hdev->name, "hpet%d", i);
635 hdev->num = i;
636
637 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
638 if (irq <= 0)
639 continue;
640
641 hdev->irq = irq;
642 hdev->flags |= HPET_DEV_FSB_CAP;
643 hdev->flags |= HPET_DEV_VALID;
644 num_timers_used++;
645 if (num_timers_used == num_possible_cpus())
646 break;
647 }
648
649 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
650 num_timers, num_timers_used);
651}
652
653#ifdef CONFIG_HPET
654static void hpet_reserve_msi_timers(struct hpet_data *hd)
655{
656 int i;
657
658 if (!hpet_devs)
659 return;
660
661 for (i = 0; i < hpet_num_timers; i++) {
662 struct hpet_dev *hdev = &hpet_devs[i];
663
664 if (!(hdev->flags & HPET_DEV_VALID))
665 continue;
666
667 hd->hd_irq[hdev->num] = hdev->irq;
668 hpet_reserve_timer(hd, hdev->num);
669 }
670}
671#endif
672
673static struct hpet_dev *hpet_get_unused_timer(void)
674{
675 int i;
676
677 if (!hpet_devs)
678 return NULL;
679
680 for (i = 0; i < hpet_num_timers; i++) {
681 struct hpet_dev *hdev = &hpet_devs[i];
682
683 if (!(hdev->flags & HPET_DEV_VALID))
684 continue;
685 if (test_and_set_bit(HPET_DEV_USED_BIT,
686 (unsigned long *)&hdev->flags))
687 continue;
688 return hdev;
689 }
690 return NULL;
691}
692
693struct hpet_work_struct {
694 struct delayed_work work;
695 struct completion complete;
696};
697
698static void hpet_work(struct work_struct *w)
699{
700 struct hpet_dev *hdev;
701 int cpu = smp_processor_id();
702 struct hpet_work_struct *hpet_work;
703
704 hpet_work = container_of(w, struct hpet_work_struct, work.work);
705
706 hdev = hpet_get_unused_timer();
707 if (hdev)
708 init_one_hpet_msi_clockevent(hdev, cpu);
709
710 complete(&hpet_work->complete);
711}
712
713static int hpet_cpuhp_notify(struct notifier_block *n,
714 unsigned long action, void *hcpu)
715{
716 unsigned long cpu = (unsigned long)hcpu;
717 struct hpet_work_struct work;
718 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
719
720 switch (action & ~CPU_TASKS_FROZEN) {
721 case CPU_ONLINE:
722 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
723 init_completion(&work.complete);
724 /* FIXME: add schedule_work_on() */
725 schedule_delayed_work_on(cpu, &work.work, 0);
726 wait_for_completion(&work.complete);
727 destroy_delayed_work_on_stack(&work.work);
728 break;
729 case CPU_DEAD:
730 if (hdev) {
731 free_irq(hdev->irq, hdev);
732 hdev->flags &= ~HPET_DEV_USED;
733 per_cpu(cpu_hpet_dev, cpu) = NULL;
734 }
735 break;
736 }
737 return NOTIFY_OK;
738}
739#else
740
741static void hpet_msi_capability_lookup(unsigned int start_timer)
742{
743 return;
744}
745
746#ifdef CONFIG_HPET
747static void hpet_reserve_msi_timers(struct hpet_data *hd)
748{
749 return;
750}
751#endif
752
753static int hpet_cpuhp_notify(struct notifier_block *n,
754 unsigned long action, void *hcpu)
755{
756 return NOTIFY_OK;
757}
758
759#endif
760
761/*
762 * Clock source related code
763 */
764static cycle_t read_hpet(struct clocksource *cs)
765{
766 return (cycle_t)hpet_readl(HPET_COUNTER);
767}
768
769static struct clocksource clocksource_hpet = {
770 .name = "hpet",
771 .rating = 250,
772 .read = read_hpet,
773 .mask = HPET_MASK,
774 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
775 .resume = hpet_resume_counter,
776 .archdata = { .vclock_mode = VCLOCK_HPET },
777};
778
779static int hpet_clocksource_register(void)
780{
781 u64 start, now;
782 cycle_t t1;
783
784 /* Start the counter */
785 hpet_restart_counter();
786
787 /* Verify whether hpet counter works */
788 t1 = hpet_readl(HPET_COUNTER);
789 start = rdtsc();
790
791 /*
792 * We don't know the TSC frequency yet, but waiting for
793 * 200000 TSC cycles is safe:
794 * 4 GHz == 50us
795 * 1 GHz == 200us
796 */
797 do {
798 rep_nop();
799 now = rdtsc();
800 } while ((now - start) < 200000UL);
801
802 if (t1 == hpet_readl(HPET_COUNTER)) {
803 printk(KERN_WARNING
804 "HPET counter not counting. HPET disabled\n");
805 return -ENODEV;
806 }
807
808 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
809 return 0;
810}
811
812static u32 *hpet_boot_cfg;
813
814/**
815 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
816 */
817int __init hpet_enable(void)
818{
819 u32 hpet_period, cfg, id;
820 u64 freq;
821 unsigned int i, last;
822
823 if (!is_hpet_capable())
824 return 0;
825
826 hpet_set_mapping();
827
828 /*
829 * Read the period and check for a sane value:
830 */
831 hpet_period = hpet_readl(HPET_PERIOD);
832
833 /*
834 * AMD SB700 based systems with spread spectrum enabled use a
835 * SMM based HPET emulation to provide proper frequency
836 * setting. The SMM code is initialized with the first HPET
837 * register access and takes some time to complete. During
838 * this time the config register reads 0xffffffff. We check
839 * for max. 1000 loops whether the config register reads a non
840 * 0xffffffff value to make sure that HPET is up and running
841 * before we go further. A counting loop is safe, as the HPET
842 * access takes thousands of CPU cycles. On non SB700 based
843 * machines this check is only done once and has no side
844 * effects.
845 */
846 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
847 if (i == 1000) {
848 printk(KERN_WARNING
849 "HPET config register value = 0xFFFFFFFF. "
850 "Disabling HPET\n");
851 goto out_nohpet;
852 }
853 }
854
855 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
856 goto out_nohpet;
857
858 /*
859 * The period is a femto seconds value. Convert it to a
860 * frequency.
861 */
862 freq = FSEC_PER_SEC;
863 do_div(freq, hpet_period);
864 hpet_freq = freq;
865
866 /*
867 * Read the HPET ID register to retrieve the IRQ routing
868 * information and the number of channels
869 */
870 id = hpet_readl(HPET_ID);
871 hpet_print_config();
872
873 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
874
875#ifdef CONFIG_HPET_EMULATE_RTC
876 /*
877 * The legacy routing mode needs at least two channels, tick timer
878 * and the rtc emulation channel.
879 */
880 if (!last)
881 goto out_nohpet;
882#endif
883
884 cfg = hpet_readl(HPET_CFG);
885 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
886 GFP_KERNEL);
887 if (hpet_boot_cfg)
888 *hpet_boot_cfg = cfg;
889 else
890 pr_warn("HPET initial state will not be saved\n");
891 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
892 hpet_writel(cfg, HPET_CFG);
893 if (cfg)
894 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
895 cfg);
896
897 for (i = 0; i <= last; ++i) {
898 cfg = hpet_readl(HPET_Tn_CFG(i));
899 if (hpet_boot_cfg)
900 hpet_boot_cfg[i + 1] = cfg;
901 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
902 hpet_writel(cfg, HPET_Tn_CFG(i));
903 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
904 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
905 | HPET_TN_FSB | HPET_TN_FSB_CAP);
906 if (cfg)
907 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
908 cfg, i);
909 }
910 hpet_print_config();
911
912 if (hpet_clocksource_register())
913 goto out_nohpet;
914
915 if (id & HPET_ID_LEGSUP) {
916 hpet_legacy_clockevent_register();
917 return 1;
918 }
919 return 0;
920
921out_nohpet:
922 hpet_clear_mapping();
923 hpet_address = 0;
924 return 0;
925}
926
927/*
928 * Needs to be late, as the reserve_timer code calls kalloc !
929 *
930 * Not a problem on i386 as hpet_enable is called from late_time_init,
931 * but on x86_64 it is necessary !
932 */
933static __init int hpet_late_init(void)
934{
935 int cpu;
936
937 if (boot_hpet_disable)
938 return -ENODEV;
939
940 if (!hpet_address) {
941 if (!force_hpet_address)
942 return -ENODEV;
943
944 hpet_address = force_hpet_address;
945 hpet_enable();
946 }
947
948 if (!hpet_virt_address)
949 return -ENODEV;
950
951 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
952 hpet_msi_capability_lookup(2);
953 else
954 hpet_msi_capability_lookup(0);
955
956 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
957 hpet_print_config();
958
959 if (hpet_msi_disable)
960 return 0;
961
962 if (boot_cpu_has(X86_FEATURE_ARAT))
963 return 0;
964
965 cpu_notifier_register_begin();
966 for_each_online_cpu(cpu) {
967 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
968 }
969
970 /* This notifier should be called after workqueue is ready */
971 __hotcpu_notifier(hpet_cpuhp_notify, -20);
972 cpu_notifier_register_done();
973
974 return 0;
975}
976fs_initcall(hpet_late_init);
977
978void hpet_disable(void)
979{
980 if (is_hpet_capable() && hpet_virt_address) {
981 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
982
983 if (hpet_boot_cfg)
984 cfg = *hpet_boot_cfg;
985 else if (hpet_legacy_int_enabled) {
986 cfg &= ~HPET_CFG_LEGACY;
987 hpet_legacy_int_enabled = false;
988 }
989 cfg &= ~HPET_CFG_ENABLE;
990 hpet_writel(cfg, HPET_CFG);
991
992 if (!hpet_boot_cfg)
993 return;
994
995 id = hpet_readl(HPET_ID);
996 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
997
998 for (id = 0; id <= last; ++id)
999 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1000
1001 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1002 hpet_writel(*hpet_boot_cfg, HPET_CFG);
1003 }
1004}
1005
1006#ifdef CONFIG_HPET_EMULATE_RTC
1007
1008/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1009 * is enabled, we support RTC interrupt functionality in software.
1010 * RTC has 3 kinds of interrupts:
1011 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1012 * is updated
1013 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1014 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1015 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1016 * (1) and (2) above are implemented using polling at a frequency of
1017 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1018 * overhead. (DEFAULT_RTC_INT_FREQ)
1019 * For (3), we use interrupts at 64Hz or user specified periodic
1020 * frequency, whichever is higher.
1021 */
1022#include <linux/mc146818rtc.h>
1023#include <linux/rtc.h>
1024#include <asm/rtc.h>
1025
1026#define DEFAULT_RTC_INT_FREQ 64
1027#define DEFAULT_RTC_SHIFT 6
1028#define RTC_NUM_INTS 1
1029
1030static unsigned long hpet_rtc_flags;
1031static int hpet_prev_update_sec;
1032static struct rtc_time hpet_alarm_time;
1033static unsigned long hpet_pie_count;
1034static u32 hpet_t1_cmp;
1035static u32 hpet_default_delta;
1036static u32 hpet_pie_delta;
1037static unsigned long hpet_pie_limit;
1038
1039static rtc_irq_handler irq_handler;
1040
1041/*
1042 * Check that the hpet counter c1 is ahead of the c2
1043 */
1044static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1045{
1046 return (s32)(c2 - c1) < 0;
1047}
1048
1049/*
1050 * Registers a IRQ handler.
1051 */
1052int hpet_register_irq_handler(rtc_irq_handler handler)
1053{
1054 if (!is_hpet_enabled())
1055 return -ENODEV;
1056 if (irq_handler)
1057 return -EBUSY;
1058
1059 irq_handler = handler;
1060
1061 return 0;
1062}
1063EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1064
1065/*
1066 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1067 * and does cleanup.
1068 */
1069void hpet_unregister_irq_handler(rtc_irq_handler handler)
1070{
1071 if (!is_hpet_enabled())
1072 return;
1073
1074 irq_handler = NULL;
1075 hpet_rtc_flags = 0;
1076}
1077EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1078
1079/*
1080 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1081 * is not supported by all HPET implementations for timer 1.
1082 *
1083 * hpet_rtc_timer_init() is called when the rtc is initialized.
1084 */
1085int hpet_rtc_timer_init(void)
1086{
1087 unsigned int cfg, cnt, delta;
1088 unsigned long flags;
1089
1090 if (!is_hpet_enabled())
1091 return 0;
1092
1093 if (!hpet_default_delta) {
1094 uint64_t clc;
1095
1096 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1097 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1098 hpet_default_delta = clc;
1099 }
1100
1101 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1102 delta = hpet_default_delta;
1103 else
1104 delta = hpet_pie_delta;
1105
1106 local_irq_save(flags);
1107
1108 cnt = delta + hpet_readl(HPET_COUNTER);
1109 hpet_writel(cnt, HPET_T1_CMP);
1110 hpet_t1_cmp = cnt;
1111
1112 cfg = hpet_readl(HPET_T1_CFG);
1113 cfg &= ~HPET_TN_PERIODIC;
1114 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1115 hpet_writel(cfg, HPET_T1_CFG);
1116
1117 local_irq_restore(flags);
1118
1119 return 1;
1120}
1121EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1122
1123static void hpet_disable_rtc_channel(void)
1124{
1125 u32 cfg = hpet_readl(HPET_T1_CFG);
1126 cfg &= ~HPET_TN_ENABLE;
1127 hpet_writel(cfg, HPET_T1_CFG);
1128}
1129
1130/*
1131 * The functions below are called from rtc driver.
1132 * Return 0 if HPET is not being used.
1133 * Otherwise do the necessary changes and return 1.
1134 */
1135int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1136{
1137 if (!is_hpet_enabled())
1138 return 0;
1139
1140 hpet_rtc_flags &= ~bit_mask;
1141 if (unlikely(!hpet_rtc_flags))
1142 hpet_disable_rtc_channel();
1143
1144 return 1;
1145}
1146EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1147
1148int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1149{
1150 unsigned long oldbits = hpet_rtc_flags;
1151
1152 if (!is_hpet_enabled())
1153 return 0;
1154
1155 hpet_rtc_flags |= bit_mask;
1156
1157 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1158 hpet_prev_update_sec = -1;
1159
1160 if (!oldbits)
1161 hpet_rtc_timer_init();
1162
1163 return 1;
1164}
1165EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1166
1167int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1168 unsigned char sec)
1169{
1170 if (!is_hpet_enabled())
1171 return 0;
1172
1173 hpet_alarm_time.tm_hour = hrs;
1174 hpet_alarm_time.tm_min = min;
1175 hpet_alarm_time.tm_sec = sec;
1176
1177 return 1;
1178}
1179EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1180
1181int hpet_set_periodic_freq(unsigned long freq)
1182{
1183 uint64_t clc;
1184
1185 if (!is_hpet_enabled())
1186 return 0;
1187
1188 if (freq <= DEFAULT_RTC_INT_FREQ)
1189 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1190 else {
1191 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1192 do_div(clc, freq);
1193 clc >>= hpet_clockevent.shift;
1194 hpet_pie_delta = clc;
1195 hpet_pie_limit = 0;
1196 }
1197 return 1;
1198}
1199EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1200
1201int hpet_rtc_dropped_irq(void)
1202{
1203 return is_hpet_enabled();
1204}
1205EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1206
1207static void hpet_rtc_timer_reinit(void)
1208{
1209 unsigned int delta;
1210 int lost_ints = -1;
1211
1212 if (unlikely(!hpet_rtc_flags))
1213 hpet_disable_rtc_channel();
1214
1215 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1216 delta = hpet_default_delta;
1217 else
1218 delta = hpet_pie_delta;
1219
1220 /*
1221 * Increment the comparator value until we are ahead of the
1222 * current count.
1223 */
1224 do {
1225 hpet_t1_cmp += delta;
1226 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1227 lost_ints++;
1228 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1229
1230 if (lost_ints) {
1231 if (hpet_rtc_flags & RTC_PIE)
1232 hpet_pie_count += lost_ints;
1233 if (printk_ratelimit())
1234 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1235 lost_ints);
1236 }
1237}
1238
1239irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1240{
1241 struct rtc_time curr_time;
1242 unsigned long rtc_int_flag = 0;
1243
1244 hpet_rtc_timer_reinit();
1245 memset(&curr_time, 0, sizeof(struct rtc_time));
1246
1247 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1248 get_rtc_time(&curr_time);
1249
1250 if (hpet_rtc_flags & RTC_UIE &&
1251 curr_time.tm_sec != hpet_prev_update_sec) {
1252 if (hpet_prev_update_sec >= 0)
1253 rtc_int_flag = RTC_UF;
1254 hpet_prev_update_sec = curr_time.tm_sec;
1255 }
1256
1257 if (hpet_rtc_flags & RTC_PIE &&
1258 ++hpet_pie_count >= hpet_pie_limit) {
1259 rtc_int_flag |= RTC_PF;
1260 hpet_pie_count = 0;
1261 }
1262
1263 if (hpet_rtc_flags & RTC_AIE &&
1264 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1265 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1266 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1267 rtc_int_flag |= RTC_AF;
1268
1269 if (rtc_int_flag) {
1270 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1271 if (irq_handler)
1272 irq_handler(rtc_int_flag, dev_id);
1273 }
1274 return IRQ_HANDLED;
1275}
1276EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1277#endif