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1#include <linux/export.h>
2#include <linux/bitops.h>
3#include <linux/elf.h>
4#include <linux/mm.h>
5
6#include <linux/io.h>
7#include <linux/sched.h>
8#include <linux/random.h>
9#include <asm/processor.h>
10#include <asm/apic.h>
11#include <asm/cpu.h>
12#include <asm/smp.h>
13#include <asm/pci-direct.h>
14#include <asm/delay.h>
15
16#ifdef CONFIG_X86_64
17# include <asm/mmconfig.h>
18# include <asm/cacheflush.h>
19#endif
20
21#include "cpu.h"
22
23static const int amd_erratum_383[];
24static const int amd_erratum_400[];
25static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
26
27/*
28 * nodes_per_socket: Stores the number of nodes per socket.
29 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
30 * Node Identifiers[10:8]
31 */
32static u32 nodes_per_socket = 1;
33
34static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
35{
36 u32 gprs[8] = { 0 };
37 int err;
38
39 WARN_ONCE((boot_cpu_data.x86 != 0xf),
40 "%s should only be used on K8!\n", __func__);
41
42 gprs[1] = msr;
43 gprs[7] = 0x9c5a203a;
44
45 err = rdmsr_safe_regs(gprs);
46
47 *p = gprs[0] | ((u64)gprs[2] << 32);
48
49 return err;
50}
51
52static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
53{
54 u32 gprs[8] = { 0 };
55
56 WARN_ONCE((boot_cpu_data.x86 != 0xf),
57 "%s should only be used on K8!\n", __func__);
58
59 gprs[0] = (u32)val;
60 gprs[1] = msr;
61 gprs[2] = val >> 32;
62 gprs[7] = 0x9c5a203a;
63
64 return wrmsr_safe_regs(gprs);
65}
66
67/*
68 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
69 * misexecution of code under Linux. Owners of such processors should
70 * contact AMD for precise details and a CPU swap.
71 *
72 * See http://www.multimania.com/poulot/k6bug.html
73 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
74 * (Publication # 21266 Issue Date: August 1998)
75 *
76 * The following test is erm.. interesting. AMD neglected to up
77 * the chip setting when fixing the bug but they also tweaked some
78 * performance at the same time..
79 */
80
81extern __visible void vide(void);
82__asm__(".globl vide\n"
83 ".type vide, @function\n"
84 ".align 4\n"
85 "vide: ret\n");
86
87static void init_amd_k5(struct cpuinfo_x86 *c)
88{
89#ifdef CONFIG_X86_32
90/*
91 * General Systems BIOSen alias the cpu frequency registers
92 * of the Elan at 0x000df000. Unfortunately, one of the Linux
93 * drivers subsequently pokes it, and changes the CPU speed.
94 * Workaround : Remove the unneeded alias.
95 */
96#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
97#define CBAR_ENB (0x80000000)
98#define CBAR_KEY (0X000000CB)
99 if (c->x86_model == 9 || c->x86_model == 10) {
100 if (inl(CBAR) & CBAR_ENB)
101 outl(0 | CBAR_KEY, CBAR);
102 }
103#endif
104}
105
106static void init_amd_k6(struct cpuinfo_x86 *c)
107{
108#ifdef CONFIG_X86_32
109 u32 l, h;
110 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
111
112 if (c->x86_model < 6) {
113 /* Based on AMD doc 20734R - June 2000 */
114 if (c->x86_model == 0) {
115 clear_cpu_cap(c, X86_FEATURE_APIC);
116 set_cpu_cap(c, X86_FEATURE_PGE);
117 }
118 return;
119 }
120
121 if (c->x86_model == 6 && c->x86_mask == 1) {
122 const int K6_BUG_LOOP = 1000000;
123 int n;
124 void (*f_vide)(void);
125 u64 d, d2;
126
127 pr_info("AMD K6 stepping B detected - ");
128
129 /*
130 * It looks like AMD fixed the 2.6.2 bug and improved indirect
131 * calls at the same time.
132 */
133
134 n = K6_BUG_LOOP;
135 f_vide = vide;
136 d = rdtsc();
137 while (n--)
138 f_vide();
139 d2 = rdtsc();
140 d = d2-d;
141
142 if (d > 20*K6_BUG_LOOP)
143 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
144 else
145 pr_cont("probably OK (after B9730xxxx).\n");
146 }
147
148 /* K6 with old style WHCR */
149 if (c->x86_model < 8 ||
150 (c->x86_model == 8 && c->x86_mask < 8)) {
151 /* We can only write allocate on the low 508Mb */
152 if (mbytes > 508)
153 mbytes = 508;
154
155 rdmsr(MSR_K6_WHCR, l, h);
156 if ((l&0x0000FFFF) == 0) {
157 unsigned long flags;
158 l = (1<<0)|((mbytes/4)<<1);
159 local_irq_save(flags);
160 wbinvd();
161 wrmsr(MSR_K6_WHCR, l, h);
162 local_irq_restore(flags);
163 pr_info("Enabling old style K6 write allocation for %d Mb\n",
164 mbytes);
165 }
166 return;
167 }
168
169 if ((c->x86_model == 8 && c->x86_mask > 7) ||
170 c->x86_model == 9 || c->x86_model == 13) {
171 /* The more serious chips .. */
172
173 if (mbytes > 4092)
174 mbytes = 4092;
175
176 rdmsr(MSR_K6_WHCR, l, h);
177 if ((l&0xFFFF0000) == 0) {
178 unsigned long flags;
179 l = ((mbytes>>2)<<22)|(1<<16);
180 local_irq_save(flags);
181 wbinvd();
182 wrmsr(MSR_K6_WHCR, l, h);
183 local_irq_restore(flags);
184 pr_info("Enabling new style K6 write allocation for %d Mb\n",
185 mbytes);
186 }
187
188 return;
189 }
190
191 if (c->x86_model == 10) {
192 /* AMD Geode LX is model 10 */
193 /* placeholder for any needed mods */
194 return;
195 }
196#endif
197}
198
199static void init_amd_k7(struct cpuinfo_x86 *c)
200{
201#ifdef CONFIG_X86_32
202 u32 l, h;
203
204 /*
205 * Bit 15 of Athlon specific MSR 15, needs to be 0
206 * to enable SSE on Palomino/Morgan/Barton CPU's.
207 * If the BIOS didn't enable it already, enable it here.
208 */
209 if (c->x86_model >= 6 && c->x86_model <= 10) {
210 if (!cpu_has(c, X86_FEATURE_XMM)) {
211 pr_info("Enabling disabled K7/SSE Support.\n");
212 msr_clear_bit(MSR_K7_HWCR, 15);
213 set_cpu_cap(c, X86_FEATURE_XMM);
214 }
215 }
216
217 /*
218 * It's been determined by AMD that Athlons since model 8 stepping 1
219 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
220 * As per AMD technical note 27212 0.2
221 */
222 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
223 rdmsr(MSR_K7_CLK_CTL, l, h);
224 if ((l & 0xfff00000) != 0x20000000) {
225 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
226 l, ((l & 0x000fffff)|0x20000000));
227 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
228 }
229 }
230
231 set_cpu_cap(c, X86_FEATURE_K7);
232
233 /* calling is from identify_secondary_cpu() ? */
234 if (!c->cpu_index)
235 return;
236
237 /*
238 * Certain Athlons might work (for various values of 'work') in SMP
239 * but they are not certified as MP capable.
240 */
241 /* Athlon 660/661 is valid. */
242 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
243 (c->x86_mask == 1)))
244 return;
245
246 /* Duron 670 is valid */
247 if ((c->x86_model == 7) && (c->x86_mask == 0))
248 return;
249
250 /*
251 * Athlon 662, Duron 671, and Athlon >model 7 have capability
252 * bit. It's worth noting that the A5 stepping (662) of some
253 * Athlon XP's have the MP bit set.
254 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
255 * more.
256 */
257 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
258 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
259 (c->x86_model > 7))
260 if (cpu_has(c, X86_FEATURE_MP))
261 return;
262
263 /* If we get here, not a certified SMP capable AMD system. */
264
265 /*
266 * Don't taint if we are running SMP kernel on a single non-MP
267 * approved Athlon
268 */
269 WARN_ONCE(1, "WARNING: This combination of AMD"
270 " processors is not suitable for SMP.\n");
271 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
272#endif
273}
274
275#ifdef CONFIG_NUMA
276/*
277 * To workaround broken NUMA config. Read the comment in
278 * srat_detect_node().
279 */
280static int nearby_node(int apicid)
281{
282 int i, node;
283
284 for (i = apicid - 1; i >= 0; i--) {
285 node = __apicid_to_node[i];
286 if (node != NUMA_NO_NODE && node_online(node))
287 return node;
288 }
289 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
290 node = __apicid_to_node[i];
291 if (node != NUMA_NO_NODE && node_online(node))
292 return node;
293 }
294 return first_node(node_online_map); /* Shouldn't happen */
295}
296#endif
297
298/*
299 * Fixup core topology information for
300 * (1) AMD multi-node processors
301 * Assumption: Number of cores in each internal node is the same.
302 * (2) AMD processors supporting compute units
303 */
304#ifdef CONFIG_SMP
305static void amd_get_topology(struct cpuinfo_x86 *c)
306{
307 u8 node_id;
308 int cpu = smp_processor_id();
309
310 /* get information required for multi-node processors */
311 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
312 u32 eax, ebx, ecx, edx;
313
314 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
315
316 node_id = ecx & 0xff;
317 smp_num_siblings = ((ebx >> 8) & 0xff) + 1;
318
319 if (c->x86 == 0x15)
320 c->cu_id = ebx & 0xff;
321
322 if (c->x86 >= 0x17) {
323 c->cpu_core_id = ebx & 0xff;
324
325 if (smp_num_siblings > 1)
326 c->x86_max_cores /= smp_num_siblings;
327 }
328
329 /*
330 * We may have multiple LLCs if L3 caches exist, so check if we
331 * have an L3 cache by looking at the L3 cache CPUID leaf.
332 */
333 if (cpuid_edx(0x80000006)) {
334 if (c->x86 == 0x17) {
335 /*
336 * LLC is at the core complex level.
337 * Core complex id is ApicId[3].
338 */
339 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
340 } else {
341 /* LLC is at the node level. */
342 per_cpu(cpu_llc_id, cpu) = node_id;
343 }
344 }
345 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
346 u64 value;
347
348 rdmsrl(MSR_FAM10H_NODE_ID, value);
349 node_id = value & 7;
350
351 per_cpu(cpu_llc_id, cpu) = node_id;
352 } else
353 return;
354
355 /* fixup multi-node processor information */
356 if (nodes_per_socket > 1) {
357 u32 cus_per_node;
358
359 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
360 cus_per_node = c->x86_max_cores / nodes_per_socket;
361
362 /* core id has to be in the [0 .. cores_per_node - 1] range */
363 c->cpu_core_id %= cus_per_node;
364 }
365}
366#endif
367
368/*
369 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
370 * Assumes number of cores is a power of two.
371 */
372static void amd_detect_cmp(struct cpuinfo_x86 *c)
373{
374#ifdef CONFIG_SMP
375 unsigned bits;
376 int cpu = smp_processor_id();
377
378 bits = c->x86_coreid_bits;
379 /* Low order bits define the core id (index of core in socket) */
380 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
381 /* Convert the initial APIC ID into the socket ID */
382 c->phys_proc_id = c->initial_apicid >> bits;
383 /* use socket ID also for last level cache */
384 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
385 amd_get_topology(c);
386#endif
387}
388
389u16 amd_get_nb_id(int cpu)
390{
391 u16 id = 0;
392#ifdef CONFIG_SMP
393 id = per_cpu(cpu_llc_id, cpu);
394#endif
395 return id;
396}
397EXPORT_SYMBOL_GPL(amd_get_nb_id);
398
399u32 amd_get_nodes_per_socket(void)
400{
401 return nodes_per_socket;
402}
403EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
404
405static void srat_detect_node(struct cpuinfo_x86 *c)
406{
407#ifdef CONFIG_NUMA
408 int cpu = smp_processor_id();
409 int node;
410 unsigned apicid = c->apicid;
411
412 node = numa_cpu_node(cpu);
413 if (node == NUMA_NO_NODE)
414 node = per_cpu(cpu_llc_id, cpu);
415
416 /*
417 * On multi-fabric platform (e.g. Numascale NumaChip) a
418 * platform-specific handler needs to be called to fixup some
419 * IDs of the CPU.
420 */
421 if (x86_cpuinit.fixup_cpu_id)
422 x86_cpuinit.fixup_cpu_id(c, node);
423
424 if (!node_online(node)) {
425 /*
426 * Two possibilities here:
427 *
428 * - The CPU is missing memory and no node was created. In
429 * that case try picking one from a nearby CPU.
430 *
431 * - The APIC IDs differ from the HyperTransport node IDs
432 * which the K8 northbridge parsing fills in. Assume
433 * they are all increased by a constant offset, but in
434 * the same order as the HT nodeids. If that doesn't
435 * result in a usable node fall back to the path for the
436 * previous case.
437 *
438 * This workaround operates directly on the mapping between
439 * APIC ID and NUMA node, assuming certain relationship
440 * between APIC ID, HT node ID and NUMA topology. As going
441 * through CPU mapping may alter the outcome, directly
442 * access __apicid_to_node[].
443 */
444 int ht_nodeid = c->initial_apicid;
445
446 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
447 node = __apicid_to_node[ht_nodeid];
448 /* Pick a nearby node */
449 if (!node_online(node))
450 node = nearby_node(apicid);
451 }
452 numa_set_node(cpu, node);
453#endif
454}
455
456static void early_init_amd_mc(struct cpuinfo_x86 *c)
457{
458#ifdef CONFIG_SMP
459 unsigned bits, ecx;
460
461 /* Multi core CPU? */
462 if (c->extended_cpuid_level < 0x80000008)
463 return;
464
465 ecx = cpuid_ecx(0x80000008);
466
467 c->x86_max_cores = (ecx & 0xff) + 1;
468
469 /* CPU telling us the core id bits shift? */
470 bits = (ecx >> 12) & 0xF;
471
472 /* Otherwise recompute */
473 if (bits == 0) {
474 while ((1 << bits) < c->x86_max_cores)
475 bits++;
476 }
477
478 c->x86_coreid_bits = bits;
479#endif
480}
481
482static void bsp_init_amd(struct cpuinfo_x86 *c)
483{
484
485#ifdef CONFIG_X86_64
486 if (c->x86 >= 0xf) {
487 unsigned long long tseg;
488
489 /*
490 * Split up direct mapping around the TSEG SMM area.
491 * Don't do it for gbpages because there seems very little
492 * benefit in doing so.
493 */
494 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
495 unsigned long pfn = tseg >> PAGE_SHIFT;
496
497 pr_debug("tseg: %010llx\n", tseg);
498 if (pfn_range_is_mapped(pfn, pfn + 1))
499 set_memory_4k((unsigned long)__va(tseg), 1);
500 }
501 }
502#endif
503
504 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
505
506 if (c->x86 > 0x10 ||
507 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
508 u64 val;
509
510 rdmsrl(MSR_K7_HWCR, val);
511 if (!(val & BIT(24)))
512 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
513 }
514 }
515
516 if (c->x86 == 0x15) {
517 unsigned long upperbit;
518 u32 cpuid, assoc;
519
520 cpuid = cpuid_edx(0x80000005);
521 assoc = cpuid >> 16 & 0xff;
522 upperbit = ((cpuid >> 24) << 10) / assoc;
523
524 va_align.mask = (upperbit - 1) & PAGE_MASK;
525 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
526
527 /* A random value per boot for bit slice [12:upper_bit) */
528 va_align.bits = get_random_int() & va_align.mask;
529 }
530
531 if (cpu_has(c, X86_FEATURE_MWAITX))
532 use_mwaitx_delay();
533
534 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
535 u32 ecx;
536
537 ecx = cpuid_ecx(0x8000001e);
538 nodes_per_socket = ((ecx >> 8) & 7) + 1;
539 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
540 u64 value;
541
542 rdmsrl(MSR_FAM10H_NODE_ID, value);
543 nodes_per_socket = ((value >> 3) & 7) + 1;
544 }
545}
546
547static void early_init_amd(struct cpuinfo_x86 *c)
548{
549 early_init_amd_mc(c);
550
551 /*
552 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
553 * with P/T states and does not stop in deep C-states
554 */
555 if (c->x86_power & (1 << 8)) {
556 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
557 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
558 if (!check_tsc_unstable())
559 set_sched_clock_stable();
560 }
561
562 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
563 if (c->x86_power & BIT(12))
564 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
565
566#ifdef CONFIG_X86_64
567 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
568#else
569 /* Set MTRR capability flag if appropriate */
570 if (c->x86 == 5)
571 if (c->x86_model == 13 || c->x86_model == 9 ||
572 (c->x86_model == 8 && c->x86_mask >= 8))
573 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
574#endif
575#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
576 /*
577 * ApicID can always be treated as an 8-bit value for AMD APIC versions
578 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
579 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
580 * after 16h.
581 */
582 if (boot_cpu_has(X86_FEATURE_APIC)) {
583 if (c->x86 > 0x16)
584 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
585 else if (c->x86 >= 0xf) {
586 /* check CPU config space for extended APIC ID */
587 unsigned int val;
588
589 val = read_pci_config(0, 24, 0, 0x68);
590 if ((val >> 17 & 0x3) == 0x3)
591 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
592 }
593 }
594#endif
595
596 /*
597 * This is only needed to tell the kernel whether to use VMCALL
598 * and VMMCALL. VMMCALL is never executed except under virt, so
599 * we can set it unconditionally.
600 */
601 set_cpu_cap(c, X86_FEATURE_VMMCALL);
602
603 /* F16h erratum 793, CVE-2013-6885 */
604 if (c->x86 == 0x16 && c->x86_model <= 0xf)
605 msr_set_bit(MSR_AMD64_LS_CFG, 15);
606
607 /*
608 * Check whether the machine is affected by erratum 400. This is
609 * used to select the proper idle routine and to enable the check
610 * whether the machine is affected in arch_post_acpi_init(), which
611 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
612 */
613 if (cpu_has_amd_erratum(c, amd_erratum_400))
614 set_cpu_bug(c, X86_BUG_AMD_E400);
615}
616
617static void init_amd_k8(struct cpuinfo_x86 *c)
618{
619 u32 level;
620 u64 value;
621
622 /* On C+ stepping K8 rep microcode works well for copy/memset */
623 level = cpuid_eax(1);
624 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
625 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
626
627 /*
628 * Some BIOSes incorrectly force this feature, but only K8 revision D
629 * (model = 0x14) and later actually support it.
630 * (AMD Erratum #110, docId: 25759).
631 */
632 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
633 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
634 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
635 value &= ~BIT_64(32);
636 wrmsrl_amd_safe(0xc001100d, value);
637 }
638 }
639
640 if (!c->x86_model_id[0])
641 strcpy(c->x86_model_id, "Hammer");
642
643#ifdef CONFIG_SMP
644 /*
645 * Disable TLB flush filter by setting HWCR.FFDIS on K8
646 * bit 6 of msr C001_0015
647 *
648 * Errata 63 for SH-B3 steppings
649 * Errata 122 for all steppings (F+ have it disabled by default)
650 */
651 msr_set_bit(MSR_K7_HWCR, 6);
652#endif
653 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
654}
655
656static void init_amd_gh(struct cpuinfo_x86 *c)
657{
658#ifdef CONFIG_X86_64
659 /* do this for boot cpu */
660 if (c == &boot_cpu_data)
661 check_enable_amd_mmconf_dmi();
662
663 fam10h_check_enable_mmcfg();
664#endif
665
666 /*
667 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
668 * is always needed when GART is enabled, even in a kernel which has no
669 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
670 * If it doesn't, we do it here as suggested by the BKDG.
671 *
672 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
673 */
674 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
675
676 /*
677 * On family 10h BIOS may not have properly enabled WC+ support, causing
678 * it to be converted to CD memtype. This may result in performance
679 * degradation for certain nested-paging guests. Prevent this conversion
680 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
681 *
682 * NOTE: we want to use the _safe accessors so as not to #GP kvm
683 * guests on older kvm hosts.
684 */
685 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
686
687 if (cpu_has_amd_erratum(c, amd_erratum_383))
688 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
689}
690
691#define MSR_AMD64_DE_CFG 0xC0011029
692
693static void init_amd_ln(struct cpuinfo_x86 *c)
694{
695 /*
696 * Apply erratum 665 fix unconditionally so machines without a BIOS
697 * fix work.
698 */
699 msr_set_bit(MSR_AMD64_DE_CFG, 31);
700}
701
702static void init_amd_bd(struct cpuinfo_x86 *c)
703{
704 u64 value;
705
706 /* re-enable TopologyExtensions if switched off by BIOS */
707 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) &&
708 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
709
710 if (msr_set_bit(0xc0011005, 54) > 0) {
711 rdmsrl(0xc0011005, value);
712 if (value & BIT_64(54)) {
713 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
714 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
715 }
716 }
717 }
718
719 /*
720 * The way access filter has a performance penalty on some workloads.
721 * Disable it on the affected CPUs.
722 */
723 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
724 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
725 value |= 0x1E;
726 wrmsrl_safe(MSR_F15H_IC_CFG, value);
727 }
728 }
729}
730
731static void init_amd(struct cpuinfo_x86 *c)
732{
733 u32 dummy;
734
735 early_init_amd(c);
736
737 /*
738 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
739 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
740 */
741 clear_cpu_cap(c, 0*32+31);
742
743 if (c->x86 >= 0x10)
744 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
745
746 /* get apicid instead of initial apic id from cpuid */
747 c->apicid = hard_smp_processor_id();
748
749 /* K6s reports MCEs but don't actually have all the MSRs */
750 if (c->x86 < 6)
751 clear_cpu_cap(c, X86_FEATURE_MCE);
752
753 switch (c->x86) {
754 case 4: init_amd_k5(c); break;
755 case 5: init_amd_k6(c); break;
756 case 6: init_amd_k7(c); break;
757 case 0xf: init_amd_k8(c); break;
758 case 0x10: init_amd_gh(c); break;
759 case 0x12: init_amd_ln(c); break;
760 case 0x15: init_amd_bd(c); break;
761 }
762
763 /* Enable workaround for FXSAVE leak */
764 if (c->x86 >= 6)
765 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
766
767 cpu_detect_cache_sizes(c);
768
769 /* Multi core CPU? */
770 if (c->extended_cpuid_level >= 0x80000008) {
771 amd_detect_cmp(c);
772 srat_detect_node(c);
773 }
774
775#ifdef CONFIG_X86_32
776 detect_ht(c);
777#endif
778
779 init_amd_cacheinfo(c);
780
781 if (c->x86 >= 0xf)
782 set_cpu_cap(c, X86_FEATURE_K8);
783
784 if (cpu_has(c, X86_FEATURE_XMM2)) {
785 /* MFENCE stops RDTSC speculation */
786 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
787 }
788
789 /*
790 * Family 0x12 and above processors have APIC timer
791 * running in deep C states.
792 */
793 if (c->x86 > 0x11)
794 set_cpu_cap(c, X86_FEATURE_ARAT);
795
796 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
797
798 /* 3DNow or LM implies PREFETCHW */
799 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
800 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
801 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
802
803 /* AMD CPUs don't reset SS attributes on SYSRET */
804 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
805}
806
807#ifdef CONFIG_X86_32
808static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
809{
810 /* AMD errata T13 (order #21922) */
811 if ((c->x86 == 6)) {
812 /* Duron Rev A0 */
813 if (c->x86_model == 3 && c->x86_mask == 0)
814 size = 64;
815 /* Tbird rev A1/A2 */
816 if (c->x86_model == 4 &&
817 (c->x86_mask == 0 || c->x86_mask == 1))
818 size = 256;
819 }
820 return size;
821}
822#endif
823
824static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
825{
826 u32 ebx, eax, ecx, edx;
827 u16 mask = 0xfff;
828
829 if (c->x86 < 0xf)
830 return;
831
832 if (c->extended_cpuid_level < 0x80000006)
833 return;
834
835 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
836
837 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
838 tlb_lli_4k[ENTRIES] = ebx & mask;
839
840 /*
841 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
842 * characteristics from the CPUID function 0x80000005 instead.
843 */
844 if (c->x86 == 0xf) {
845 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
846 mask = 0xff;
847 }
848
849 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
850 if (!((eax >> 16) & mask))
851 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
852 else
853 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
854
855 /* a 4M entry uses two 2M entries */
856 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
857
858 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
859 if (!(eax & mask)) {
860 /* Erratum 658 */
861 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
862 tlb_lli_2m[ENTRIES] = 1024;
863 } else {
864 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
865 tlb_lli_2m[ENTRIES] = eax & 0xff;
866 }
867 } else
868 tlb_lli_2m[ENTRIES] = eax & mask;
869
870 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
871}
872
873static const struct cpu_dev amd_cpu_dev = {
874 .c_vendor = "AMD",
875 .c_ident = { "AuthenticAMD" },
876#ifdef CONFIG_X86_32
877 .legacy_models = {
878 { .family = 4, .model_names =
879 {
880 [3] = "486 DX/2",
881 [7] = "486 DX/2-WB",
882 [8] = "486 DX/4",
883 [9] = "486 DX/4-WB",
884 [14] = "Am5x86-WT",
885 [15] = "Am5x86-WB"
886 }
887 },
888 },
889 .legacy_cache_size = amd_size_cache,
890#endif
891 .c_early_init = early_init_amd,
892 .c_detect_tlb = cpu_detect_tlb_amd,
893 .c_bsp_init = bsp_init_amd,
894 .c_init = init_amd,
895 .c_x86_vendor = X86_VENDOR_AMD,
896};
897
898cpu_dev_register(amd_cpu_dev);
899
900/*
901 * AMD errata checking
902 *
903 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
904 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
905 * have an OSVW id assigned, which it takes as first argument. Both take a
906 * variable number of family-specific model-stepping ranges created by
907 * AMD_MODEL_RANGE().
908 *
909 * Example:
910 *
911 * const int amd_erratum_319[] =
912 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
913 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
914 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
915 */
916
917#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
918#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
919#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
920 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
921#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
922#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
923#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
924
925static const int amd_erratum_400[] =
926 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
927 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
928
929static const int amd_erratum_383[] =
930 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
931
932
933static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
934{
935 int osvw_id = *erratum++;
936 u32 range;
937 u32 ms;
938
939 if (osvw_id >= 0 && osvw_id < 65536 &&
940 cpu_has(cpu, X86_FEATURE_OSVW)) {
941 u64 osvw_len;
942
943 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
944 if (osvw_id < osvw_len) {
945 u64 osvw_bits;
946
947 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
948 osvw_bits);
949 return osvw_bits & (1ULL << (osvw_id & 0x3f));
950 }
951 }
952
953 /* OSVW unavailable or ID unknown, match family-model-stepping range */
954 ms = (cpu->x86_model << 4) | cpu->x86_mask;
955 while ((range = *erratum++))
956 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
957 (ms >= AMD_MODEL_RANGE_START(range)) &&
958 (ms <= AMD_MODEL_RANGE_END(range)))
959 return true;
960
961 return false;
962}
963
964void set_dr_addr_mask(unsigned long mask, int dr)
965{
966 if (!boot_cpu_has(X86_FEATURE_BPEXT))
967 return;
968
969 switch (dr) {
970 case 0:
971 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
972 break;
973 case 1:
974 case 2:
975 case 3:
976 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
977 break;
978 default:
979 break;
980 }
981}
1#include <linux/export.h>
2#include <linux/bitops.h>
3#include <linux/elf.h>
4#include <linux/mm.h>
5
6#include <linux/io.h>
7#include <linux/sched.h>
8#include <linux/random.h>
9#include <asm/processor.h>
10#include <asm/apic.h>
11#include <asm/cpu.h>
12#include <asm/smp.h>
13#include <asm/pci-direct.h>
14#include <asm/delay.h>
15
16#ifdef CONFIG_X86_64
17# include <asm/mmconfig.h>
18# include <asm/cacheflush.h>
19#endif
20
21#include "cpu.h"
22
23/*
24 * nodes_per_socket: Stores the number of nodes per socket.
25 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
26 * Node Identifiers[10:8]
27 */
28static u32 nodes_per_socket = 1;
29
30static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
31{
32 u32 gprs[8] = { 0 };
33 int err;
34
35 WARN_ONCE((boot_cpu_data.x86 != 0xf),
36 "%s should only be used on K8!\n", __func__);
37
38 gprs[1] = msr;
39 gprs[7] = 0x9c5a203a;
40
41 err = rdmsr_safe_regs(gprs);
42
43 *p = gprs[0] | ((u64)gprs[2] << 32);
44
45 return err;
46}
47
48static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
49{
50 u32 gprs[8] = { 0 };
51
52 WARN_ONCE((boot_cpu_data.x86 != 0xf),
53 "%s should only be used on K8!\n", __func__);
54
55 gprs[0] = (u32)val;
56 gprs[1] = msr;
57 gprs[2] = val >> 32;
58 gprs[7] = 0x9c5a203a;
59
60 return wrmsr_safe_regs(gprs);
61}
62
63/*
64 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
65 * misexecution of code under Linux. Owners of such processors should
66 * contact AMD for precise details and a CPU swap.
67 *
68 * See http://www.multimania.com/poulot/k6bug.html
69 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
70 * (Publication # 21266 Issue Date: August 1998)
71 *
72 * The following test is erm.. interesting. AMD neglected to up
73 * the chip setting when fixing the bug but they also tweaked some
74 * performance at the same time..
75 */
76
77extern __visible void vide(void);
78__asm__(".globl vide\n"
79 ".type vide, @function\n"
80 ".align 4\n"
81 "vide: ret\n");
82
83static void init_amd_k5(struct cpuinfo_x86 *c)
84{
85#ifdef CONFIG_X86_32
86/*
87 * General Systems BIOSen alias the cpu frequency registers
88 * of the Elan at 0x000df000. Unfortunately, one of the Linux
89 * drivers subsequently pokes it, and changes the CPU speed.
90 * Workaround : Remove the unneeded alias.
91 */
92#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
93#define CBAR_ENB (0x80000000)
94#define CBAR_KEY (0X000000CB)
95 if (c->x86_model == 9 || c->x86_model == 10) {
96 if (inl(CBAR) & CBAR_ENB)
97 outl(0 | CBAR_KEY, CBAR);
98 }
99#endif
100}
101
102static void init_amd_k6(struct cpuinfo_x86 *c)
103{
104#ifdef CONFIG_X86_32
105 u32 l, h;
106 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
107
108 if (c->x86_model < 6) {
109 /* Based on AMD doc 20734R - June 2000 */
110 if (c->x86_model == 0) {
111 clear_cpu_cap(c, X86_FEATURE_APIC);
112 set_cpu_cap(c, X86_FEATURE_PGE);
113 }
114 return;
115 }
116
117 if (c->x86_model == 6 && c->x86_mask == 1) {
118 const int K6_BUG_LOOP = 1000000;
119 int n;
120 void (*f_vide)(void);
121 u64 d, d2;
122
123 pr_info("AMD K6 stepping B detected - ");
124
125 /*
126 * It looks like AMD fixed the 2.6.2 bug and improved indirect
127 * calls at the same time.
128 */
129
130 n = K6_BUG_LOOP;
131 f_vide = vide;
132 d = rdtsc();
133 while (n--)
134 f_vide();
135 d2 = rdtsc();
136 d = d2-d;
137
138 if (d > 20*K6_BUG_LOOP)
139 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
140 else
141 pr_cont("probably OK (after B9730xxxx).\n");
142 }
143
144 /* K6 with old style WHCR */
145 if (c->x86_model < 8 ||
146 (c->x86_model == 8 && c->x86_mask < 8)) {
147 /* We can only write allocate on the low 508Mb */
148 if (mbytes > 508)
149 mbytes = 508;
150
151 rdmsr(MSR_K6_WHCR, l, h);
152 if ((l&0x0000FFFF) == 0) {
153 unsigned long flags;
154 l = (1<<0)|((mbytes/4)<<1);
155 local_irq_save(flags);
156 wbinvd();
157 wrmsr(MSR_K6_WHCR, l, h);
158 local_irq_restore(flags);
159 pr_info("Enabling old style K6 write allocation for %d Mb\n",
160 mbytes);
161 }
162 return;
163 }
164
165 if ((c->x86_model == 8 && c->x86_mask > 7) ||
166 c->x86_model == 9 || c->x86_model == 13) {
167 /* The more serious chips .. */
168
169 if (mbytes > 4092)
170 mbytes = 4092;
171
172 rdmsr(MSR_K6_WHCR, l, h);
173 if ((l&0xFFFF0000) == 0) {
174 unsigned long flags;
175 l = ((mbytes>>2)<<22)|(1<<16);
176 local_irq_save(flags);
177 wbinvd();
178 wrmsr(MSR_K6_WHCR, l, h);
179 local_irq_restore(flags);
180 pr_info("Enabling new style K6 write allocation for %d Mb\n",
181 mbytes);
182 }
183
184 return;
185 }
186
187 if (c->x86_model == 10) {
188 /* AMD Geode LX is model 10 */
189 /* placeholder for any needed mods */
190 return;
191 }
192#endif
193}
194
195static void init_amd_k7(struct cpuinfo_x86 *c)
196{
197#ifdef CONFIG_X86_32
198 u32 l, h;
199
200 /*
201 * Bit 15 of Athlon specific MSR 15, needs to be 0
202 * to enable SSE on Palomino/Morgan/Barton CPU's.
203 * If the BIOS didn't enable it already, enable it here.
204 */
205 if (c->x86_model >= 6 && c->x86_model <= 10) {
206 if (!cpu_has(c, X86_FEATURE_XMM)) {
207 pr_info("Enabling disabled K7/SSE Support.\n");
208 msr_clear_bit(MSR_K7_HWCR, 15);
209 set_cpu_cap(c, X86_FEATURE_XMM);
210 }
211 }
212
213 /*
214 * It's been determined by AMD that Athlons since model 8 stepping 1
215 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
216 * As per AMD technical note 27212 0.2
217 */
218 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
219 rdmsr(MSR_K7_CLK_CTL, l, h);
220 if ((l & 0xfff00000) != 0x20000000) {
221 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
222 l, ((l & 0x000fffff)|0x20000000));
223 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
224 }
225 }
226
227 set_cpu_cap(c, X86_FEATURE_K7);
228
229 /* calling is from identify_secondary_cpu() ? */
230 if (!c->cpu_index)
231 return;
232
233 /*
234 * Certain Athlons might work (for various values of 'work') in SMP
235 * but they are not certified as MP capable.
236 */
237 /* Athlon 660/661 is valid. */
238 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
239 (c->x86_mask == 1)))
240 return;
241
242 /* Duron 670 is valid */
243 if ((c->x86_model == 7) && (c->x86_mask == 0))
244 return;
245
246 /*
247 * Athlon 662, Duron 671, and Athlon >model 7 have capability
248 * bit. It's worth noting that the A5 stepping (662) of some
249 * Athlon XP's have the MP bit set.
250 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
251 * more.
252 */
253 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
254 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
255 (c->x86_model > 7))
256 if (cpu_has(c, X86_FEATURE_MP))
257 return;
258
259 /* If we get here, not a certified SMP capable AMD system. */
260
261 /*
262 * Don't taint if we are running SMP kernel on a single non-MP
263 * approved Athlon
264 */
265 WARN_ONCE(1, "WARNING: This combination of AMD"
266 " processors is not suitable for SMP.\n");
267 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
268#endif
269}
270
271#ifdef CONFIG_NUMA
272/*
273 * To workaround broken NUMA config. Read the comment in
274 * srat_detect_node().
275 */
276static int nearby_node(int apicid)
277{
278 int i, node;
279
280 for (i = apicid - 1; i >= 0; i--) {
281 node = __apicid_to_node[i];
282 if (node != NUMA_NO_NODE && node_online(node))
283 return node;
284 }
285 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
286 node = __apicid_to_node[i];
287 if (node != NUMA_NO_NODE && node_online(node))
288 return node;
289 }
290 return first_node(node_online_map); /* Shouldn't happen */
291}
292#endif
293
294/*
295 * Fixup core topology information for
296 * (1) AMD multi-node processors
297 * Assumption: Number of cores in each internal node is the same.
298 * (2) AMD processors supporting compute units
299 */
300#ifdef CONFIG_SMP
301static void amd_get_topology(struct cpuinfo_x86 *c)
302{
303 u8 node_id;
304 int cpu = smp_processor_id();
305
306 /* get information required for multi-node processors */
307 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
308 u32 eax, ebx, ecx, edx;
309
310 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
311 node_id = ecx & 7;
312
313 /* get compute unit information */
314 smp_num_siblings = ((ebx >> 8) & 3) + 1;
315 c->x86_max_cores /= smp_num_siblings;
316 c->cpu_core_id = ebx & 0xff;
317 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
318 u64 value;
319
320 rdmsrl(MSR_FAM10H_NODE_ID, value);
321 node_id = value & 7;
322 } else
323 return;
324
325 /* fixup multi-node processor information */
326 if (nodes_per_socket > 1) {
327 u32 cus_per_node;
328
329 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
330 cus_per_node = c->x86_max_cores / nodes_per_socket;
331
332 /* store NodeID, use llc_shared_map to store sibling info */
333 per_cpu(cpu_llc_id, cpu) = node_id;
334
335 /* core id has to be in the [0 .. cores_per_node - 1] range */
336 c->cpu_core_id %= cus_per_node;
337 }
338}
339#endif
340
341/*
342 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
343 * Assumes number of cores is a power of two.
344 */
345static void amd_detect_cmp(struct cpuinfo_x86 *c)
346{
347#ifdef CONFIG_SMP
348 unsigned bits;
349 int cpu = smp_processor_id();
350 unsigned int socket_id, core_complex_id;
351
352 bits = c->x86_coreid_bits;
353 /* Low order bits define the core id (index of core in socket) */
354 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
355 /* Convert the initial APIC ID into the socket ID */
356 c->phys_proc_id = c->initial_apicid >> bits;
357 /* use socket ID also for last level cache */
358 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
359 amd_get_topology(c);
360
361 /*
362 * Fix percpu cpu_llc_id here as LLC topology is different
363 * for Fam17h systems.
364 */
365 if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
366 return;
367
368 socket_id = (c->apicid >> bits) - 1;
369 core_complex_id = (c->apicid & ((1 << bits) - 1)) >> 3;
370
371 per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
372#endif
373}
374
375u16 amd_get_nb_id(int cpu)
376{
377 u16 id = 0;
378#ifdef CONFIG_SMP
379 id = per_cpu(cpu_llc_id, cpu);
380#endif
381 return id;
382}
383EXPORT_SYMBOL_GPL(amd_get_nb_id);
384
385u32 amd_get_nodes_per_socket(void)
386{
387 return nodes_per_socket;
388}
389EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
390
391static void srat_detect_node(struct cpuinfo_x86 *c)
392{
393#ifdef CONFIG_NUMA
394 int cpu = smp_processor_id();
395 int node;
396 unsigned apicid = c->apicid;
397
398 node = numa_cpu_node(cpu);
399 if (node == NUMA_NO_NODE)
400 node = per_cpu(cpu_llc_id, cpu);
401
402 /*
403 * On multi-fabric platform (e.g. Numascale NumaChip) a
404 * platform-specific handler needs to be called to fixup some
405 * IDs of the CPU.
406 */
407 if (x86_cpuinit.fixup_cpu_id)
408 x86_cpuinit.fixup_cpu_id(c, node);
409
410 if (!node_online(node)) {
411 /*
412 * Two possibilities here:
413 *
414 * - The CPU is missing memory and no node was created. In
415 * that case try picking one from a nearby CPU.
416 *
417 * - The APIC IDs differ from the HyperTransport node IDs
418 * which the K8 northbridge parsing fills in. Assume
419 * they are all increased by a constant offset, but in
420 * the same order as the HT nodeids. If that doesn't
421 * result in a usable node fall back to the path for the
422 * previous case.
423 *
424 * This workaround operates directly on the mapping between
425 * APIC ID and NUMA node, assuming certain relationship
426 * between APIC ID, HT node ID and NUMA topology. As going
427 * through CPU mapping may alter the outcome, directly
428 * access __apicid_to_node[].
429 */
430 int ht_nodeid = c->initial_apicid;
431
432 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
433 node = __apicid_to_node[ht_nodeid];
434 /* Pick a nearby node */
435 if (!node_online(node))
436 node = nearby_node(apicid);
437 }
438 numa_set_node(cpu, node);
439#endif
440}
441
442static void early_init_amd_mc(struct cpuinfo_x86 *c)
443{
444#ifdef CONFIG_SMP
445 unsigned bits, ecx;
446
447 /* Multi core CPU? */
448 if (c->extended_cpuid_level < 0x80000008)
449 return;
450
451 ecx = cpuid_ecx(0x80000008);
452
453 c->x86_max_cores = (ecx & 0xff) + 1;
454
455 /* CPU telling us the core id bits shift? */
456 bits = (ecx >> 12) & 0xF;
457
458 /* Otherwise recompute */
459 if (bits == 0) {
460 while ((1 << bits) < c->x86_max_cores)
461 bits++;
462 }
463
464 c->x86_coreid_bits = bits;
465#endif
466}
467
468static void bsp_init_amd(struct cpuinfo_x86 *c)
469{
470
471#ifdef CONFIG_X86_64
472 if (c->x86 >= 0xf) {
473 unsigned long long tseg;
474
475 /*
476 * Split up direct mapping around the TSEG SMM area.
477 * Don't do it for gbpages because there seems very little
478 * benefit in doing so.
479 */
480 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
481 unsigned long pfn = tseg >> PAGE_SHIFT;
482
483 pr_debug("tseg: %010llx\n", tseg);
484 if (pfn_range_is_mapped(pfn, pfn + 1))
485 set_memory_4k((unsigned long)__va(tseg), 1);
486 }
487 }
488#endif
489
490 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
491
492 if (c->x86 > 0x10 ||
493 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
494 u64 val;
495
496 rdmsrl(MSR_K7_HWCR, val);
497 if (!(val & BIT(24)))
498 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
499 }
500 }
501
502 if (c->x86 == 0x15) {
503 unsigned long upperbit;
504 u32 cpuid, assoc;
505
506 cpuid = cpuid_edx(0x80000005);
507 assoc = cpuid >> 16 & 0xff;
508 upperbit = ((cpuid >> 24) << 10) / assoc;
509
510 va_align.mask = (upperbit - 1) & PAGE_MASK;
511 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
512
513 /* A random value per boot for bit slice [12:upper_bit) */
514 va_align.bits = get_random_int() & va_align.mask;
515 }
516
517 if (cpu_has(c, X86_FEATURE_MWAITX))
518 use_mwaitx_delay();
519
520 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
521 u32 ecx;
522
523 ecx = cpuid_ecx(0x8000001e);
524 nodes_per_socket = ((ecx >> 8) & 7) + 1;
525 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
526 u64 value;
527
528 rdmsrl(MSR_FAM10H_NODE_ID, value);
529 nodes_per_socket = ((value >> 3) & 7) + 1;
530 }
531}
532
533static void early_init_amd(struct cpuinfo_x86 *c)
534{
535 early_init_amd_mc(c);
536
537 /*
538 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
539 * with P/T states and does not stop in deep C-states
540 */
541 if (c->x86_power & (1 << 8)) {
542 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
543 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
544 if (!check_tsc_unstable())
545 set_sched_clock_stable();
546 }
547
548 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
549 if (c->x86_power & BIT(12))
550 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
551
552#ifdef CONFIG_X86_64
553 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
554#else
555 /* Set MTRR capability flag if appropriate */
556 if (c->x86 == 5)
557 if (c->x86_model == 13 || c->x86_model == 9 ||
558 (c->x86_model == 8 && c->x86_mask >= 8))
559 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
560#endif
561#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
562 /*
563 * ApicID can always be treated as an 8-bit value for AMD APIC versions
564 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
565 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
566 * after 16h.
567 */
568 if (cpu_has_apic && c->x86 > 0x16) {
569 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
570 } else if (cpu_has_apic && c->x86 >= 0xf) {
571 /* check CPU config space for extended APIC ID */
572 unsigned int val;
573 val = read_pci_config(0, 24, 0, 0x68);
574 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
575 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
576 }
577#endif
578
579 /*
580 * This is only needed to tell the kernel whether to use VMCALL
581 * and VMMCALL. VMMCALL is never executed except under virt, so
582 * we can set it unconditionally.
583 */
584 set_cpu_cap(c, X86_FEATURE_VMMCALL);
585
586 /* F16h erratum 793, CVE-2013-6885 */
587 if (c->x86 == 0x16 && c->x86_model <= 0xf)
588 msr_set_bit(MSR_AMD64_LS_CFG, 15);
589}
590
591static const int amd_erratum_383[];
592static const int amd_erratum_400[];
593static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
594
595static void init_amd_k8(struct cpuinfo_x86 *c)
596{
597 u32 level;
598 u64 value;
599
600 /* On C+ stepping K8 rep microcode works well for copy/memset */
601 level = cpuid_eax(1);
602 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
603 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
604
605 /*
606 * Some BIOSes incorrectly force this feature, but only K8 revision D
607 * (model = 0x14) and later actually support it.
608 * (AMD Erratum #110, docId: 25759).
609 */
610 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
611 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
612 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
613 value &= ~BIT_64(32);
614 wrmsrl_amd_safe(0xc001100d, value);
615 }
616 }
617
618 if (!c->x86_model_id[0])
619 strcpy(c->x86_model_id, "Hammer");
620
621#ifdef CONFIG_SMP
622 /*
623 * Disable TLB flush filter by setting HWCR.FFDIS on K8
624 * bit 6 of msr C001_0015
625 *
626 * Errata 63 for SH-B3 steppings
627 * Errata 122 for all steppings (F+ have it disabled by default)
628 */
629 msr_set_bit(MSR_K7_HWCR, 6);
630#endif
631}
632
633static void init_amd_gh(struct cpuinfo_x86 *c)
634{
635#ifdef CONFIG_X86_64
636 /* do this for boot cpu */
637 if (c == &boot_cpu_data)
638 check_enable_amd_mmconf_dmi();
639
640 fam10h_check_enable_mmcfg();
641#endif
642
643 /*
644 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
645 * is always needed when GART is enabled, even in a kernel which has no
646 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
647 * If it doesn't, we do it here as suggested by the BKDG.
648 *
649 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
650 */
651 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
652
653 /*
654 * On family 10h BIOS may not have properly enabled WC+ support, causing
655 * it to be converted to CD memtype. This may result in performance
656 * degradation for certain nested-paging guests. Prevent this conversion
657 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
658 *
659 * NOTE: we want to use the _safe accessors so as not to #GP kvm
660 * guests on older kvm hosts.
661 */
662 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
663
664 if (cpu_has_amd_erratum(c, amd_erratum_383))
665 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
666}
667
668static void init_amd_bd(struct cpuinfo_x86 *c)
669{
670 u64 value;
671
672 /* re-enable TopologyExtensions if switched off by BIOS */
673 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
674 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
675
676 if (msr_set_bit(0xc0011005, 54) > 0) {
677 rdmsrl(0xc0011005, value);
678 if (value & BIT_64(54)) {
679 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
680 pr_info(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
681 }
682 }
683 }
684
685 /*
686 * The way access filter has a performance penalty on some workloads.
687 * Disable it on the affected CPUs.
688 */
689 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
690 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
691 value |= 0x1E;
692 wrmsrl_safe(MSR_F15H_IC_CFG, value);
693 }
694 }
695}
696
697static void init_amd(struct cpuinfo_x86 *c)
698{
699 u32 dummy;
700
701 early_init_amd(c);
702
703 /*
704 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
705 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
706 */
707 clear_cpu_cap(c, 0*32+31);
708
709 if (c->x86 >= 0x10)
710 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
711
712 /* get apicid instead of initial apic id from cpuid */
713 c->apicid = hard_smp_processor_id();
714
715 /* K6s reports MCEs but don't actually have all the MSRs */
716 if (c->x86 < 6)
717 clear_cpu_cap(c, X86_FEATURE_MCE);
718
719 switch (c->x86) {
720 case 4: init_amd_k5(c); break;
721 case 5: init_amd_k6(c); break;
722 case 6: init_amd_k7(c); break;
723 case 0xf: init_amd_k8(c); break;
724 case 0x10: init_amd_gh(c); break;
725 case 0x15: init_amd_bd(c); break;
726 }
727
728 /* Enable workaround for FXSAVE leak */
729 if (c->x86 >= 6)
730 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
731
732 cpu_detect_cache_sizes(c);
733
734 /* Multi core CPU? */
735 if (c->extended_cpuid_level >= 0x80000008) {
736 amd_detect_cmp(c);
737 srat_detect_node(c);
738 }
739
740#ifdef CONFIG_X86_32
741 detect_ht(c);
742#endif
743
744 init_amd_cacheinfo(c);
745
746 if (c->x86 >= 0xf)
747 set_cpu_cap(c, X86_FEATURE_K8);
748
749 if (cpu_has_xmm2) {
750 /* MFENCE stops RDTSC speculation */
751 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
752 }
753
754 /*
755 * Family 0x12 and above processors have APIC timer
756 * running in deep C states.
757 */
758 if (c->x86 > 0x11)
759 set_cpu_cap(c, X86_FEATURE_ARAT);
760
761 if (cpu_has_amd_erratum(c, amd_erratum_400))
762 set_cpu_bug(c, X86_BUG_AMD_APIC_C1E);
763
764 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
765
766 /* 3DNow or LM implies PREFETCHW */
767 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
768 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
769 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
770
771 /* AMD CPUs don't reset SS attributes on SYSRET */
772 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
773}
774
775#ifdef CONFIG_X86_32
776static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
777{
778 /* AMD errata T13 (order #21922) */
779 if ((c->x86 == 6)) {
780 /* Duron Rev A0 */
781 if (c->x86_model == 3 && c->x86_mask == 0)
782 size = 64;
783 /* Tbird rev A1/A2 */
784 if (c->x86_model == 4 &&
785 (c->x86_mask == 0 || c->x86_mask == 1))
786 size = 256;
787 }
788 return size;
789}
790#endif
791
792static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
793{
794 u32 ebx, eax, ecx, edx;
795 u16 mask = 0xfff;
796
797 if (c->x86 < 0xf)
798 return;
799
800 if (c->extended_cpuid_level < 0x80000006)
801 return;
802
803 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
804
805 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
806 tlb_lli_4k[ENTRIES] = ebx & mask;
807
808 /*
809 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
810 * characteristics from the CPUID function 0x80000005 instead.
811 */
812 if (c->x86 == 0xf) {
813 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
814 mask = 0xff;
815 }
816
817 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
818 if (!((eax >> 16) & mask))
819 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
820 else
821 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
822
823 /* a 4M entry uses two 2M entries */
824 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
825
826 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
827 if (!(eax & mask)) {
828 /* Erratum 658 */
829 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
830 tlb_lli_2m[ENTRIES] = 1024;
831 } else {
832 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
833 tlb_lli_2m[ENTRIES] = eax & 0xff;
834 }
835 } else
836 tlb_lli_2m[ENTRIES] = eax & mask;
837
838 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
839}
840
841static const struct cpu_dev amd_cpu_dev = {
842 .c_vendor = "AMD",
843 .c_ident = { "AuthenticAMD" },
844#ifdef CONFIG_X86_32
845 .legacy_models = {
846 { .family = 4, .model_names =
847 {
848 [3] = "486 DX/2",
849 [7] = "486 DX/2-WB",
850 [8] = "486 DX/4",
851 [9] = "486 DX/4-WB",
852 [14] = "Am5x86-WT",
853 [15] = "Am5x86-WB"
854 }
855 },
856 },
857 .legacy_cache_size = amd_size_cache,
858#endif
859 .c_early_init = early_init_amd,
860 .c_detect_tlb = cpu_detect_tlb_amd,
861 .c_bsp_init = bsp_init_amd,
862 .c_init = init_amd,
863 .c_x86_vendor = X86_VENDOR_AMD,
864};
865
866cpu_dev_register(amd_cpu_dev);
867
868/*
869 * AMD errata checking
870 *
871 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
872 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
873 * have an OSVW id assigned, which it takes as first argument. Both take a
874 * variable number of family-specific model-stepping ranges created by
875 * AMD_MODEL_RANGE().
876 *
877 * Example:
878 *
879 * const int amd_erratum_319[] =
880 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
881 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
882 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
883 */
884
885#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
886#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
887#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
888 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
889#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
890#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
891#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
892
893static const int amd_erratum_400[] =
894 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
895 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
896
897static const int amd_erratum_383[] =
898 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
899
900
901static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
902{
903 int osvw_id = *erratum++;
904 u32 range;
905 u32 ms;
906
907 if (osvw_id >= 0 && osvw_id < 65536 &&
908 cpu_has(cpu, X86_FEATURE_OSVW)) {
909 u64 osvw_len;
910
911 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
912 if (osvw_id < osvw_len) {
913 u64 osvw_bits;
914
915 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
916 osvw_bits);
917 return osvw_bits & (1ULL << (osvw_id & 0x3f));
918 }
919 }
920
921 /* OSVW unavailable or ID unknown, match family-model-stepping range */
922 ms = (cpu->x86_model << 4) | cpu->x86_mask;
923 while ((range = *erratum++))
924 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
925 (ms >= AMD_MODEL_RANGE_START(range)) &&
926 (ms <= AMD_MODEL_RANGE_END(range)))
927 return true;
928
929 return false;
930}
931
932void set_dr_addr_mask(unsigned long mask, int dr)
933{
934 if (!boot_cpu_has(X86_FEATURE_BPEXT))
935 return;
936
937 switch (dr) {
938 case 0:
939 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
940 break;
941 case 1:
942 case 2:
943 case 3:
944 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
945 break;
946 default:
947 break;
948 }
949}