Loading...
Note: File does not exist in v4.10.11.
1/*
2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * vineetg: Jan 1011
9 * -sched_clock( ) no longer jiffies based. Uses the same clocksource
10 * as gtod
11 *
12 * Rajeshwarr/Vineetg: Mar 2008
13 * -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
14 * for arch independent gettimeofday()
15 * -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
16 *
17 * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
18 */
19
20/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
21 * Each can programmed to go from @count to @limit and optionally
22 * interrupt when that happens.
23 * A write to Control Register clears the Interrupt
24 *
25 * We've designated TIMER0 for events (clockevents)
26 * while TIMER1 for free running (clocksource)
27 *
28 * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
29 * which however is currently broken
30 */
31
32#include <linux/spinlock.h>
33#include <linux/interrupt.h>
34#include <linux/module.h>
35#include <linux/sched.h>
36#include <linux/kernel.h>
37#include <linux/time.h>
38#include <linux/init.h>
39#include <linux/timex.h>
40#include <linux/profile.h>
41#include <linux/clocksource.h>
42#include <linux/clockchips.h>
43#include <asm/irq.h>
44#include <asm/arcregs.h>
45#include <asm/clk.h>
46#include <asm/mach_desc.h>
47
48#include <asm/mcip.h>
49
50/* Timer related Aux registers */
51#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
52#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
53#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
54#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
55#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
56#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
57
58#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
59#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
60
61#define ARC_TIMER_MAX 0xFFFFFFFF
62
63/********** Clock Source Device *********/
64
65#ifdef CONFIG_ARC_HAS_GFRC
66
67static int arc_counter_setup(void)
68{
69 return 1;
70}
71
72static cycle_t arc_counter_read(struct clocksource *cs)
73{
74 unsigned long flags;
75 union {
76#ifdef CONFIG_CPU_BIG_ENDIAN
77 struct { u32 h, l; };
78#else
79 struct { u32 l, h; };
80#endif
81 cycle_t full;
82 } stamp;
83
84 local_irq_save(flags);
85
86 __mcip_cmd(CMD_GFRC_READ_LO, 0);
87 stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);
88
89 __mcip_cmd(CMD_GFRC_READ_HI, 0);
90 stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);
91
92 local_irq_restore(flags);
93
94 return stamp.full;
95}
96
97static struct clocksource arc_counter = {
98 .name = "ARConnect GFRC",
99 .rating = 400,
100 .read = arc_counter_read,
101 .mask = CLOCKSOURCE_MASK(64),
102 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
103};
104
105#else
106
107#ifdef CONFIG_ARC_HAS_RTC
108
109#define AUX_RTC_CTRL 0x103
110#define AUX_RTC_LOW 0x104
111#define AUX_RTC_HIGH 0x105
112
113int arc_counter_setup(void)
114{
115 write_aux_reg(AUX_RTC_CTRL, 1);
116
117 /* Not usable in SMP */
118 return !IS_ENABLED(CONFIG_SMP);
119}
120
121static cycle_t arc_counter_read(struct clocksource *cs)
122{
123 unsigned long status;
124 union {
125#ifdef CONFIG_CPU_BIG_ENDIAN
126 struct { u32 high, low; };
127#else
128 struct { u32 low, high; };
129#endif
130 cycle_t full;
131 } stamp;
132
133
134 __asm__ __volatile(
135 "1: \n"
136 " lr %0, [AUX_RTC_LOW] \n"
137 " lr %1, [AUX_RTC_HIGH] \n"
138 " lr %2, [AUX_RTC_CTRL] \n"
139 " bbit0.nt %2, 31, 1b \n"
140 : "=r" (stamp.low), "=r" (stamp.high), "=r" (status));
141
142 return stamp.full;
143}
144
145static struct clocksource arc_counter = {
146 .name = "ARCv2 RTC",
147 .rating = 350,
148 .read = arc_counter_read,
149 .mask = CLOCKSOURCE_MASK(64),
150 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
151};
152
153#else /* !CONFIG_ARC_HAS_RTC */
154
155/*
156 * set 32bit TIMER1 to keep counting monotonically and wraparound
157 */
158int arc_counter_setup(void)
159{
160 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
161 write_aux_reg(ARC_REG_TIMER1_CNT, 0);
162 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
163
164 /* Not usable in SMP */
165 return !IS_ENABLED(CONFIG_SMP);
166}
167
168static cycle_t arc_counter_read(struct clocksource *cs)
169{
170 return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
171}
172
173static struct clocksource arc_counter = {
174 .name = "ARC Timer1",
175 .rating = 300,
176 .read = arc_counter_read,
177 .mask = CLOCKSOURCE_MASK(32),
178 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
179};
180
181#endif
182#endif
183
184/********** Clock Event Device *********/
185
186/*
187 * Arm the timer to interrupt after @cycles
188 * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
189 */
190static void arc_timer_event_setup(unsigned int cycles)
191{
192 write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
193 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
194
195 write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
196}
197
198
199static int arc_clkevent_set_next_event(unsigned long delta,
200 struct clock_event_device *dev)
201{
202 arc_timer_event_setup(delta);
203 return 0;
204}
205
206static int arc_clkevent_set_periodic(struct clock_event_device *dev)
207{
208 /*
209 * At X Hz, 1 sec = 1000ms -> X cycles;
210 * 10ms -> X / 100 cycles
211 */
212 arc_timer_event_setup(arc_get_core_freq() / HZ);
213 return 0;
214}
215
216static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
217 .name = "ARC Timer0",
218 .features = CLOCK_EVT_FEAT_ONESHOT |
219 CLOCK_EVT_FEAT_PERIODIC,
220 .rating = 300,
221 .irq = TIMER0_IRQ, /* hardwired, no need for resources */
222 .set_next_event = arc_clkevent_set_next_event,
223 .set_state_periodic = arc_clkevent_set_periodic,
224};
225
226static irqreturn_t timer_irq_handler(int irq, void *dev_id)
227{
228 /*
229 * Note that generic IRQ core could have passed @evt for @dev_id if
230 * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
231 */
232 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
233 int irq_reenable = clockevent_state_periodic(evt);
234
235 /*
236 * Any write to CTRL reg ACks the interrupt, we rewrite the
237 * Count when [N]ot [H]alted bit.
238 * And re-arm it if perioid by [I]nterrupt [E]nable bit
239 */
240 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
241
242 evt->event_handler(evt);
243
244 return IRQ_HANDLED;
245}
246
247/*
248 * Setup the local event timer for @cpu
249 */
250void arc_local_timer_setup()
251{
252 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
253 int cpu = smp_processor_id();
254
255 evt->cpumask = cpumask_of(cpu);
256 clockevents_config_and_register(evt, arc_get_core_freq(),
257 0, ARC_TIMER_MAX);
258
259 /* setup the per-cpu timer IRQ handler - for all cpus */
260 arc_request_percpu_irq(TIMER0_IRQ, cpu, timer_irq_handler,
261 "Timer0 (per-cpu-tick)", evt);
262}
263
264/*
265 * Called from start_kernel() - boot CPU only
266 *
267 * -Sets up h/w timers as applicable on boot cpu
268 * -Also sets up any global state needed for timer subsystem:
269 * - for "counting" timer, registers a clocksource, usable across CPUs
270 * (provided that underlying counter h/w is synchronized across cores)
271 * - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic)
272 */
273void __init time_init(void)
274{
275 /*
276 * sets up the timekeeping free-flowing counter which also returns
277 * whether the counter is usable as clocksource
278 */
279 if (arc_counter_setup())
280 /*
281 * CLK upto 4.29 GHz can be safely represented in 32 bits
282 * because Max 32 bit number is 4,294,967,295
283 */
284 clocksource_register_hz(&arc_counter, arc_get_core_freq());
285
286 /* sets up the periodic event timer */
287 arc_local_timer_setup();
288}