1/*
   2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
   3 *
   4 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
   5 *
   6 * Authors: Younghwan Joo <yhwan.joo@samsung.com>
   7 *	    Sylwester Nawrocki <s.nawrocki@samsung.com>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 */
  13#ifndef FIMC_IS_PARAM_H_
  14#define FIMC_IS_PARAM_H_
  15
  16#include <linux/compiler.h>
  17
  18#define FIMC_IS_CONFIG_TIMEOUT		3000 /* ms */
  19#define IS_DEFAULT_WIDTH		1280
  20#define IS_DEFAULT_HEIGHT		720
  21
  22#define DEFAULT_PREVIEW_STILL_WIDTH	IS_DEFAULT_WIDTH
  23#define DEFAULT_PREVIEW_STILL_HEIGHT	IS_DEFAULT_HEIGHT
  24#define DEFAULT_CAPTURE_STILL_WIDTH	IS_DEFAULT_WIDTH
  25#define DEFAULT_CAPTURE_STILL_HEIGHT	IS_DEFAULT_HEIGHT
  26#define DEFAULT_PREVIEW_VIDEO_WIDTH	IS_DEFAULT_WIDTH
  27#define DEFAULT_PREVIEW_VIDEO_HEIGHT	IS_DEFAULT_HEIGHT
  28#define DEFAULT_CAPTURE_VIDEO_WIDTH	IS_DEFAULT_WIDTH
  29#define DEFAULT_CAPTURE_VIDEO_HEIGHT	IS_DEFAULT_HEIGHT
  30
  31#define DEFAULT_PREVIEW_STILL_FRAMERATE	30
  32#define DEFAULT_CAPTURE_STILL_FRAMERATE	15
  33#define DEFAULT_PREVIEW_VIDEO_FRAMERATE	30
  34#define DEFAULT_CAPTURE_VIDEO_FRAMERATE	30
  35
  36#define FIMC_IS_REGION_VER		124 /* IS REGION VERSION 1.24 */
  37#define FIMC_IS_PARAM_SIZE		(FIMC_IS_REGION_SIZE + 1)
  38#define FIMC_IS_MAGIC_NUMBER		0x01020304
  39#define FIMC_IS_PARAM_MAX_SIZE		64 /* in bytes */
  40#define FIMC_IS_PARAM_MAX_ENTRIES	(FIMC_IS_PARAM_MAX_SIZE / 4)
  41
  42/* The parameter bitmask bit definitions. */
  43enum is_param_bit {
  44	PARAM_GLOBAL_SHOTMODE,
  45	PARAM_SENSOR_CONTROL,
  46	PARAM_SENSOR_OTF_OUTPUT,
  47	PARAM_SENSOR_FRAME_RATE,
  48	PARAM_BUFFER_CONTROL,
  49	PARAM_BUFFER_OTF_INPUT,
  50	PARAM_BUFFER_OTF_OUTPUT,
  51	PARAM_ISP_CONTROL,
  52	PARAM_ISP_OTF_INPUT,
  53	PARAM_ISP_DMA1_INPUT,
  54	/* 10 */
  55	PARAM_ISP_DMA2_INPUT,
  56	PARAM_ISP_AA,
  57	PARAM_ISP_FLASH,
  58	PARAM_ISP_AWB,
  59	PARAM_ISP_IMAGE_EFFECT,
  60	PARAM_ISP_ISO,
  61	PARAM_ISP_ADJUST,
  62	PARAM_ISP_METERING,
  63	PARAM_ISP_AFC,
  64	PARAM_ISP_OTF_OUTPUT,
  65	/* 20 */
  66	PARAM_ISP_DMA1_OUTPUT,
  67	PARAM_ISP_DMA2_OUTPUT,
  68	PARAM_DRC_CONTROL,
  69	PARAM_DRC_OTF_INPUT,
  70	PARAM_DRC_DMA_INPUT,
  71	PARAM_DRC_OTF_OUTPUT,
  72	PARAM_SCALERC_CONTROL,
  73	PARAM_SCALERC_OTF_INPUT,
  74	PARAM_SCALERC_IMAGE_EFFECT,
  75	PARAM_SCALERC_INPUT_CROP,
  76	/* 30 */
  77	PARAM_SCALERC_OUTPUT_CROP,
  78	PARAM_SCALERC_OTF_OUTPUT,
  79	PARAM_SCALERC_DMA_OUTPUT,
  80	PARAM_ODC_CONTROL,
  81	PARAM_ODC_OTF_INPUT,
  82	PARAM_ODC_OTF_OUTPUT,
  83	PARAM_DIS_CONTROL,
  84	PARAM_DIS_OTF_INPUT,
  85	PARAM_DIS_OTF_OUTPUT,
  86	PARAM_TDNR_CONTROL,
  87	/* 40 */
  88	PARAM_TDNR_OTF_INPUT,
  89	PARAM_TDNR_1ST_FRAME,
  90	PARAM_TDNR_OTF_OUTPUT,
  91	PARAM_TDNR_DMA_OUTPUT,
  92	PARAM_SCALERP_CONTROL,
  93	PARAM_SCALERP_OTF_INPUT,
  94	PARAM_SCALERP_IMAGE_EFFECT,
  95	PARAM_SCALERP_INPUT_CROP,
  96	PARAM_SCALERP_OUTPUT_CROP,
  97	PARAM_SCALERP_ROTATION,
  98	/* 50 */
  99	PARAM_SCALERP_FLIP,
 100	PARAM_SCALERP_OTF_OUTPUT,
 101	PARAM_SCALERP_DMA_OUTPUT,
 102	PARAM_FD_CONTROL,
 103	PARAM_FD_OTF_INPUT,
 104	PARAM_FD_DMA_INPUT,
 105	PARAM_FD_CONFIG,
 106};
 107
 108/* Interrupt map */
 109#define	FIMC_IS_INT_GENERAL			0
 110#define	FIMC_IS_INT_FRAME_DONE_ISP		1
 111
 112/* Input */
 113
 114#define CONTROL_COMMAND_STOP			0
 115#define CONTROL_COMMAND_START			1
 116
 117#define CONTROL_BYPASS_DISABLE			0
 118#define CONTROL_BYPASS_ENABLE			1
 119
 120#define CONTROL_ERROR_NONE			0
 121
 122/* OTF (On-The-Fly) input interface commands */
 123#define OTF_INPUT_COMMAND_DISABLE		0
 124#define OTF_INPUT_COMMAND_ENABLE		1
 125
 126/* OTF input interface color formats */
 127enum oft_input_fmt {
 128	OTF_INPUT_FORMAT_BAYER			= 0, /* 1 channel */
 129	OTF_INPUT_FORMAT_YUV444			= 1, /* 3 channels */
 130	OTF_INPUT_FORMAT_YUV422			= 2, /* 3 channels */
 131	OTF_INPUT_FORMAT_YUV420			= 3, /* 3 channels */
 132	OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER	= 10,
 133	OTF_INPUT_FORMAT_BAYER_DMA		= 11,
 134};
 135
 136#define OTF_INPUT_ORDER_BAYER_GR_BG		0
 137
 138/* OTF input error codes */
 139#define OTF_INPUT_ERROR_NONE			0 /* Input setting is done */
 140
 141/* DMA input commands */
 142#define DMA_INPUT_COMMAND_DISABLE		0
 143#define DMA_INPUT_COMMAND_ENABLE		1
 144
 145/* DMA input color formats */
 146enum dma_input_fmt {
 147	DMA_INPUT_FORMAT_BAYER			= 0,
 148	DMA_INPUT_FORMAT_YUV444			= 1,
 149	DMA_INPUT_FORMAT_YUV422			= 2,
 150	DMA_INPUT_FORMAT_YUV420			= 3,
 151};
 152
 153enum dma_input_order {
 154	/* (for DMA_INPUT_PLANE_3) */
 155	DMA_INPUT_ORDER_NO	= 0,
 156	/* (only valid at DMA_INPUT_PLANE_2) */
 157	DMA_INPUT_ORDER_CBCR	= 1,
 158	/* (only valid at DMA_INPUT_PLANE_2) */
 159	DMA_INPUT_ORDER_CRCB	= 2,
 160	/* (only valid at DMA_INPUT_PLANE_1 & DMA_INPUT_FORMAT_YUV444) */
 161	DMA_INPUT_ORDER_YCBCR	= 3,
 162	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
 163	DMA_INPUT_ORDER_YYCBCR	= 4,
 164	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
 165	DMA_INPUT_ORDER_YCBYCR	= 5,
 166	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
 167	DMA_INPUT_ORDER_YCRYCB	= 6,
 168	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
 169	DMA_INPUT_ORDER_CBYCRY	= 7,
 170	/* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
 171	DMA_INPUT_ORDER_CRYCBY	= 8,
 172	/* (only valid at DMA_INPUT_FORMAT_BAYER) */
 173	DMA_INPUT_ORDER_GR_BG	= 9
 174};
 175
 176#define DMA_INPUT_ERROR_NONE			0 /* DMA input setting
 177						     is done */
 178/*
 179 * Data output parameter definitions
 180 */
 181#define OTF_OUTPUT_CROP_DISABLE			0
 182#define OTF_OUTPUT_CROP_ENABLE			1
 183
 184#define OTF_OUTPUT_COMMAND_DISABLE		0
 185#define OTF_OUTPUT_COMMAND_ENABLE		1
 186
 187enum otf_output_fmt {
 188	OTF_OUTPUT_FORMAT_YUV444		= 1,
 189	OTF_OUTPUT_FORMAT_YUV422		= 2,
 190	OTF_OUTPUT_FORMAT_YUV420		= 3,
 191	OTF_OUTPUT_FORMAT_RGB			= 4,
 192};
 193
 194#define OTF_OUTPUT_ORDER_BAYER_GR_BG		0
 195
 196#define OTF_OUTPUT_ERROR_NONE			0 /* Output Setting is done */
 197
 198#define DMA_OUTPUT_COMMAND_DISABLE		0
 199#define DMA_OUTPUT_COMMAND_ENABLE		1
 200
 201enum dma_output_fmt {
 202	DMA_OUTPUT_FORMAT_BAYER			= 0,
 203	DMA_OUTPUT_FORMAT_YUV444		= 1,
 204	DMA_OUTPUT_FORMAT_YUV422		= 2,
 205	DMA_OUTPUT_FORMAT_YUV420		= 3,
 206	DMA_OUTPUT_FORMAT_RGB			= 4,
 207};
 208
 209enum dma_output_order {
 210	DMA_OUTPUT_ORDER_NO		= 0,
 211	/* for DMA_OUTPUT_PLANE_3 */
 212	DMA_OUTPUT_ORDER_CBCR		= 1,
 213	/* only valid at DMA_INPUT_PLANE_2) */
 214	DMA_OUTPUT_ORDER_CRCB		= 2,
 215	/* only valid at DMA_OUTPUT_PLANE_2) */
 216	DMA_OUTPUT_ORDER_YYCBCR		= 3,
 217	/* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
 218	DMA_OUTPUT_ORDER_YCBYCR		= 4,
 219	/* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
 220	DMA_OUTPUT_ORDER_YCRYCB		= 5,
 221	/* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
 222	DMA_OUTPUT_ORDER_CBYCRY		= 6,
 223	/* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
 224	DMA_OUTPUT_ORDER_CRYCBY		= 7,
 225	/* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
 226	DMA_OUTPUT_ORDER_YCBCR		= 8,
 227	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 228	DMA_OUTPUT_ORDER_CRYCB		= 9,
 229	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 230	DMA_OUTPUT_ORDER_CRCBY		= 10,
 231	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 232	DMA_OUTPUT_ORDER_CBYCR		= 11,
 233	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 234	DMA_OUTPUT_ORDER_YCRCB		= 12,
 235	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 236	DMA_OUTPUT_ORDER_CBCRY		= 13,
 237	/* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
 238	DMA_OUTPUT_ORDER_BGR		= 14,
 239	/* only valid at DMA_OUTPUT_FORMAT_RGB */
 240	DMA_OUTPUT_ORDER_GB_BG		= 15
 241	/* only valid at DMA_OUTPUT_FORMAT_BAYER */
 242};
 243
 244/* enum dma_output_notify_dma_done */
 245#define DMA_OUTPUT_NOTIFY_DMA_DONE_DISABLE	0
 246#define DMA_OUTPUT_NOTIFY_DMA_DONE_ENABLE	1
 247
 248/* DMA output error codes */
 249#define DMA_OUTPUT_ERROR_NONE			0 /* DMA output setting
 250						     is done */
 251
 252/* ----------------------  Global  ----------------------------------- */
 253#define GLOBAL_SHOTMODE_ERROR_NONE		0 /* shot-mode setting
 254						     is done */
 255/* 3A lock commands */
 256#define ISP_AA_COMMAND_START			0
 257#define ISP_AA_COMMAND_STOP			1
 258
 259/* 3A lock target */
 260#define ISP_AA_TARGET_AF			1
 261#define ISP_AA_TARGET_AE			2
 262#define ISP_AA_TARGET_AWB			4
 263
 264enum isp_af_mode {
 265	ISP_AF_MODE_MANUAL			= 0,
 266	ISP_AF_MODE_SINGLE			= 1,
 267	ISP_AF_MODE_CONTINUOUS			= 2,
 268	ISP_AF_MODE_TOUCH			= 3,
 269	ISP_AF_MODE_SLEEP			= 4,
 270	ISP_AF_MODE_INIT			= 5,
 271	ISP_AF_MODE_SET_CENTER_WINDOW		= 6,
 272	ISP_AF_MODE_SET_TOUCH_WINDOW		= 7
 273};
 274
 275/* Face AF commands */
 276#define ISP_AF_FACE_DISABLE			0
 277#define ISP_AF_FACE_ENABLE			1
 278
 279/* AF range */
 280#define ISP_AF_RANGE_NORMAL			0
 281#define ISP_AF_RANGE_MACRO			1
 282
 283/* AF sleep */
 284#define ISP_AF_SLEEP_OFF			0
 285#define ISP_AF_SLEEP_ON				1
 286
 287/* Continuous AF commands */
 288#define ISP_AF_CONTINUOUS_DISABLE		0
 289#define ISP_AF_CONTINUOUS_ENABLE		1
 290
 291/* ISP AF error codes */
 292#define ISP_AF_ERROR_NONE			0 /* AF mode change is done */
 293#define ISP_AF_ERROR_NONE_LOCK_DONE		1 /* AF lock is done */
 294
 295/* Flash commands */
 296#define ISP_FLASH_COMMAND_DISABLE		0
 297#define ISP_FLASH_COMMAND_MANUAL_ON		1 /* (forced flash) */
 298#define ISP_FLASH_COMMAND_AUTO			2
 299#define ISP_FLASH_COMMAND_TORCH			3 /* 3 sec */
 300
 301/* Flash red-eye commads */
 302#define ISP_FLASH_REDEYE_DISABLE		0
 303#define ISP_FLASH_REDEYE_ENABLE			1
 304
 305/* Flash error codes */
 306#define ISP_FLASH_ERROR_NONE			0 /* Flash setting is done */
 307
 308/* --------------------------  AWB  ------------------------------------ */
 309enum isp_awb_command {
 310	ISP_AWB_COMMAND_AUTO			= 0,
 311	ISP_AWB_COMMAND_ILLUMINATION		= 1,
 312	ISP_AWB_COMMAND_MANUAL			= 2
 313};
 314
 315enum isp_awb_illumination {
 316	ISP_AWB_ILLUMINATION_DAYLIGHT		= 0,
 317	ISP_AWB_ILLUMINATION_CLOUDY		= 1,
 318	ISP_AWB_ILLUMINATION_TUNGSTEN		= 2,
 319	ISP_AWB_ILLUMINATION_FLUORESCENT	= 3
 320};
 321
 322/* ISP AWN error codes */
 323#define ISP_AWB_ERROR_NONE			0 /* AWB setting is done */
 324
 325/* --------------------------  Effect  ----------------------------------- */
 326enum isp_imageeffect_command {
 327	ISP_IMAGE_EFFECT_DISABLE		= 0,
 328	ISP_IMAGE_EFFECT_MONOCHROME		= 1,
 329	ISP_IMAGE_EFFECT_NEGATIVE_MONO		= 2,
 330	ISP_IMAGE_EFFECT_NEGATIVE_COLOR		= 3,
 331	ISP_IMAGE_EFFECT_SEPIA			= 4
 332};
 333
 334/* Image effect error codes */
 335#define ISP_IMAGE_EFFECT_ERROR_NONE		0 /* Image effect setting
 336						     is done */
 337/* ISO commands */
 338#define ISP_ISO_COMMAND_AUTO			0
 339#define ISP_ISO_COMMAND_MANUAL			1
 340
 341/* ISO error codes */
 342#define ISP_ISO_ERROR_NONE			0 /* ISO setting is done */
 343
 344/* ISP adjust commands */
 345#define ISP_ADJUST_COMMAND_AUTO			(0 << 0)
 346#define ISP_ADJUST_COMMAND_MANUAL_CONTRAST	(1 << 0)
 347#define ISP_ADJUST_COMMAND_MANUAL_SATURATION	(1 << 1)
 348#define ISP_ADJUST_COMMAND_MANUAL_SHARPNESS	(1 << 2)
 349#define ISP_ADJUST_COMMAND_MANUAL_EXPOSURE	(1 << 3)
 350#define ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS	(1 << 4)
 351#define ISP_ADJUST_COMMAND_MANUAL_HUE		(1 << 5)
 352#define ISP_ADJUST_COMMAND_MANUAL_ALL		0x7f
 353
 354/* ISP adjustment error codes */
 355#define ISP_ADJUST_ERROR_NONE			0 /* Adjust setting is done */
 356
 357/*
 358 *  Exposure metering
 359 */
 360enum isp_metering_command {
 361	ISP_METERING_COMMAND_AVERAGE	= 0,
 362	ISP_METERING_COMMAND_SPOT	= 1,
 363	ISP_METERING_COMMAND_MATRIX	= 2,
 364	ISP_METERING_COMMAND_CENTER	= 3
 365};
 366
 367/* ISP metering error codes */
 368#define ISP_METERING_ERROR_NONE		0 /* Metering setting is done */
 369
 370/*
 371 * AFC
 372 */
 373enum isp_afc_command {
 374	ISP_AFC_COMMAND_DISABLE		= 0,
 375	ISP_AFC_COMMAND_AUTO		= 1,
 376	ISP_AFC_COMMAND_MANUAL		= 2,
 377};
 378
 379#define ISP_AFC_MANUAL_50HZ		50
 380#define ISP_AFC_MANUAL_60HZ		60
 381
 382/* ------------------------  SCENE MODE--------------------------------- */
 383enum isp_scene_mode {
 384	ISP_SCENE_NONE			= 0,
 385	ISP_SCENE_PORTRAIT		= 1,
 386	ISP_SCENE_LANDSCAPE		= 2,
 387	ISP_SCENE_SPORTS		= 3,
 388	ISP_SCENE_PARTYINDOOR		= 4,
 389	ISP_SCENE_BEACHSNOW		= 5,
 390	ISP_SCENE_SUNSET		= 6,
 391	ISP_SCENE_DAWN			= 7,
 392	ISP_SCENE_FALL			= 8,
 393	ISP_SCENE_NIGHT			= 9,
 394	ISP_SCENE_AGAINSTLIGHTWLIGHT	= 10,
 395	ISP_SCENE_AGAINSTLIGHTWOLIGHT	= 11,
 396	ISP_SCENE_FIRE			= 12,
 397	ISP_SCENE_TEXT			= 13,
 398	ISP_SCENE_CANDLE		= 14
 399};
 400
 401/* AFC error codes */
 402#define ISP_AFC_ERROR_NONE		0 /* AFC setting is done */
 403
 404/* ----------------------------  FD  ------------------------------------- */
 405enum fd_config_command {
 406	FD_CONFIG_COMMAND_MAXIMUM_NUMBER	= 0x1,
 407	FD_CONFIG_COMMAND_ROLL_ANGLE		= 0x2,
 408	FD_CONFIG_COMMAND_YAW_ANGLE		= 0x4,
 409	FD_CONFIG_COMMAND_SMILE_MODE		= 0x8,
 410	FD_CONFIG_COMMAND_BLINK_MODE		= 0x10,
 411	FD_CONFIG_COMMAND_EYES_DETECT		= 0x20,
 412	FD_CONFIG_COMMAND_MOUTH_DETECT		= 0x40,
 413	FD_CONFIG_COMMAND_ORIENTATION		= 0x80,
 414	FD_CONFIG_COMMAND_ORIENTATION_VALUE	= 0x100
 415};
 416
 417enum fd_config_roll_angle {
 418	FD_CONFIG_ROLL_ANGLE_BASIC		= 0,
 419	FD_CONFIG_ROLL_ANGLE_PRECISE_BASIC	= 1,
 420	FD_CONFIG_ROLL_ANGLE_SIDES		= 2,
 421	FD_CONFIG_ROLL_ANGLE_PRECISE_SIDES	= 3,
 422	FD_CONFIG_ROLL_ANGLE_FULL		= 4,
 423	FD_CONFIG_ROLL_ANGLE_PRECISE_FULL	= 5,
 424};
 425
 426enum fd_config_yaw_angle {
 427	FD_CONFIG_YAW_ANGLE_0			= 0,
 428	FD_CONFIG_YAW_ANGLE_45			= 1,
 429	FD_CONFIG_YAW_ANGLE_90			= 2,
 430	FD_CONFIG_YAW_ANGLE_45_90		= 3,
 431};
 432
 433/* Smile mode configuration */
 434#define FD_CONFIG_SMILE_MODE_DISABLE		0
 435#define FD_CONFIG_SMILE_MODE_ENABLE		1
 436
 437/* Blink mode configuration */
 438#define FD_CONFIG_BLINK_MODE_DISABLE		0
 439#define FD_CONFIG_BLINK_MODE_ENABLE		1
 440
 441/* Eyes detection configuration */
 442#define FD_CONFIG_EYES_DETECT_DISABLE		0
 443#define FD_CONFIG_EYES_DETECT_ENABLE		1
 444
 445/* Mouth detection configuration */
 446#define FD_CONFIG_MOUTH_DETECT_DISABLE		0
 447#define FD_CONFIG_MOUTH_DETECT_ENABLE		1
 448
 449#define FD_CONFIG_ORIENTATION_DISABLE		0
 450#define FD_CONFIG_ORIENTATION_ENABLE		1
 451
 452struct param_control {
 453	u32 cmd;
 454	u32 bypass;
 455	u32 buffer_address;
 456	u32 buffer_size;
 457	u32 skip_frames; /* only valid at ISP */
 458	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 6];
 459	u32 err;
 460};
 461
 462struct param_otf_input {
 463	u32 cmd;
 464	u32 width;
 465	u32 height;
 466	u32 format;
 467	u32 bitwidth;
 468	u32 order;
 469	u32 crop_offset_x;
 470	u32 crop_offset_y;
 471	u32 crop_width;
 472	u32 crop_height;
 473	u32 frametime_min;
 474	u32 frametime_max;
 475	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 13];
 476	u32 err;
 477};
 478
 479struct param_dma_input {
 480	u32 cmd;
 481	u32 width;
 482	u32 height;
 483	u32 format;
 484	u32 bitwidth;
 485	u32 plane;
 486	u32 order;
 487	u32 buffer_number;
 488	u32 buffer_address;
 489	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 10];
 490	u32 err;
 491};
 492
 493struct param_otf_output {
 494	u32 cmd;
 495	u32 width;
 496	u32 height;
 497	u32 format;
 498	u32 bitwidth;
 499	u32 order;
 500	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 7];
 501	u32 err;
 502};
 503
 504struct param_dma_output {
 505	u32 cmd;
 506	u32 width;
 507	u32 height;
 508	u32 format;
 509	u32 bitwidth;
 510	u32 plane;
 511	u32 order;
 512	u32 buffer_number;
 513	u32 buffer_address;
 514	u32 notify_dma_done;
 515	u32 dma_out_mask;
 516	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 12];
 517	u32 err;
 518};
 519
 520struct param_global_shotmode {
 521	u32 cmd;
 522	u32 skip_frames;
 523	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 3];
 524	u32 err;
 525};
 526
 527struct param_sensor_framerate {
 528	u32 frame_rate;
 529	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 2];
 530	u32 err;
 531};
 532
 533struct param_isp_aa {
 534	u32 cmd;
 535	u32 target;
 536	u32 mode;
 537	u32 scene;
 538	u32 sleep;
 539	u32 face;
 540	u32 touch_x;
 541	u32 touch_y;
 542	u32 manual_af_setting;
 543	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 10];
 544	u32 err;
 545};
 546
 547struct param_isp_flash {
 548	u32 cmd;
 549	u32 redeye;
 550	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 3];
 551	u32 err;
 552};
 553
 554struct param_isp_awb {
 555	u32 cmd;
 556	u32 illumination;
 557	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 3];
 558	u32 err;
 559};
 560
 561struct param_isp_imageeffect {
 562	u32 cmd;
 563	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 2];
 564	u32 err;
 565};
 566
 567struct param_isp_iso {
 568	u32 cmd;
 569	u32 value;
 570	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 3];
 571	u32 err;
 572};
 573
 574struct param_isp_adjust {
 575	u32 cmd;
 576	s32 contrast;
 577	s32 saturation;
 578	s32 sharpness;
 579	s32 exposure;
 580	s32 brightness;
 581	s32 hue;
 582	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 8];
 583	u32 err;
 584};
 585
 586struct param_isp_metering {
 587	u32 cmd;
 588	u32 win_pos_x;
 589	u32 win_pos_y;
 590	u32 win_width;
 591	u32 win_height;
 592	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 6];
 593	u32 err;
 594};
 595
 596struct param_isp_afc {
 597	u32 cmd;
 598	u32 manual;
 599	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 3];
 600	u32 err;
 601};
 602
 603struct param_scaler_imageeffect {
 604	u32 cmd;
 605	u32 arbitrary_cb;
 606	u32 arbitrary_cr;
 607	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 4];
 608	u32 err;
 609};
 610
 611struct param_scaler_input_crop {
 612	u32 cmd;
 613	u32 crop_offset_x;
 614	u32 crop_offset_y;
 615	u32 crop_width;
 616	u32 crop_height;
 617	u32 in_width;
 618	u32 in_height;
 619	u32 out_width;
 620	u32 out_height;
 621	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 10];
 622	u32 err;
 623};
 624
 625struct param_scaler_output_crop {
 626	u32 cmd;
 627	u32 crop_offset_x;
 628	u32 crop_offset_y;
 629	u32 crop_width;
 630	u32 crop_height;
 631	u32 out_format;
 632	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 7];
 633	u32 err;
 634};
 635
 636struct param_scaler_rotation {
 637	u32 cmd;
 638	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 2];
 639	u32 err;
 640};
 641
 642struct param_scaler_flip {
 643	u32 cmd;
 644	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 2];
 645	u32 err;
 646};
 647
 648struct param_3dnr_1stframe {
 649	u32 cmd;
 650	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 2];
 651	u32 err;
 652};
 653
 654struct param_fd_config {
 655	u32 cmd;
 656	u32 max_number;
 657	u32 roll_angle;
 658	u32 yaw_angle;
 659	u32 smile_mode;
 660	u32 blink_mode;
 661	u32 eye_detect;
 662	u32 mouth_detect;
 663	u32 orientation;
 664	u32 orientation_value;
 665	u32 reserved[FIMC_IS_PARAM_MAX_ENTRIES - 11];
 666	u32 err;
 667};
 668
 669struct global_param {
 670	struct param_global_shotmode	shotmode;
 671};
 672
 673struct sensor_param {
 674	struct param_control		control;
 675	struct param_otf_output		otf_output;
 676	struct param_sensor_framerate	frame_rate;
 677} __packed;
 678
 679struct buffer_param {
 680	struct param_control		control;
 681	struct param_otf_input		otf_input;
 682	struct param_otf_output		otf_output;
 683} __packed;
 684
 685struct isp_param {
 686	struct param_control		control;
 687	struct param_otf_input		otf_input;
 688	struct param_dma_input		dma1_input;
 689	struct param_dma_input		dma2_input;
 690	struct param_isp_aa		aa;
 691	struct param_isp_flash		flash;
 692	struct param_isp_awb		awb;
 693	struct param_isp_imageeffect	effect;
 694	struct param_isp_iso		iso;
 695	struct param_isp_adjust		adjust;
 696	struct param_isp_metering	metering;
 697	struct param_isp_afc		afc;
 698	struct param_otf_output		otf_output;
 699	struct param_dma_output		dma1_output;
 700	struct param_dma_output		dma2_output;
 701} __packed;
 702
 703struct drc_param {
 704	struct param_control		control;
 705	struct param_otf_input		otf_input;
 706	struct param_dma_input		dma_input;
 707	struct param_otf_output		otf_output;
 708} __packed;
 709
 710struct scalerc_param {
 711	struct param_control		control;
 712	struct param_otf_input		otf_input;
 713	struct param_scaler_imageeffect	effect;
 714	struct param_scaler_input_crop	input_crop;
 715	struct param_scaler_output_crop	output_crop;
 716	struct param_otf_output		otf_output;
 717	struct param_dma_output		dma_output;
 718} __packed;
 719
 720struct odc_param {
 721	struct param_control		control;
 722	struct param_otf_input		otf_input;
 723	struct param_otf_output		otf_output;
 724} __packed;
 725
 726struct dis_param {
 727	struct param_control		control;
 728	struct param_otf_output		otf_input;
 729	struct param_otf_output		otf_output;
 730} __packed;
 731
 732struct tdnr_param {
 733	struct param_control		control;
 734	struct param_otf_input		otf_input;
 735	struct param_3dnr_1stframe	frame;
 736	struct param_otf_output		otf_output;
 737	struct param_dma_output		dma_output;
 738} __packed;
 739
 740struct scalerp_param {
 741	struct param_control		control;
 742	struct param_otf_input		otf_input;
 743	struct param_scaler_imageeffect	effect;
 744	struct param_scaler_input_crop	input_crop;
 745	struct param_scaler_output_crop	output_crop;
 746	struct param_scaler_rotation	rotation;
 747	struct param_scaler_flip	flip;
 748	struct param_otf_output		otf_output;
 749	struct param_dma_output		dma_output;
 750} __packed;
 751
 752struct fd_param {
 753	struct param_control		control;
 754	struct param_otf_input		otf_input;
 755	struct param_dma_input		dma_input;
 756	struct param_fd_config		config;
 757} __packed;
 758
 759struct is_param_region {
 760	struct global_param		global;
 761	struct sensor_param		sensor;
 762	struct buffer_param		buf;
 763	struct isp_param		isp;
 764	struct drc_param		drc;
 765	struct scalerc_param		scalerc;
 766	struct odc_param		odc;
 767	struct dis_param		dis;
 768	struct tdnr_param		tdnr;
 769	struct scalerp_param		scalerp;
 770	struct fd_param			fd;
 771} __packed;
 772
 773#define NUMBER_OF_GAMMA_CURVE_POINTS	32
 774
 775struct is_tune_sensor {
 776	u32 exposure;
 777	u32 analog_gain;
 778	u32 frame_rate;
 779	u32 actuator_position;
 780};
 781
 782struct is_tune_gammacurve {
 783	u32 num_pts_x[NUMBER_OF_GAMMA_CURVE_POINTS];
 784	u32 num_pts_y_r[NUMBER_OF_GAMMA_CURVE_POINTS];
 785	u32 num_pts_y_g[NUMBER_OF_GAMMA_CURVE_POINTS];
 786	u32 num_pts_y_b[NUMBER_OF_GAMMA_CURVE_POINTS];
 787};
 788
 789struct is_tune_isp {
 790	/* Brightness level: range 0...100, default 7. */
 791	u32 brightness_level;
 792	/* Contrast level: range -127...127, default 0. */
 793	s32 contrast_level;
 794	/* Saturation level: range -127...127, default 0. */
 795	s32 saturation_level;
 796	s32 gamma_level;
 797	struct is_tune_gammacurve gamma_curve[4];
 798	/* Hue: range -127...127, default 0. */
 799	s32 hue;
 800	/* Sharpness blur: range -127...127, default 0. */
 801	s32 sharpness_blur;
 802	/* Despeckle : range -127~127, default : 0 */
 803	s32 despeckle;
 804	/* Edge color supression: range -127...127, default 0. */
 805	s32 edge_color_supression;
 806	/* Noise reduction: range -127...127, default 0. */
 807	s32 noise_reduction;
 808	/* (32 * 4 + 9) * 4 = 548 bytes */
 809} __packed;
 810
 811struct is_tune_region {
 812	struct is_tune_sensor sensor;
 813	struct is_tune_isp isp;
 814} __packed;
 815
 816struct rational {
 817	u32 num;
 818	u32 den;
 819};
 820
 821struct srational {
 822	s32 num;
 823	s32 den;
 824};
 825
 826#define FLASH_FIRED_SHIFT			0
 827#define FLASH_NOT_FIRED				0
 828#define FLASH_FIRED				1
 829
 830#define FLASH_STROBE_SHIFT			1
 831#define FLASH_STROBE_NO_DETECTION		0
 832#define FLASH_STROBE_RESERVED			1
 833#define FLASH_STROBE_RETURN_LIGHT_NOT_DETECTED	2
 834#define FLASH_STROBE_RETURN_LIGHT_DETECTED	3
 835
 836#define FLASH_MODE_SHIFT			3
 837#define FLASH_MODE_UNKNOWN			0
 838#define FLASH_MODE_COMPULSORY_FLASH_FIRING	1
 839#define FLASH_MODE_COMPULSORY_FLASH_SUPPRESSION	2
 840#define FLASH_MODE_AUTO_MODE			3
 841
 842#define FLASH_FUNCTION_SHIFT			5
 843#define FLASH_FUNCTION_PRESENT			0
 844#define FLASH_FUNCTION_NONE			1
 845
 846#define FLASH_RED_EYE_SHIFT			6
 847#define FLASH_RED_EYE_DISABLED			0
 848#define FLASH_RED_EYE_SUPPORTED			1
 849
 850enum apex_aperture_value {
 851	F1_0	= 0,
 852	F1_4	= 1,
 853	F2_0	= 2,
 854	F2_8	= 3,
 855	F4_0	= 4,
 856	F5_6	= 5,
 857	F8_9	= 6,
 858	F11_0	= 7,
 859	F16_0	= 8,
 860	F22_0	= 9,
 861	F32_0	= 10,
 862};
 863
 864struct exif_attribute {
 865	struct rational exposure_time;
 866	struct srational shutter_speed;
 867	u32 iso_speed_rating;
 868	u32 flash;
 869	struct srational brightness;
 870} __packed;
 871
 872struct is_frame_header {
 873	u32 valid;
 874	u32 bad_mark;
 875	u32 captured;
 876	u32 frame_number;
 877	struct exif_attribute exif;
 878} __packed;
 879
 880struct is_fd_rect {
 881	u32 offset_x;
 882	u32 offset_y;
 883	u32 width;
 884	u32 height;
 885};
 886
 887struct is_face_marker {
 888	u32 frame_number;
 889	struct is_fd_rect face;
 890	struct is_fd_rect left_eye;
 891	struct is_fd_rect right_eye;
 892	struct is_fd_rect mouth;
 893	u32 roll_angle;
 894	u32 yaw_angle;
 895	u32 confidence;
 896	s32 smile_level;
 897	s32 blink_level;
 898} __packed;
 899
 900#define MAX_FRAME_COUNT				8
 901#define MAX_FRAME_COUNT_PREVIEW			4
 902#define MAX_FRAME_COUNT_CAPTURE			1
 903#define MAX_FACE_COUNT				16
 904#define MAX_SHARED_COUNT			500
 905
 906struct is_region {
 907	struct is_param_region parameter;
 908	struct is_tune_region tune;
 909	struct is_frame_header header[MAX_FRAME_COUNT];
 910	struct is_face_marker face[MAX_FACE_COUNT];
 911	u32 shared[MAX_SHARED_COUNT];
 912} __packed;
 913
 914/* Offset to the ISP DMA2 output buffer address array. */
 915#define DMA2_OUTPUT_ADDR_ARRAY_OFFS \
 916	(offsetof(struct is_region, shared) + 32 * sizeof(u32))
 917
 918struct is_debug_frame_descriptor {
 919	u32 sensor_frame_time;
 920	u32 sensor_exposure_time;
 921	s32 sensor_analog_gain;
 922	/* monitor for AA */
 923	u32 req_lei;
 924
 925	u32 next_next_lei_exp;
 926	u32 next_next_lei_a_gain;
 927	u32 next_next_lei_d_gain;
 928	u32 next_next_lei_statlei;
 929	u32 next_next_lei_lei;
 930
 931	u32 dummy0;
 932};
 933
 934#define MAX_FRAMEDESCRIPTOR_CONTEXT_NUM	(30*20)	/* 600 frames */
 935#define MAX_VERSION_DISPLAY_BUF	32
 936
 937struct is_share_region {
 938	u32 frame_time;
 939	u32 exposure_time;
 940	s32 analog_gain;
 941
 942	u32 r_gain;
 943	u32 g_gain;
 944	u32 b_gain;
 945
 946	u32 af_position;
 947	u32 af_status;
 948	/* 0 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_NOMESSAGE */
 949	/* 1 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_REACHED */
 950	/* 2 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_UNABLETOREACH */
 951	/* 3 : SIRC_ISP_CAMERA_AUTOFOCUSMESSAGE_LOST */
 952	/* default : unknown */
 953	u32 af_scene_type;
 954
 955	u32 frame_descp_onoff_control;
 956	u32 frame_descp_update_done;
 957	u32 frame_descp_idx;
 958	u32 frame_descp_max_idx;
 959	struct is_debug_frame_descriptor
 960		dbg_frame_descp_ctx[MAX_FRAMEDESCRIPTOR_CONTEXT_NUM];
 961
 962	u32 chip_id;
 963	u32 chip_rev_no;
 964	u8 isp_fw_ver_no[MAX_VERSION_DISPLAY_BUF];
 965	u8 isp_fw_ver_date[MAX_VERSION_DISPLAY_BUF];
 966	u8 sirc_sdk_ver_no[MAX_VERSION_DISPLAY_BUF];
 967	u8 sirc_sdk_rev_no[MAX_VERSION_DISPLAY_BUF];
 968	u8 sirc_sdk_rev_date[MAX_VERSION_DISPLAY_BUF];
 969} __packed;
 970
 971struct is_debug_control {
 972	u32 write_point;	/* 0~ 500KB boundary */
 973	u32 assert_flag;	/* 0: Not invoked, 1: Invoked */
 974	u32 pabort_flag;	/* 0: Not invoked, 1: Invoked */
 975	u32 dabort_flag;	/* 0: Not invoked, 1: Invoked */
 976};
 977
 978struct sensor_open_extended {
 979	u32 actuator_type;
 980	u32 mclk;
 981	u32 mipi_lane_num;
 982	u32 mipi_speed;
 983	/* Skip setfile loading when fast_open_sensor is not 0 */
 984	u32 fast_open_sensor;
 985	/* Activating sensor self calibration mode (6A3) */
 986	u32 self_calibration_mode;
 987	/* This field is to adjust I2c clock based on ACLK200 */
 988	/* This value is varied in case of rev 0.2 */
 989	u32 i2c_sclk;
 990};
 991
 992struct fimc_is;
 993
 994int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is);
 995int __fimc_is_hw_update_param(struct fimc_is *is, u32 offset);
 996void fimc_is_set_initial_params(struct fimc_is *is);
 997unsigned int __get_pending_param_count(struct fimc_is *is);
 998
 999int  __is_hw_update_params(struct fimc_is *is);
1000void __is_get_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf);
1001void __is_set_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf);
1002void __is_set_sensor(struct fimc_is *is, int fps);
1003void __is_set_isp_aa_ae(struct fimc_is *is);
1004void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye);
1005void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val);
1006void __is_set_isp_effect(struct fimc_is *is, u32 cmd);
1007void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val);
1008void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val);
1009void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val);
1010void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val);
1011void __is_set_drc_control(struct fimc_is *is, u32 val);
1012void __is_set_fd_control(struct fimc_is *is, u32 val);
1013void __is_set_fd_config_maxface(struct fimc_is *is, u32 val);
1014void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val);
1015void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val);
1016void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val);
1017void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val);
1018void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val);
1019void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val);
1020void __is_set_fd_config_orientation(struct fimc_is *is, u32 val);
1021void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val);
1022void __is_set_isp_aa_af_mode(struct fimc_is *is, int cmd);
1023void __is_set_isp_aa_af_start_stop(struct fimc_is *is, int cmd);
1024
1025#endif