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v4.10.11
  1/*
  2 * Copyright 2014 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22
 23#ifndef KFD_CRAT_H_INCLUDED
 24#define KFD_CRAT_H_INCLUDED
 25
 26#include <linux/types.h>
 27
 28#pragma pack(1)
 29
 30/*
 31 * 4CC signature values for the CRAT and CDIT ACPI tables
 32 */
 33
 34#define CRAT_SIGNATURE	"CRAT"
 35#define CDIT_SIGNATURE	"CDIT"
 36
 37/*
 38 * Component Resource Association Table (CRAT)
 39 */
 40
 41#define CRAT_OEMID_LENGTH	6
 42#define CRAT_OEMTABLEID_LENGTH	8
 43#define CRAT_RESERVED_LENGTH	6
 44
 45#define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
 46
 47struct crat_header {
 48	uint32_t	signature;
 49	uint32_t	length;
 50	uint8_t		revision;
 51	uint8_t		checksum;
 52	uint8_t		oem_id[CRAT_OEMID_LENGTH];
 53	uint8_t		oem_table_id[CRAT_OEMTABLEID_LENGTH];
 54	uint32_t	oem_revision;
 55	uint32_t	creator_id;
 56	uint32_t	creator_revision;
 57	uint32_t	total_entries;
 58	uint16_t	num_domains;
 59	uint8_t		reserved[CRAT_RESERVED_LENGTH];
 60};
 61
 62/*
 63 * The header structure is immediately followed by total_entries of the
 64 * data definitions
 65 */
 66
 67/*
 68 * The currently defined subtype entries in the CRAT
 69 */
 70#define CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY	0
 71#define CRAT_SUBTYPE_MEMORY_AFFINITY		1
 72#define CRAT_SUBTYPE_CACHE_AFFINITY		2
 73#define CRAT_SUBTYPE_TLB_AFFINITY		3
 74#define CRAT_SUBTYPE_CCOMPUTE_AFFINITY		4
 75#define CRAT_SUBTYPE_IOLINK_AFFINITY		5
 76#define CRAT_SUBTYPE_MAX			6
 77
 78#define CRAT_SIBLINGMAP_SIZE	32
 79
 80/*
 81 * ComputeUnit Affinity structure and definitions
 82 */
 83#define CRAT_CU_FLAGS_ENABLED		0x00000001
 84#define CRAT_CU_FLAGS_HOT_PLUGGABLE	0x00000002
 85#define CRAT_CU_FLAGS_CPU_PRESENT	0x00000004
 86#define CRAT_CU_FLAGS_GPU_PRESENT	0x00000008
 87#define CRAT_CU_FLAGS_IOMMU_PRESENT	0x00000010
 88#define CRAT_CU_FLAGS_RESERVED		0xffffffe0
 89
 90#define CRAT_COMPUTEUNIT_RESERVED_LENGTH 4
 91
 92struct crat_subtype_computeunit {
 93	uint8_t		type;
 94	uint8_t		length;
 95	uint16_t	reserved;
 96	uint32_t	flags;
 97	uint32_t	proximity_domain;
 98	uint32_t	processor_id_low;
 99	uint16_t	num_cpu_cores;
100	uint16_t	num_simd_cores;
101	uint16_t	max_waves_simd;
102	uint16_t	io_count;
103	uint16_t	hsa_capability;
104	uint16_t	lds_size_in_kb;
105	uint8_t		wave_front_size;
106	uint8_t		num_banks;
107	uint16_t	micro_engine_id;
108	uint8_t		num_arrays;
109	uint8_t		num_cu_per_array;
110	uint8_t		num_simd_per_cu;
111	uint8_t		max_slots_scatch_cu;
112	uint8_t		reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
113};
114
115/*
116 * HSA Memory Affinity structure and definitions
117 */
118#define CRAT_MEM_FLAGS_ENABLED		0x00000001
119#define CRAT_MEM_FLAGS_HOT_PLUGGABLE	0x00000002
120#define CRAT_MEM_FLAGS_NON_VOLATILE	0x00000004
121#define CRAT_MEM_FLAGS_RESERVED		0xfffffff8
122
123#define CRAT_MEMORY_RESERVED_LENGTH 8
124
125struct crat_subtype_memory {
126	uint8_t		type;
127	uint8_t		length;
128	uint16_t	reserved;
129	uint32_t	flags;
130	uint32_t	promixity_domain;
131	uint32_t	base_addr_low;
132	uint32_t	base_addr_high;
133	uint32_t	length_low;
134	uint32_t	length_high;
135	uint32_t	width;
136	uint8_t		reserved2[CRAT_MEMORY_RESERVED_LENGTH];
137};
138
139/*
140 * HSA Cache Affinity structure and definitions
141 */
142#define CRAT_CACHE_FLAGS_ENABLED	0x00000001
143#define CRAT_CACHE_FLAGS_DATA_CACHE	0x00000002
144#define CRAT_CACHE_FLAGS_INST_CACHE	0x00000004
145#define CRAT_CACHE_FLAGS_CPU_CACHE	0x00000008
146#define CRAT_CACHE_FLAGS_SIMD_CACHE	0x00000010
147#define CRAT_CACHE_FLAGS_RESERVED	0xffffffe0
148
149#define CRAT_CACHE_RESERVED_LENGTH 8
150
151struct crat_subtype_cache {
152	uint8_t		type;
153	uint8_t		length;
154	uint16_t	reserved;
155	uint32_t	flags;
156	uint32_t	processor_id_low;
157	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
158	uint32_t	cache_size;
159	uint8_t		cache_level;
160	uint8_t		lines_per_tag;
161	uint16_t	cache_line_size;
162	uint8_t		associativity;
163	uint8_t		cache_properties;
164	uint16_t	cache_latency;
165	uint8_t		reserved2[CRAT_CACHE_RESERVED_LENGTH];
166};
167
168/*
169 * HSA TLB Affinity structure and definitions
170 */
171#define CRAT_TLB_FLAGS_ENABLED	0x00000001
172#define CRAT_TLB_FLAGS_DATA_TLB	0x00000002
173#define CRAT_TLB_FLAGS_INST_TLB	0x00000004
174#define CRAT_TLB_FLAGS_CPU_TLB	0x00000008
175#define CRAT_TLB_FLAGS_SIMD_TLB	0x00000010
176#define CRAT_TLB_FLAGS_RESERVED	0xffffffe0
177
178#define CRAT_TLB_RESERVED_LENGTH 4
179
180struct crat_subtype_tlb {
181	uint8_t		type;
182	uint8_t		length;
183	uint16_t	reserved;
184	uint32_t	flags;
185	uint32_t	processor_id_low;
186	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
187	uint32_t	tlb_level;
188	uint8_t		data_tlb_associativity_2mb;
189	uint8_t		data_tlb_size_2mb;
190	uint8_t		instruction_tlb_associativity_2mb;
191	uint8_t		instruction_tlb_size_2mb;
192	uint8_t		data_tlb_associativity_4k;
193	uint8_t		data_tlb_size_4k;
194	uint8_t		instruction_tlb_associativity_4k;
195	uint8_t		instruction_tlb_size_4k;
196	uint8_t		data_tlb_associativity_1gb;
197	uint8_t		data_tlb_size_1gb;
198	uint8_t		instruction_tlb_associativity_1gb;
199	uint8_t		instruction_tlb_size_1gb;
200	uint8_t		reserved2[CRAT_TLB_RESERVED_LENGTH];
201};
202
203/*
204 * HSA CCompute/APU Affinity structure and definitions
205 */
206#define CRAT_CCOMPUTE_FLAGS_ENABLED	0x00000001
207#define CRAT_CCOMPUTE_FLAGS_RESERVED	0xfffffffe
208
209#define CRAT_CCOMPUTE_RESERVED_LENGTH 16
210
211struct crat_subtype_ccompute {
212	uint8_t		type;
213	uint8_t		length;
214	uint16_t	reserved;
215	uint32_t	flags;
216	uint32_t	processor_id_low;
217	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
218	uint32_t	apu_size;
219	uint8_t		reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
220};
221
222/*
223 * HSA IO Link Affinity structure and definitions
224 */
225#define CRAT_IOLINK_FLAGS_ENABLED	0x00000001
226#define CRAT_IOLINK_FLAGS_COHERENCY	0x00000002
227#define CRAT_IOLINK_FLAGS_RESERVED	0xfffffffc
228
229/*
230 * IO interface types
231 */
232#define CRAT_IOLINK_TYPE_UNDEFINED	0
233#define CRAT_IOLINK_TYPE_HYPERTRANSPORT	1
234#define CRAT_IOLINK_TYPE_PCIEXPRESS	2
235#define CRAT_IOLINK_TYPE_OTHER		3
236#define CRAT_IOLINK_TYPE_MAX		255
237
238#define CRAT_IOLINK_RESERVED_LENGTH 24
239
240struct crat_subtype_iolink {
241	uint8_t		type;
242	uint8_t		length;
243	uint16_t	reserved;
244	uint32_t	flags;
245	uint32_t	proximity_domain_from;
246	uint32_t	proximity_domain_to;
247	uint8_t		io_interface_type;
248	uint8_t		version_major;
249	uint16_t	version_minor;
250	uint32_t	minimum_latency;
251	uint32_t	maximum_latency;
252	uint32_t	minimum_bandwidth_mbs;
253	uint32_t	maximum_bandwidth_mbs;
254	uint32_t	recommended_transfer_size;
255	uint8_t		reserved2[CRAT_IOLINK_RESERVED_LENGTH];
256};
257
258/*
259 * HSA generic sub-type header
260 */
261
262#define CRAT_SUBTYPE_FLAGS_ENABLED 0x00000001
263
264struct crat_subtype_generic {
265	uint8_t		type;
266	uint8_t		length;
267	uint16_t	reserved;
268	uint32_t	flags;
269};
270
271/*
272 * Component Locality Distance Information Table (CDIT)
273 */
274#define CDIT_OEMID_LENGTH	6
275#define CDIT_OEMTABLEID_LENGTH	8
276
277struct cdit_header {
278	uint32_t	signature;
279	uint32_t	length;
280	uint8_t		revision;
281	uint8_t		checksum;
282	uint8_t		oem_id[CDIT_OEMID_LENGTH];
283	uint8_t		oem_table_id[CDIT_OEMTABLEID_LENGTH];
284	uint32_t	oem_revision;
285	uint32_t	creator_id;
286	uint32_t	creator_revision;
287	uint32_t	total_entries;
288	uint16_t	num_domains;
289	uint8_t		entry[1];
290};
291
292#pragma pack()
293
294#endif /* KFD_CRAT_H_INCLUDED */
v4.6
  1/*
  2 * Copyright 2014 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22
 23#ifndef KFD_CRAT_H_INCLUDED
 24#define KFD_CRAT_H_INCLUDED
 25
 26#include <linux/types.h>
 27
 28#pragma pack(1)
 29
 30/*
 31 * 4CC signature values for the CRAT and CDIT ACPI tables
 32 */
 33
 34#define CRAT_SIGNATURE	"CRAT"
 35#define CDIT_SIGNATURE	"CDIT"
 36
 37/*
 38 * Component Resource Association Table (CRAT)
 39 */
 40
 41#define CRAT_OEMID_LENGTH	6
 42#define CRAT_OEMTABLEID_LENGTH	8
 43#define CRAT_RESERVED_LENGTH	6
 44
 45#define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
 46
 47struct crat_header {
 48	uint32_t	signature;
 49	uint32_t	length;
 50	uint8_t		revision;
 51	uint8_t		checksum;
 52	uint8_t		oem_id[CRAT_OEMID_LENGTH];
 53	uint8_t		oem_table_id[CRAT_OEMTABLEID_LENGTH];
 54	uint32_t	oem_revision;
 55	uint32_t	creator_id;
 56	uint32_t	creator_revision;
 57	uint32_t	total_entries;
 58	uint16_t	num_domains;
 59	uint8_t		reserved[CRAT_RESERVED_LENGTH];
 60};
 61
 62/*
 63 * The header structure is immediately followed by total_entries of the
 64 * data definitions
 65 */
 66
 67/*
 68 * The currently defined subtype entries in the CRAT
 69 */
 70#define CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY	0
 71#define CRAT_SUBTYPE_MEMORY_AFFINITY		1
 72#define CRAT_SUBTYPE_CACHE_AFFINITY		2
 73#define CRAT_SUBTYPE_TLB_AFFINITY		3
 74#define CRAT_SUBTYPE_CCOMPUTE_AFFINITY		4
 75#define CRAT_SUBTYPE_IOLINK_AFFINITY		5
 76#define CRAT_SUBTYPE_MAX			6
 77
 78#define CRAT_SIBLINGMAP_SIZE	32
 79
 80/*
 81 * ComputeUnit Affinity structure and definitions
 82 */
 83#define CRAT_CU_FLAGS_ENABLED		0x00000001
 84#define CRAT_CU_FLAGS_HOT_PLUGGABLE	0x00000002
 85#define CRAT_CU_FLAGS_CPU_PRESENT	0x00000004
 86#define CRAT_CU_FLAGS_GPU_PRESENT	0x00000008
 87#define CRAT_CU_FLAGS_IOMMU_PRESENT	0x00000010
 88#define CRAT_CU_FLAGS_RESERVED		0xffffffe0
 89
 90#define CRAT_COMPUTEUNIT_RESERVED_LENGTH 4
 91
 92struct crat_subtype_computeunit {
 93	uint8_t		type;
 94	uint8_t		length;
 95	uint16_t	reserved;
 96	uint32_t	flags;
 97	uint32_t	proximity_domain;
 98	uint32_t	processor_id_low;
 99	uint16_t	num_cpu_cores;
100	uint16_t	num_simd_cores;
101	uint16_t	max_waves_simd;
102	uint16_t	io_count;
103	uint16_t	hsa_capability;
104	uint16_t	lds_size_in_kb;
105	uint8_t		wave_front_size;
106	uint8_t		num_banks;
107	uint16_t	micro_engine_id;
108	uint8_t		num_arrays;
109	uint8_t		num_cu_per_array;
110	uint8_t		num_simd_per_cu;
111	uint8_t		max_slots_scatch_cu;
112	uint8_t		reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
113};
114
115/*
116 * HSA Memory Affinity structure and definitions
117 */
118#define CRAT_MEM_FLAGS_ENABLED		0x00000001
119#define CRAT_MEM_FLAGS_HOT_PLUGGABLE	0x00000002
120#define CRAT_MEM_FLAGS_NON_VOLATILE	0x00000004
121#define CRAT_MEM_FLAGS_RESERVED		0xfffffff8
122
123#define CRAT_MEMORY_RESERVED_LENGTH 8
124
125struct crat_subtype_memory {
126	uint8_t		type;
127	uint8_t		length;
128	uint16_t	reserved;
129	uint32_t	flags;
130	uint32_t	promixity_domain;
131	uint32_t	base_addr_low;
132	uint32_t	base_addr_high;
133	uint32_t	length_low;
134	uint32_t	length_high;
135	uint32_t	width;
136	uint8_t		reserved2[CRAT_MEMORY_RESERVED_LENGTH];
137};
138
139/*
140 * HSA Cache Affinity structure and definitions
141 */
142#define CRAT_CACHE_FLAGS_ENABLED	0x00000001
143#define CRAT_CACHE_FLAGS_DATA_CACHE	0x00000002
144#define CRAT_CACHE_FLAGS_INST_CACHE	0x00000004
145#define CRAT_CACHE_FLAGS_CPU_CACHE	0x00000008
146#define CRAT_CACHE_FLAGS_SIMD_CACHE	0x00000010
147#define CRAT_CACHE_FLAGS_RESERVED	0xffffffe0
148
149#define CRAT_CACHE_RESERVED_LENGTH 8
150
151struct crat_subtype_cache {
152	uint8_t		type;
153	uint8_t		length;
154	uint16_t	reserved;
155	uint32_t	flags;
156	uint32_t	processor_id_low;
157	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
158	uint32_t	cache_size;
159	uint8_t		cache_level;
160	uint8_t		lines_per_tag;
161	uint16_t	cache_line_size;
162	uint8_t		associativity;
163	uint8_t		cache_properties;
164	uint16_t	cache_latency;
165	uint8_t		reserved2[CRAT_CACHE_RESERVED_LENGTH];
166};
167
168/*
169 * HSA TLB Affinity structure and definitions
170 */
171#define CRAT_TLB_FLAGS_ENABLED	0x00000001
172#define CRAT_TLB_FLAGS_DATA_TLB	0x00000002
173#define CRAT_TLB_FLAGS_INST_TLB	0x00000004
174#define CRAT_TLB_FLAGS_CPU_TLB	0x00000008
175#define CRAT_TLB_FLAGS_SIMD_TLB	0x00000010
176#define CRAT_TLB_FLAGS_RESERVED	0xffffffe0
177
178#define CRAT_TLB_RESERVED_LENGTH 4
179
180struct crat_subtype_tlb {
181	uint8_t		type;
182	uint8_t		length;
183	uint16_t	reserved;
184	uint32_t	flags;
185	uint32_t	processor_id_low;
186	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
187	uint32_t	tlb_level;
188	uint8_t		data_tlb_associativity_2mb;
189	uint8_t		data_tlb_size_2mb;
190	uint8_t		instruction_tlb_associativity_2mb;
191	uint8_t		instruction_tlb_size_2mb;
192	uint8_t		data_tlb_associativity_4k;
193	uint8_t		data_tlb_size_4k;
194	uint8_t		instruction_tlb_associativity_4k;
195	uint8_t		instruction_tlb_size_4k;
196	uint8_t		data_tlb_associativity_1gb;
197	uint8_t		data_tlb_size_1gb;
198	uint8_t		instruction_tlb_associativity_1gb;
199	uint8_t		instruction_tlb_size_1gb;
200	uint8_t		reserved2[CRAT_TLB_RESERVED_LENGTH];
201};
202
203/*
204 * HSA CCompute/APU Affinity structure and definitions
205 */
206#define CRAT_CCOMPUTE_FLAGS_ENABLED	0x00000001
207#define CRAT_CCOMPUTE_FLAGS_RESERVED	0xfffffffe
208
209#define CRAT_CCOMPUTE_RESERVED_LENGTH 16
210
211struct crat_subtype_ccompute {
212	uint8_t		type;
213	uint8_t		length;
214	uint16_t	reserved;
215	uint32_t	flags;
216	uint32_t	processor_id_low;
217	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
218	uint32_t	apu_size;
219	uint8_t		reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
220};
221
222/*
223 * HSA IO Link Affinity structure and definitions
224 */
225#define CRAT_IOLINK_FLAGS_ENABLED	0x00000001
226#define CRAT_IOLINK_FLAGS_COHERENCY	0x00000002
227#define CRAT_IOLINK_FLAGS_RESERVED	0xfffffffc
228
229/*
230 * IO interface types
231 */
232#define CRAT_IOLINK_TYPE_UNDEFINED	0
233#define CRAT_IOLINK_TYPE_HYPERTRANSPORT	1
234#define CRAT_IOLINK_TYPE_PCIEXPRESS	2
235#define CRAT_IOLINK_TYPE_OTHER		3
236#define CRAT_IOLINK_TYPE_MAX		255
237
238#define CRAT_IOLINK_RESERVED_LENGTH 24
239
240struct crat_subtype_iolink {
241	uint8_t		type;
242	uint8_t		length;
243	uint16_t	reserved;
244	uint32_t	flags;
245	uint32_t	proximity_domain_from;
246	uint32_t	proximity_domain_to;
247	uint8_t		io_interface_type;
248	uint8_t		version_major;
249	uint16_t	version_minor;
250	uint32_t	minimum_latency;
251	uint32_t	maximum_latency;
252	uint32_t	minimum_bandwidth_mbs;
253	uint32_t	maximum_bandwidth_mbs;
254	uint32_t	recommended_transfer_size;
255	uint8_t		reserved2[CRAT_IOLINK_RESERVED_LENGTH];
256};
257
258/*
259 * HSA generic sub-type header
260 */
261
262#define CRAT_SUBTYPE_FLAGS_ENABLED 0x00000001
263
264struct crat_subtype_generic {
265	uint8_t		type;
266	uint8_t		length;
267	uint16_t	reserved;
268	uint32_t	flags;
269};
270
271/*
272 * Component Locality Distance Information Table (CDIT)
273 */
274#define CDIT_OEMID_LENGTH	6
275#define CDIT_OEMTABLEID_LENGTH	8
276
277struct cdit_header {
278	uint32_t	signature;
279	uint32_t	length;
280	uint8_t		revision;
281	uint8_t		checksum;
282	uint8_t		oem_id[CDIT_OEMID_LENGTH];
283	uint8_t		oem_table_id[CDIT_OEMTABLEID_LENGTH];
284	uint32_t	oem_revision;
285	uint32_t	creator_id;
286	uint32_t	creator_revision;
287	uint32_t	total_entries;
288	uint16_t	num_domains;
289	uint8_t		entry[1];
290};
291
292#pragma pack()
293
294#endif /* KFD_CRAT_H_INCLUDED */