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1/*
2 * hw.h - DesignWare HS OTG Controller hardware definitions
3 *
4 * Copyright 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_HW_H__
38#define __DWC2_HW_H__
39
40#define HSOTG_REG(x) (x)
41
42#define GOTGCTL HSOTG_REG(0x000)
43#define GOTGCTL_CHIRPEN (1 << 27)
44#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
45#define GOTGCTL_MULT_VALID_BC_SHIFT 22
46#define GOTGCTL_OTGVER (1 << 20)
47#define GOTGCTL_BSESVLD (1 << 19)
48#define GOTGCTL_ASESVLD (1 << 18)
49#define GOTGCTL_DBNC_SHORT (1 << 17)
50#define GOTGCTL_CONID_B (1 << 16)
51#define GOTGCTL_DBNCE_FLTR_BYPASS (1 << 15)
52#define GOTGCTL_DEVHNPEN (1 << 11)
53#define GOTGCTL_HSTSETHNPEN (1 << 10)
54#define GOTGCTL_HNPREQ (1 << 9)
55#define GOTGCTL_HSTNEGSCS (1 << 8)
56#define GOTGCTL_SESREQ (1 << 1)
57#define GOTGCTL_SESREQSCS (1 << 0)
58
59#define GOTGINT HSOTG_REG(0x004)
60#define GOTGINT_DBNCE_DONE (1 << 19)
61#define GOTGINT_A_DEV_TOUT_CHG (1 << 18)
62#define GOTGINT_HST_NEG_DET (1 << 17)
63#define GOTGINT_HST_NEG_SUC_STS_CHNG (1 << 9)
64#define GOTGINT_SES_REQ_SUC_STS_CHNG (1 << 8)
65#define GOTGINT_SES_END_DET (1 << 2)
66
67#define GAHBCFG HSOTG_REG(0x008)
68#define GAHBCFG_AHB_SINGLE (1 << 23)
69#define GAHBCFG_NOTI_ALL_DMA_WRIT (1 << 22)
70#define GAHBCFG_REM_MEM_SUPP (1 << 21)
71#define GAHBCFG_P_TXF_EMP_LVL (1 << 8)
72#define GAHBCFG_NP_TXF_EMP_LVL (1 << 7)
73#define GAHBCFG_DMA_EN (1 << 5)
74#define GAHBCFG_HBSTLEN_MASK (0xf << 1)
75#define GAHBCFG_HBSTLEN_SHIFT 1
76#define GAHBCFG_HBSTLEN_SINGLE 0
77#define GAHBCFG_HBSTLEN_INCR 1
78#define GAHBCFG_HBSTLEN_INCR4 3
79#define GAHBCFG_HBSTLEN_INCR8 5
80#define GAHBCFG_HBSTLEN_INCR16 7
81#define GAHBCFG_GLBL_INTR_EN (1 << 0)
82#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
83 GAHBCFG_NP_TXF_EMP_LVL | \
84 GAHBCFG_DMA_EN | \
85 GAHBCFG_GLBL_INTR_EN)
86
87#define GUSBCFG HSOTG_REG(0x00C)
88#define GUSBCFG_FORCEDEVMODE (1 << 30)
89#define GUSBCFG_FORCEHOSTMODE (1 << 29)
90#define GUSBCFG_TXENDDELAY (1 << 28)
91#define GUSBCFG_ICTRAFFICPULLREMOVE (1 << 27)
92#define GUSBCFG_ICUSBCAP (1 << 26)
93#define GUSBCFG_ULPI_INT_PROT_DIS (1 << 25)
94#define GUSBCFG_INDICATORPASSTHROUGH (1 << 24)
95#define GUSBCFG_INDICATORCOMPLEMENT (1 << 23)
96#define GUSBCFG_TERMSELDLPULSE (1 << 22)
97#define GUSBCFG_ULPI_INT_VBUS_IND (1 << 21)
98#define GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20)
99#define GUSBCFG_ULPI_CLK_SUSP_M (1 << 19)
100#define GUSBCFG_ULPI_AUTO_RES (1 << 18)
101#define GUSBCFG_ULPI_FS_LS (1 << 17)
102#define GUSBCFG_OTG_UTMI_FS_SEL (1 << 16)
103#define GUSBCFG_PHY_LP_CLK_SEL (1 << 15)
104#define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
105#define GUSBCFG_USBTRDTIM_SHIFT 10
106#define GUSBCFG_HNPCAP (1 << 9)
107#define GUSBCFG_SRPCAP (1 << 8)
108#define GUSBCFG_DDRSEL (1 << 7)
109#define GUSBCFG_PHYSEL (1 << 6)
110#define GUSBCFG_FSINTF (1 << 5)
111#define GUSBCFG_ULPI_UTMI_SEL (1 << 4)
112#define GUSBCFG_PHYIF16 (1 << 3)
113#define GUSBCFG_PHYIF8 (0 << 3)
114#define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
115#define GUSBCFG_TOUTCAL_SHIFT 0
116#define GUSBCFG_TOUTCAL_LIMIT 0x7
117#define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
118
119#define GRSTCTL HSOTG_REG(0x010)
120#define GRSTCTL_AHBIDLE (1 << 31)
121#define GRSTCTL_DMAREQ (1 << 30)
122#define GRSTCTL_TXFNUM_MASK (0x1f << 6)
123#define GRSTCTL_TXFNUM_SHIFT 6
124#define GRSTCTL_TXFNUM_LIMIT 0x1f
125#define GRSTCTL_TXFNUM(_x) ((_x) << 6)
126#define GRSTCTL_TXFFLSH (1 << 5)
127#define GRSTCTL_RXFFLSH (1 << 4)
128#define GRSTCTL_IN_TKNQ_FLSH (1 << 3)
129#define GRSTCTL_FRMCNTRRST (1 << 2)
130#define GRSTCTL_HSFTRST (1 << 1)
131#define GRSTCTL_CSFTRST (1 << 0)
132
133#define GINTSTS HSOTG_REG(0x014)
134#define GINTMSK HSOTG_REG(0x018)
135#define GINTSTS_WKUPINT (1 << 31)
136#define GINTSTS_SESSREQINT (1 << 30)
137#define GINTSTS_DISCONNINT (1 << 29)
138#define GINTSTS_CONIDSTSCHNG (1 << 28)
139#define GINTSTS_LPMTRANRCVD (1 << 27)
140#define GINTSTS_PTXFEMP (1 << 26)
141#define GINTSTS_HCHINT (1 << 25)
142#define GINTSTS_PRTINT (1 << 24)
143#define GINTSTS_RESETDET (1 << 23)
144#define GINTSTS_FET_SUSP (1 << 22)
145#define GINTSTS_INCOMPL_IP (1 << 21)
146#define GINTSTS_INCOMPL_SOOUT (1 << 21)
147#define GINTSTS_INCOMPL_SOIN (1 << 20)
148#define GINTSTS_OEPINT (1 << 19)
149#define GINTSTS_IEPINT (1 << 18)
150#define GINTSTS_EPMIS (1 << 17)
151#define GINTSTS_RESTOREDONE (1 << 16)
152#define GINTSTS_EOPF (1 << 15)
153#define GINTSTS_ISOUTDROP (1 << 14)
154#define GINTSTS_ENUMDONE (1 << 13)
155#define GINTSTS_USBRST (1 << 12)
156#define GINTSTS_USBSUSP (1 << 11)
157#define GINTSTS_ERLYSUSP (1 << 10)
158#define GINTSTS_I2CINT (1 << 9)
159#define GINTSTS_ULPI_CK_INT (1 << 8)
160#define GINTSTS_GOUTNAKEFF (1 << 7)
161#define GINTSTS_GINNAKEFF (1 << 6)
162#define GINTSTS_NPTXFEMP (1 << 5)
163#define GINTSTS_RXFLVL (1 << 4)
164#define GINTSTS_SOF (1 << 3)
165#define GINTSTS_OTGINT (1 << 2)
166#define GINTSTS_MODEMIS (1 << 1)
167#define GINTSTS_CURMODE_HOST (1 << 0)
168
169#define GRXSTSR HSOTG_REG(0x01C)
170#define GRXSTSP HSOTG_REG(0x020)
171#define GRXSTS_FN_MASK (0x7f << 25)
172#define GRXSTS_FN_SHIFT 25
173#define GRXSTS_PKTSTS_MASK (0xf << 17)
174#define GRXSTS_PKTSTS_SHIFT 17
175#define GRXSTS_PKTSTS_GLOBALOUTNAK 1
176#define GRXSTS_PKTSTS_OUTRX 2
177#define GRXSTS_PKTSTS_HCHIN 2
178#define GRXSTS_PKTSTS_OUTDONE 3
179#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
180#define GRXSTS_PKTSTS_SETUPDONE 4
181#define GRXSTS_PKTSTS_DATATOGGLEERR 5
182#define GRXSTS_PKTSTS_SETUPRX 6
183#define GRXSTS_PKTSTS_HCHHALTED 7
184#define GRXSTS_HCHNUM_MASK (0xf << 0)
185#define GRXSTS_HCHNUM_SHIFT 0
186#define GRXSTS_DPID_MASK (0x3 << 15)
187#define GRXSTS_DPID_SHIFT 15
188#define GRXSTS_BYTECNT_MASK (0x7ff << 4)
189#define GRXSTS_BYTECNT_SHIFT 4
190#define GRXSTS_EPNUM_MASK (0xf << 0)
191#define GRXSTS_EPNUM_SHIFT 0
192
193#define GRXFSIZ HSOTG_REG(0x024)
194#define GRXFSIZ_DEPTH_MASK (0xffff << 0)
195#define GRXFSIZ_DEPTH_SHIFT 0
196
197#define GNPTXFSIZ HSOTG_REG(0x028)
198/* Use FIFOSIZE_* constants to access this register */
199
200#define GNPTXSTS HSOTG_REG(0x02C)
201#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
202#define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
203#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16)
204#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16
205#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff)
206#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0)
207#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0
208#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
209
210#define GI2CCTL HSOTG_REG(0x0030)
211#define GI2CCTL_BSYDNE (1 << 31)
212#define GI2CCTL_RW (1 << 30)
213#define GI2CCTL_I2CDATSE0 (1 << 28)
214#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
215#define GI2CCTL_I2CDEVADDR_SHIFT 26
216#define GI2CCTL_I2CSUSPCTL (1 << 25)
217#define GI2CCTL_ACK (1 << 24)
218#define GI2CCTL_I2CEN (1 << 23)
219#define GI2CCTL_ADDR_MASK (0x7f << 16)
220#define GI2CCTL_ADDR_SHIFT 16
221#define GI2CCTL_REGADDR_MASK (0xff << 8)
222#define GI2CCTL_REGADDR_SHIFT 8
223#define GI2CCTL_RWDATA_MASK (0xff << 0)
224#define GI2CCTL_RWDATA_SHIFT 0
225
226#define GPVNDCTL HSOTG_REG(0x0034)
227#define GGPIO HSOTG_REG(0x0038)
228#define GUID HSOTG_REG(0x003c)
229#define GSNPSID HSOTG_REG(0x0040)
230#define GHWCFG1 HSOTG_REG(0x0044)
231
232#define GHWCFG2 HSOTG_REG(0x0048)
233#define GHWCFG2_OTG_ENABLE_IC_USB (1 << 31)
234#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
235#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
236#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
237#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
238#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
239#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
240#define GHWCFG2_MULTI_PROC_INT (1 << 20)
241#define GHWCFG2_DYNAMIC_FIFO (1 << 19)
242#define GHWCFG2_PERIO_EP_SUPPORTED (1 << 18)
243#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
244#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
245#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
246#define GHWCFG2_NUM_DEV_EP_SHIFT 10
247#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
248#define GHWCFG2_FS_PHY_TYPE_SHIFT 8
249#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
250#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1
251#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2
252#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
253#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
254#define GHWCFG2_HS_PHY_TYPE_SHIFT 6
255#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
256#define GHWCFG2_HS_PHY_TYPE_UTMI 1
257#define GHWCFG2_HS_PHY_TYPE_ULPI 2
258#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
259#define GHWCFG2_POINT2POINT (1 << 5)
260#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
261#define GHWCFG2_ARCHITECTURE_SHIFT 3
262#define GHWCFG2_SLAVE_ONLY_ARCH 0
263#define GHWCFG2_EXT_DMA_ARCH 1
264#define GHWCFG2_INT_DMA_ARCH 2
265#define GHWCFG2_OP_MODE_MASK (0x7 << 0)
266#define GHWCFG2_OP_MODE_SHIFT 0
267#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0
268#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1
269#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2
270#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
271#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
272#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
273#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
274#define GHWCFG2_OP_MODE_UNDEFINED 7
275
276#define GHWCFG3 HSOTG_REG(0x004c)
277#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
278#define GHWCFG3_DFIFO_DEPTH_SHIFT 16
279#define GHWCFG3_OTG_LPM_EN (1 << 15)
280#define GHWCFG3_BC_SUPPORT (1 << 14)
281#define GHWCFG3_OTG_ENABLE_HSIC (1 << 13)
282#define GHWCFG3_ADP_SUPP (1 << 12)
283#define GHWCFG3_SYNCH_RESET_TYPE (1 << 11)
284#define GHWCFG3_OPTIONAL_FEATURES (1 << 10)
285#define GHWCFG3_VENDOR_CTRL_IF (1 << 9)
286#define GHWCFG3_I2C (1 << 8)
287#define GHWCFG3_OTG_FUNC (1 << 7)
288#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
289#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
290#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
291#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
292
293#define GHWCFG4 HSOTG_REG(0x0050)
294#define GHWCFG4_DESC_DMA_DYN (1 << 31)
295#define GHWCFG4_DESC_DMA (1 << 30)
296#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
297#define GHWCFG4_NUM_IN_EPS_SHIFT 26
298#define GHWCFG4_DED_FIFO_EN (1 << 25)
299#define GHWCFG4_DED_FIFO_SHIFT 25
300#define GHWCFG4_SESSION_END_FILT_EN (1 << 24)
301#define GHWCFG4_B_VALID_FILT_EN (1 << 23)
302#define GHWCFG4_A_VALID_FILT_EN (1 << 22)
303#define GHWCFG4_VBUS_VALID_FILT_EN (1 << 21)
304#define GHWCFG4_IDDIG_FILT_EN (1 << 20)
305#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
306#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
307#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
308#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
309#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
310#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
311#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
312#define GHWCFG4_XHIBER (1 << 7)
313#define GHWCFG4_HIBER (1 << 6)
314#define GHWCFG4_MIN_AHB_FREQ (1 << 5)
315#define GHWCFG4_POWER_OPTIMIZ (1 << 4)
316#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
317#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
318
319#define GLPMCFG HSOTG_REG(0x0054)
320#define GLPMCFG_INV_SEL_HSIC (1 << 31)
321#define GLPMCFG_HSIC_CONNECT (1 << 30)
322#define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25)
323#define GLPMCFG_RETRY_COUNT_STS_SHIFT 25
324#define GLPMCFG_SEND_LPM (1 << 24)
325#define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21)
326#define GLPMCFG_RETRY_COUNT_SHIFT 21
327#define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17)
328#define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17
329#define GLPMCFG_SLEEP_STATE_RESUMEOK (1 << 16)
330#define GLPMCFG_PRT_SLEEP_STS (1 << 15)
331#define GLPMCFG_LPM_RESP_MASK (0x3 << 13)
332#define GLPMCFG_LPM_RESP_SHIFT 13
333#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
334#define GLPMCFG_HIRD_THRES_SHIFT 8
335#define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
336#define GLPMCFG_EN_UTMI_SLEEP (1 << 7)
337#define GLPMCFG_REM_WKUP_EN (1 << 6)
338#define GLPMCFG_HIRD_MASK (0xf << 2)
339#define GLPMCFG_HIRD_SHIFT 2
340#define GLPMCFG_APPL_RESP (1 << 1)
341#define GLPMCFG_LPM_CAP_EN (1 << 0)
342
343#define GPWRDN HSOTG_REG(0x0058)
344#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
345#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
346#define GPWRDN_ADP_INT (1 << 23)
347#define GPWRDN_BSESSVLD (1 << 22)
348#define GPWRDN_IDSTS (1 << 21)
349#define GPWRDN_LINESTATE_MASK (0x3 << 19)
350#define GPWRDN_LINESTATE_SHIFT 19
351#define GPWRDN_STS_CHGINT_MSK (1 << 18)
352#define GPWRDN_STS_CHGINT (1 << 17)
353#define GPWRDN_SRP_DET_MSK (1 << 16)
354#define GPWRDN_SRP_DET (1 << 15)
355#define GPWRDN_CONNECT_DET_MSK (1 << 14)
356#define GPWRDN_CONNECT_DET (1 << 13)
357#define GPWRDN_DISCONN_DET_MSK (1 << 12)
358#define GPWRDN_DISCONN_DET (1 << 11)
359#define GPWRDN_RST_DET_MSK (1 << 10)
360#define GPWRDN_RST_DET (1 << 9)
361#define GPWRDN_LNSTSCHG_MSK (1 << 8)
362#define GPWRDN_LNSTSCHG (1 << 7)
363#define GPWRDN_DIS_VBUS (1 << 6)
364#define GPWRDN_PWRDNSWTCH (1 << 5)
365#define GPWRDN_PWRDNRSTN (1 << 4)
366#define GPWRDN_PWRDNCLMP (1 << 3)
367#define GPWRDN_RESTORE (1 << 2)
368#define GPWRDN_PMUACTV (1 << 1)
369#define GPWRDN_PMUINTSEL (1 << 0)
370
371#define GDFIFOCFG HSOTG_REG(0x005c)
372#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
373#define GDFIFOCFG_EPINFOBASE_SHIFT 16
374#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
375#define GDFIFOCFG_GDFIFOCFG_SHIFT 0
376
377#define ADPCTL HSOTG_REG(0x0060)
378#define ADPCTL_AR_MASK (0x3 << 27)
379#define ADPCTL_AR_SHIFT 27
380#define ADPCTL_ADP_TMOUT_INT_MSK (1 << 26)
381#define ADPCTL_ADP_SNS_INT_MSK (1 << 25)
382#define ADPCTL_ADP_PRB_INT_MSK (1 << 24)
383#define ADPCTL_ADP_TMOUT_INT (1 << 23)
384#define ADPCTL_ADP_SNS_INT (1 << 22)
385#define ADPCTL_ADP_PRB_INT (1 << 21)
386#define ADPCTL_ADPENA (1 << 20)
387#define ADPCTL_ADPRES (1 << 19)
388#define ADPCTL_ENASNS (1 << 18)
389#define ADPCTL_ENAPRB (1 << 17)
390#define ADPCTL_RTIM_MASK (0x7ff << 6)
391#define ADPCTL_RTIM_SHIFT 6
392#define ADPCTL_PRB_PER_MASK (0x3 << 4)
393#define ADPCTL_PRB_PER_SHIFT 4
394#define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
395#define ADPCTL_PRB_DELTA_SHIFT 2
396#define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
397#define ADPCTL_PRB_DSCHRG_SHIFT 0
398
399#define HPTXFSIZ HSOTG_REG(0x100)
400/* Use FIFOSIZE_* constants to access this register */
401
402#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
403/* Use FIFOSIZE_* constants to access this register */
404
405/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
406#define FIFOSIZE_DEPTH_MASK (0xffff << 16)
407#define FIFOSIZE_DEPTH_SHIFT 16
408#define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
409#define FIFOSIZE_STARTADDR_SHIFT 0
410#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff)
411
412/* Device mode registers */
413
414#define DCFG HSOTG_REG(0x800)
415#define DCFG_DESCDMA_EN (1 << 23)
416#define DCFG_EPMISCNT_MASK (0x1f << 18)
417#define DCFG_EPMISCNT_SHIFT 18
418#define DCFG_EPMISCNT_LIMIT 0x1f
419#define DCFG_EPMISCNT(_x) ((_x) << 18)
420#define DCFG_PERFRINT_MASK (0x3 << 11)
421#define DCFG_PERFRINT_SHIFT 11
422#define DCFG_PERFRINT_LIMIT 0x3
423#define DCFG_PERFRINT(_x) ((_x) << 11)
424#define DCFG_DEVADDR_MASK (0x7f << 4)
425#define DCFG_DEVADDR_SHIFT 4
426#define DCFG_DEVADDR_LIMIT 0x7f
427#define DCFG_DEVADDR(_x) ((_x) << 4)
428#define DCFG_NZ_STS_OUT_HSHK (1 << 2)
429#define DCFG_DEVSPD_MASK (0x3 << 0)
430#define DCFG_DEVSPD_SHIFT 0
431#define DCFG_DEVSPD_HS 0
432#define DCFG_DEVSPD_FS 1
433#define DCFG_DEVSPD_LS 2
434#define DCFG_DEVSPD_FS48 3
435
436#define DCTL HSOTG_REG(0x804)
437#define DCTL_PWRONPRGDONE (1 << 11)
438#define DCTL_CGOUTNAK (1 << 10)
439#define DCTL_SGOUTNAK (1 << 9)
440#define DCTL_CGNPINNAK (1 << 8)
441#define DCTL_SGNPINNAK (1 << 7)
442#define DCTL_TSTCTL_MASK (0x7 << 4)
443#define DCTL_TSTCTL_SHIFT 4
444#define DCTL_GOUTNAKSTS (1 << 3)
445#define DCTL_GNPINNAKSTS (1 << 2)
446#define DCTL_SFTDISCON (1 << 1)
447#define DCTL_RMTWKUPSIG (1 << 0)
448
449#define DSTS HSOTG_REG(0x808)
450#define DSTS_SOFFN_MASK (0x3fff << 8)
451#define DSTS_SOFFN_SHIFT 8
452#define DSTS_SOFFN_LIMIT 0x3fff
453#define DSTS_SOFFN(_x) ((_x) << 8)
454#define DSTS_ERRATICERR (1 << 3)
455#define DSTS_ENUMSPD_MASK (0x3 << 1)
456#define DSTS_ENUMSPD_SHIFT 1
457#define DSTS_ENUMSPD_HS 0
458#define DSTS_ENUMSPD_FS 1
459#define DSTS_ENUMSPD_LS 2
460#define DSTS_ENUMSPD_FS48 3
461#define DSTS_SUSPSTS (1 << 0)
462
463#define DIEPMSK HSOTG_REG(0x810)
464#define DIEPMSK_NAKMSK (1 << 13)
465#define DIEPMSK_BNAININTRMSK (1 << 9)
466#define DIEPMSK_TXFIFOUNDRNMSK (1 << 8)
467#define DIEPMSK_TXFIFOEMPTY (1 << 7)
468#define DIEPMSK_INEPNAKEFFMSK (1 << 6)
469#define DIEPMSK_INTKNEPMISMSK (1 << 5)
470#define DIEPMSK_INTKNTXFEMPMSK (1 << 4)
471#define DIEPMSK_TIMEOUTMSK (1 << 3)
472#define DIEPMSK_AHBERRMSK (1 << 2)
473#define DIEPMSK_EPDISBLDMSK (1 << 1)
474#define DIEPMSK_XFERCOMPLMSK (1 << 0)
475
476#define DOEPMSK HSOTG_REG(0x814)
477#define DOEPMSK_BNAMSK (1 << 9)
478#define DOEPMSK_BACK2BACKSETUP (1 << 6)
479#define DOEPMSK_STSPHSERCVDMSK (1 << 5)
480#define DOEPMSK_OUTTKNEPDISMSK (1 << 4)
481#define DOEPMSK_SETUPMSK (1 << 3)
482#define DOEPMSK_AHBERRMSK (1 << 2)
483#define DOEPMSK_EPDISBLDMSK (1 << 1)
484#define DOEPMSK_XFERCOMPLMSK (1 << 0)
485
486#define DAINT HSOTG_REG(0x818)
487#define DAINTMSK HSOTG_REG(0x81C)
488#define DAINT_OUTEP_SHIFT 16
489#define DAINT_OUTEP(_x) (1 << ((_x) + 16))
490#define DAINT_INEP(_x) (1 << (_x))
491
492#define DTKNQR1 HSOTG_REG(0x820)
493#define DTKNQR2 HSOTG_REG(0x824)
494#define DTKNQR3 HSOTG_REG(0x830)
495#define DTKNQR4 HSOTG_REG(0x834)
496#define DIEPEMPMSK HSOTG_REG(0x834)
497
498#define DVBUSDIS HSOTG_REG(0x828)
499#define DVBUSPULSE HSOTG_REG(0x82C)
500
501#define DIEPCTL0 HSOTG_REG(0x900)
502#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
503
504#define DOEPCTL0 HSOTG_REG(0xB00)
505#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
506
507/* EP0 specialness:
508 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
509 * bits[25..22] - should always be zero, this isn't a periodic endpoint
510 * bits[10..0] - MPS setting different for EP0
511 */
512#define D0EPCTL_MPS_MASK (0x3 << 0)
513#define D0EPCTL_MPS_SHIFT 0
514#define D0EPCTL_MPS_64 0
515#define D0EPCTL_MPS_32 1
516#define D0EPCTL_MPS_16 2
517#define D0EPCTL_MPS_8 3
518
519#define DXEPCTL_EPENA (1 << 31)
520#define DXEPCTL_EPDIS (1 << 30)
521#define DXEPCTL_SETD1PID (1 << 29)
522#define DXEPCTL_SETODDFR (1 << 29)
523#define DXEPCTL_SETD0PID (1 << 28)
524#define DXEPCTL_SETEVENFR (1 << 28)
525#define DXEPCTL_SNAK (1 << 27)
526#define DXEPCTL_CNAK (1 << 26)
527#define DXEPCTL_TXFNUM_MASK (0xf << 22)
528#define DXEPCTL_TXFNUM_SHIFT 22
529#define DXEPCTL_TXFNUM_LIMIT 0xf
530#define DXEPCTL_TXFNUM(_x) ((_x) << 22)
531#define DXEPCTL_STALL (1 << 21)
532#define DXEPCTL_SNP (1 << 20)
533#define DXEPCTL_EPTYPE_MASK (0x3 << 18)
534#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
535#define DXEPCTL_EPTYPE_ISO (0x1 << 18)
536#define DXEPCTL_EPTYPE_BULK (0x2 << 18)
537#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
538
539#define DXEPCTL_NAKSTS (1 << 17)
540#define DXEPCTL_DPID (1 << 16)
541#define DXEPCTL_EOFRNUM (1 << 16)
542#define DXEPCTL_USBACTEP (1 << 15)
543#define DXEPCTL_NEXTEP_MASK (0xf << 11)
544#define DXEPCTL_NEXTEP_SHIFT 11
545#define DXEPCTL_NEXTEP_LIMIT 0xf
546#define DXEPCTL_NEXTEP(_x) ((_x) << 11)
547#define DXEPCTL_MPS_MASK (0x7ff << 0)
548#define DXEPCTL_MPS_SHIFT 0
549#define DXEPCTL_MPS_LIMIT 0x7ff
550#define DXEPCTL_MPS(_x) ((_x) << 0)
551
552#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
553#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
554#define DXEPINT_SETUP_RCVD (1 << 15)
555#define DXEPINT_NYETINTRPT (1 << 14)
556#define DXEPINT_NAKINTRPT (1 << 13)
557#define DXEPINT_BBLEERRINTRPT (1 << 12)
558#define DXEPINT_PKTDRPSTS (1 << 11)
559#define DXEPINT_BNAINTR (1 << 9)
560#define DXEPINT_TXFIFOUNDRN (1 << 8)
561#define DXEPINT_OUTPKTERR (1 << 8)
562#define DXEPINT_TXFEMP (1 << 7)
563#define DXEPINT_INEPNAKEFF (1 << 6)
564#define DXEPINT_BACK2BACKSETUP (1 << 6)
565#define DXEPINT_INTKNEPMIS (1 << 5)
566#define DXEPINT_STSPHSERCVD (1 << 5)
567#define DXEPINT_INTKNTXFEMP (1 << 4)
568#define DXEPINT_OUTTKNEPDIS (1 << 4)
569#define DXEPINT_TIMEOUT (1 << 3)
570#define DXEPINT_SETUP (1 << 3)
571#define DXEPINT_AHBERR (1 << 2)
572#define DXEPINT_EPDISBLD (1 << 1)
573#define DXEPINT_XFERCOMPL (1 << 0)
574
575#define DIEPTSIZ0 HSOTG_REG(0x910)
576#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
577#define DIEPTSIZ0_PKTCNT_SHIFT 19
578#define DIEPTSIZ0_PKTCNT_LIMIT 0x3
579#define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19)
580#define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
581#define DIEPTSIZ0_XFERSIZE_SHIFT 0
582#define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f
583#define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0)
584
585#define DOEPTSIZ0 HSOTG_REG(0xB10)
586#define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
587#define DOEPTSIZ0_SUPCNT_SHIFT 29
588#define DOEPTSIZ0_SUPCNT_LIMIT 0x3
589#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
590#define DOEPTSIZ0_PKTCNT (1 << 19)
591#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
592#define DOEPTSIZ0_XFERSIZE_SHIFT 0
593
594#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
595#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
596#define DXEPTSIZ_MC_MASK (0x3 << 29)
597#define DXEPTSIZ_MC_SHIFT 29
598#define DXEPTSIZ_MC_LIMIT 0x3
599#define DXEPTSIZ_MC(_x) ((_x) << 29)
600#define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19)
601#define DXEPTSIZ_PKTCNT_SHIFT 19
602#define DXEPTSIZ_PKTCNT_LIMIT 0x3ff
603#define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff)
604#define DXEPTSIZ_PKTCNT(_x) ((_x) << 19)
605#define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0)
606#define DXEPTSIZ_XFERSIZE_SHIFT 0
607#define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff
608#define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff)
609#define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0)
610
611#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
612#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
613
614#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
615
616#define PCGCTL HSOTG_REG(0x0e00)
617#define PCGCTL_IF_DEV_MODE (1 << 31)
618#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
619#define PCGCTL_P2HD_PRT_SPD_SHIFT 29
620#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
621#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
622#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
623#define PCGCTL_MAC_DEV_ADDR_SHIFT 20
624#define PCGCTL_MAX_TERMSEL (1 << 19)
625#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
626#define PCGCTL_MAX_XCVRSELECT_SHIFT 17
627#define PCGCTL_PORT_POWER (1 << 16)
628#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
629#define PCGCTL_PRT_CLK_SEL_SHIFT 14
630#define PCGCTL_ESS_REG_RESTORED (1 << 13)
631#define PCGCTL_EXTND_HIBER_SWITCH (1 << 12)
632#define PCGCTL_EXTND_HIBER_PWRCLMP (1 << 11)
633#define PCGCTL_ENBL_EXTND_HIBER (1 << 10)
634#define PCGCTL_RESTOREMODE (1 << 9)
635#define PCGCTL_RESETAFTSUSP (1 << 8)
636#define PCGCTL_DEEP_SLEEP (1 << 7)
637#define PCGCTL_PHY_IN_SLEEP (1 << 6)
638#define PCGCTL_ENBL_SLEEP_GATING (1 << 5)
639#define PCGCTL_RSTPDWNMODULE (1 << 3)
640#define PCGCTL_PWRCLMP (1 << 2)
641#define PCGCTL_GATEHCLK (1 << 1)
642#define PCGCTL_STOPPCLK (1 << 0)
643
644#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
645
646/* Host Mode Registers */
647
648#define HCFG HSOTG_REG(0x0400)
649#define HCFG_MODECHTIMEN (1 << 31)
650#define HCFG_PERSCHEDENA (1 << 26)
651#define HCFG_FRLISTEN_MASK (0x3 << 24)
652#define HCFG_FRLISTEN_SHIFT 24
653#define HCFG_FRLISTEN_8 (0 << 24)
654#define FRLISTEN_8_SIZE 8
655#define HCFG_FRLISTEN_16 (1 << 24)
656#define FRLISTEN_16_SIZE 16
657#define HCFG_FRLISTEN_32 (2 << 24)
658#define FRLISTEN_32_SIZE 32
659#define HCFG_FRLISTEN_64 (3 << 24)
660#define FRLISTEN_64_SIZE 64
661#define HCFG_DESCDMA (1 << 23)
662#define HCFG_RESVALID_MASK (0xff << 8)
663#define HCFG_RESVALID_SHIFT 8
664#define HCFG_ENA32KHZ (1 << 7)
665#define HCFG_FSLSSUPP (1 << 2)
666#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
667#define HCFG_FSLSPCLKSEL_SHIFT 0
668#define HCFG_FSLSPCLKSEL_30_60_MHZ 0
669#define HCFG_FSLSPCLKSEL_48_MHZ 1
670#define HCFG_FSLSPCLKSEL_6_MHZ 2
671
672#define HFIR HSOTG_REG(0x0404)
673#define HFIR_FRINT_MASK (0xffff << 0)
674#define HFIR_FRINT_SHIFT 0
675#define HFIR_RLDCTRL (1 << 16)
676
677#define HFNUM HSOTG_REG(0x0408)
678#define HFNUM_FRREM_MASK (0xffff << 16)
679#define HFNUM_FRREM_SHIFT 16
680#define HFNUM_FRNUM_MASK (0xffff << 0)
681#define HFNUM_FRNUM_SHIFT 0
682#define HFNUM_MAX_FRNUM 0x3fff
683
684#define HPTXSTS HSOTG_REG(0x0410)
685#define TXSTS_QTOP_ODD (1 << 31)
686#define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
687#define TXSTS_QTOP_CHNEP_SHIFT 27
688#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
689#define TXSTS_QTOP_TOKEN_SHIFT 25
690#define TXSTS_QTOP_TERMINATE (1 << 24)
691#define TXSTS_QSPCAVAIL_MASK (0xff << 16)
692#define TXSTS_QSPCAVAIL_SHIFT 16
693#define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
694#define TXSTS_FSPCAVAIL_SHIFT 0
695
696#define HAINT HSOTG_REG(0x0414)
697#define HAINTMSK HSOTG_REG(0x0418)
698#define HFLBADDR HSOTG_REG(0x041c)
699
700#define HPRT0 HSOTG_REG(0x0440)
701#define HPRT0_SPD_MASK (0x3 << 17)
702#define HPRT0_SPD_SHIFT 17
703#define HPRT0_SPD_HIGH_SPEED 0
704#define HPRT0_SPD_FULL_SPEED 1
705#define HPRT0_SPD_LOW_SPEED 2
706#define HPRT0_TSTCTL_MASK (0xf << 13)
707#define HPRT0_TSTCTL_SHIFT 13
708#define HPRT0_PWR (1 << 12)
709#define HPRT0_LNSTS_MASK (0x3 << 10)
710#define HPRT0_LNSTS_SHIFT 10
711#define HPRT0_RST (1 << 8)
712#define HPRT0_SUSP (1 << 7)
713#define HPRT0_RES (1 << 6)
714#define HPRT0_OVRCURRCHG (1 << 5)
715#define HPRT0_OVRCURRACT (1 << 4)
716#define HPRT0_ENACHG (1 << 3)
717#define HPRT0_ENA (1 << 2)
718#define HPRT0_CONNDET (1 << 1)
719#define HPRT0_CONNSTS (1 << 0)
720
721#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
722#define HCCHAR_CHENA (1 << 31)
723#define HCCHAR_CHDIS (1 << 30)
724#define HCCHAR_ODDFRM (1 << 29)
725#define HCCHAR_DEVADDR_MASK (0x7f << 22)
726#define HCCHAR_DEVADDR_SHIFT 22
727#define HCCHAR_MULTICNT_MASK (0x3 << 20)
728#define HCCHAR_MULTICNT_SHIFT 20
729#define HCCHAR_EPTYPE_MASK (0x3 << 18)
730#define HCCHAR_EPTYPE_SHIFT 18
731#define HCCHAR_LSPDDEV (1 << 17)
732#define HCCHAR_EPDIR (1 << 15)
733#define HCCHAR_EPNUM_MASK (0xf << 11)
734#define HCCHAR_EPNUM_SHIFT 11
735#define HCCHAR_MPS_MASK (0x7ff << 0)
736#define HCCHAR_MPS_SHIFT 0
737
738#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
739#define HCSPLT_SPLTENA (1 << 31)
740#define HCSPLT_COMPSPLT (1 << 16)
741#define HCSPLT_XACTPOS_MASK (0x3 << 14)
742#define HCSPLT_XACTPOS_SHIFT 14
743#define HCSPLT_XACTPOS_MID 0
744#define HCSPLT_XACTPOS_END 1
745#define HCSPLT_XACTPOS_BEGIN 2
746#define HCSPLT_XACTPOS_ALL 3
747#define HCSPLT_HUBADDR_MASK (0x7f << 7)
748#define HCSPLT_HUBADDR_SHIFT 7
749#define HCSPLT_PRTADDR_MASK (0x7f << 0)
750#define HCSPLT_PRTADDR_SHIFT 0
751
752#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
753#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
754#define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
755#define HCINTMSK_FRM_LIST_ROLL (1 << 13)
756#define HCINTMSK_XCS_XACT (1 << 12)
757#define HCINTMSK_BNA (1 << 11)
758#define HCINTMSK_DATATGLERR (1 << 10)
759#define HCINTMSK_FRMOVRUN (1 << 9)
760#define HCINTMSK_BBLERR (1 << 8)
761#define HCINTMSK_XACTERR (1 << 7)
762#define HCINTMSK_NYET (1 << 6)
763#define HCINTMSK_ACK (1 << 5)
764#define HCINTMSK_NAK (1 << 4)
765#define HCINTMSK_STALL (1 << 3)
766#define HCINTMSK_AHBERR (1 << 2)
767#define HCINTMSK_CHHLTD (1 << 1)
768#define HCINTMSK_XFERCOMPL (1 << 0)
769
770#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
771#define TSIZ_DOPNG (1 << 31)
772#define TSIZ_SC_MC_PID_MASK (0x3 << 29)
773#define TSIZ_SC_MC_PID_SHIFT 29
774#define TSIZ_SC_MC_PID_DATA0 0
775#define TSIZ_SC_MC_PID_DATA2 1
776#define TSIZ_SC_MC_PID_DATA1 2
777#define TSIZ_SC_MC_PID_MDATA 3
778#define TSIZ_SC_MC_PID_SETUP 3
779#define TSIZ_PKTCNT_MASK (0x3ff << 19)
780#define TSIZ_PKTCNT_SHIFT 19
781#define TSIZ_NTD_MASK (0xff << 8)
782#define TSIZ_NTD_SHIFT 8
783#define TSIZ_SCHINFO_MASK (0xff << 0)
784#define TSIZ_SCHINFO_SHIFT 0
785#define TSIZ_XFERSIZE_MASK (0x7ffff << 0)
786#define TSIZ_XFERSIZE_SHIFT 0
787
788#define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch))
789
790#define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch))
791
792#define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch))
793
794/**
795 * struct dwc2_dma_desc - DMA descriptor structure,
796 * used for both host and gadget modes
797 *
798 * @status: DMA descriptor status quadlet
799 * @buf: DMA descriptor data buffer pointer
800 *
801 * DMA Descriptor structure contains two quadlets:
802 * Status quadlet and Data buffer pointer.
803 */
804struct dwc2_dma_desc {
805 u32 status;
806 u32 buf;
807} __packed;
808
809/* Host Mode DMA descriptor status quadlet */
810
811#define HOST_DMA_A (1 << 31)
812#define HOST_DMA_STS_MASK (0x3 << 28)
813#define HOST_DMA_STS_SHIFT 28
814#define HOST_DMA_STS_PKTERR (1 << 28)
815#define HOST_DMA_EOL (1 << 26)
816#define HOST_DMA_IOC (1 << 25)
817#define HOST_DMA_SUP (1 << 24)
818#define HOST_DMA_ALT_QTD (1 << 23)
819#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
820#define HOST_DMA_QTD_OFFSET_SHIFT 17
821#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
822#define HOST_DMA_ISOC_NBYTES_SHIFT 0
823#define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
824#define HOST_DMA_NBYTES_SHIFT 0
825#define HOST_DMA_NBYTES_LIMIT 131071
826
827/* Device Mode DMA descriptor status quadlet */
828
829#define DEV_DMA_BUFF_STS_MASK (0x3 << 30)
830#define DEV_DMA_BUFF_STS_SHIFT 30
831#define DEV_DMA_BUFF_STS_HREADY 0
832#define DEV_DMA_BUFF_STS_DMABUSY 1
833#define DEV_DMA_BUFF_STS_DMADONE 2
834#define DEV_DMA_BUFF_STS_HBUSY 3
835#define DEV_DMA_STS_MASK (0x3 << 28)
836#define DEV_DMA_STS_SHIFT 28
837#define DEV_DMA_STS_SUCC 0
838#define DEV_DMA_STS_BUFF_FLUSH 1
839#define DEV_DMA_STS_BUFF_ERR 3
840#define DEV_DMA_L (1 << 27)
841#define DEV_DMA_SHORT (1 << 26)
842#define DEV_DMA_IOC (1 << 25)
843#define DEV_DMA_SR (1 << 24)
844#define DEV_DMA_MTRF (1 << 23)
845#define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
846#define DEV_DMA_ISOC_PID_SHIFT 23
847#define DEV_DMA_ISOC_PID_DATA0 0
848#define DEV_DMA_ISOC_PID_DATA2 1
849#define DEV_DMA_ISOC_PID_DATA1 2
850#define DEV_DMA_ISOC_PID_MDATA 3
851#define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12)
852#define DEV_DMA_ISOC_FRNUM_SHIFT 12
853#define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0)
854#define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff
855#define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0)
856#define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff
857#define DEV_DMA_ISOC_NBYTES_SHIFT 0
858#define DEV_DMA_NBYTES_MASK (0xffff << 0)
859#define DEV_DMA_NBYTES_SHIFT 0
860#define DEV_DMA_NBYTES_LIMIT 0xffff
861
862#define MAX_DMA_DESC_NUM_GENERIC 64
863#define MAX_DMA_DESC_NUM_HS_ISOC 256
864
865#endif /* __DWC2_HW_H__ */
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * hw.h - DesignWare HS OTG Controller hardware definitions
4 *
5 * Copyright 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __DWC2_HW_H__
39#define __DWC2_HW_H__
40
41#define HSOTG_REG(x) (x)
42
43#define GOTGCTL HSOTG_REG(0x000)
44#define GOTGCTL_CHIRPEN BIT(27)
45#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
46#define GOTGCTL_MULT_VALID_BC_SHIFT 22
47#define GOTGCTL_OTGVER BIT(20)
48#define GOTGCTL_BSESVLD BIT(19)
49#define GOTGCTL_ASESVLD BIT(18)
50#define GOTGCTL_DBNC_SHORT BIT(17)
51#define GOTGCTL_CONID_B BIT(16)
52#define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
53#define GOTGCTL_DEVHNPEN BIT(11)
54#define GOTGCTL_HSTSETHNPEN BIT(10)
55#define GOTGCTL_HNPREQ BIT(9)
56#define GOTGCTL_HSTNEGSCS BIT(8)
57#define GOTGCTL_SESREQ BIT(1)
58#define GOTGCTL_SESREQSCS BIT(0)
59
60#define GOTGINT HSOTG_REG(0x004)
61#define GOTGINT_DBNCE_DONE BIT(19)
62#define GOTGINT_A_DEV_TOUT_CHG BIT(18)
63#define GOTGINT_HST_NEG_DET BIT(17)
64#define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9)
65#define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8)
66#define GOTGINT_SES_END_DET BIT(2)
67
68#define GAHBCFG HSOTG_REG(0x008)
69#define GAHBCFG_AHB_SINGLE BIT(23)
70#define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22)
71#define GAHBCFG_REM_MEM_SUPP BIT(21)
72#define GAHBCFG_P_TXF_EMP_LVL BIT(8)
73#define GAHBCFG_NP_TXF_EMP_LVL BIT(7)
74#define GAHBCFG_DMA_EN BIT(5)
75#define GAHBCFG_HBSTLEN_MASK (0xf << 1)
76#define GAHBCFG_HBSTLEN_SHIFT 1
77#define GAHBCFG_HBSTLEN_SINGLE 0
78#define GAHBCFG_HBSTLEN_INCR 1
79#define GAHBCFG_HBSTLEN_INCR4 3
80#define GAHBCFG_HBSTLEN_INCR8 5
81#define GAHBCFG_HBSTLEN_INCR16 7
82#define GAHBCFG_GLBL_INTR_EN BIT(0)
83#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
84 GAHBCFG_NP_TXF_EMP_LVL | \
85 GAHBCFG_DMA_EN | \
86 GAHBCFG_GLBL_INTR_EN)
87
88#define GUSBCFG HSOTG_REG(0x00C)
89#define GUSBCFG_FORCEDEVMODE BIT(30)
90#define GUSBCFG_FORCEHOSTMODE BIT(29)
91#define GUSBCFG_TXENDDELAY BIT(28)
92#define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
93#define GUSBCFG_ICUSBCAP BIT(26)
94#define GUSBCFG_ULPI_INT_PROT_DIS BIT(25)
95#define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
96#define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
97#define GUSBCFG_TERMSELDLPULSE BIT(22)
98#define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
99#define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
100#define GUSBCFG_ULPI_CLK_SUSP_M BIT(19)
101#define GUSBCFG_ULPI_AUTO_RES BIT(18)
102#define GUSBCFG_ULPI_FS_LS BIT(17)
103#define GUSBCFG_OTG_UTMI_FS_SEL BIT(16)
104#define GUSBCFG_PHY_LP_CLK_SEL BIT(15)
105#define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
106#define GUSBCFG_USBTRDTIM_SHIFT 10
107#define GUSBCFG_HNPCAP BIT(9)
108#define GUSBCFG_SRPCAP BIT(8)
109#define GUSBCFG_DDRSEL BIT(7)
110#define GUSBCFG_PHYSEL BIT(6)
111#define GUSBCFG_FSINTF BIT(5)
112#define GUSBCFG_ULPI_UTMI_SEL BIT(4)
113#define GUSBCFG_PHYIF16 BIT(3)
114#define GUSBCFG_PHYIF8 (0 << 3)
115#define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
116#define GUSBCFG_TOUTCAL_SHIFT 0
117#define GUSBCFG_TOUTCAL_LIMIT 0x7
118#define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
119
120#define GRSTCTL HSOTG_REG(0x010)
121#define GRSTCTL_AHBIDLE BIT(31)
122#define GRSTCTL_DMAREQ BIT(30)
123#define GRSTCTL_TXFNUM_MASK (0x1f << 6)
124#define GRSTCTL_TXFNUM_SHIFT 6
125#define GRSTCTL_TXFNUM_LIMIT 0x1f
126#define GRSTCTL_TXFNUM(_x) ((_x) << 6)
127#define GRSTCTL_TXFFLSH BIT(5)
128#define GRSTCTL_RXFFLSH BIT(4)
129#define GRSTCTL_IN_TKNQ_FLSH BIT(3)
130#define GRSTCTL_FRMCNTRRST BIT(2)
131#define GRSTCTL_HSFTRST BIT(1)
132#define GRSTCTL_CSFTRST BIT(0)
133
134#define GINTSTS HSOTG_REG(0x014)
135#define GINTMSK HSOTG_REG(0x018)
136#define GINTSTS_WKUPINT BIT(31)
137#define GINTSTS_SESSREQINT BIT(30)
138#define GINTSTS_DISCONNINT BIT(29)
139#define GINTSTS_CONIDSTSCHNG BIT(28)
140#define GINTSTS_LPMTRANRCVD BIT(27)
141#define GINTSTS_PTXFEMP BIT(26)
142#define GINTSTS_HCHINT BIT(25)
143#define GINTSTS_PRTINT BIT(24)
144#define GINTSTS_RESETDET BIT(23)
145#define GINTSTS_FET_SUSP BIT(22)
146#define GINTSTS_INCOMPL_IP BIT(21)
147#define GINTSTS_INCOMPL_SOOUT BIT(21)
148#define GINTSTS_INCOMPL_SOIN BIT(20)
149#define GINTSTS_OEPINT BIT(19)
150#define GINTSTS_IEPINT BIT(18)
151#define GINTSTS_EPMIS BIT(17)
152#define GINTSTS_RESTOREDONE BIT(16)
153#define GINTSTS_EOPF BIT(15)
154#define GINTSTS_ISOUTDROP BIT(14)
155#define GINTSTS_ENUMDONE BIT(13)
156#define GINTSTS_USBRST BIT(12)
157#define GINTSTS_USBSUSP BIT(11)
158#define GINTSTS_ERLYSUSP BIT(10)
159#define GINTSTS_I2CINT BIT(9)
160#define GINTSTS_ULPI_CK_INT BIT(8)
161#define GINTSTS_GOUTNAKEFF BIT(7)
162#define GINTSTS_GINNAKEFF BIT(6)
163#define GINTSTS_NPTXFEMP BIT(5)
164#define GINTSTS_RXFLVL BIT(4)
165#define GINTSTS_SOF BIT(3)
166#define GINTSTS_OTGINT BIT(2)
167#define GINTSTS_MODEMIS BIT(1)
168#define GINTSTS_CURMODE_HOST BIT(0)
169
170#define GRXSTSR HSOTG_REG(0x01C)
171#define GRXSTSP HSOTG_REG(0x020)
172#define GRXSTS_FN_MASK (0x7f << 25)
173#define GRXSTS_FN_SHIFT 25
174#define GRXSTS_PKTSTS_MASK (0xf << 17)
175#define GRXSTS_PKTSTS_SHIFT 17
176#define GRXSTS_PKTSTS_GLOBALOUTNAK 1
177#define GRXSTS_PKTSTS_OUTRX 2
178#define GRXSTS_PKTSTS_HCHIN 2
179#define GRXSTS_PKTSTS_OUTDONE 3
180#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
181#define GRXSTS_PKTSTS_SETUPDONE 4
182#define GRXSTS_PKTSTS_DATATOGGLEERR 5
183#define GRXSTS_PKTSTS_SETUPRX 6
184#define GRXSTS_PKTSTS_HCHHALTED 7
185#define GRXSTS_HCHNUM_MASK (0xf << 0)
186#define GRXSTS_HCHNUM_SHIFT 0
187#define GRXSTS_DPID_MASK (0x3 << 15)
188#define GRXSTS_DPID_SHIFT 15
189#define GRXSTS_BYTECNT_MASK (0x7ff << 4)
190#define GRXSTS_BYTECNT_SHIFT 4
191#define GRXSTS_EPNUM_MASK (0xf << 0)
192#define GRXSTS_EPNUM_SHIFT 0
193
194#define GRXFSIZ HSOTG_REG(0x024)
195#define GRXFSIZ_DEPTH_MASK (0xffff << 0)
196#define GRXFSIZ_DEPTH_SHIFT 0
197
198#define GNPTXFSIZ HSOTG_REG(0x028)
199/* Use FIFOSIZE_* constants to access this register */
200
201#define GNPTXSTS HSOTG_REG(0x02C)
202#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
203#define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
204#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16)
205#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16
206#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff)
207#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0)
208#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0
209#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
210
211#define GI2CCTL HSOTG_REG(0x0030)
212#define GI2CCTL_BSYDNE BIT(31)
213#define GI2CCTL_RW BIT(30)
214#define GI2CCTL_I2CDATSE0 BIT(28)
215#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
216#define GI2CCTL_I2CDEVADDR_SHIFT 26
217#define GI2CCTL_I2CSUSPCTL BIT(25)
218#define GI2CCTL_ACK BIT(24)
219#define GI2CCTL_I2CEN BIT(23)
220#define GI2CCTL_ADDR_MASK (0x7f << 16)
221#define GI2CCTL_ADDR_SHIFT 16
222#define GI2CCTL_REGADDR_MASK (0xff << 8)
223#define GI2CCTL_REGADDR_SHIFT 8
224#define GI2CCTL_RWDATA_MASK (0xff << 0)
225#define GI2CCTL_RWDATA_SHIFT 0
226
227#define GPVNDCTL HSOTG_REG(0x0034)
228#define GGPIO HSOTG_REG(0x0038)
229#define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16)
230
231#define GUID HSOTG_REG(0x003c)
232#define GSNPSID HSOTG_REG(0x0040)
233#define GHWCFG1 HSOTG_REG(0x0044)
234#define GSNPSID_ID_MASK GENMASK(31, 16)
235
236#define GHWCFG2 HSOTG_REG(0x0048)
237#define GHWCFG2_OTG_ENABLE_IC_USB BIT(31)
238#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
239#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
240#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
241#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
242#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
243#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
244#define GHWCFG2_MULTI_PROC_INT BIT(20)
245#define GHWCFG2_DYNAMIC_FIFO BIT(19)
246#define GHWCFG2_PERIO_EP_SUPPORTED BIT(18)
247#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
248#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
249#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
250#define GHWCFG2_NUM_DEV_EP_SHIFT 10
251#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
252#define GHWCFG2_FS_PHY_TYPE_SHIFT 8
253#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
254#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1
255#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2
256#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
257#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
258#define GHWCFG2_HS_PHY_TYPE_SHIFT 6
259#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
260#define GHWCFG2_HS_PHY_TYPE_UTMI 1
261#define GHWCFG2_HS_PHY_TYPE_ULPI 2
262#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
263#define GHWCFG2_POINT2POINT BIT(5)
264#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
265#define GHWCFG2_ARCHITECTURE_SHIFT 3
266#define GHWCFG2_SLAVE_ONLY_ARCH 0
267#define GHWCFG2_EXT_DMA_ARCH 1
268#define GHWCFG2_INT_DMA_ARCH 2
269#define GHWCFG2_OP_MODE_MASK (0x7 << 0)
270#define GHWCFG2_OP_MODE_SHIFT 0
271#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0
272#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1
273#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2
274#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
275#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
276#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
277#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
278#define GHWCFG2_OP_MODE_UNDEFINED 7
279
280#define GHWCFG3 HSOTG_REG(0x004c)
281#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
282#define GHWCFG3_DFIFO_DEPTH_SHIFT 16
283#define GHWCFG3_OTG_LPM_EN BIT(15)
284#define GHWCFG3_BC_SUPPORT BIT(14)
285#define GHWCFG3_OTG_ENABLE_HSIC BIT(13)
286#define GHWCFG3_ADP_SUPP BIT(12)
287#define GHWCFG3_SYNCH_RESET_TYPE BIT(11)
288#define GHWCFG3_OPTIONAL_FEATURES BIT(10)
289#define GHWCFG3_VENDOR_CTRL_IF BIT(9)
290#define GHWCFG3_I2C BIT(8)
291#define GHWCFG3_OTG_FUNC BIT(7)
292#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
293#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
294#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
295#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
296
297#define GHWCFG4 HSOTG_REG(0x0050)
298#define GHWCFG4_DESC_DMA_DYN BIT(31)
299#define GHWCFG4_DESC_DMA BIT(30)
300#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
301#define GHWCFG4_NUM_IN_EPS_SHIFT 26
302#define GHWCFG4_DED_FIFO_EN BIT(25)
303#define GHWCFG4_DED_FIFO_SHIFT 25
304#define GHWCFG4_SESSION_END_FILT_EN BIT(24)
305#define GHWCFG4_B_VALID_FILT_EN BIT(23)
306#define GHWCFG4_A_VALID_FILT_EN BIT(22)
307#define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
308#define GHWCFG4_IDDIG_FILT_EN BIT(20)
309#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
310#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
311#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
312#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
313#define GHWCFG4_ACG_SUPPORTED BIT(12)
314#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
315#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
316#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
317#define GHWCFG4_XHIBER BIT(7)
318#define GHWCFG4_HIBER BIT(6)
319#define GHWCFG4_MIN_AHB_FREQ BIT(5)
320#define GHWCFG4_POWER_OPTIMIZ BIT(4)
321#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
322#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
323
324#define GLPMCFG HSOTG_REG(0x0054)
325#define GLPMCFG_INVSELHSIC BIT(31)
326#define GLPMCFG_HSICCON BIT(30)
327#define GLPMCFG_RSTRSLPSTS BIT(29)
328#define GLPMCFG_ENBESL BIT(28)
329#define GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7 << 25)
330#define GLPMCFG_LPM_RETRYCNT_STS_SHIFT 25
331#define GLPMCFG_SNDLPM BIT(24)
332#define GLPMCFG_RETRY_CNT_MASK (0x7 << 21)
333#define GLPMCFG_RETRY_CNT_SHIFT 21
334#define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17)
335#define GLPMCFG_LPM_CHNL_INDX_SHIFT 17
336#define GLPMCFG_L1RESUMEOK BIT(16)
337#define GLPMCFG_SLPSTS BIT(15)
338#define GLPMCFG_COREL1RES_MASK (0x3 << 13)
339#define GLPMCFG_COREL1RES_SHIFT 13
340#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
341#define GLPMCFG_HIRD_THRES_SHIFT 8
342#define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
343#define GLPMCFG_ENBLSLPM BIT(7)
344#define GLPMCFG_BREMOTEWAKE BIT(6)
345#define GLPMCFG_HIRD_MASK (0xf << 2)
346#define GLPMCFG_HIRD_SHIFT 2
347#define GLPMCFG_APPL1RES BIT(1)
348#define GLPMCFG_LPMCAP BIT(0)
349
350#define GPWRDN HSOTG_REG(0x0058)
351#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
352#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
353#define GPWRDN_ADP_INT BIT(23)
354#define GPWRDN_BSESSVLD BIT(22)
355#define GPWRDN_IDSTS BIT(21)
356#define GPWRDN_LINESTATE_MASK (0x3 << 19)
357#define GPWRDN_LINESTATE_SHIFT 19
358#define GPWRDN_STS_CHGINT_MSK BIT(18)
359#define GPWRDN_STS_CHGINT BIT(17)
360#define GPWRDN_SRP_DET_MSK BIT(16)
361#define GPWRDN_SRP_DET BIT(15)
362#define GPWRDN_CONNECT_DET_MSK BIT(14)
363#define GPWRDN_CONNECT_DET BIT(13)
364#define GPWRDN_DISCONN_DET_MSK BIT(12)
365#define GPWRDN_DISCONN_DET BIT(11)
366#define GPWRDN_RST_DET_MSK BIT(10)
367#define GPWRDN_RST_DET BIT(9)
368#define GPWRDN_LNSTSCHG_MSK BIT(8)
369#define GPWRDN_LNSTSCHG BIT(7)
370#define GPWRDN_DIS_VBUS BIT(6)
371#define GPWRDN_PWRDNSWTCH BIT(5)
372#define GPWRDN_PWRDNRSTN BIT(4)
373#define GPWRDN_PWRDNCLMP BIT(3)
374#define GPWRDN_RESTORE BIT(2)
375#define GPWRDN_PMUACTV BIT(1)
376#define GPWRDN_PMUINTSEL BIT(0)
377
378#define GDFIFOCFG HSOTG_REG(0x005c)
379#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
380#define GDFIFOCFG_EPINFOBASE_SHIFT 16
381#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
382#define GDFIFOCFG_GDFIFOCFG_SHIFT 0
383
384#define ADPCTL HSOTG_REG(0x0060)
385#define ADPCTL_AR_MASK (0x3 << 27)
386#define ADPCTL_AR_SHIFT 27
387#define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
388#define ADPCTL_ADP_SNS_INT_MSK BIT(25)
389#define ADPCTL_ADP_PRB_INT_MSK BIT(24)
390#define ADPCTL_ADP_TMOUT_INT BIT(23)
391#define ADPCTL_ADP_SNS_INT BIT(22)
392#define ADPCTL_ADP_PRB_INT BIT(21)
393#define ADPCTL_ADPENA BIT(20)
394#define ADPCTL_ADPRES BIT(19)
395#define ADPCTL_ENASNS BIT(18)
396#define ADPCTL_ENAPRB BIT(17)
397#define ADPCTL_RTIM_MASK (0x7ff << 6)
398#define ADPCTL_RTIM_SHIFT 6
399#define ADPCTL_PRB_PER_MASK (0x3 << 4)
400#define ADPCTL_PRB_PER_SHIFT 4
401#define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
402#define ADPCTL_PRB_DELTA_SHIFT 2
403#define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
404#define ADPCTL_PRB_DSCHRG_SHIFT 0
405
406#define HPTXFSIZ HSOTG_REG(0x100)
407/* Use FIFOSIZE_* constants to access this register */
408
409#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
410/* Use FIFOSIZE_* constants to access this register */
411
412/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
413#define FIFOSIZE_DEPTH_MASK (0xffff << 16)
414#define FIFOSIZE_DEPTH_SHIFT 16
415#define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
416#define FIFOSIZE_STARTADDR_SHIFT 0
417#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff)
418
419/* Device mode registers */
420
421#define DCFG HSOTG_REG(0x800)
422#define DCFG_DESCDMA_EN BIT(23)
423#define DCFG_EPMISCNT_MASK (0x1f << 18)
424#define DCFG_EPMISCNT_SHIFT 18
425#define DCFG_EPMISCNT_LIMIT 0x1f
426#define DCFG_EPMISCNT(_x) ((_x) << 18)
427#define DCFG_PERFRINT_MASK (0x3 << 11)
428#define DCFG_PERFRINT_SHIFT 11
429#define DCFG_PERFRINT_LIMIT 0x3
430#define DCFG_PERFRINT(_x) ((_x) << 11)
431#define DCFG_DEVADDR_MASK (0x7f << 4)
432#define DCFG_DEVADDR_SHIFT 4
433#define DCFG_DEVADDR_LIMIT 0x7f
434#define DCFG_DEVADDR(_x) ((_x) << 4)
435#define DCFG_NZ_STS_OUT_HSHK BIT(2)
436#define DCFG_DEVSPD_MASK (0x3 << 0)
437#define DCFG_DEVSPD_SHIFT 0
438#define DCFG_DEVSPD_HS 0
439#define DCFG_DEVSPD_FS 1
440#define DCFG_DEVSPD_LS 2
441#define DCFG_DEVSPD_FS48 3
442
443#define DCTL HSOTG_REG(0x804)
444#define DCTL_PWRONPRGDONE BIT(11)
445#define DCTL_CGOUTNAK BIT(10)
446#define DCTL_SGOUTNAK BIT(9)
447#define DCTL_CGNPINNAK BIT(8)
448#define DCTL_SGNPINNAK BIT(7)
449#define DCTL_TSTCTL_MASK (0x7 << 4)
450#define DCTL_TSTCTL_SHIFT 4
451#define DCTL_GOUTNAKSTS BIT(3)
452#define DCTL_GNPINNAKSTS BIT(2)
453#define DCTL_SFTDISCON BIT(1)
454#define DCTL_RMTWKUPSIG BIT(0)
455
456#define DSTS HSOTG_REG(0x808)
457#define DSTS_SOFFN_MASK (0x3fff << 8)
458#define DSTS_SOFFN_SHIFT 8
459#define DSTS_SOFFN_LIMIT 0x3fff
460#define DSTS_SOFFN(_x) ((_x) << 8)
461#define DSTS_ERRATICERR BIT(3)
462#define DSTS_ENUMSPD_MASK (0x3 << 1)
463#define DSTS_ENUMSPD_SHIFT 1
464#define DSTS_ENUMSPD_HS 0
465#define DSTS_ENUMSPD_FS 1
466#define DSTS_ENUMSPD_LS 2
467#define DSTS_ENUMSPD_FS48 3
468#define DSTS_SUSPSTS BIT(0)
469
470#define DIEPMSK HSOTG_REG(0x810)
471#define DIEPMSK_NAKMSK BIT(13)
472#define DIEPMSK_BNAININTRMSK BIT(9)
473#define DIEPMSK_TXFIFOUNDRNMSK BIT(8)
474#define DIEPMSK_TXFIFOEMPTY BIT(7)
475#define DIEPMSK_INEPNAKEFFMSK BIT(6)
476#define DIEPMSK_INTKNEPMISMSK BIT(5)
477#define DIEPMSK_INTKNTXFEMPMSK BIT(4)
478#define DIEPMSK_TIMEOUTMSK BIT(3)
479#define DIEPMSK_AHBERRMSK BIT(2)
480#define DIEPMSK_EPDISBLDMSK BIT(1)
481#define DIEPMSK_XFERCOMPLMSK BIT(0)
482
483#define DOEPMSK HSOTG_REG(0x814)
484#define DOEPMSK_BNAMSK BIT(9)
485#define DOEPMSK_BACK2BACKSETUP BIT(6)
486#define DOEPMSK_STSPHSERCVDMSK BIT(5)
487#define DOEPMSK_OUTTKNEPDISMSK BIT(4)
488#define DOEPMSK_SETUPMSK BIT(3)
489#define DOEPMSK_AHBERRMSK BIT(2)
490#define DOEPMSK_EPDISBLDMSK BIT(1)
491#define DOEPMSK_XFERCOMPLMSK BIT(0)
492
493#define DAINT HSOTG_REG(0x818)
494#define DAINTMSK HSOTG_REG(0x81C)
495#define DAINT_OUTEP_SHIFT 16
496#define DAINT_OUTEP(_x) (1 << ((_x) + 16))
497#define DAINT_INEP(_x) (1 << (_x))
498
499#define DTKNQR1 HSOTG_REG(0x820)
500#define DTKNQR2 HSOTG_REG(0x824)
501#define DTKNQR3 HSOTG_REG(0x830)
502#define DTKNQR4 HSOTG_REG(0x834)
503#define DIEPEMPMSK HSOTG_REG(0x834)
504
505#define DVBUSDIS HSOTG_REG(0x828)
506#define DVBUSPULSE HSOTG_REG(0x82C)
507
508#define DIEPCTL0 HSOTG_REG(0x900)
509#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
510
511#define DOEPCTL0 HSOTG_REG(0xB00)
512#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
513
514/* EP0 specialness:
515 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
516 * bits[25..22] - should always be zero, this isn't a periodic endpoint
517 * bits[10..0] - MPS setting different for EP0
518 */
519#define D0EPCTL_MPS_MASK (0x3 << 0)
520#define D0EPCTL_MPS_SHIFT 0
521#define D0EPCTL_MPS_64 0
522#define D0EPCTL_MPS_32 1
523#define D0EPCTL_MPS_16 2
524#define D0EPCTL_MPS_8 3
525
526#define DXEPCTL_EPENA BIT(31)
527#define DXEPCTL_EPDIS BIT(30)
528#define DXEPCTL_SETD1PID BIT(29)
529#define DXEPCTL_SETODDFR BIT(29)
530#define DXEPCTL_SETD0PID BIT(28)
531#define DXEPCTL_SETEVENFR BIT(28)
532#define DXEPCTL_SNAK BIT(27)
533#define DXEPCTL_CNAK BIT(26)
534#define DXEPCTL_TXFNUM_MASK (0xf << 22)
535#define DXEPCTL_TXFNUM_SHIFT 22
536#define DXEPCTL_TXFNUM_LIMIT 0xf
537#define DXEPCTL_TXFNUM(_x) ((_x) << 22)
538#define DXEPCTL_STALL BIT(21)
539#define DXEPCTL_SNP BIT(20)
540#define DXEPCTL_EPTYPE_MASK (0x3 << 18)
541#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
542#define DXEPCTL_EPTYPE_ISO (0x1 << 18)
543#define DXEPCTL_EPTYPE_BULK (0x2 << 18)
544#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
545
546#define DXEPCTL_NAKSTS BIT(17)
547#define DXEPCTL_DPID BIT(16)
548#define DXEPCTL_EOFRNUM BIT(16)
549#define DXEPCTL_USBACTEP BIT(15)
550#define DXEPCTL_NEXTEP_MASK (0xf << 11)
551#define DXEPCTL_NEXTEP_SHIFT 11
552#define DXEPCTL_NEXTEP_LIMIT 0xf
553#define DXEPCTL_NEXTEP(_x) ((_x) << 11)
554#define DXEPCTL_MPS_MASK (0x7ff << 0)
555#define DXEPCTL_MPS_SHIFT 0
556#define DXEPCTL_MPS_LIMIT 0x7ff
557#define DXEPCTL_MPS(_x) ((_x) << 0)
558
559#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
560#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
561#define DXEPINT_SETUP_RCVD BIT(15)
562#define DXEPINT_NYETINTRPT BIT(14)
563#define DXEPINT_NAKINTRPT BIT(13)
564#define DXEPINT_BBLEERRINTRPT BIT(12)
565#define DXEPINT_PKTDRPSTS BIT(11)
566#define DXEPINT_BNAINTR BIT(9)
567#define DXEPINT_TXFIFOUNDRN BIT(8)
568#define DXEPINT_OUTPKTERR BIT(8)
569#define DXEPINT_TXFEMP BIT(7)
570#define DXEPINT_INEPNAKEFF BIT(6)
571#define DXEPINT_BACK2BACKSETUP BIT(6)
572#define DXEPINT_INTKNEPMIS BIT(5)
573#define DXEPINT_STSPHSERCVD BIT(5)
574#define DXEPINT_INTKNTXFEMP BIT(4)
575#define DXEPINT_OUTTKNEPDIS BIT(4)
576#define DXEPINT_TIMEOUT BIT(3)
577#define DXEPINT_SETUP BIT(3)
578#define DXEPINT_AHBERR BIT(2)
579#define DXEPINT_EPDISBLD BIT(1)
580#define DXEPINT_XFERCOMPL BIT(0)
581
582#define DIEPTSIZ0 HSOTG_REG(0x910)
583#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
584#define DIEPTSIZ0_PKTCNT_SHIFT 19
585#define DIEPTSIZ0_PKTCNT_LIMIT 0x3
586#define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19)
587#define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
588#define DIEPTSIZ0_XFERSIZE_SHIFT 0
589#define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f
590#define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0)
591
592#define DOEPTSIZ0 HSOTG_REG(0xB10)
593#define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
594#define DOEPTSIZ0_SUPCNT_SHIFT 29
595#define DOEPTSIZ0_SUPCNT_LIMIT 0x3
596#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
597#define DOEPTSIZ0_PKTCNT BIT(19)
598#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
599#define DOEPTSIZ0_XFERSIZE_SHIFT 0
600
601#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
602#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
603#define DXEPTSIZ_MC_MASK (0x3 << 29)
604#define DXEPTSIZ_MC_SHIFT 29
605#define DXEPTSIZ_MC_LIMIT 0x3
606#define DXEPTSIZ_MC(_x) ((_x) << 29)
607#define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19)
608#define DXEPTSIZ_PKTCNT_SHIFT 19
609#define DXEPTSIZ_PKTCNT_LIMIT 0x3ff
610#define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff)
611#define DXEPTSIZ_PKTCNT(_x) ((_x) << 19)
612#define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0)
613#define DXEPTSIZ_XFERSIZE_SHIFT 0
614#define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff
615#define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff)
616#define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0)
617
618#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
619#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
620
621#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
622
623#define PCGCTL HSOTG_REG(0x0e00)
624#define PCGCTL_IF_DEV_MODE BIT(31)
625#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
626#define PCGCTL_P2HD_PRT_SPD_SHIFT 29
627#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
628#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
629#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
630#define PCGCTL_MAC_DEV_ADDR_SHIFT 20
631#define PCGCTL_MAX_TERMSEL BIT(19)
632#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
633#define PCGCTL_MAX_XCVRSELECT_SHIFT 17
634#define PCGCTL_PORT_POWER BIT(16)
635#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
636#define PCGCTL_PRT_CLK_SEL_SHIFT 14
637#define PCGCTL_ESS_REG_RESTORED BIT(13)
638#define PCGCTL_EXTND_HIBER_SWITCH BIT(12)
639#define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11)
640#define PCGCTL_ENBL_EXTND_HIBER BIT(10)
641#define PCGCTL_RESTOREMODE BIT(9)
642#define PCGCTL_RESETAFTSUSP BIT(8)
643#define PCGCTL_DEEP_SLEEP BIT(7)
644#define PCGCTL_PHY_IN_SLEEP BIT(6)
645#define PCGCTL_ENBL_SLEEP_GATING BIT(5)
646#define PCGCTL_RSTPDWNMODULE BIT(3)
647#define PCGCTL_PWRCLMP BIT(2)
648#define PCGCTL_GATEHCLK BIT(1)
649#define PCGCTL_STOPPCLK BIT(0)
650
651#define PCGCCTL1 HSOTG_REG(0xe04)
652#define PCGCCTL1_TIMER (0x3 << 1)
653#define PCGCCTL1_GATEEN BIT(0)
654
655#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
656
657/* Host Mode Registers */
658
659#define HCFG HSOTG_REG(0x0400)
660#define HCFG_MODECHTIMEN BIT(31)
661#define HCFG_PERSCHEDENA BIT(26)
662#define HCFG_FRLISTEN_MASK (0x3 << 24)
663#define HCFG_FRLISTEN_SHIFT 24
664#define HCFG_FRLISTEN_8 (0 << 24)
665#define FRLISTEN_8_SIZE 8
666#define HCFG_FRLISTEN_16 BIT(24)
667#define FRLISTEN_16_SIZE 16
668#define HCFG_FRLISTEN_32 (2 << 24)
669#define FRLISTEN_32_SIZE 32
670#define HCFG_FRLISTEN_64 (3 << 24)
671#define FRLISTEN_64_SIZE 64
672#define HCFG_DESCDMA BIT(23)
673#define HCFG_RESVALID_MASK (0xff << 8)
674#define HCFG_RESVALID_SHIFT 8
675#define HCFG_ENA32KHZ BIT(7)
676#define HCFG_FSLSSUPP BIT(2)
677#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
678#define HCFG_FSLSPCLKSEL_SHIFT 0
679#define HCFG_FSLSPCLKSEL_30_60_MHZ 0
680#define HCFG_FSLSPCLKSEL_48_MHZ 1
681#define HCFG_FSLSPCLKSEL_6_MHZ 2
682
683#define HFIR HSOTG_REG(0x0404)
684#define HFIR_FRINT_MASK (0xffff << 0)
685#define HFIR_FRINT_SHIFT 0
686#define HFIR_RLDCTRL BIT(16)
687
688#define HFNUM HSOTG_REG(0x0408)
689#define HFNUM_FRREM_MASK (0xffff << 16)
690#define HFNUM_FRREM_SHIFT 16
691#define HFNUM_FRNUM_MASK (0xffff << 0)
692#define HFNUM_FRNUM_SHIFT 0
693#define HFNUM_MAX_FRNUM 0x3fff
694
695#define HPTXSTS HSOTG_REG(0x0410)
696#define TXSTS_QTOP_ODD BIT(31)
697#define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
698#define TXSTS_QTOP_CHNEP_SHIFT 27
699#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
700#define TXSTS_QTOP_TOKEN_SHIFT 25
701#define TXSTS_QTOP_TERMINATE BIT(24)
702#define TXSTS_QSPCAVAIL_MASK (0xff << 16)
703#define TXSTS_QSPCAVAIL_SHIFT 16
704#define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
705#define TXSTS_FSPCAVAIL_SHIFT 0
706
707#define HAINT HSOTG_REG(0x0414)
708#define HAINTMSK HSOTG_REG(0x0418)
709#define HFLBADDR HSOTG_REG(0x041c)
710
711#define HPRT0 HSOTG_REG(0x0440)
712#define HPRT0_SPD_MASK (0x3 << 17)
713#define HPRT0_SPD_SHIFT 17
714#define HPRT0_SPD_HIGH_SPEED 0
715#define HPRT0_SPD_FULL_SPEED 1
716#define HPRT0_SPD_LOW_SPEED 2
717#define HPRT0_TSTCTL_MASK (0xf << 13)
718#define HPRT0_TSTCTL_SHIFT 13
719#define HPRT0_PWR BIT(12)
720#define HPRT0_LNSTS_MASK (0x3 << 10)
721#define HPRT0_LNSTS_SHIFT 10
722#define HPRT0_RST BIT(8)
723#define HPRT0_SUSP BIT(7)
724#define HPRT0_RES BIT(6)
725#define HPRT0_OVRCURRCHG BIT(5)
726#define HPRT0_OVRCURRACT BIT(4)
727#define HPRT0_ENACHG BIT(3)
728#define HPRT0_ENA BIT(2)
729#define HPRT0_CONNDET BIT(1)
730#define HPRT0_CONNSTS BIT(0)
731
732#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
733#define HCCHAR_CHENA BIT(31)
734#define HCCHAR_CHDIS BIT(30)
735#define HCCHAR_ODDFRM BIT(29)
736#define HCCHAR_DEVADDR_MASK (0x7f << 22)
737#define HCCHAR_DEVADDR_SHIFT 22
738#define HCCHAR_MULTICNT_MASK (0x3 << 20)
739#define HCCHAR_MULTICNT_SHIFT 20
740#define HCCHAR_EPTYPE_MASK (0x3 << 18)
741#define HCCHAR_EPTYPE_SHIFT 18
742#define HCCHAR_LSPDDEV BIT(17)
743#define HCCHAR_EPDIR BIT(15)
744#define HCCHAR_EPNUM_MASK (0xf << 11)
745#define HCCHAR_EPNUM_SHIFT 11
746#define HCCHAR_MPS_MASK (0x7ff << 0)
747#define HCCHAR_MPS_SHIFT 0
748
749#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
750#define HCSPLT_SPLTENA BIT(31)
751#define HCSPLT_COMPSPLT BIT(16)
752#define HCSPLT_XACTPOS_MASK (0x3 << 14)
753#define HCSPLT_XACTPOS_SHIFT 14
754#define HCSPLT_XACTPOS_MID 0
755#define HCSPLT_XACTPOS_END 1
756#define HCSPLT_XACTPOS_BEGIN 2
757#define HCSPLT_XACTPOS_ALL 3
758#define HCSPLT_HUBADDR_MASK (0x7f << 7)
759#define HCSPLT_HUBADDR_SHIFT 7
760#define HCSPLT_PRTADDR_MASK (0x7f << 0)
761#define HCSPLT_PRTADDR_SHIFT 0
762
763#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
764#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
765#define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
766#define HCINTMSK_FRM_LIST_ROLL BIT(13)
767#define HCINTMSK_XCS_XACT BIT(12)
768#define HCINTMSK_BNA BIT(11)
769#define HCINTMSK_DATATGLERR BIT(10)
770#define HCINTMSK_FRMOVRUN BIT(9)
771#define HCINTMSK_BBLERR BIT(8)
772#define HCINTMSK_XACTERR BIT(7)
773#define HCINTMSK_NYET BIT(6)
774#define HCINTMSK_ACK BIT(5)
775#define HCINTMSK_NAK BIT(4)
776#define HCINTMSK_STALL BIT(3)
777#define HCINTMSK_AHBERR BIT(2)
778#define HCINTMSK_CHHLTD BIT(1)
779#define HCINTMSK_XFERCOMPL BIT(0)
780
781#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
782#define TSIZ_DOPNG BIT(31)
783#define TSIZ_SC_MC_PID_MASK (0x3 << 29)
784#define TSIZ_SC_MC_PID_SHIFT 29
785#define TSIZ_SC_MC_PID_DATA0 0
786#define TSIZ_SC_MC_PID_DATA2 1
787#define TSIZ_SC_MC_PID_DATA1 2
788#define TSIZ_SC_MC_PID_MDATA 3
789#define TSIZ_SC_MC_PID_SETUP 3
790#define TSIZ_PKTCNT_MASK (0x3ff << 19)
791#define TSIZ_PKTCNT_SHIFT 19
792#define TSIZ_NTD_MASK (0xff << 8)
793#define TSIZ_NTD_SHIFT 8
794#define TSIZ_SCHINFO_MASK (0xff << 0)
795#define TSIZ_SCHINFO_SHIFT 0
796#define TSIZ_XFERSIZE_MASK (0x7ffff << 0)
797#define TSIZ_XFERSIZE_SHIFT 0
798
799#define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch))
800
801#define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch))
802
803#define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch))
804
805/**
806 * struct dwc2_dma_desc - DMA descriptor structure,
807 * used for both host and gadget modes
808 *
809 * @status: DMA descriptor status quadlet
810 * @buf: DMA descriptor data buffer pointer
811 *
812 * DMA Descriptor structure contains two quadlets:
813 * Status quadlet and Data buffer pointer.
814 */
815struct dwc2_dma_desc {
816 u32 status;
817 u32 buf;
818} __packed;
819
820/* Host Mode DMA descriptor status quadlet */
821
822#define HOST_DMA_A BIT(31)
823#define HOST_DMA_STS_MASK (0x3 << 28)
824#define HOST_DMA_STS_SHIFT 28
825#define HOST_DMA_STS_PKTERR BIT(28)
826#define HOST_DMA_EOL BIT(26)
827#define HOST_DMA_IOC BIT(25)
828#define HOST_DMA_SUP BIT(24)
829#define HOST_DMA_ALT_QTD BIT(23)
830#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
831#define HOST_DMA_QTD_OFFSET_SHIFT 17
832#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
833#define HOST_DMA_ISOC_NBYTES_SHIFT 0
834#define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
835#define HOST_DMA_NBYTES_SHIFT 0
836#define HOST_DMA_NBYTES_LIMIT 131071
837
838/* Device Mode DMA descriptor status quadlet */
839
840#define DEV_DMA_BUFF_STS_MASK (0x3 << 30)
841#define DEV_DMA_BUFF_STS_SHIFT 30
842#define DEV_DMA_BUFF_STS_HREADY 0
843#define DEV_DMA_BUFF_STS_DMABUSY 1
844#define DEV_DMA_BUFF_STS_DMADONE 2
845#define DEV_DMA_BUFF_STS_HBUSY 3
846#define DEV_DMA_STS_MASK (0x3 << 28)
847#define DEV_DMA_STS_SHIFT 28
848#define DEV_DMA_STS_SUCC 0
849#define DEV_DMA_STS_BUFF_FLUSH 1
850#define DEV_DMA_STS_BUFF_ERR 3
851#define DEV_DMA_L BIT(27)
852#define DEV_DMA_SHORT BIT(26)
853#define DEV_DMA_IOC BIT(25)
854#define DEV_DMA_SR BIT(24)
855#define DEV_DMA_MTRF BIT(23)
856#define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
857#define DEV_DMA_ISOC_PID_SHIFT 23
858#define DEV_DMA_ISOC_PID_DATA0 0
859#define DEV_DMA_ISOC_PID_DATA2 1
860#define DEV_DMA_ISOC_PID_DATA1 2
861#define DEV_DMA_ISOC_PID_MDATA 3
862#define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12)
863#define DEV_DMA_ISOC_FRNUM_SHIFT 12
864#define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0)
865#define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff
866#define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0)
867#define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff
868#define DEV_DMA_ISOC_NBYTES_SHIFT 0
869#define DEV_DMA_NBYTES_MASK (0xffff << 0)
870#define DEV_DMA_NBYTES_SHIFT 0
871#define DEV_DMA_NBYTES_LIMIT 0xffff
872
873#define MAX_DMA_DESC_NUM_GENERIC 64
874#define MAX_DMA_DESC_NUM_HS_ISOC 256
875
876#endif /* __DWC2_HW_H__ */