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1/*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/gpio.h>
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/platform_data/gpio-davinci.h>
25#include <linux/irqchip/chained_irq.h>
26
27struct davinci_gpio_regs {
28 u32 dir;
29 u32 out_data;
30 u32 set_data;
31 u32 clr_data;
32 u32 in_data;
33 u32 set_rising;
34 u32 clr_rising;
35 u32 set_falling;
36 u32 clr_falling;
37 u32 intstat;
38};
39
40typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
41
42#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
43#define MAX_LABEL_SIZE 20
44
45static void __iomem *gpio_base;
46
47static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
48{
49 void __iomem *ptr;
50
51 if (gpio < 32 * 1)
52 ptr = gpio_base + 0x10;
53 else if (gpio < 32 * 2)
54 ptr = gpio_base + 0x38;
55 else if (gpio < 32 * 3)
56 ptr = gpio_base + 0x60;
57 else if (gpio < 32 * 4)
58 ptr = gpio_base + 0x88;
59 else if (gpio < 32 * 5)
60 ptr = gpio_base + 0xb0;
61 else
62 ptr = NULL;
63 return ptr;
64}
65
66static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
67{
68 struct davinci_gpio_regs __iomem *g;
69
70 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
71
72 return g;
73}
74
75static int davinci_gpio_irq_setup(struct platform_device *pdev);
76
77/*--------------------------------------------------------------------------*/
78
79/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
80static inline int __davinci_direction(struct gpio_chip *chip,
81 unsigned offset, bool out, int value)
82{
83 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
84 struct davinci_gpio_regs __iomem *g = d->regs;
85 unsigned long flags;
86 u32 temp;
87 u32 mask = 1 << offset;
88
89 spin_lock_irqsave(&d->lock, flags);
90 temp = readl_relaxed(&g->dir);
91 if (out) {
92 temp &= ~mask;
93 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
94 } else {
95 temp |= mask;
96 }
97 writel_relaxed(temp, &g->dir);
98 spin_unlock_irqrestore(&d->lock, flags);
99
100 return 0;
101}
102
103static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
104{
105 return __davinci_direction(chip, offset, false, 0);
106}
107
108static int
109davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
110{
111 return __davinci_direction(chip, offset, true, value);
112}
113
114/*
115 * Read the pin's value (works even if it's set up as output);
116 * returns zero/nonzero.
117 *
118 * Note that changes are synched to the GPIO clock, so reading values back
119 * right after you've set them may give old values.
120 */
121static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
122{
123 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
124 struct davinci_gpio_regs __iomem *g = d->regs;
125
126 return !!((1 << offset) & readl_relaxed(&g->in_data));
127}
128
129/*
130 * Assuming the pin is muxed as a gpio output, set its output value.
131 */
132static void
133davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
134{
135 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
136 struct davinci_gpio_regs __iomem *g = d->regs;
137
138 writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
139}
140
141static struct davinci_gpio_platform_data *
142davinci_gpio_get_pdata(struct platform_device *pdev)
143{
144 struct device_node *dn = pdev->dev.of_node;
145 struct davinci_gpio_platform_data *pdata;
146 int ret;
147 u32 val;
148
149 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
150 return dev_get_platdata(&pdev->dev);
151
152 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
153 if (!pdata)
154 return NULL;
155
156 ret = of_property_read_u32(dn, "ti,ngpio", &val);
157 if (ret)
158 goto of_err;
159
160 pdata->ngpio = val;
161
162 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
163 if (ret)
164 goto of_err;
165
166 pdata->gpio_unbanked = val;
167
168 return pdata;
169
170of_err:
171 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
172 return NULL;
173}
174
175#ifdef CONFIG_OF_GPIO
176static int davinci_gpio_of_xlate(struct gpio_chip *gc,
177 const struct of_phandle_args *gpiospec,
178 u32 *flags)
179{
180 struct davinci_gpio_controller *chips = dev_get_drvdata(gc->parent);
181 struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->parent);
182
183 if (gpiospec->args[0] > pdata->ngpio)
184 return -EINVAL;
185
186 if (gc != &chips[gpiospec->args[0] / 32].chip)
187 return -EINVAL;
188
189 if (flags)
190 *flags = gpiospec->args[1];
191
192 return gpiospec->args[0] % 32;
193}
194#endif
195
196static int davinci_gpio_probe(struct platform_device *pdev)
197{
198 int i, base;
199 unsigned ngpio, nbank;
200 struct davinci_gpio_controller *chips;
201 struct davinci_gpio_platform_data *pdata;
202 struct davinci_gpio_regs __iomem *regs;
203 struct device *dev = &pdev->dev;
204 struct resource *res;
205 char label[MAX_LABEL_SIZE];
206
207 pdata = davinci_gpio_get_pdata(pdev);
208 if (!pdata) {
209 dev_err(dev, "No platform data found\n");
210 return -EINVAL;
211 }
212
213 dev->platform_data = pdata;
214
215 /*
216 * The gpio banks conceptually expose a segmented bitmap,
217 * and "ngpio" is one more than the largest zero-based
218 * bit index that's valid.
219 */
220 ngpio = pdata->ngpio;
221 if (ngpio == 0) {
222 dev_err(dev, "How many GPIOs?\n");
223 return -EINVAL;
224 }
225
226 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
227 ngpio = ARCH_NR_GPIOS;
228
229 nbank = DIV_ROUND_UP(ngpio, 32);
230 chips = devm_kzalloc(dev,
231 nbank * sizeof(struct davinci_gpio_controller),
232 GFP_KERNEL);
233 if (!chips)
234 return -ENOMEM;
235
236 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
237 gpio_base = devm_ioremap_resource(dev, res);
238 if (IS_ERR(gpio_base))
239 return PTR_ERR(gpio_base);
240
241 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
242 snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", i);
243 chips[i].chip.label = devm_kstrdup(dev, label, GFP_KERNEL);
244 if (!chips[i].chip.label)
245 return -ENOMEM;
246
247 chips[i].chip.direction_input = davinci_direction_in;
248 chips[i].chip.get = davinci_gpio_get;
249 chips[i].chip.direction_output = davinci_direction_out;
250 chips[i].chip.set = davinci_gpio_set;
251
252 chips[i].chip.base = base;
253 chips[i].chip.ngpio = ngpio - base;
254 if (chips[i].chip.ngpio > 32)
255 chips[i].chip.ngpio = 32;
256
257#ifdef CONFIG_OF_GPIO
258 chips[i].chip.of_gpio_n_cells = 2;
259 chips[i].chip.of_xlate = davinci_gpio_of_xlate;
260 chips[i].chip.parent = dev;
261 chips[i].chip.of_node = dev->of_node;
262#endif
263 spin_lock_init(&chips[i].lock);
264
265 regs = gpio2regs(base);
266 if (!regs)
267 return -ENXIO;
268 chips[i].regs = regs;
269 chips[i].set_data = ®s->set_data;
270 chips[i].clr_data = ®s->clr_data;
271 chips[i].in_data = ®s->in_data;
272
273 gpiochip_add_data(&chips[i].chip, &chips[i]);
274 }
275
276 platform_set_drvdata(pdev, chips);
277 davinci_gpio_irq_setup(pdev);
278 return 0;
279}
280
281/*--------------------------------------------------------------------------*/
282/*
283 * We expect irqs will normally be set up as input pins, but they can also be
284 * used as output pins ... which is convenient for testing.
285 *
286 * NOTE: The first few GPIOs also have direct INTC hookups in addition
287 * to their GPIOBNK0 irq, with a bit less overhead.
288 *
289 * All those INTC hookups (direct, plus several IRQ banks) can also
290 * serve as EDMA event triggers.
291 */
292
293static void gpio_irq_disable(struct irq_data *d)
294{
295 struct davinci_gpio_regs __iomem *g = irq2regs(d);
296 u32 mask = (u32) irq_data_get_irq_handler_data(d);
297
298 writel_relaxed(mask, &g->clr_falling);
299 writel_relaxed(mask, &g->clr_rising);
300}
301
302static void gpio_irq_enable(struct irq_data *d)
303{
304 struct davinci_gpio_regs __iomem *g = irq2regs(d);
305 u32 mask = (u32) irq_data_get_irq_handler_data(d);
306 unsigned status = irqd_get_trigger_type(d);
307
308 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
309 if (!status)
310 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
311
312 if (status & IRQ_TYPE_EDGE_FALLING)
313 writel_relaxed(mask, &g->set_falling);
314 if (status & IRQ_TYPE_EDGE_RISING)
315 writel_relaxed(mask, &g->set_rising);
316}
317
318static int gpio_irq_type(struct irq_data *d, unsigned trigger)
319{
320 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
321 return -EINVAL;
322
323 return 0;
324}
325
326static struct irq_chip gpio_irqchip = {
327 .name = "GPIO",
328 .irq_enable = gpio_irq_enable,
329 .irq_disable = gpio_irq_disable,
330 .irq_set_type = gpio_irq_type,
331 .flags = IRQCHIP_SET_TYPE_MASKED,
332};
333
334static void gpio_irq_handler(struct irq_desc *desc)
335{
336 unsigned int irq = irq_desc_get_irq(desc);
337 struct davinci_gpio_regs __iomem *g;
338 u32 mask = 0xffff;
339 struct davinci_gpio_controller *d;
340
341 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
342 g = (struct davinci_gpio_regs __iomem *)d->regs;
343
344 /* we only care about one bank */
345 if (irq & 1)
346 mask <<= 16;
347
348 /* temporarily mask (level sensitive) parent IRQ */
349 chained_irq_enter(irq_desc_get_chip(desc), desc);
350 while (1) {
351 u32 status;
352 int bit;
353
354 /* ack any irqs */
355 status = readl_relaxed(&g->intstat) & mask;
356 if (!status)
357 break;
358 writel_relaxed(status, &g->intstat);
359
360 /* now demux them to the right lowlevel handler */
361
362 while (status) {
363 bit = __ffs(status);
364 status &= ~BIT(bit);
365 generic_handle_irq(
366 irq_find_mapping(d->irq_domain,
367 d->chip.base + bit));
368 }
369 }
370 chained_irq_exit(irq_desc_get_chip(desc), desc);
371 /* now it may re-trigger */
372}
373
374static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
375{
376 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
377
378 if (d->irq_domain)
379 return irq_create_mapping(d->irq_domain, d->chip.base + offset);
380 else
381 return -ENXIO;
382}
383
384static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
385{
386 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
387
388 /*
389 * NOTE: we assume for now that only irqs in the first gpio_chip
390 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
391 */
392 if (offset < d->gpio_unbanked)
393 return d->gpio_irq + offset;
394 else
395 return -ENODEV;
396}
397
398static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
399{
400 struct davinci_gpio_controller *d;
401 struct davinci_gpio_regs __iomem *g;
402 u32 mask;
403
404 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
405 g = (struct davinci_gpio_regs __iomem *)d->regs;
406 mask = __gpio_mask(data->irq - d->gpio_irq);
407
408 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
409 return -EINVAL;
410
411 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
412 ? &g->set_falling : &g->clr_falling);
413 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
414 ? &g->set_rising : &g->clr_rising);
415
416 return 0;
417}
418
419static int
420davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
421 irq_hw_number_t hw)
422{
423 struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
424
425 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
426 "davinci_gpio");
427 irq_set_irq_type(irq, IRQ_TYPE_NONE);
428 irq_set_chip_data(irq, (__force void *)g);
429 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
430
431 return 0;
432}
433
434static const struct irq_domain_ops davinci_gpio_irq_ops = {
435 .map = davinci_gpio_irq_map,
436 .xlate = irq_domain_xlate_onetwocell,
437};
438
439static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
440{
441 static struct irq_chip_type gpio_unbanked;
442
443 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
444
445 return &gpio_unbanked.chip;
446};
447
448static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
449{
450 static struct irq_chip gpio_unbanked;
451
452 gpio_unbanked = *irq_get_chip(irq);
453 return &gpio_unbanked;
454};
455
456static const struct of_device_id davinci_gpio_ids[];
457
458/*
459 * NOTE: for suspend/resume, probably best to make a platform_device with
460 * suspend_late/resume_resume calls hooking into results of the set_wake()
461 * calls ... so if no gpios are wakeup events the clock can be disabled,
462 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
463 * (dm6446) can be set appropriately for GPIOV33 pins.
464 */
465
466static int davinci_gpio_irq_setup(struct platform_device *pdev)
467{
468 unsigned gpio, bank;
469 int irq;
470 struct clk *clk;
471 u32 binten = 0;
472 unsigned ngpio, bank_irq;
473 struct device *dev = &pdev->dev;
474 struct resource *res;
475 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
476 struct davinci_gpio_platform_data *pdata = dev->platform_data;
477 struct davinci_gpio_regs __iomem *g;
478 struct irq_domain *irq_domain = NULL;
479 const struct of_device_id *match;
480 struct irq_chip *irq_chip;
481 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
482
483 /*
484 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
485 */
486 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
487 match = of_match_device(of_match_ptr(davinci_gpio_ids),
488 dev);
489 if (match)
490 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
491
492 ngpio = pdata->ngpio;
493 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
494 if (!res) {
495 dev_err(dev, "Invalid IRQ resource\n");
496 return -EBUSY;
497 }
498
499 bank_irq = res->start;
500
501 if (!bank_irq) {
502 dev_err(dev, "Invalid IRQ resource\n");
503 return -ENODEV;
504 }
505
506 clk = devm_clk_get(dev, "gpio");
507 if (IS_ERR(clk)) {
508 printk(KERN_ERR "Error %ld getting gpio clock?\n",
509 PTR_ERR(clk));
510 return PTR_ERR(clk);
511 }
512 clk_prepare_enable(clk);
513
514 if (!pdata->gpio_unbanked) {
515 irq = irq_alloc_descs(-1, 0, ngpio, 0);
516 if (irq < 0) {
517 dev_err(dev, "Couldn't allocate IRQ numbers\n");
518 return irq;
519 }
520
521 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
522 &davinci_gpio_irq_ops,
523 chips);
524 if (!irq_domain) {
525 dev_err(dev, "Couldn't register an IRQ domain\n");
526 return -ENODEV;
527 }
528 }
529
530 /*
531 * Arrange gpio_to_irq() support, handling either direct IRQs or
532 * banked IRQs. Having GPIOs in the first GPIO bank use direct
533 * IRQs, while the others use banked IRQs, would need some setup
534 * tweaks to recognize hardware which can do that.
535 */
536 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
537 chips[bank].chip.to_irq = gpio_to_irq_banked;
538 chips[bank].irq_domain = irq_domain;
539 }
540
541 /*
542 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
543 * controller only handling trigger modes. We currently assume no
544 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
545 */
546 if (pdata->gpio_unbanked) {
547 /* pass "bank 0" GPIO IRQs to AINTC */
548 chips[0].chip.to_irq = gpio_to_irq_unbanked;
549 chips[0].gpio_irq = bank_irq;
550 chips[0].gpio_unbanked = pdata->gpio_unbanked;
551 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
552
553 /* AINTC handles mask/unmask; GPIO handles triggering */
554 irq = bank_irq;
555 irq_chip = gpio_get_irq_chip(irq);
556 irq_chip->name = "GPIO-AINTC";
557 irq_chip->irq_set_type = gpio_irq_type_unbanked;
558
559 /* default trigger: both edges */
560 g = gpio2regs(0);
561 writel_relaxed(~0, &g->set_falling);
562 writel_relaxed(~0, &g->set_rising);
563
564 /* set the direct IRQs up to use that irqchip */
565 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
566 irq_set_chip(irq, irq_chip);
567 irq_set_handler_data(irq, &chips[gpio / 32]);
568 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
569 }
570
571 goto done;
572 }
573
574 /*
575 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
576 * then chain through our own handler.
577 */
578 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
579 /* disabled by default, enabled only as needed */
580 g = gpio2regs(gpio);
581 writel_relaxed(~0, &g->clr_falling);
582 writel_relaxed(~0, &g->clr_rising);
583
584 /*
585 * Each chip handles 32 gpios, and each irq bank consists of 16
586 * gpio irqs. Pass the irq bank's corresponding controller to
587 * the chained irq handler.
588 */
589 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
590 &chips[gpio / 32]);
591
592 binten |= BIT(bank);
593 }
594
595done:
596 /*
597 * BINTEN -- per-bank interrupt enable. genirq would also let these
598 * bits be set/cleared dynamically.
599 */
600 writel_relaxed(binten, gpio_base + BINTEN);
601
602 return 0;
603}
604
605#if IS_ENABLED(CONFIG_OF)
606static const struct of_device_id davinci_gpio_ids[] = {
607 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
608 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
609 { /* sentinel */ },
610};
611MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
612#endif
613
614static struct platform_driver davinci_gpio_driver = {
615 .probe = davinci_gpio_probe,
616 .driver = {
617 .name = "davinci_gpio",
618 .of_match_table = of_match_ptr(davinci_gpio_ids),
619 },
620};
621
622/**
623 * GPIO driver registration needs to be done before machine_init functions
624 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
625 */
626static int __init davinci_gpio_drv_reg(void)
627{
628 return platform_driver_register(&davinci_gpio_driver);
629}
630postcore_initcall(davinci_gpio_drv_reg);
1/*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/gpio/driver.h>
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/platform_device.h>
25#include <linux/platform_data/gpio-davinci.h>
26#include <linux/irqchip/chained_irq.h>
27
28struct davinci_gpio_regs {
29 u32 dir;
30 u32 out_data;
31 u32 set_data;
32 u32 clr_data;
33 u32 in_data;
34 u32 set_rising;
35 u32 clr_rising;
36 u32 set_falling;
37 u32 clr_falling;
38 u32 intstat;
39};
40
41typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
42
43#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
44#define MAX_LABEL_SIZE 20
45
46static void __iomem *gpio_base;
47static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
48
49static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
50{
51 struct davinci_gpio_regs __iomem *g;
52
53 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
54
55 return g;
56}
57
58static int davinci_gpio_irq_setup(struct platform_device *pdev);
59
60/*--------------------------------------------------------------------------*/
61
62/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
63static inline int __davinci_direction(struct gpio_chip *chip,
64 unsigned offset, bool out, int value)
65{
66 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
67 struct davinci_gpio_regs __iomem *g;
68 unsigned long flags;
69 u32 temp;
70 int bank = offset / 32;
71 u32 mask = __gpio_mask(offset);
72
73 g = d->regs[bank];
74 spin_lock_irqsave(&d->lock, flags);
75 temp = readl_relaxed(&g->dir);
76 if (out) {
77 temp &= ~mask;
78 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
79 } else {
80 temp |= mask;
81 }
82 writel_relaxed(temp, &g->dir);
83 spin_unlock_irqrestore(&d->lock, flags);
84
85 return 0;
86}
87
88static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
89{
90 return __davinci_direction(chip, offset, false, 0);
91}
92
93static int
94davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
95{
96 return __davinci_direction(chip, offset, true, value);
97}
98
99/*
100 * Read the pin's value (works even if it's set up as output);
101 * returns zero/nonzero.
102 *
103 * Note that changes are synched to the GPIO clock, so reading values back
104 * right after you've set them may give old values.
105 */
106static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
107{
108 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
109 struct davinci_gpio_regs __iomem *g;
110 int bank = offset / 32;
111
112 g = d->regs[bank];
113
114 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
115}
116
117/*
118 * Assuming the pin is muxed as a gpio output, set its output value.
119 */
120static void
121davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
122{
123 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
124 struct davinci_gpio_regs __iomem *g;
125 int bank = offset / 32;
126
127 g = d->regs[bank];
128
129 writel_relaxed(__gpio_mask(offset),
130 value ? &g->set_data : &g->clr_data);
131}
132
133static struct davinci_gpio_platform_data *
134davinci_gpio_get_pdata(struct platform_device *pdev)
135{
136 struct device_node *dn = pdev->dev.of_node;
137 struct davinci_gpio_platform_data *pdata;
138 int ret;
139 u32 val;
140
141 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
142 return dev_get_platdata(&pdev->dev);
143
144 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
145 if (!pdata)
146 return NULL;
147
148 ret = of_property_read_u32(dn, "ti,ngpio", &val);
149 if (ret)
150 goto of_err;
151
152 pdata->ngpio = val;
153
154 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
155 if (ret)
156 goto of_err;
157
158 pdata->gpio_unbanked = val;
159
160 return pdata;
161
162of_err:
163 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
164 return NULL;
165}
166
167static int davinci_gpio_probe(struct platform_device *pdev)
168{
169 static int ctrl_num, bank_base;
170 int gpio, bank, ret = 0;
171 unsigned ngpio, nbank;
172 struct davinci_gpio_controller *chips;
173 struct davinci_gpio_platform_data *pdata;
174 struct device *dev = &pdev->dev;
175 struct resource *res;
176 char label[MAX_LABEL_SIZE];
177
178 pdata = davinci_gpio_get_pdata(pdev);
179 if (!pdata) {
180 dev_err(dev, "No platform data found\n");
181 return -EINVAL;
182 }
183
184 dev->platform_data = pdata;
185
186 /*
187 * The gpio banks conceptually expose a segmented bitmap,
188 * and "ngpio" is one more than the largest zero-based
189 * bit index that's valid.
190 */
191 ngpio = pdata->ngpio;
192 if (ngpio == 0) {
193 dev_err(dev, "How many GPIOs?\n");
194 return -EINVAL;
195 }
196
197 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
198 ngpio = ARCH_NR_GPIOS;
199
200 nbank = DIV_ROUND_UP(ngpio, 32);
201 chips = devm_kzalloc(dev,
202 nbank * sizeof(struct davinci_gpio_controller),
203 GFP_KERNEL);
204 if (!chips)
205 return -ENOMEM;
206
207 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208 gpio_base = devm_ioremap_resource(dev, res);
209 if (IS_ERR(gpio_base))
210 return PTR_ERR(gpio_base);
211
212 snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", ctrl_num++);
213 chips->chip.label = devm_kstrdup(dev, label, GFP_KERNEL);
214 if (!chips->chip.label)
215 return -ENOMEM;
216
217 chips->chip.direction_input = davinci_direction_in;
218 chips->chip.get = davinci_gpio_get;
219 chips->chip.direction_output = davinci_direction_out;
220 chips->chip.set = davinci_gpio_set;
221
222 chips->chip.ngpio = ngpio;
223 chips->chip.base = bank_base;
224
225#ifdef CONFIG_OF_GPIO
226 chips->chip.of_gpio_n_cells = 2;
227 chips->chip.parent = dev;
228 chips->chip.of_node = dev->of_node;
229
230 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
231 chips->chip.request = gpiochip_generic_request;
232 chips->chip.free = gpiochip_generic_free;
233 }
234#endif
235 spin_lock_init(&chips->lock);
236 bank_base += ngpio;
237
238 for (gpio = 0, bank = 0; gpio < ngpio; gpio += 32, bank++)
239 chips->regs[bank] = gpio_base + offset_array[bank];
240
241 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
242 if (ret)
243 goto err;
244
245 platform_set_drvdata(pdev, chips);
246 ret = davinci_gpio_irq_setup(pdev);
247 if (ret)
248 goto err;
249
250 return 0;
251
252err:
253 /* Revert the static variable increments */
254 ctrl_num--;
255 bank_base -= ngpio;
256
257 return ret;
258}
259
260/*--------------------------------------------------------------------------*/
261/*
262 * We expect irqs will normally be set up as input pins, but they can also be
263 * used as output pins ... which is convenient for testing.
264 *
265 * NOTE: The first few GPIOs also have direct INTC hookups in addition
266 * to their GPIOBNK0 irq, with a bit less overhead.
267 *
268 * All those INTC hookups (direct, plus several IRQ banks) can also
269 * serve as EDMA event triggers.
270 */
271
272static void gpio_irq_disable(struct irq_data *d)
273{
274 struct davinci_gpio_regs __iomem *g = irq2regs(d);
275 u32 mask = (u32) irq_data_get_irq_handler_data(d);
276
277 writel_relaxed(mask, &g->clr_falling);
278 writel_relaxed(mask, &g->clr_rising);
279}
280
281static void gpio_irq_enable(struct irq_data *d)
282{
283 struct davinci_gpio_regs __iomem *g = irq2regs(d);
284 u32 mask = (u32) irq_data_get_irq_handler_data(d);
285 unsigned status = irqd_get_trigger_type(d);
286
287 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
288 if (!status)
289 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
290
291 if (status & IRQ_TYPE_EDGE_FALLING)
292 writel_relaxed(mask, &g->set_falling);
293 if (status & IRQ_TYPE_EDGE_RISING)
294 writel_relaxed(mask, &g->set_rising);
295}
296
297static int gpio_irq_type(struct irq_data *d, unsigned trigger)
298{
299 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
300 return -EINVAL;
301
302 return 0;
303}
304
305static struct irq_chip gpio_irqchip = {
306 .name = "GPIO",
307 .irq_enable = gpio_irq_enable,
308 .irq_disable = gpio_irq_disable,
309 .irq_set_type = gpio_irq_type,
310 .flags = IRQCHIP_SET_TYPE_MASKED,
311};
312
313static void gpio_irq_handler(struct irq_desc *desc)
314{
315 struct davinci_gpio_regs __iomem *g;
316 u32 mask = 0xffff;
317 int bank_num;
318 struct davinci_gpio_controller *d;
319 struct davinci_gpio_irq_data *irqdata;
320
321 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
322 bank_num = irqdata->bank_num;
323 g = irqdata->regs;
324 d = irqdata->chip;
325
326 /* we only care about one bank */
327 if ((bank_num % 2) == 1)
328 mask <<= 16;
329
330 /* temporarily mask (level sensitive) parent IRQ */
331 chained_irq_enter(irq_desc_get_chip(desc), desc);
332 while (1) {
333 u32 status;
334 int bit;
335 irq_hw_number_t hw_irq;
336
337 /* ack any irqs */
338 status = readl_relaxed(&g->intstat) & mask;
339 if (!status)
340 break;
341 writel_relaxed(status, &g->intstat);
342
343 /* now demux them to the right lowlevel handler */
344
345 while (status) {
346 bit = __ffs(status);
347 status &= ~BIT(bit);
348 /* Max number of gpios per controller is 144 so
349 * hw_irq will be in [0..143]
350 */
351 hw_irq = (bank_num / 2) * 32 + bit;
352
353 generic_handle_irq(
354 irq_find_mapping(d->irq_domain, hw_irq));
355 }
356 }
357 chained_irq_exit(irq_desc_get_chip(desc), desc);
358 /* now it may re-trigger */
359}
360
361static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
362{
363 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
364
365 if (d->irq_domain)
366 return irq_create_mapping(d->irq_domain, offset);
367 else
368 return -ENXIO;
369}
370
371static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
372{
373 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
374
375 /*
376 * NOTE: we assume for now that only irqs in the first gpio_chip
377 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
378 */
379 if (offset < d->gpio_unbanked)
380 return d->base_irq + offset;
381 else
382 return -ENODEV;
383}
384
385static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
386{
387 struct davinci_gpio_controller *d;
388 struct davinci_gpio_regs __iomem *g;
389 u32 mask;
390
391 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
392 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
393 mask = __gpio_mask(data->irq - d->base_irq);
394
395 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
396 return -EINVAL;
397
398 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
399 ? &g->set_falling : &g->clr_falling);
400 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
401 ? &g->set_rising : &g->clr_rising);
402
403 return 0;
404}
405
406static int
407davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
408 irq_hw_number_t hw)
409{
410 struct davinci_gpio_controller *chips =
411 (struct davinci_gpio_controller *)d->host_data;
412 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
413
414 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
415 "davinci_gpio");
416 irq_set_irq_type(irq, IRQ_TYPE_NONE);
417 irq_set_chip_data(irq, (__force void *)g);
418 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
419
420 return 0;
421}
422
423static const struct irq_domain_ops davinci_gpio_irq_ops = {
424 .map = davinci_gpio_irq_map,
425 .xlate = irq_domain_xlate_onetwocell,
426};
427
428static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
429{
430 static struct irq_chip_type gpio_unbanked;
431
432 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
433
434 return &gpio_unbanked.chip;
435};
436
437static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
438{
439 static struct irq_chip gpio_unbanked;
440
441 gpio_unbanked = *irq_get_chip(irq);
442 return &gpio_unbanked;
443};
444
445static const struct of_device_id davinci_gpio_ids[];
446
447/*
448 * NOTE: for suspend/resume, probably best to make a platform_device with
449 * suspend_late/resume_resume calls hooking into results of the set_wake()
450 * calls ... so if no gpios are wakeup events the clock can be disabled,
451 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
452 * (dm6446) can be set appropriately for GPIOV33 pins.
453 */
454
455static int davinci_gpio_irq_setup(struct platform_device *pdev)
456{
457 unsigned gpio, bank;
458 int irq;
459 int ret;
460 struct clk *clk;
461 u32 binten = 0;
462 unsigned ngpio, bank_irq;
463 struct device *dev = &pdev->dev;
464 struct resource *res;
465 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
466 struct davinci_gpio_platform_data *pdata = dev->platform_data;
467 struct davinci_gpio_regs __iomem *g;
468 struct irq_domain *irq_domain = NULL;
469 const struct of_device_id *match;
470 struct irq_chip *irq_chip;
471 struct davinci_gpio_irq_data *irqdata;
472 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
473
474 /*
475 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
476 */
477 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
478 match = of_match_device(of_match_ptr(davinci_gpio_ids),
479 dev);
480 if (match)
481 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
482
483 ngpio = pdata->ngpio;
484 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
485 if (!res) {
486 dev_err(dev, "Invalid IRQ resource\n");
487 return -EBUSY;
488 }
489
490 bank_irq = res->start;
491
492 if (!bank_irq) {
493 dev_err(dev, "Invalid IRQ resource\n");
494 return -ENODEV;
495 }
496
497 clk = devm_clk_get(dev, "gpio");
498 if (IS_ERR(clk)) {
499 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
500 return PTR_ERR(clk);
501 }
502 ret = clk_prepare_enable(clk);
503 if (ret)
504 return ret;
505
506 if (!pdata->gpio_unbanked) {
507 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
508 if (irq < 0) {
509 dev_err(dev, "Couldn't allocate IRQ numbers\n");
510 clk_disable_unprepare(clk);
511 return irq;
512 }
513
514 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
515 &davinci_gpio_irq_ops,
516 chips);
517 if (!irq_domain) {
518 dev_err(dev, "Couldn't register an IRQ domain\n");
519 clk_disable_unprepare(clk);
520 return -ENODEV;
521 }
522 }
523
524 /*
525 * Arrange gpio_to_irq() support, handling either direct IRQs or
526 * banked IRQs. Having GPIOs in the first GPIO bank use direct
527 * IRQs, while the others use banked IRQs, would need some setup
528 * tweaks to recognize hardware which can do that.
529 */
530 chips->chip.to_irq = gpio_to_irq_banked;
531 chips->irq_domain = irq_domain;
532
533 /*
534 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
535 * controller only handling trigger modes. We currently assume no
536 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
537 */
538 if (pdata->gpio_unbanked) {
539 /* pass "bank 0" GPIO IRQs to AINTC */
540 chips->chip.to_irq = gpio_to_irq_unbanked;
541 chips->base_irq = bank_irq;
542 chips->gpio_unbanked = pdata->gpio_unbanked;
543 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
544
545 /* AINTC handles mask/unmask; GPIO handles triggering */
546 irq = bank_irq;
547 irq_chip = gpio_get_irq_chip(irq);
548 irq_chip->name = "GPIO-AINTC";
549 irq_chip->irq_set_type = gpio_irq_type_unbanked;
550
551 /* default trigger: both edges */
552 g = chips->regs[0];
553 writel_relaxed(~0, &g->set_falling);
554 writel_relaxed(~0, &g->set_rising);
555
556 /* set the direct IRQs up to use that irqchip */
557 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
558 irq_set_chip(irq, irq_chip);
559 irq_set_handler_data(irq, chips);
560 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
561 }
562
563 goto done;
564 }
565
566 /*
567 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
568 * then chain through our own handler.
569 */
570 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
571 /* disabled by default, enabled only as needed
572 * There are register sets for 32 GPIOs. 2 banks of 16
573 * GPIOs are covered by each set of registers hence divide by 2
574 */
575 g = chips->regs[bank / 2];
576 writel_relaxed(~0, &g->clr_falling);
577 writel_relaxed(~0, &g->clr_rising);
578
579 /*
580 * Each chip handles 32 gpios, and each irq bank consists of 16
581 * gpio irqs. Pass the irq bank's corresponding controller to
582 * the chained irq handler.
583 */
584 irqdata = devm_kzalloc(&pdev->dev,
585 sizeof(struct
586 davinci_gpio_irq_data),
587 GFP_KERNEL);
588 if (!irqdata) {
589 clk_disable_unprepare(clk);
590 return -ENOMEM;
591 }
592
593 irqdata->regs = g;
594 irqdata->bank_num = bank;
595 irqdata->chip = chips;
596
597 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
598 irqdata);
599
600 binten |= BIT(bank);
601 }
602
603done:
604 /*
605 * BINTEN -- per-bank interrupt enable. genirq would also let these
606 * bits be set/cleared dynamically.
607 */
608 writel_relaxed(binten, gpio_base + BINTEN);
609
610 return 0;
611}
612
613#if IS_ENABLED(CONFIG_OF)
614static const struct of_device_id davinci_gpio_ids[] = {
615 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
616 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
617 { /* sentinel */ },
618};
619MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
620#endif
621
622static struct platform_driver davinci_gpio_driver = {
623 .probe = davinci_gpio_probe,
624 .driver = {
625 .name = "davinci_gpio",
626 .of_match_table = of_match_ptr(davinci_gpio_ids),
627 },
628};
629
630/**
631 * GPIO driver registration needs to be done before machine_init functions
632 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
633 */
634static int __init davinci_gpio_drv_reg(void)
635{
636 return platform_driver_register(&davinci_gpio_driver);
637}
638postcore_initcall(davinci_gpio_drv_reg);