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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef SMU74_DISCRETE_H
25#define SMU74_DISCRETE_H
26
27#include "smu74.h"
28
29#pragma pack(push, 1)
30
31
32#define NUM_SCLK_RANGE 8
33
34#define VCO_3_6 1
35#define VCO_2_4 3
36
37#define POSTDIV_DIV_BY_1 0
38#define POSTDIV_DIV_BY_2 1
39#define POSTDIV_DIV_BY_4 2
40#define POSTDIV_DIV_BY_8 3
41#define POSTDIV_DIV_BY_16 4
42
43struct sclkFcwRange_t {
44 uint8_t vco_setting;
45 uint8_t postdiv;
46 uint16_t fcw_pcc;
47
48 uint16_t fcw_trans_upper;
49 uint16_t fcw_trans_lower;
50};
51typedef struct sclkFcwRange_t sclkFcwRange_t;
52
53struct SMIO_Pattern {
54 uint16_t Voltage;
55 uint8_t Smio;
56 uint8_t padding;
57};
58
59typedef struct SMIO_Pattern SMIO_Pattern;
60
61struct SMIO_Table {
62 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
63};
64
65typedef struct SMIO_Table SMIO_Table;
66
67struct SMU_SclkSetting {
68 uint32_t SclkFrequency;
69 uint16_t Fcw_int;
70 uint16_t Fcw_frac;
71 uint16_t Pcc_fcw_int;
72 uint8_t PllRange;
73 uint8_t SSc_En;
74 uint16_t Sclk_slew_rate;
75 uint16_t Pcc_up_slew_rate;
76 uint16_t Pcc_down_slew_rate;
77 uint16_t Fcw1_int;
78 uint16_t Fcw1_frac;
79 uint16_t Sclk_ss_slew_rate;
80};
81typedef struct SMU_SclkSetting SMU_SclkSetting;
82
83struct SMU74_Discrete_GraphicsLevel {
84 SMU_VoltageLevel MinVoltage;
85 uint8_t pcieDpmLevel;
86 uint8_t DeepSleepDivId;
87 uint16_t ActivityLevel;
88 uint32_t CgSpllFuncCntl3;
89 uint32_t CgSpllFuncCntl4;
90 uint32_t CcPwrDynRm;
91 uint32_t CcPwrDynRm1;
92 uint8_t SclkDid;
93 uint8_t padding;
94 uint8_t EnabledForActivity;
95 uint8_t EnabledForThrottle;
96 uint8_t UpHyst;
97 uint8_t DownHyst;
98 uint8_t VoltageDownHyst;
99 uint8_t PowerThrottle;
100 SMU_SclkSetting SclkSetting;
101};
102
103typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel;
104
105struct SMU74_Discrete_ACPILevel {
106 uint32_t Flags;
107 SMU_VoltageLevel MinVoltage;
108 uint32_t SclkFrequency;
109 uint8_t SclkDid;
110 uint8_t DisplayWatermark;
111 uint8_t DeepSleepDivId;
112 uint8_t padding;
113 uint32_t CcPwrDynRm;
114 uint32_t CcPwrDynRm1;
115
116 SMU_SclkSetting SclkSetting;
117};
118
119typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel;
120
121struct SMU74_Discrete_Ulv {
122 uint32_t CcPwrDynRm;
123 uint32_t CcPwrDynRm1;
124 uint16_t VddcOffset;
125 uint8_t VddcOffsetVid;
126 uint8_t VddcPhase;
127 uint16_t BifSclkDfs;
128 uint16_t Reserved;
129};
130
131typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
132
133struct SMU74_Discrete_MemoryLevel {
134 SMU_VoltageLevel MinVoltage;
135 uint32_t MinMvdd;
136
137 uint32_t MclkFrequency;
138
139 uint8_t StutterEnable;
140 uint8_t EnabledForThrottle;
141 uint8_t EnabledForActivity;
142 uint8_t padding_0;
143
144 uint8_t UpHyst;
145 uint8_t DownHyst;
146 uint8_t VoltageDownHyst;
147 uint8_t padding_1;
148
149 uint16_t ActivityLevel;
150 uint8_t DisplayWatermark;
151 uint8_t Reserved;
152};
153
154typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel;
155
156struct SMU74_Discrete_LinkLevel {
157 uint8_t PcieGenSpeed;
158 uint8_t PcieLaneCount;
159 uint8_t EnabledForActivity;
160 uint8_t SPC;
161 uint32_t DownThreshold;
162 uint32_t UpThreshold;
163 uint16_t BifSclkDfs;
164 uint16_t Reserved;
165};
166
167typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
168
169struct SMU74_Discrete_MCArbDramTimingTableEntry {
170 uint32_t McArbDramTiming;
171 uint32_t McArbDramTiming2;
172 uint8_t McArbBurstTime;
173 uint8_t padding[3];
174};
175
176typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry;
177
178struct SMU74_Discrete_MCArbDramTimingTable {
179 SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
180};
181
182typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable;
183
184struct SMU74_Discrete_UvdLevel {
185 uint32_t VclkFrequency;
186 uint32_t DclkFrequency;
187 SMU_VoltageLevel MinVoltage;
188 uint8_t VclkDivider;
189 uint8_t DclkDivider;
190 uint8_t padding[2];
191};
192
193typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel;
194
195struct SMU74_Discrete_ExtClkLevel {
196 uint32_t Frequency;
197 SMU_VoltageLevel MinVoltage;
198 uint8_t Divider;
199 uint8_t padding[3];
200};
201
202typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel;
203
204struct SMU74_Discrete_StateInfo {
205 uint32_t SclkFrequency;
206 uint32_t MclkFrequency;
207 uint32_t VclkFrequency;
208 uint32_t DclkFrequency;
209 uint32_t SamclkFrequency;
210 uint32_t AclkFrequency;
211 uint32_t EclkFrequency;
212 uint16_t MvddVoltage;
213 uint16_t padding16;
214 uint8_t DisplayWatermark;
215 uint8_t McArbIndex;
216 uint8_t McRegIndex;
217 uint8_t SeqIndex;
218 uint8_t SclkDid;
219 int8_t SclkIndex;
220 int8_t MclkIndex;
221 uint8_t PCIeGen;
222};
223
224typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
225
226struct SMU_QuadraticCoeffs {
227 int32_t m1;
228 uint32_t b;
229
230 int16_t m2;
231 uint8_t m1_shift;
232 uint8_t m2_shift;
233};
234typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
235
236struct SMU74_Discrete_DpmTable {
237
238 SMU74_PIDController GraphicsPIDController;
239 SMU74_PIDController MemoryPIDController;
240 SMU74_PIDController LinkPIDController;
241
242 uint32_t SystemFlags;
243
244 uint32_t VRConfig;
245 uint32_t SmioMask1;
246 uint32_t SmioMask2;
247 SMIO_Table SmioTable1;
248 SMIO_Table SmioTable2;
249
250 uint32_t MvddLevelCount;
251
252
253 uint8_t BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
254 uint8_t BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
255 uint8_t BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
256
257 uint8_t GraphicsDpmLevelCount;
258 uint8_t MemoryDpmLevelCount;
259 uint8_t LinkLevelCount;
260 uint8_t MasterDeepSleepControl;
261
262 uint8_t UvdLevelCount;
263 uint8_t VceLevelCount;
264 uint8_t AcpLevelCount;
265 uint8_t SamuLevelCount;
266
267 uint8_t ThermOutGpio;
268 uint8_t ThermOutPolarity;
269 uint8_t ThermOutMode;
270 uint8_t BootPhases;
271
272 uint8_t VRHotLevel;
273 uint8_t LdoRefSel;
274 uint8_t Reserved1[2];
275 uint16_t FanStartTemperature;
276 uint16_t FanStopTemperature;
277 uint16_t MaxVoltage;
278 uint16_t Reserved2;
279 uint32_t Reserved[1];
280
281 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
282 SMU74_Discrete_MemoryLevel MemoryACPILevel;
283 SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
284 SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK];
285 SMU74_Discrete_ACPILevel ACPILevel;
286 SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD];
287 SMU74_Discrete_ExtClkLevel VceLevel[SMU74_MAX_LEVELS_VCE];
288 SMU74_Discrete_ExtClkLevel AcpLevel[SMU74_MAX_LEVELS_ACP];
289 SMU74_Discrete_ExtClkLevel SamuLevel[SMU74_MAX_LEVELS_SAMU];
290 SMU74_Discrete_Ulv Ulv;
291
292 uint8_t DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
293
294 uint32_t SclkStepSize;
295 uint32_t Smio[SMU74_MAX_ENTRIES_SMIO];
296
297 uint8_t UvdBootLevel;
298 uint8_t VceBootLevel;
299 uint8_t AcpBootLevel;
300 uint8_t SamuBootLevel;
301
302 uint8_t GraphicsBootLevel;
303 uint8_t GraphicsVoltageChangeEnable;
304 uint8_t GraphicsThermThrottleEnable;
305 uint8_t GraphicsInterval;
306
307 uint8_t VoltageInterval;
308 uint8_t ThermalInterval;
309 uint16_t TemperatureLimitHigh;
310
311 uint16_t TemperatureLimitLow;
312 uint8_t MemoryBootLevel;
313 uint8_t MemoryVoltageChangeEnable;
314
315 uint16_t BootMVdd;
316 uint8_t MemoryInterval;
317 uint8_t MemoryThermThrottleEnable;
318
319 uint16_t VoltageResponseTime;
320 uint16_t PhaseResponseTime;
321
322 uint8_t PCIeBootLinkLevel;
323 uint8_t PCIeGenInterval;
324 uint8_t DTEInterval;
325 uint8_t DTEMode;
326
327 uint8_t SVI2Enable;
328 uint8_t VRHotGpio;
329 uint8_t AcDcGpio;
330 uint8_t ThermGpio;
331
332 uint16_t PPM_PkgPwrLimit;
333 uint16_t PPM_TemperatureLimit;
334
335 uint16_t DefaultTdp;
336 uint16_t TargetTdp;
337
338 uint16_t FpsHighThreshold;
339 uint16_t FpsLowThreshold;
340
341 uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
342 uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
343
344 uint16_t TemperatureLimitEdge;
345 uint16_t TemperatureLimitHotspot;
346
347 uint16_t BootVddc;
348 uint16_t BootVddci;
349
350 uint16_t FanGainEdge;
351 uint16_t FanGainHotspot;
352
353 uint32_t LowSclkInterruptThreshold;
354 uint32_t VddGfxReChkWait;
355
356 uint8_t ClockStretcherAmount;
357 uint8_t Sclk_CKS_masterEn0_7;
358 uint8_t Sclk_CKS_masterEn8_15;
359 uint8_t DPMFreezeAndForced;
360
361 uint8_t Sclk_voltageOffset[8];
362
363 SMU_ClockStretcherDataTable ClockStretcherDataTable;
364 SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
365
366 uint32_t CurrSclkPllRange;
367 sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
368 GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
369 SMU_QuadraticCoeffs AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
370};
371
372typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
373
374
375struct SMU74_Discrete_FanTable {
376 uint16_t FdoMode;
377 int16_t TempMin;
378 int16_t TempMed;
379 int16_t TempMax;
380 int16_t Slope1;
381 int16_t Slope2;
382 int16_t FdoMin;
383 int16_t HystUp;
384 int16_t HystDown;
385 int16_t HystSlope;
386 int16_t TempRespLim;
387 int16_t TempCurr;
388 int16_t SlopeCurr;
389 int16_t PwmCurr;
390 uint32_t RefreshPeriod;
391 int16_t FdoMax;
392 uint8_t TempSrc;
393 int8_t Padding;
394};
395
396typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable;
397
398#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
399#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
400
401
402struct SMU7_MclkDpmScoreboard {
403 uint32_t PercentageBusy;
404
405 int32_t PIDError;
406 int32_t PIDIntegral;
407 int32_t PIDOutput;
408
409 uint32_t SigmaDeltaAccum;
410 uint32_t SigmaDeltaOutput;
411 uint32_t SigmaDeltaLevel;
412
413 uint32_t UtilizationSetpoint;
414
415 uint8_t TdpClampMode;
416 uint8_t TdcClampMode;
417 uint8_t ThermClampMode;
418 uint8_t VoltageBusy;
419
420 int8_t CurrLevel;
421 int8_t TargLevel;
422 uint8_t LevelChangeInProgress;
423 uint8_t UpHyst;
424
425 uint8_t DownHyst;
426 uint8_t VoltageDownHyst;
427 uint8_t DpmEnable;
428 uint8_t DpmRunning;
429
430 uint8_t DpmForce;
431 uint8_t DpmForceLevel;
432 uint8_t padding2;
433 uint8_t McArbIndex;
434
435 uint32_t MinimumPerfMclk;
436
437 uint8_t AcpiReq;
438 uint8_t AcpiAck;
439 uint8_t MclkSwitchInProgress;
440 uint8_t MclkSwitchCritical;
441
442 uint8_t IgnoreVBlank;
443 uint8_t TargetMclkIndex;
444 uint16_t VbiFailureCount;
445 uint8_t VbiWaitCounter;
446 uint8_t EnabledLevelsChange;
447
448 uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY];
449 uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY];
450
451 void (*TargetStateCalculator)(uint8_t);
452 void (*SavedTargetStateCalculator)(uint8_t);
453
454 uint16_t AutoDpmInterval;
455 uint16_t AutoDpmRange;
456
457 uint16_t VbiTimeoutCount;
458 uint16_t MclkSwitchingTime;
459
460 uint8_t fastSwitch;
461 uint8_t Save_PIC_VDDGFX_EXIT;
462 uint8_t Save_PIC_VDDGFX_ENTER;
463 uint8_t padding;
464};
465
466typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
467
468struct SMU7_UlvScoreboard {
469 uint8_t EnterUlv;
470 uint8_t ExitUlv;
471 uint8_t UlvActive;
472 uint8_t WaitingForUlv;
473 uint8_t UlvEnable;
474 uint8_t UlvRunning;
475 uint8_t UlvMasterEnable;
476 uint8_t padding;
477 uint32_t UlvAbortedCount;
478 uint32_t UlvTimeStamp;
479};
480
481typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
482
483struct VddgfxSavedRegisters {
484 uint32_t GPU_DBG[3];
485 uint32_t MEC_BaseAddress_Hi;
486 uint32_t MEC_BaseAddress_Lo;
487 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
488 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
489 uint32_t CP_INT_CNTL;
490};
491
492typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
493
494struct SMU7_VddGfxScoreboard {
495 uint8_t VddGfxEnable;
496 uint8_t VddGfxActive;
497 uint8_t VPUResetOccured;
498 uint8_t padding;
499
500 uint32_t VddGfxEnteredCount;
501 uint32_t VddGfxAbortedCount;
502
503 uint32_t VddGfxVid;
504
505 VddgfxSavedRegisters SavedRegisters;
506};
507
508typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
509
510struct SMU7_TdcLimitScoreboard {
511 uint8_t Enable;
512 uint8_t Running;
513 uint16_t Alpha;
514 uint32_t FilteredIddc;
515 uint32_t IddcLimit;
516 uint32_t IddcHyst;
517 SMU7_HystController_Data HystControllerData;
518};
519
520typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
521
522struct SMU7_PkgPwrLimitScoreboard {
523 uint8_t Enable;
524 uint8_t Running;
525 uint16_t Alpha;
526 uint32_t FilteredPkgPwr;
527 uint32_t Limit;
528 uint32_t Hyst;
529 uint32_t LimitFromDriver;
530 SMU7_HystController_Data HystControllerData;
531};
532
533typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
534
535struct SMU7_BapmScoreboard {
536 uint32_t source_powers[SMU74_DTE_SOURCES];
537 uint32_t source_powers_last[SMU74_DTE_SOURCES];
538 int32_t entity_temperatures[SMU74_NUM_GPU_TES];
539 int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES];
540 int32_t Limit;
541 int32_t Hyst;
542 int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2];
543 int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
544 uint16_t ConfigTDPPowerScalar;
545 uint16_t FanSpeedPowerScalar;
546 uint16_t OverDrivePowerScalar;
547 uint16_t OverDriveLimitScalar;
548 uint16_t FinalPowerScalar;
549 uint8_t VariantID;
550 uint8_t spare997;
551
552 SMU7_HystController_Data HystControllerData;
553
554 int32_t temperature_gradient_slope;
555 int32_t temperature_gradient;
556 uint32_t measured_temperature;
557};
558
559
560typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
561
562struct SMU7_AcpiScoreboard {
563 uint32_t SavedInterruptMask[2];
564 uint8_t LastACPIRequest;
565 uint8_t CgBifResp;
566 uint8_t RequestType;
567 uint8_t Padding;
568 SMU74_Discrete_ACPILevel D0Level;
569};
570
571typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
572
573struct SMU74_Discrete_PmFuses {
574 uint8_t BapmVddCVidHiSidd[8];
575 uint8_t BapmVddCVidLoSidd[8];
576 uint8_t VddCVid[8];
577 uint8_t SviLoadLineEn;
578 uint8_t SviLoadLineVddC;
579 uint8_t SviLoadLineTrimVddC;
580 uint8_t SviLoadLineOffsetVddC;
581 uint16_t TDC_VDDC_PkgLimit;
582 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
583 uint8_t TDC_MAWt;
584 uint8_t TdcWaterfallCtl;
585 uint8_t LPMLTemperatureMin;
586 uint8_t LPMLTemperatureMax;
587 uint8_t Reserved;
588
589 uint8_t LPMLTemperatureScaler[16];
590
591 int16_t FuzzyFan_ErrorSetDelta;
592 int16_t FuzzyFan_ErrorRateSetDelta;
593 int16_t FuzzyFan_PwmSetDelta;
594 uint16_t Reserved6;
595
596 uint8_t GnbLPML[16];
597
598 uint8_t GnbLPMLMaxVid;
599 uint8_t GnbLPMLMinVid;
600 uint8_t Reserved1[2];
601
602 uint16_t BapmVddCBaseLeakageHiSidd;
603 uint16_t BapmVddCBaseLeakageLoSidd;
604
605 uint16_t VFT_Temp[3];
606 uint16_t padding;
607
608 SMU_QuadraticCoeffs VFT_ATE[3];
609
610 SMU_QuadraticCoeffs AVFS_GB;
611 SMU_QuadraticCoeffs ATE_ACBTC_GB;
612
613 SMU_QuadraticCoeffs P2V;
614
615 uint32_t PsmCharzFreq;
616
617 uint16_t InversionVoltage;
618 uint16_t PsmCharzTemp;
619
620 uint32_t EnabledAvfsModules;
621};
622
623typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses;
624
625struct SMU7_Discrete_Log_Header_Table {
626 uint32_t version;
627 uint32_t asic_id;
628 uint16_t flags;
629 uint16_t entry_size;
630 uint32_t total_size;
631 uint32_t num_of_entries;
632 uint8_t type;
633 uint8_t mode;
634 uint8_t filler_0[2];
635 uint32_t filler_1[2];
636};
637
638typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
639
640struct SMU7_Discrete_Log_Cntl {
641 uint8_t Enabled;
642 uint8_t Type;
643 uint8_t padding[2];
644 uint32_t BufferSize;
645 uint32_t SamplesLogged;
646 uint32_t SampleSize;
647 uint32_t AddrL;
648 uint32_t AddrH;
649};
650
651typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
652
653#if defined SMU__DGPU_ONLY
654#define CAC_ACC_NW_NUM_OF_SIGNALS 87
655#endif
656
657
658struct SMU7_Discrete_Cac_Collection_Table {
659 uint32_t temperature;
660 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
661};
662
663typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
664
665struct SMU7_Discrete_Cac_Verification_Table {
666 uint32_t VddcTotalPower;
667 uint32_t VddcLeakagePower;
668 uint32_t VddcConstantPower;
669 uint32_t VddcGfxDynamicPower;
670 uint32_t VddcUvdDynamicPower;
671 uint32_t VddcVceDynamicPower;
672 uint32_t VddcAcpDynamicPower;
673 uint32_t VddcPcieDynamicPower;
674 uint32_t VddcDceDynamicPower;
675 uint32_t VddcCurrent;
676 uint32_t VddcVoltage;
677 uint32_t VddciTotalPower;
678 uint32_t VddciLeakagePower;
679 uint32_t VddciConstantPower;
680 uint32_t VddciDynamicPower;
681 uint32_t Vddr1TotalPower;
682 uint32_t Vddr1LeakagePower;
683 uint32_t Vddr1ConstantPower;
684 uint32_t Vddr1DynamicPower;
685 uint32_t spare[4];
686 uint32_t temperature;
687};
688
689typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
690
691struct SMU7_Discrete_Pm_Status_Table {
692 int32_t T_meas_max;
693 int32_t T_meas_acc;
694 int32_t T_calc_max;
695 int32_t T_calc_acc;
696 uint32_t P_scalar_acc;
697 uint32_t P_calc_max;
698 uint32_t P_calc_acc;
699
700 uint32_t I_calc_max;
701 uint32_t I_calc_acc;
702 uint32_t I_calc_acc_vddci;
703 uint32_t V_calc_noload_acc;
704 uint32_t V_calc_load_acc;
705 uint32_t V_calc_noload_acc_vddci;
706 uint32_t P_meas_acc;
707 uint32_t V_meas_noload_acc;
708 uint32_t V_meas_load_acc;
709 uint32_t I_meas_acc;
710 uint32_t P_meas_acc_vddci;
711 uint32_t V_meas_noload_acc_vddci;
712 uint32_t V_meas_load_acc_vddci;
713 uint32_t I_meas_acc_vddci;
714
715 uint16_t Sclk_dpm_residency[8];
716 uint16_t Uvd_dpm_residency[8];
717 uint16_t Vce_dpm_residency[8];
718 uint16_t Mclk_dpm_residency[4];
719
720 uint32_t P_vddci_acc;
721 uint32_t P_vddr1_acc;
722 uint32_t P_nte1_acc;
723 uint32_t PkgPwr_max;
724 uint32_t PkgPwr_acc;
725 uint32_t MclkSwitchingTime_max;
726 uint32_t MclkSwitchingTime_acc;
727 uint32_t FanPwm_acc;
728 uint32_t FanRpm_acc;
729
730 uint32_t AccCnt;
731};
732
733typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
734
735#define SMU7_MAX_GFX_CU_COUNT 16
736
737struct SMU7_GfxCuPgScoreboard {
738 uint8_t Enabled;
739 uint8_t WaterfallUp;
740 uint8_t WaterfallDown;
741 uint8_t WaterfallLimit;
742 uint8_t CurrMaxCu;
743 uint8_t TargMaxCu;
744 uint8_t ClampMode;
745 uint8_t Active;
746 uint8_t MaxSupportedCu;
747 uint8_t MinSupportedCu;
748 uint8_t PendingGfxCuHostInterrupt;
749 uint8_t LastFilteredMaxCuInteger;
750 uint16_t FilteredMaxCu;
751 uint16_t FilteredMaxCuAlpha;
752 uint16_t FilterResetCount;
753 uint16_t FilterResetCountLimit;
754 uint8_t ForceCu;
755 uint8_t ForceCuCount;
756 uint8_t spare[2];
757};
758
759typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
760
761#define SMU7_SCLK_CAC 0x561
762#define SMU7_MCLK_CAC 0xF9
763#define SMU7_VCLK_CAC 0x2DE
764#define SMU7_DCLK_CAC 0x2DE
765#define SMU7_ECLK_CAC 0x25E
766#define SMU7_ACLK_CAC 0x25E
767#define SMU7_SAMCLK_CAC 0x25E
768#define SMU7_DISPCLK_CAC 0x100
769#define SMU7_CAC_CONSTANT 0x2EE3430
770#define SMU7_CAC_CONSTANT_SHIFT 18
771
772#define SMU7_VDDCI_MCLK_CONST 1765
773#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
774#define SMU7_VDDCI_VDDCI_CONST 50958
775#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
776#define SMU7_VDDCI_CONST 11781
777#define SMU7_VDDCI_STROBE_PWR 1331
778
779#define SMU7_VDDR1_CONST 693
780#define SMU7_VDDR1_CAC_WEIGHT 20
781#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
782#define SMU7_VDDR1_STROBE_PWR 512
783
784#define SMU7_AREA_COEFF_UVD 0xA78
785#define SMU7_AREA_COEFF_VCE 0x190A
786#define SMU7_AREA_COEFF_ACP 0x22D1
787#define SMU7_AREA_COEFF_SAMU 0x534
788
789#define SMU7_THERM_OUT_MODE_DISABLE 0x0
790#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
791#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
792
793// DIDT Defines
794#define SQ_Enable_MASK 0x1
795#define SQ_IR_MASK 0x2
796#define SQ_PCC_MASK 0x4
797#define SQ_EDC_MASK 0x8
798
799#define TCP_Enable_MASK 0x100
800#define TCP_IR_MASK 0x200
801#define TCP_PCC_MASK 0x400
802#define TCP_EDC_MASK 0x800
803
804#define TD_Enable_MASK 0x10000
805#define TD_IR_MASK 0x20000
806#define TD_PCC_MASK 0x40000
807#define TD_EDC_MASK 0x80000
808
809#define DB_Enable_MASK 0x1000000
810#define DB_IR_MASK 0x2000000
811#define DB_PCC_MASK 0x4000000
812#define DB_EDC_MASK 0x8000000
813
814#define SQ_Enable_SHIFT 0
815#define SQ_IR_SHIFT 1
816#define SQ_PCC_SHIFT 2
817#define SQ_EDC_SHIFT 3
818
819#define TCP_Enable_SHIFT 8
820#define TCP_IR_SHIFT 9
821#define TCP_PCC_SHIFT 10
822#define TCP_EDC_SHIFT 11
823
824#define TD_Enable_SHIFT 16
825#define TD_IR_SHIFT 17
826#define TD_PCC_SHIFT 18
827#define TD_EDC_SHIFT 19
828
829#define DB_Enable_SHIFT 24
830#define DB_IR_SHIFT 25
831#define DB_PCC_SHIFT 26
832#define DB_EDC_SHIFT 27
833
834#define BTCGB0_Vdroop_Enable_MASK 0x1
835#define BTCGB1_Vdroop_Enable_MASK 0x2
836#define AVFSGB0_Vdroop_Enable_MASK 0x4
837#define AVFSGB1_Vdroop_Enable_MASK 0x8
838
839#define BTCGB0_Vdroop_Enable_SHIFT 0
840#define BTCGB1_Vdroop_Enable_SHIFT 1
841#define AVFSGB0_Vdroop_Enable_SHIFT 2
842#define AVFSGB1_Vdroop_Enable_SHIFT 3
843
844
845#pragma pack(pop)
846
847
848#endif
849
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef SMU74_DISCRETE_H
25#define SMU74_DISCRETE_H
26
27#include "smu74.h"
28
29#pragma pack(push, 1)
30
31
32#define NUM_SCLK_RANGE 8
33
34#define VCO_3_6 1
35#define VCO_2_4 3
36
37#define POSTDIV_DIV_BY_1 0
38#define POSTDIV_DIV_BY_2 1
39#define POSTDIV_DIV_BY_4 2
40#define POSTDIV_DIV_BY_8 3
41#define POSTDIV_DIV_BY_16 4
42
43struct sclkFcwRange_t {
44 uint8_t vco_setting;
45 uint8_t postdiv;
46 uint16_t fcw_pcc;
47
48 uint16_t fcw_trans_upper;
49 uint16_t fcw_trans_lower;
50};
51typedef struct sclkFcwRange_t sclkFcwRange_t;
52
53struct SMIO_Pattern {
54 uint16_t Voltage;
55 uint8_t Smio;
56 uint8_t padding;
57};
58
59typedef struct SMIO_Pattern SMIO_Pattern;
60
61struct SMIO_Table {
62 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
63};
64
65typedef struct SMIO_Table SMIO_Table;
66
67struct SMU_SclkSetting {
68 uint32_t SclkFrequency;
69 uint16_t Fcw_int;
70 uint16_t Fcw_frac;
71 uint16_t Pcc_fcw_int;
72 uint8_t PllRange;
73 uint8_t SSc_En;
74 uint16_t Sclk_slew_rate;
75 uint16_t Pcc_up_slew_rate;
76 uint16_t Pcc_down_slew_rate;
77 uint16_t Fcw1_int;
78 uint16_t Fcw1_frac;
79 uint16_t Sclk_ss_slew_rate;
80};
81typedef struct SMU_SclkSetting SMU_SclkSetting;
82
83struct SMU74_Discrete_GraphicsLevel {
84 SMU_VoltageLevel MinVoltage;
85 uint8_t pcieDpmLevel;
86 uint8_t DeepSleepDivId;
87 uint16_t ActivityLevel;
88 uint32_t CgSpllFuncCntl3;
89 uint32_t CgSpllFuncCntl4;
90 uint32_t CcPwrDynRm;
91 uint32_t CcPwrDynRm1;
92 uint8_t SclkDid;
93 uint8_t padding;
94 uint8_t EnabledForActivity;
95 uint8_t EnabledForThrottle;
96 uint8_t UpHyst;
97 uint8_t DownHyst;
98 uint8_t VoltageDownHyst;
99 uint8_t PowerThrottle;
100 SMU_SclkSetting SclkSetting;
101};
102
103typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel;
104
105struct SMU74_Discrete_ACPILevel {
106 uint32_t Flags;
107 SMU_VoltageLevel MinVoltage;
108 uint32_t SclkFrequency;
109 uint8_t SclkDid;
110 uint8_t DisplayWatermark;
111 uint8_t DeepSleepDivId;
112 uint8_t padding;
113 uint32_t CcPwrDynRm;
114 uint32_t CcPwrDynRm1;
115
116 SMU_SclkSetting SclkSetting;
117};
118
119typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel;
120
121struct SMU74_Discrete_Ulv {
122 uint32_t CcPwrDynRm;
123 uint32_t CcPwrDynRm1;
124 uint16_t VddcOffset;
125 uint8_t VddcOffsetVid;
126 uint8_t VddcPhase;
127 uint16_t BifSclkDfs;
128 uint16_t Reserved;
129};
130
131typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
132
133struct SMU74_Discrete_MemoryLevel {
134 SMU_VoltageLevel MinVoltage;
135 uint32_t MinMvdd;
136
137 uint32_t MclkFrequency;
138
139 uint8_t StutterEnable;
140 uint8_t EnabledForThrottle;
141 uint8_t EnabledForActivity;
142 uint8_t padding_0;
143
144 uint8_t UpHyst;
145 uint8_t DownHyst;
146 uint8_t VoltageDownHyst;
147 uint8_t padding_1;
148
149 uint16_t ActivityLevel;
150 uint8_t DisplayWatermark;
151 uint8_t Reserved;
152};
153
154typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel;
155
156struct SMU74_Discrete_LinkLevel {
157 uint8_t PcieGenSpeed;
158 uint8_t PcieLaneCount;
159 uint8_t EnabledForActivity;
160 uint8_t SPC;
161 uint32_t DownThreshold;
162 uint32_t UpThreshold;
163 uint16_t BifSclkDfs;
164 uint16_t Reserved;
165};
166
167typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
168
169struct SMU74_Discrete_MCArbDramTimingTableEntry {
170 uint32_t McArbDramTiming;
171 uint32_t McArbDramTiming2;
172 uint8_t McArbBurstTime;
173 uint8_t padding[3];
174};
175
176typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry;
177
178struct SMU74_Discrete_MCArbDramTimingTable {
179 SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
180};
181
182typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable;
183
184struct SMU74_Discrete_UvdLevel {
185 uint32_t VclkFrequency;
186 uint32_t DclkFrequency;
187 SMU_VoltageLevel MinVoltage;
188 uint8_t VclkDivider;
189 uint8_t DclkDivider;
190 uint8_t padding[2];
191};
192
193typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel;
194
195struct SMU74_Discrete_ExtClkLevel {
196 uint32_t Frequency;
197 SMU_VoltageLevel MinVoltage;
198 uint8_t Divider;
199 uint8_t padding[3];
200};
201
202typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel;
203
204struct SMU74_Discrete_StateInfo {
205 uint32_t SclkFrequency;
206 uint32_t MclkFrequency;
207 uint32_t VclkFrequency;
208 uint32_t DclkFrequency;
209 uint32_t SamclkFrequency;
210 uint32_t AclkFrequency;
211 uint32_t EclkFrequency;
212 uint16_t MvddVoltage;
213 uint16_t padding16;
214 uint8_t DisplayWatermark;
215 uint8_t McArbIndex;
216 uint8_t McRegIndex;
217 uint8_t SeqIndex;
218 uint8_t SclkDid;
219 int8_t SclkIndex;
220 int8_t MclkIndex;
221 uint8_t PCIeGen;
222};
223
224typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
225
226struct SMU_QuadraticCoeffs {
227 int32_t m1;
228 uint32_t b;
229
230 int16_t m2;
231 uint8_t m1_shift;
232 uint8_t m2_shift;
233};
234typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
235
236struct SMU74_Discrete_DpmTable {
237
238 SMU74_PIDController GraphicsPIDController;
239 SMU74_PIDController MemoryPIDController;
240 SMU74_PIDController LinkPIDController;
241
242 uint32_t SystemFlags;
243
244 uint32_t VRConfig;
245 uint32_t SmioMask1;
246 uint32_t SmioMask2;
247 SMIO_Table SmioTable1;
248 SMIO_Table SmioTable2;
249
250 uint32_t MvddLevelCount;
251
252
253 uint8_t BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
254 uint8_t BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
255 uint8_t BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
256
257 uint8_t GraphicsDpmLevelCount;
258 uint8_t MemoryDpmLevelCount;
259 uint8_t LinkLevelCount;
260 uint8_t MasterDeepSleepControl;
261
262 uint8_t UvdLevelCount;
263 uint8_t VceLevelCount;
264 uint8_t AcpLevelCount;
265 uint8_t SamuLevelCount;
266
267 uint8_t ThermOutGpio;
268 uint8_t ThermOutPolarity;
269 uint8_t ThermOutMode;
270 uint8_t BootPhases;
271
272 uint8_t VRHotLevel;
273 uint8_t LdoRefSel;
274 uint8_t Reserved1[2];
275 uint16_t FanStartTemperature;
276 uint16_t FanStopTemperature;
277 uint16_t MaxVoltage;
278 uint16_t Reserved2;
279 uint32_t Reserved[1];
280
281 SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
282 SMU74_Discrete_MemoryLevel MemoryACPILevel;
283 SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
284 SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK];
285 SMU74_Discrete_ACPILevel ACPILevel;
286 SMU74_Discrete_UvdLevel UvdLevel[SMU74_MAX_LEVELS_UVD];
287 SMU74_Discrete_ExtClkLevel VceLevel[SMU74_MAX_LEVELS_VCE];
288 SMU74_Discrete_ExtClkLevel AcpLevel[SMU74_MAX_LEVELS_ACP];
289 SMU74_Discrete_ExtClkLevel SamuLevel[SMU74_MAX_LEVELS_SAMU];
290 SMU74_Discrete_Ulv Ulv;
291
292 uint8_t DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
293
294 uint32_t SclkStepSize;
295 uint32_t Smio[SMU74_MAX_ENTRIES_SMIO];
296
297 uint8_t UvdBootLevel;
298 uint8_t VceBootLevel;
299 uint8_t AcpBootLevel;
300 uint8_t SamuBootLevel;
301
302 uint8_t GraphicsBootLevel;
303 uint8_t GraphicsVoltageChangeEnable;
304 uint8_t GraphicsThermThrottleEnable;
305 uint8_t GraphicsInterval;
306
307 uint8_t VoltageInterval;
308 uint8_t ThermalInterval;
309 uint16_t TemperatureLimitHigh;
310
311 uint16_t TemperatureLimitLow;
312 uint8_t MemoryBootLevel;
313 uint8_t MemoryVoltageChangeEnable;
314
315 uint16_t BootMVdd;
316 uint8_t MemoryInterval;
317 uint8_t MemoryThermThrottleEnable;
318
319 uint16_t VoltageResponseTime;
320 uint16_t PhaseResponseTime;
321
322 uint8_t PCIeBootLinkLevel;
323 uint8_t PCIeGenInterval;
324 uint8_t DTEInterval;
325 uint8_t DTEMode;
326
327 uint8_t SVI2Enable;
328 uint8_t VRHotGpio;
329 uint8_t AcDcGpio;
330 uint8_t ThermGpio;
331
332 uint16_t PPM_PkgPwrLimit;
333 uint16_t PPM_TemperatureLimit;
334
335 uint16_t DefaultTdp;
336 uint16_t TargetTdp;
337
338 uint16_t FpsHighThreshold;
339 uint16_t FpsLowThreshold;
340
341 uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
342 uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
343
344 uint16_t TemperatureLimitEdge;
345 uint16_t TemperatureLimitHotspot;
346
347 uint16_t BootVddc;
348 uint16_t BootVddci;
349
350 uint16_t FanGainEdge;
351 uint16_t FanGainHotspot;
352
353 uint32_t LowSclkInterruptThreshold;
354 uint32_t VddGfxReChkWait;
355
356 uint8_t ClockStretcherAmount;
357 uint8_t Sclk_CKS_masterEn0_7;
358 uint8_t Sclk_CKS_masterEn8_15;
359 uint8_t DPMFreezeAndForced;
360
361 uint8_t Sclk_voltageOffset[8];
362
363 SMU_ClockStretcherDataTable ClockStretcherDataTable;
364 SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
365
366 uint32_t CurrSclkPllRange;
367 sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
368 GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
369 SMU_QuadraticCoeffs AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
370};
371
372typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
373
374
375struct SMU74_Discrete_FanTable {
376 uint16_t FdoMode;
377 int16_t TempMin;
378 int16_t TempMed;
379 int16_t TempMax;
380 int16_t Slope1;
381 int16_t Slope2;
382 int16_t FdoMin;
383 int16_t HystUp;
384 int16_t HystDown;
385 int16_t HystSlope;
386 int16_t TempRespLim;
387 int16_t TempCurr;
388 int16_t SlopeCurr;
389 int16_t PwmCurr;
390 uint32_t RefreshPeriod;
391 int16_t FdoMax;
392 uint8_t TempSrc;
393 int8_t Padding;
394};
395
396typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable;
397
398#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
399#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
400
401
402struct SMU7_MclkDpmScoreboard {
403 uint32_t PercentageBusy;
404
405 int32_t PIDError;
406 int32_t PIDIntegral;
407 int32_t PIDOutput;
408
409 uint32_t SigmaDeltaAccum;
410 uint32_t SigmaDeltaOutput;
411 uint32_t SigmaDeltaLevel;
412
413 uint32_t UtilizationSetpoint;
414
415 uint8_t TdpClampMode;
416 uint8_t TdcClampMode;
417 uint8_t ThermClampMode;
418 uint8_t VoltageBusy;
419
420 int8_t CurrLevel;
421 int8_t TargLevel;
422 uint8_t LevelChangeInProgress;
423 uint8_t UpHyst;
424
425 uint8_t DownHyst;
426 uint8_t VoltageDownHyst;
427 uint8_t DpmEnable;
428 uint8_t DpmRunning;
429
430 uint8_t DpmForce;
431 uint8_t DpmForceLevel;
432 uint8_t padding2;
433 uint8_t McArbIndex;
434
435 uint32_t MinimumPerfMclk;
436
437 uint8_t AcpiReq;
438 uint8_t AcpiAck;
439 uint8_t MclkSwitchInProgress;
440 uint8_t MclkSwitchCritical;
441
442 uint8_t IgnoreVBlank;
443 uint8_t TargetMclkIndex;
444 uint16_t VbiFailureCount;
445 uint8_t VbiWaitCounter;
446 uint8_t EnabledLevelsChange;
447
448 uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY];
449 uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY];
450
451 void (*TargetStateCalculator)(uint8_t);
452 void (*SavedTargetStateCalculator)(uint8_t);
453
454 uint16_t AutoDpmInterval;
455 uint16_t AutoDpmRange;
456
457 uint16_t VbiTimeoutCount;
458 uint16_t MclkSwitchingTime;
459
460 uint8_t fastSwitch;
461 uint8_t Save_PIC_VDDGFX_EXIT;
462 uint8_t Save_PIC_VDDGFX_ENTER;
463 uint8_t padding;
464};
465
466typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
467
468struct SMU7_UlvScoreboard {
469 uint8_t EnterUlv;
470 uint8_t ExitUlv;
471 uint8_t UlvActive;
472 uint8_t WaitingForUlv;
473 uint8_t UlvEnable;
474 uint8_t UlvRunning;
475 uint8_t UlvMasterEnable;
476 uint8_t padding;
477 uint32_t UlvAbortedCount;
478 uint32_t UlvTimeStamp;
479};
480
481typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
482
483struct VddgfxSavedRegisters {
484 uint32_t GPU_DBG[3];
485 uint32_t MEC_BaseAddress_Hi;
486 uint32_t MEC_BaseAddress_Lo;
487 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
488 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
489 uint32_t CP_INT_CNTL;
490};
491
492typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
493
494struct SMU7_VddGfxScoreboard {
495 uint8_t VddGfxEnable;
496 uint8_t VddGfxActive;
497 uint8_t VPUResetOccured;
498 uint8_t padding;
499
500 uint32_t VddGfxEnteredCount;
501 uint32_t VddGfxAbortedCount;
502
503 uint32_t VddGfxVid;
504
505 VddgfxSavedRegisters SavedRegisters;
506};
507
508typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
509
510struct SMU7_TdcLimitScoreboard {
511 uint8_t Enable;
512 uint8_t Running;
513 uint16_t Alpha;
514 uint32_t FilteredIddc;
515 uint32_t IddcLimit;
516 uint32_t IddcHyst;
517 SMU7_HystController_Data HystControllerData;
518};
519
520typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
521
522struct SMU7_PkgPwrLimitScoreboard {
523 uint8_t Enable;
524 uint8_t Running;
525 uint16_t Alpha;
526 uint32_t FilteredPkgPwr;
527 uint32_t Limit;
528 uint32_t Hyst;
529 uint32_t LimitFromDriver;
530 SMU7_HystController_Data HystControllerData;
531};
532
533typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
534
535struct SMU7_BapmScoreboard {
536 uint32_t source_powers[SMU74_DTE_SOURCES];
537 uint32_t source_powers_last[SMU74_DTE_SOURCES];
538 int32_t entity_temperatures[SMU74_NUM_GPU_TES];
539 int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES];
540 int32_t Limit;
541 int32_t Hyst;
542 int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2];
543 int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
544 uint16_t ConfigTDPPowerScalar;
545 uint16_t FanSpeedPowerScalar;
546 uint16_t OverDrivePowerScalar;
547 uint16_t OverDriveLimitScalar;
548 uint16_t FinalPowerScalar;
549 uint8_t VariantID;
550 uint8_t spare997;
551
552 SMU7_HystController_Data HystControllerData;
553
554 int32_t temperature_gradient_slope;
555 int32_t temperature_gradient;
556 uint32_t measured_temperature;
557};
558
559
560typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
561
562struct SMU7_AcpiScoreboard {
563 uint32_t SavedInterruptMask[2];
564 uint8_t LastACPIRequest;
565 uint8_t CgBifResp;
566 uint8_t RequestType;
567 uint8_t Padding;
568 SMU74_Discrete_ACPILevel D0Level;
569};
570
571typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
572
573struct SMU74_Discrete_PmFuses {
574 uint8_t BapmVddCVidHiSidd[8];
575 uint8_t BapmVddCVidLoSidd[8];
576 uint8_t VddCVid[8];
577 uint8_t SviLoadLineEn;
578 uint8_t SviLoadLineVddC;
579 uint8_t SviLoadLineTrimVddC;
580 uint8_t SviLoadLineOffsetVddC;
581 uint16_t TDC_VDDC_PkgLimit;
582 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
583 uint8_t TDC_MAWt;
584 uint8_t TdcWaterfallCtl;
585 uint8_t LPMLTemperatureMin;
586 uint8_t LPMLTemperatureMax;
587 uint8_t Reserved;
588
589 uint8_t LPMLTemperatureScaler[16];
590
591 int16_t FuzzyFan_ErrorSetDelta;
592 int16_t FuzzyFan_ErrorRateSetDelta;
593 int16_t FuzzyFan_PwmSetDelta;
594 uint16_t Reserved6;
595
596 uint8_t GnbLPML[16];
597
598 uint8_t GnbLPMLMaxVid;
599 uint8_t GnbLPMLMinVid;
600 uint8_t Reserved1[2];
601
602 uint16_t BapmVddCBaseLeakageHiSidd;
603 uint16_t BapmVddCBaseLeakageLoSidd;
604
605 uint16_t VFT_Temp[3];
606 uint16_t padding;
607
608 SMU_QuadraticCoeffs VFT_ATE[3];
609
610 SMU_QuadraticCoeffs AVFS_GB;
611 SMU_QuadraticCoeffs ATE_ACBTC_GB;
612
613 SMU_QuadraticCoeffs P2V;
614
615 uint32_t PsmCharzFreq;
616
617 uint16_t InversionVoltage;
618 uint16_t PsmCharzTemp;
619
620 uint32_t EnabledAvfsModules;
621};
622
623typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses;
624
625struct SMU7_Discrete_Log_Header_Table {
626 uint32_t version;
627 uint32_t asic_id;
628 uint16_t flags;
629 uint16_t entry_size;
630 uint32_t total_size;
631 uint32_t num_of_entries;
632 uint8_t type;
633 uint8_t mode;
634 uint8_t filler_0[2];
635 uint32_t filler_1[2];
636};
637
638typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
639
640struct SMU7_Discrete_Log_Cntl {
641 uint8_t Enabled;
642 uint8_t Type;
643 uint8_t padding[2];
644 uint32_t BufferSize;
645 uint32_t SamplesLogged;
646 uint32_t SampleSize;
647 uint32_t AddrL;
648 uint32_t AddrH;
649};
650
651typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
652
653#if defined SMU__DGPU_ONLY
654#define CAC_ACC_NW_NUM_OF_SIGNALS 87
655#endif
656
657
658struct SMU7_Discrete_Cac_Collection_Table {
659 uint32_t temperature;
660 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
661};
662
663typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
664
665struct SMU7_Discrete_Cac_Verification_Table {
666 uint32_t VddcTotalPower;
667 uint32_t VddcLeakagePower;
668 uint32_t VddcConstantPower;
669 uint32_t VddcGfxDynamicPower;
670 uint32_t VddcUvdDynamicPower;
671 uint32_t VddcVceDynamicPower;
672 uint32_t VddcAcpDynamicPower;
673 uint32_t VddcPcieDynamicPower;
674 uint32_t VddcDceDynamicPower;
675 uint32_t VddcCurrent;
676 uint32_t VddcVoltage;
677 uint32_t VddciTotalPower;
678 uint32_t VddciLeakagePower;
679 uint32_t VddciConstantPower;
680 uint32_t VddciDynamicPower;
681 uint32_t Vddr1TotalPower;
682 uint32_t Vddr1LeakagePower;
683 uint32_t Vddr1ConstantPower;
684 uint32_t Vddr1DynamicPower;
685 uint32_t spare[4];
686 uint32_t temperature;
687};
688
689typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
690
691struct SMU7_Discrete_Pm_Status_Table {
692 int32_t T_meas_max;
693 int32_t T_meas_acc;
694 int32_t T_calc_max;
695 int32_t T_calc_acc;
696 uint32_t P_scalar_acc;
697 uint32_t P_calc_max;
698 uint32_t P_calc_acc;
699
700 uint32_t I_calc_max;
701 uint32_t I_calc_acc;
702 uint32_t I_calc_acc_vddci;
703 uint32_t V_calc_noload_acc;
704 uint32_t V_calc_load_acc;
705 uint32_t V_calc_noload_acc_vddci;
706 uint32_t P_meas_acc;
707 uint32_t V_meas_noload_acc;
708 uint32_t V_meas_load_acc;
709 uint32_t I_meas_acc;
710 uint32_t P_meas_acc_vddci;
711 uint32_t V_meas_noload_acc_vddci;
712 uint32_t V_meas_load_acc_vddci;
713 uint32_t I_meas_acc_vddci;
714
715 uint16_t Sclk_dpm_residency[8];
716 uint16_t Uvd_dpm_residency[8];
717 uint16_t Vce_dpm_residency[8];
718 uint16_t Mclk_dpm_residency[4];
719
720 uint32_t P_vddci_acc;
721 uint32_t P_vddr1_acc;
722 uint32_t P_nte1_acc;
723 uint32_t PkgPwr_max;
724 uint32_t PkgPwr_acc;
725 uint32_t MclkSwitchingTime_max;
726 uint32_t MclkSwitchingTime_acc;
727 uint32_t FanPwm_acc;
728 uint32_t FanRpm_acc;
729
730 uint32_t AccCnt;
731};
732
733typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
734
735#define SMU7_MAX_GFX_CU_COUNT 16
736
737struct SMU7_GfxCuPgScoreboard {
738 uint8_t Enabled;
739 uint8_t WaterfallUp;
740 uint8_t WaterfallDown;
741 uint8_t WaterfallLimit;
742 uint8_t CurrMaxCu;
743 uint8_t TargMaxCu;
744 uint8_t ClampMode;
745 uint8_t Active;
746 uint8_t MaxSupportedCu;
747 uint8_t MinSupportedCu;
748 uint8_t PendingGfxCuHostInterrupt;
749 uint8_t LastFilteredMaxCuInteger;
750 uint16_t FilteredMaxCu;
751 uint16_t FilteredMaxCuAlpha;
752 uint16_t FilterResetCount;
753 uint16_t FilterResetCountLimit;
754 uint8_t ForceCu;
755 uint8_t ForceCuCount;
756 uint8_t spare[2];
757};
758
759typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
760
761#define SMU7_SCLK_CAC 0x561
762#define SMU7_MCLK_CAC 0xF9
763#define SMU7_VCLK_CAC 0x2DE
764#define SMU7_DCLK_CAC 0x2DE
765#define SMU7_ECLK_CAC 0x25E
766#define SMU7_ACLK_CAC 0x25E
767#define SMU7_SAMCLK_CAC 0x25E
768#define SMU7_DISPCLK_CAC 0x100
769#define SMU7_CAC_CONSTANT 0x2EE3430
770#define SMU7_CAC_CONSTANT_SHIFT 18
771
772#define SMU7_VDDCI_MCLK_CONST 1765
773#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
774#define SMU7_VDDCI_VDDCI_CONST 50958
775#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
776#define SMU7_VDDCI_CONST 11781
777#define SMU7_VDDCI_STROBE_PWR 1331
778
779#define SMU7_VDDR1_CONST 693
780#define SMU7_VDDR1_CAC_WEIGHT 20
781#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
782#define SMU7_VDDR1_STROBE_PWR 512
783
784#define SMU7_AREA_COEFF_UVD 0xA78
785#define SMU7_AREA_COEFF_VCE 0x190A
786#define SMU7_AREA_COEFF_ACP 0x22D1
787#define SMU7_AREA_COEFF_SAMU 0x534
788
789#define SMU7_THERM_OUT_MODE_DISABLE 0x0
790#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
791#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
792
793// DIDT Defines
794#define SQ_Enable_MASK 0x1
795#define SQ_IR_MASK 0x2
796#define SQ_PCC_MASK 0x4
797#define SQ_EDC_MASK 0x8
798
799#define TCP_Enable_MASK 0x100
800#define TCP_IR_MASK 0x200
801#define TCP_PCC_MASK 0x400
802#define TCP_EDC_MASK 0x800
803
804#define TD_Enable_MASK 0x10000
805#define TD_IR_MASK 0x20000
806#define TD_PCC_MASK 0x40000
807#define TD_EDC_MASK 0x80000
808
809#define DB_Enable_MASK 0x1000000
810#define DB_IR_MASK 0x2000000
811#define DB_PCC_MASK 0x4000000
812#define DB_EDC_MASK 0x8000000
813
814#define SQ_Enable_SHIFT 0
815#define SQ_IR_SHIFT 1
816#define SQ_PCC_SHIFT 2
817#define SQ_EDC_SHIFT 3
818
819#define TCP_Enable_SHIFT 8
820#define TCP_IR_SHIFT 9
821#define TCP_PCC_SHIFT 10
822#define TCP_EDC_SHIFT 11
823
824#define TD_Enable_SHIFT 16
825#define TD_IR_SHIFT 17
826#define TD_PCC_SHIFT 18
827#define TD_EDC_SHIFT 19
828
829#define DB_Enable_SHIFT 24
830#define DB_IR_SHIFT 25
831#define DB_PCC_SHIFT 26
832#define DB_EDC_SHIFT 27
833
834#define BTCGB0_Vdroop_Enable_MASK 0x1
835#define BTCGB1_Vdroop_Enable_MASK 0x2
836#define AVFSGB0_Vdroop_Enable_MASK 0x4
837#define AVFSGB1_Vdroop_Enable_MASK 0x8
838
839#define BTCGB0_Vdroop_Enable_SHIFT 0
840#define BTCGB1_Vdroop_Enable_SHIFT 1
841#define AVFSGB0_Vdroop_Enable_SHIFT 2
842#define AVFSGB1_Vdroop_Enable_SHIFT 3
843
844
845#pragma pack(pop)
846
847
848#endif
849