1/*
 2 * Debugging macro include header
 3 *
 4 *  Copyright (C) 2011 Xilinx
 5 *
 6 * This software is licensed under the terms of the GNU General Public
 7 * License version 2, as published by the Free Software Foundation, and
 8 * may be copied, distributed, and modified under those terms.
 9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 */
15#define UART_CR_OFFSET		0x00  /* Control Register [8:0] */
16#define UART_SR_OFFSET		0x2C  /* Channel Status [11:0] */
17#define UART_FIFO_OFFSET	0x30  /* FIFO [15:0] or [7:0] */
18
19#define UART_SR_TXFULL		0x00000010	/* TX FIFO full */
20#define UART_SR_TXEMPTY		0x00000008	/* TX FIFO empty */
21
22#define UART0_PHYS		0xE0000000
23#define UART0_VIRT		0xF0800000
24#define UART1_PHYS		0xE0001000
25#define UART1_VIRT		0xF0801000
26
27#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
28# define LL_UART_PADDR		UART1_PHYS
29# define LL_UART_VADDR		UART1_VIRT
30#else
31# define LL_UART_PADDR		UART0_PHYS
32# define LL_UART_VADDR		UART0_VIRT
33#endif
34
35		.macro	addruart, rp, rv, tmp
36		ldr	\rp, =LL_UART_PADDR	@ physical
37		ldr	\rv, =LL_UART_VADDR	@ virtual
38		.endm
39
40		.macro	senduart,rd,rx
41		strb	\rd, [\rx, #UART_FIFO_OFFSET]	@ TXDATA
42		.endm
43
44		.macro	waituart,rd,rx
451001:		ldr	\rd, [\rx, #UART_SR_OFFSET]
46ARM_BE8(	rev	\rd, \rd )
47		tst	\rd, #UART_SR_TXEMPTY
48		beq	1001b
49		.endm
50
51		.macro	busyuart,rd,rx
521002:		ldr	\rd, [\rx, #UART_SR_OFFSET]	@ get status register
53ARM_BE8(	rev	\rd, \rd )
54		tst	\rd, #UART_SR_TXFULL		@
55		bne	1002b			@ wait if FIFO is full
56		.endm

 1/*
 2 * Debugging macro include header
 3 *
 4 *  Copyright (C) 2011 Xilinx
 5 *
 6 * This software is licensed under the terms of the GNU General Public
 7 * License version 2, as published by the Free Software Foundation, and
 8 * may be copied, distributed, and modified under those terms.
 9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 */
15#define UART_CR_OFFSET		0x00  /* Control Register [8:0] */
16#define UART_SR_OFFSET		0x2C  /* Channel Status [11:0] */
17#define UART_FIFO_OFFSET	0x30  /* FIFO [15:0] or [7:0] */
18
19#define UART_SR_TXFULL		0x00000010	/* TX FIFO full */
20#define UART_SR_TXEMPTY		0x00000008	/* TX FIFO empty */
21
22#define UART0_PHYS		0xE0000000
23#define UART0_VIRT		0xF0800000
24#define UART1_PHYS		0xE0001000
25#define UART1_VIRT		0xF0801000
26
27#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
28# define LL_UART_PADDR		UART1_PHYS
29# define LL_UART_VADDR		UART1_VIRT
30#else
31# define LL_UART_PADDR		UART0_PHYS
32# define LL_UART_VADDR		UART0_VIRT
33#endif
34
35		.macro	addruart, rp, rv, tmp
36		ldr	\rp, =LL_UART_PADDR	@ physical
37		ldr	\rv, =LL_UART_VADDR	@ virtual
38		.endm
39
40		.macro	senduart,rd,rx
41		strb	\rd, [\rx, #UART_FIFO_OFFSET]	@ TXDATA
42		.endm
43
44		.macro	waituart,rd,rx
451001:		ldr	\rd, [\rx, #UART_SR_OFFSET]
46ARM_BE8(	rev	\rd, \rd )
47		tst	\rd, #UART_SR_TXEMPTY
48		beq	1001b
49		.endm
50
51		.macro	busyuart,rd,rx
521002:		ldr	\rd, [\rx, #UART_SR_OFFSET]	@ get status register
53ARM_BE8(	rev	\rd, \rd )
54		tst	\rd, #UART_SR_TXFULL		@
55		bne	1002b			@ wait if FIFO is full
56		.endm