1/*
   2 * Driver for high-speed SCC boards (those with DMA support)
   3 * Copyright (C) 1997-2000 Klaus Kudielka
   4 *
   5 * S5SCC/DMA support by Janko Koleznik S52HI
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22
  23#include <linux/module.h>
  24#include <linux/bitops.h>
  25#include <linux/delay.h>
  26#include <linux/errno.h>
  27#include <linux/if_arp.h>
  28#include <linux/in.h>
  29#include <linux/init.h>
  30#include <linux/interrupt.h>
  31#include <linux/ioport.h>
  32#include <linux/kernel.h>
  33#include <linux/mm.h>
  34#include <linux/netdevice.h>
  35#include <linux/slab.h>
  36#include <linux/rtnetlink.h>
  37#include <linux/sockios.h>
  38#include <linux/workqueue.h>
  39#include <linux/atomic.h>
  40#include <asm/dma.h>
  41#include <asm/io.h>
  42#include <asm/irq.h>
  43#include <linux/uaccess.h>
  44#include <net/ax25.h>
  45#include "z8530.h"
  46
  47
  48/* Number of buffers per channel */
  49
  50#define NUM_TX_BUF      2	/* NUM_TX_BUF >= 1 (min. 2 recommended) */
  51#define NUM_RX_BUF      6	/* NUM_RX_BUF >= 1 (min. 2 recommended) */
  52#define BUF_SIZE        1576	/* BUF_SIZE >= mtu + hard_header_len */
  53
  54
  55/* Cards supported */
  56
  57#define HW_PI           { "Ottawa PI", 0x300, 0x20, 0x10, 8, \
  58                            0, 8, 1843200, 3686400 }
  59#define HW_PI2          { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \
  60			    0, 8, 3686400, 7372800 }
  61#define HW_TWIN         { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \
  62			    0, 4, 6144000, 6144000 }
  63#define HW_S5           { "S5SCC/DMA", 0x200, 0x10, 0x10, 32, \
  64                          0, 8, 4915200, 9830400 }
  65
  66#define HARDWARE        { HW_PI, HW_PI2, HW_TWIN, HW_S5 }
  67
  68#define TMR_0_HZ        25600	/* Frequency of timer 0 */
  69
  70#define TYPE_PI         0
  71#define TYPE_PI2        1
  72#define TYPE_TWIN       2
  73#define TYPE_S5         3
  74#define NUM_TYPES       4
  75
  76#define MAX_NUM_DEVS    32
  77
  78
  79/* SCC chips supported */
  80
  81#define Z8530           0
  82#define Z85C30          1
  83#define Z85230          2
  84
  85#define CHIPNAMES       { "Z8530", "Z85C30", "Z85230" }
  86
  87
  88/* I/O registers */
  89
  90/* 8530 registers relative to card base */
  91#define SCCB_CMD        0x00
  92#define SCCB_DATA       0x01
  93#define SCCA_CMD        0x02
  94#define SCCA_DATA       0x03
  95
  96/* 8253/8254 registers relative to card base */
  97#define TMR_CNT0        0x00
  98#define TMR_CNT1        0x01
  99#define TMR_CNT2        0x02
 100#define TMR_CTRL        0x03
 101
 102/* Additional PI/PI2 registers relative to card base */
 103#define PI_DREQ_MASK    0x04
 104
 105/* Additional PackeTwin registers relative to card base */
 106#define TWIN_INT_REG    0x08
 107#define TWIN_CLR_TMR1   0x09
 108#define TWIN_CLR_TMR2   0x0a
 109#define TWIN_SPARE_1    0x0b
 110#define TWIN_DMA_CFG    0x08
 111#define TWIN_SERIAL_CFG 0x09
 112#define TWIN_DMA_CLR_FF 0x0a
 113#define TWIN_SPARE_2    0x0b
 114
 115
 116/* PackeTwin I/O register values */
 117
 118/* INT_REG */
 119#define TWIN_SCC_MSK       0x01
 120#define TWIN_TMR1_MSK      0x02
 121#define TWIN_TMR2_MSK      0x04
 122#define TWIN_INT_MSK       0x07
 123
 124/* SERIAL_CFG */
 125#define TWIN_DTRA_ON       0x01
 126#define TWIN_DTRB_ON       0x02
 127#define TWIN_EXTCLKA       0x04
 128#define TWIN_EXTCLKB       0x08
 129#define TWIN_LOOPA_ON      0x10
 130#define TWIN_LOOPB_ON      0x20
 131#define TWIN_EI            0x80
 132
 133/* DMA_CFG */
 134#define TWIN_DMA_HDX_T1    0x08
 135#define TWIN_DMA_HDX_R1    0x0a
 136#define TWIN_DMA_HDX_T3    0x14
 137#define TWIN_DMA_HDX_R3    0x16
 138#define TWIN_DMA_FDX_T3R1  0x1b
 139#define TWIN_DMA_FDX_T1R3  0x1d
 140
 141
 142/* Status values */
 143
 144#define IDLE      0
 145#define TX_HEAD   1
 146#define TX_DATA   2
 147#define TX_PAUSE  3
 148#define TX_TAIL   4
 149#define RTS_OFF   5
 150#define WAIT      6
 151#define DCD_ON    7
 152#define RX_ON     8
 153#define DCD_OFF   9
 154
 155
 156/* Ioctls */
 157
 158#define SIOCGSCCPARAM SIOCDEVPRIVATE
 159#define SIOCSSCCPARAM (SIOCDEVPRIVATE+1)
 160
 161
 162/* Data types */
 163
 164struct scc_param {
 165	int pclk_hz;		/* frequency of BRG input (don't change) */
 166	int brg_tc;		/* BRG terminal count; BRG disabled if < 0 */
 167	int nrzi;		/* 0 (nrz), 1 (nrzi) */
 168	int clocks;		/* see dmascc_cfg documentation */
 169	int txdelay;		/* [1/TMR_0_HZ] */
 170	int txtimeout;		/* [1/HZ] */
 171	int txtail;		/* [1/TMR_0_HZ] */
 172	int waittime;		/* [1/TMR_0_HZ] */
 173	int slottime;		/* [1/TMR_0_HZ] */
 174	int persist;		/* 1 ... 256 */
 175	int dma;		/* -1 (disable), 0, 1, 3 */
 176	int txpause;		/* [1/TMR_0_HZ] */
 177	int rtsoff;		/* [1/TMR_0_HZ] */
 178	int dcdon;		/* [1/TMR_0_HZ] */
 179	int dcdoff;		/* [1/TMR_0_HZ] */
 180};
 181
 182struct scc_hardware {
 183	char *name;
 184	int io_region;
 185	int io_delta;
 186	int io_size;
 187	int num_devs;
 188	int scc_offset;
 189	int tmr_offset;
 190	int tmr_hz;
 191	int pclk_hz;
 192};
 193
 194struct scc_priv {
 195	int type;
 196	int chip;
 197	struct net_device *dev;
 198	struct scc_info *info;
 199
 200	int channel;
 201	int card_base, scc_cmd, scc_data;
 202	int tmr_cnt, tmr_ctrl, tmr_mode;
 203	struct scc_param param;
 204	char rx_buf[NUM_RX_BUF][BUF_SIZE];
 205	int rx_len[NUM_RX_BUF];
 206	int rx_ptr;
 207	struct work_struct rx_work;
 208	int rx_head, rx_tail, rx_count;
 209	int rx_over;
 210	char tx_buf[NUM_TX_BUF][BUF_SIZE];
 211	int tx_len[NUM_TX_BUF];
 212	int tx_ptr;
 213	int tx_head, tx_tail, tx_count;
 214	int state;
 215	unsigned long tx_start;
 216	int rr0;
 217	spinlock_t *register_lock;	/* Per scc_info */
 218	spinlock_t ring_lock;
 219};
 220
 221struct scc_info {
 222	int irq_used;
 223	int twin_serial_cfg;
 224	struct net_device *dev[2];
 225	struct scc_priv priv[2];
 226	struct scc_info *next;
 227	spinlock_t register_lock;	/* Per device register lock */
 228};
 229
 230
 231/* Function declarations */
 232static int setup_adapter(int card_base, int type, int n) __init;
 233
 234static void write_scc(struct scc_priv *priv, int reg, int val);
 235static void write_scc_data(struct scc_priv *priv, int val, int fast);
 236static int read_scc(struct scc_priv *priv, int reg);
 237static int read_scc_data(struct scc_priv *priv);
 238
 239static int scc_open(struct net_device *dev);
 240static int scc_close(struct net_device *dev);
 241static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
 242static int scc_send_packet(struct sk_buff *skb, struct net_device *dev);
 243static int scc_set_mac_address(struct net_device *dev, void *sa);
 244
 245static inline void tx_on(struct scc_priv *priv);
 246static inline void rx_on(struct scc_priv *priv);
 247static inline void rx_off(struct scc_priv *priv);
 248static void start_timer(struct scc_priv *priv, int t, int r15);
 249static inline unsigned char random(void);
 250
 251static inline void z8530_isr(struct scc_info *info);
 252static irqreturn_t scc_isr(int irq, void *dev_id);
 253static void rx_isr(struct scc_priv *priv);
 254static void special_condition(struct scc_priv *priv, int rc);
 255static void rx_bh(struct work_struct *);
 256static void tx_isr(struct scc_priv *priv);
 257static void es_isr(struct scc_priv *priv);
 258static void tm_isr(struct scc_priv *priv);
 259
 260
 261/* Initialization variables */
 262
 263static int io[MAX_NUM_DEVS] __initdata = { 0, };
 264
 265/* Beware! hw[] is also used in dmascc_exit(). */
 266static struct scc_hardware hw[NUM_TYPES] = HARDWARE;
 267
 268
 269/* Global variables */
 270
 271static struct scc_info *first;
 272static unsigned long rand;
 273
 274
 275MODULE_AUTHOR("Klaus Kudielka");
 276MODULE_DESCRIPTION("Driver for high-speed SCC boards");
 277module_param_array(io, int, NULL, 0);
 278MODULE_LICENSE("GPL");
 279
 280static void __exit dmascc_exit(void)
 281{
 282	int i;
 283	struct scc_info *info;
 284
 285	while (first) {
 286		info = first;
 287
 288		/* Unregister devices */
 289		for (i = 0; i < 2; i++)
 290			unregister_netdev(info->dev[i]);
 291
 292		/* Reset board */
 293		if (info->priv[0].type == TYPE_TWIN)
 294			outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
 295		write_scc(&info->priv[0], R9, FHWRES);
 296		release_region(info->dev[0]->base_addr,
 297			       hw[info->priv[0].type].io_size);
 298
 299		for (i = 0; i < 2; i++)
 300			free_netdev(info->dev[i]);
 301
 302		/* Free memory */
 303		first = info->next;
 304		kfree(info);
 305	}
 306}
 307
 308static int __init dmascc_init(void)
 309{
 310	int h, i, j, n;
 311	int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS],
 312	    t1[MAX_NUM_DEVS];
 313	unsigned t_val;
 314	unsigned long time, start[MAX_NUM_DEVS], delay[MAX_NUM_DEVS],
 315	    counting[MAX_NUM_DEVS];
 316
 317	/* Initialize random number generator */
 318	rand = jiffies;
 319	/* Cards found = 0 */
 320	n = 0;
 321	/* Warning message */
 322	if (!io[0])
 323		printk(KERN_INFO "dmascc: autoprobing (dangerous)\n");
 324
 325	/* Run autodetection for each card type */
 326	for (h = 0; h < NUM_TYPES; h++) {
 327
 328		if (io[0]) {
 329			/* User-specified I/O address regions */
 330			for (i = 0; i < hw[h].num_devs; i++)
 331				base[i] = 0;
 332			for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) {
 333				j = (io[i] -
 334				     hw[h].io_region) / hw[h].io_delta;
 335				if (j >= 0 && j < hw[h].num_devs &&
 336				    hw[h].io_region +
 337				    j * hw[h].io_delta == io[i]) {
 338					base[j] = io[i];
 339				}
 340			}
 341		} else {
 342			/* Default I/O address regions */
 343			for (i = 0; i < hw[h].num_devs; i++) {
 344				base[i] =
 345				    hw[h].io_region + i * hw[h].io_delta;
 346			}
 347		}
 348
 349		/* Check valid I/O address regions */
 350		for (i = 0; i < hw[h].num_devs; i++)
 351			if (base[i]) {
 352				if (!request_region
 353				    (base[i], hw[h].io_size, "dmascc"))
 354					base[i] = 0;
 355				else {
 356					tcmd[i] =
 357					    base[i] + hw[h].tmr_offset +
 358					    TMR_CTRL;
 359					t0[i] =
 360					    base[i] + hw[h].tmr_offset +
 361					    TMR_CNT0;
 362					t1[i] =
 363					    base[i] + hw[h].tmr_offset +
 364					    TMR_CNT1;
 365				}
 366			}
 367
 368		/* Start timers */
 369		for (i = 0; i < hw[h].num_devs; i++)
 370			if (base[i]) {
 371				/* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */
 372				outb(0x36, tcmd[i]);
 373				outb((hw[h].tmr_hz / TMR_0_HZ) & 0xFF,
 374				     t0[i]);
 375				outb((hw[h].tmr_hz / TMR_0_HZ) >> 8,
 376				     t0[i]);
 377				/* Timer 1: LSB+MSB, Mode 0, HZ/10 */
 378				outb(0x70, tcmd[i]);
 379				outb((TMR_0_HZ / HZ * 10) & 0xFF, t1[i]);
 380				outb((TMR_0_HZ / HZ * 10) >> 8, t1[i]);
 381				start[i] = jiffies;
 382				delay[i] = 0;
 383				counting[i] = 1;
 384				/* Timer 2: LSB+MSB, Mode 0 */
 385				outb(0xb0, tcmd[i]);
 386			}
 387		time = jiffies;
 388		/* Wait until counter registers are loaded */
 389		udelay(2000000 / TMR_0_HZ);
 390
 391		/* Timing loop */
 392		while (jiffies - time < 13) {
 393			for (i = 0; i < hw[h].num_devs; i++)
 394				if (base[i] && counting[i]) {
 395					/* Read back Timer 1: latch; read LSB; read MSB */
 396					outb(0x40, tcmd[i]);
 397					t_val =
 398					    inb(t1[i]) + (inb(t1[i]) << 8);
 399					/* Also check whether counter did wrap */
 400					if (t_val == 0 ||
 401					    t_val > TMR_0_HZ / HZ * 10)
 402						counting[i] = 0;
 403					delay[i] = jiffies - start[i];
 404				}
 405		}
 406
 407		/* Evaluate measurements */
 408		for (i = 0; i < hw[h].num_devs; i++)
 409			if (base[i]) {
 410				if ((delay[i] >= 9 && delay[i] <= 11) &&
 411				    /* Ok, we have found an adapter */
 412				    (setup_adapter(base[i], h, n) == 0))
 413					n++;
 414				else
 415					release_region(base[i],
 416						       hw[h].io_size);
 417			}
 418
 419	}			/* NUM_TYPES */
 420
 421	/* If any adapter was successfully initialized, return ok */
 422	if (n)
 423		return 0;
 424
 425	/* If no adapter found, return error */
 426	printk(KERN_INFO "dmascc: no adapters found\n");
 427	return -EIO;
 428}
 429
 430module_init(dmascc_init);
 431module_exit(dmascc_exit);
 432
 433static void __init dev_setup(struct net_device *dev)
 434{
 435	dev->type = ARPHRD_AX25;
 436	dev->hard_header_len = AX25_MAX_HEADER_LEN;
 437	dev->mtu = 1500;
 438	dev->addr_len = AX25_ADDR_LEN;
 439	dev->tx_queue_len = 64;
 440	memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
 441	memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
 442}
 443
 444static const struct net_device_ops scc_netdev_ops = {
 445	.ndo_open = scc_open,
 446	.ndo_stop = scc_close,
 447	.ndo_start_xmit = scc_send_packet,
 448	.ndo_do_ioctl = scc_ioctl,
 449	.ndo_set_mac_address = scc_set_mac_address,
 450};
 451
 452static int __init setup_adapter(int card_base, int type, int n)
 453{
 454	int i, irq, chip, err;
 455	struct scc_info *info;
 456	struct net_device *dev;
 457	struct scc_priv *priv;
 458	unsigned long time;
 459	unsigned int irqs;
 460	int tmr_base = card_base + hw[type].tmr_offset;
 461	int scc_base = card_base + hw[type].scc_offset;
 462	char *chipnames[] = CHIPNAMES;
 463
 464	/* Initialize what is necessary for write_scc and write_scc_data */
 465	info = kzalloc(sizeof(struct scc_info), GFP_KERNEL | GFP_DMA);
 466	if (!info) {
 467		err = -ENOMEM;
 
 
 468		goto out;
 469	}
 470
 471	info->dev[0] = alloc_netdev(0, "", NET_NAME_UNKNOWN, dev_setup);
 
 472	if (!info->dev[0]) {
 473		printk(KERN_ERR "dmascc: "
 474		       "could not allocate memory for %s at %#3x\n",
 475		       hw[type].name, card_base);
 476		err = -ENOMEM;
 477		goto out1;
 478	}
 479
 480	info->dev[1] = alloc_netdev(0, "", NET_NAME_UNKNOWN, dev_setup);
 481	if (!info->dev[1]) {
 482		printk(KERN_ERR "dmascc: "
 483		       "could not allocate memory for %s at %#3x\n",
 484		       hw[type].name, card_base);
 485		err = -ENOMEM;
 486		goto out2;
 487	}
 488	spin_lock_init(&info->register_lock);
 489
 490	priv = &info->priv[0];
 491	priv->type = type;
 492	priv->card_base = card_base;
 493	priv->scc_cmd = scc_base + SCCA_CMD;
 494	priv->scc_data = scc_base + SCCA_DATA;
 495	priv->register_lock = &info->register_lock;
 496
 497	/* Reset SCC */
 498	write_scc(priv, R9, FHWRES | MIE | NV);
 499
 500	/* Determine type of chip by enabling SDLC/HDLC enhancements */
 501	write_scc(priv, R15, SHDLCE);
 502	if (!read_scc(priv, R15)) {
 503		/* WR7' not present. This is an ordinary Z8530 SCC. */
 504		chip = Z8530;
 505	} else {
 506		/* Put one character in TX FIFO */
 507		write_scc_data(priv, 0, 0);
 508		if (read_scc(priv, R0) & Tx_BUF_EMP) {
 509			/* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */
 510			chip = Z85230;
 511		} else {
 512			/* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */
 513			chip = Z85C30;
 514		}
 515	}
 516	write_scc(priv, R15, 0);
 517
 518	/* Start IRQ auto-detection */
 519	irqs = probe_irq_on();
 520
 521	/* Enable interrupts */
 522	if (type == TYPE_TWIN) {
 523		outb(0, card_base + TWIN_DMA_CFG);
 524		inb(card_base + TWIN_CLR_TMR1);
 525		inb(card_base + TWIN_CLR_TMR2);
 526		info->twin_serial_cfg = TWIN_EI;
 527		outb(info->twin_serial_cfg, card_base + TWIN_SERIAL_CFG);
 528	} else {
 529		write_scc(priv, R15, CTSIE);
 530		write_scc(priv, R0, RES_EXT_INT);
 531		write_scc(priv, R1, EXT_INT_ENAB);
 532	}
 533
 534	/* Start timer */
 535	outb(1, tmr_base + TMR_CNT1);
 536	outb(0, tmr_base + TMR_CNT1);
 537
 538	/* Wait and detect IRQ */
 539	time = jiffies;
 540	while (jiffies - time < 2 + HZ / TMR_0_HZ);
 541	irq = probe_irq_off(irqs);
 542
 543	/* Clear pending interrupt, disable interrupts */
 544	if (type == TYPE_TWIN) {
 545		inb(card_base + TWIN_CLR_TMR1);
 546	} else {
 547		write_scc(priv, R1, 0);
 548		write_scc(priv, R15, 0);
 549		write_scc(priv, R0, RES_EXT_INT);
 550	}
 551
 552	if (irq <= 0) {
 553		printk(KERN_ERR
 554		       "dmascc: could not find irq of %s at %#3x (irq=%d)\n",
 555		       hw[type].name, card_base, irq);
 556		err = -ENODEV;
 557		goto out3;
 558	}
 559
 560	/* Set up data structures */
 561	for (i = 0; i < 2; i++) {
 562		dev = info->dev[i];
 563		priv = &info->priv[i];
 564		priv->type = type;
 565		priv->chip = chip;
 566		priv->dev = dev;
 567		priv->info = info;
 568		priv->channel = i;
 569		spin_lock_init(&priv->ring_lock);
 570		priv->register_lock = &info->register_lock;
 571		priv->card_base = card_base;
 572		priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD);
 573		priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA);
 574		priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
 575		priv->tmr_ctrl = tmr_base + TMR_CTRL;
 576		priv->tmr_mode = i ? 0xb0 : 0x70;
 577		priv->param.pclk_hz = hw[type].pclk_hz;
 578		priv->param.brg_tc = -1;
 579		priv->param.clocks = TCTRxCP | RCRTxCP;
 580		priv->param.persist = 256;
 581		priv->param.dma = -1;
 582		INIT_WORK(&priv->rx_work, rx_bh);
 583		dev->ml_priv = priv;
 584		sprintf(dev->name, "dmascc%i", 2 * n + i);
 585		dev->base_addr = card_base;
 586		dev->irq = irq;
 587		dev->netdev_ops = &scc_netdev_ops;
 588		dev->header_ops = &ax25_header_ops;
 589	}
 590	if (register_netdev(info->dev[0])) {
 591		printk(KERN_ERR "dmascc: could not register %s\n",
 592		       info->dev[0]->name);
 593		err = -ENODEV;
 594		goto out3;
 595	}
 596	if (register_netdev(info->dev[1])) {
 597		printk(KERN_ERR "dmascc: could not register %s\n",
 598		       info->dev[1]->name);
 599		err = -ENODEV;
 600		goto out4;
 601	}
 602
 603
 604	info->next = first;
 605	first = info;
 606	printk(KERN_INFO "dmascc: found %s (%s) at %#3x, irq %d\n",
 607	       hw[type].name, chipnames[chip], card_base, irq);
 608	return 0;
 609
 610      out4:
 611	unregister_netdev(info->dev[0]);
 612      out3:
 613	if (info->priv[0].type == TYPE_TWIN)
 614		outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
 615	write_scc(&info->priv[0], R9, FHWRES);
 616	free_netdev(info->dev[1]);
 617      out2:
 618	free_netdev(info->dev[0]);
 619      out1:
 620	kfree(info);
 621      out:
 622	return err;
 623}
 624
 625
 626/* Driver functions */
 627
 628static void write_scc(struct scc_priv *priv, int reg, int val)
 629{
 630	unsigned long flags;
 631	switch (priv->type) {
 632	case TYPE_S5:
 633		if (reg)
 634			outb(reg, priv->scc_cmd);
 635		outb(val, priv->scc_cmd);
 636		return;
 637	case TYPE_TWIN:
 638		if (reg)
 639			outb_p(reg, priv->scc_cmd);
 640		outb_p(val, priv->scc_cmd);
 641		return;
 642	default:
 643		spin_lock_irqsave(priv->register_lock, flags);
 644		outb_p(0, priv->card_base + PI_DREQ_MASK);
 645		if (reg)
 646			outb_p(reg, priv->scc_cmd);
 647		outb_p(val, priv->scc_cmd);
 648		outb(1, priv->card_base + PI_DREQ_MASK);
 649		spin_unlock_irqrestore(priv->register_lock, flags);
 650		return;
 651	}
 652}
 653
 654
 655static void write_scc_data(struct scc_priv *priv, int val, int fast)
 656{
 657	unsigned long flags;
 658	switch (priv->type) {
 659	case TYPE_S5:
 660		outb(val, priv->scc_data);
 661		return;
 662	case TYPE_TWIN:
 663		outb_p(val, priv->scc_data);
 664		return;
 665	default:
 666		if (fast)
 667			outb_p(val, priv->scc_data);
 668		else {
 669			spin_lock_irqsave(priv->register_lock, flags);
 670			outb_p(0, priv->card_base + PI_DREQ_MASK);
 671			outb_p(val, priv->scc_data);
 672			outb(1, priv->card_base + PI_DREQ_MASK);
 673			spin_unlock_irqrestore(priv->register_lock, flags);
 674		}
 675		return;
 676	}
 677}
 678
 679
 680static int read_scc(struct scc_priv *priv, int reg)
 681{
 682	int rc;
 683	unsigned long flags;
 684	switch (priv->type) {
 685	case TYPE_S5:
 686		if (reg)
 687			outb(reg, priv->scc_cmd);
 688		return inb(priv->scc_cmd);
 689	case TYPE_TWIN:
 690		if (reg)
 691			outb_p(reg, priv->scc_cmd);
 692		return inb_p(priv->scc_cmd);
 693	default:
 694		spin_lock_irqsave(priv->register_lock, flags);
 695		outb_p(0, priv->card_base + PI_DREQ_MASK);
 696		if (reg)
 697			outb_p(reg, priv->scc_cmd);
 698		rc = inb_p(priv->scc_cmd);
 699		outb(1, priv->card_base + PI_DREQ_MASK);
 700		spin_unlock_irqrestore(priv->register_lock, flags);
 701		return rc;
 702	}
 703}
 704
 705
 706static int read_scc_data(struct scc_priv *priv)
 707{
 708	int rc;
 709	unsigned long flags;
 710	switch (priv->type) {
 711	case TYPE_S5:
 712		return inb(priv->scc_data);
 713	case TYPE_TWIN:
 714		return inb_p(priv->scc_data);
 715	default:
 716		spin_lock_irqsave(priv->register_lock, flags);
 717		outb_p(0, priv->card_base + PI_DREQ_MASK);
 718		rc = inb_p(priv->scc_data);
 719		outb(1, priv->card_base + PI_DREQ_MASK);
 720		spin_unlock_irqrestore(priv->register_lock, flags);
 721		return rc;
 722	}
 723}
 724
 725
 726static int scc_open(struct net_device *dev)
 727{
 728	struct scc_priv *priv = dev->ml_priv;
 729	struct scc_info *info = priv->info;
 730	int card_base = priv->card_base;
 731
 732	/* Request IRQ if not already used by other channel */
 733	if (!info->irq_used) {
 734		if (request_irq(dev->irq, scc_isr, 0, "dmascc", info)) {
 735			return -EAGAIN;
 736		}
 737	}
 738	info->irq_used++;
 739
 740	/* Request DMA if required */
 741	if (priv->param.dma >= 0) {
 742		if (request_dma(priv->param.dma, "dmascc")) {
 743			if (--info->irq_used == 0)
 744				free_irq(dev->irq, info);
 745			return -EAGAIN;
 746		} else {
 747			unsigned long flags = claim_dma_lock();
 748			clear_dma_ff(priv->param.dma);
 749			release_dma_lock(flags);
 750		}
 751	}
 752
 753	/* Initialize local variables */
 754	priv->rx_ptr = 0;
 755	priv->rx_over = 0;
 756	priv->rx_head = priv->rx_tail = priv->rx_count = 0;
 757	priv->state = IDLE;
 758	priv->tx_head = priv->tx_tail = priv->tx_count = 0;
 759	priv->tx_ptr = 0;
 760
 761	/* Reset channel */
 762	write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
 763	/* X1 clock, SDLC mode */
 764	write_scc(priv, R4, SDLC | X1CLK);
 765	/* DMA */
 766	write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
 767	/* 8 bit RX char, RX disable */
 768	write_scc(priv, R3, Rx8);
 769	/* 8 bit TX char, TX disable */
 770	write_scc(priv, R5, Tx8);
 771	/* SDLC address field */
 772	write_scc(priv, R6, 0);
 773	/* SDLC flag */
 774	write_scc(priv, R7, FLAG);
 775	switch (priv->chip) {
 776	case Z85C30:
 777		/* Select WR7' */
 778		write_scc(priv, R15, SHDLCE);
 779		/* Auto EOM reset */
 780		write_scc(priv, R7, AUTOEOM);
 781		write_scc(priv, R15, 0);
 782		break;
 783	case Z85230:
 784		/* Select WR7' */
 785		write_scc(priv, R15, SHDLCE);
 786		/* The following bits are set (see 2.5.2.1):
 787		   - Automatic EOM reset
 788		   - Interrupt request if RX FIFO is half full
 789		   This bit should be ignored in DMA mode (according to the
 790		   documentation), but actually isn't. The receiver doesn't work if
 791		   it is set. Thus, we have to clear it in DMA mode.
 792		   - Interrupt/DMA request if TX FIFO is completely empty
 793		   a) If set, the ESCC behaves as if it had no TX FIFO (Z85C30
 794		   compatibility).
 795		   b) If cleared, DMA requests may follow each other very quickly,
 796		   filling up the TX FIFO.
 797		   Advantage: TX works even in case of high bus latency.
 798		   Disadvantage: Edge-triggered DMA request circuitry may miss
 799		   a request. No more data is delivered, resulting
 800		   in a TX FIFO underrun.
 801		   Both PI2 and S5SCC/DMA seem to work fine with TXFIFOE cleared.
 802		   The PackeTwin doesn't. I don't know about the PI, but let's
 803		   assume it behaves like the PI2.
 804		 */
 805		if (priv->param.dma >= 0) {
 806			if (priv->type == TYPE_TWIN)
 807				write_scc(priv, R7, AUTOEOM | TXFIFOE);
 808			else
 809				write_scc(priv, R7, AUTOEOM);
 810		} else {
 811			write_scc(priv, R7, AUTOEOM | RXFIFOH);
 812		}
 813		write_scc(priv, R15, 0);
 814		break;
 815	}
 816	/* Preset CRC, NRZ(I) encoding */
 817	write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
 818
 819	/* Configure baud rate generator */
 820	if (priv->param.brg_tc >= 0) {
 821		/* Program BR generator */
 822		write_scc(priv, R12, priv->param.brg_tc & 0xFF);
 823		write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF);
 824		/* BRG source = SYS CLK; enable BRG; DTR REQ function (required by
 825		   PackeTwin, not connected on the PI2); set DPLL source to BRG */
 826		write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
 827		/* Enable DPLL */
 828		write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
 829	} else {
 830		/* Disable BR generator */
 831		write_scc(priv, R14, DTRREQ | BRSRC);
 832	}
 833
 834	/* Configure clocks */
 835	if (priv->type == TYPE_TWIN) {
 836		/* Disable external TX clock receiver */
 837		outb((info->twin_serial_cfg &=
 838		      ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
 839		     card_base + TWIN_SERIAL_CFG);
 840	}
 841	write_scc(priv, R11, priv->param.clocks);
 842	if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
 843		/* Enable external TX clock receiver */
 844		outb((info->twin_serial_cfg |=
 845		      (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
 846		     card_base + TWIN_SERIAL_CFG);
 847	}
 848
 849	/* Configure PackeTwin */
 850	if (priv->type == TYPE_TWIN) {
 851		/* Assert DTR, enable interrupts */
 852		outb((info->twin_serial_cfg |= TWIN_EI |
 853		      (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
 854		     card_base + TWIN_SERIAL_CFG);
 855	}
 856
 857	/* Read current status */
 858	priv->rr0 = read_scc(priv, R0);
 859	/* Enable DCD interrupt */
 860	write_scc(priv, R15, DCDIE);
 861
 862	netif_start_queue(dev);
 863
 864	return 0;
 865}
 866
 867
 868static int scc_close(struct net_device *dev)
 869{
 870	struct scc_priv *priv = dev->ml_priv;
 871	struct scc_info *info = priv->info;
 872	int card_base = priv->card_base;
 873
 874	netif_stop_queue(dev);
 875
 876	if (priv->type == TYPE_TWIN) {
 877		/* Drop DTR */
 878		outb((info->twin_serial_cfg &=
 879		      (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
 880		     card_base + TWIN_SERIAL_CFG);
 881	}
 882
 883	/* Reset channel, free DMA and IRQ */
 884	write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
 885	if (priv->param.dma >= 0) {
 886		if (priv->type == TYPE_TWIN)
 887			outb(0, card_base + TWIN_DMA_CFG);
 888		free_dma(priv->param.dma);
 889	}
 890	if (--info->irq_used == 0)
 891		free_irq(dev->irq, info);
 892
 893	return 0;
 894}
 895
 896
 897static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 898{
 899	struct scc_priv *priv = dev->ml_priv;
 900
 901	switch (cmd) {
 902	case SIOCGSCCPARAM:
 903		if (copy_to_user
 904		    (ifr->ifr_data, &priv->param,
 905		     sizeof(struct scc_param)))
 906			return -EFAULT;
 907		return 0;
 908	case SIOCSSCCPARAM:
 909		if (!capable(CAP_NET_ADMIN))
 910			return -EPERM;
 911		if (netif_running(dev))
 912			return -EAGAIN;
 913		if (copy_from_user
 914		    (&priv->param, ifr->ifr_data,
 915		     sizeof(struct scc_param)))
 916			return -EFAULT;
 917		return 0;
 918	default:
 919		return -EINVAL;
 920	}
 921}
 922
 923
 924static int scc_send_packet(struct sk_buff *skb, struct net_device *dev)
 925{
 926	struct scc_priv *priv = dev->ml_priv;
 927	unsigned long flags;
 928	int i;
 929
 930	if (skb->protocol == htons(ETH_P_IP))
 931		return ax25_ip_xmit(skb);
 932
 933	/* Temporarily stop the scheduler feeding us packets */
 934	netif_stop_queue(dev);
 935
 936	/* Transfer data to DMA buffer */
 937	i = priv->tx_head;
 938	skb_copy_from_linear_data_offset(skb, 1, priv->tx_buf[i], skb->len - 1);
 939	priv->tx_len[i] = skb->len - 1;
 940
 941	/* Clear interrupts while we touch our circular buffers */
 942
 943	spin_lock_irqsave(&priv->ring_lock, flags);
 944	/* Move the ring buffer's head */
 945	priv->tx_head = (i + 1) % NUM_TX_BUF;
 946	priv->tx_count++;
 947
 948	/* If we just filled up the last buffer, leave queue stopped.
 949	   The higher layers must wait until we have a DMA buffer
 950	   to accept the data. */
 951	if (priv->tx_count < NUM_TX_BUF)
 952		netif_wake_queue(dev);
 953
 954	/* Set new TX state */
 955	if (priv->state == IDLE) {
 956		/* Assert RTS, start timer */
 957		priv->state = TX_HEAD;
 958		priv->tx_start = jiffies;
 959		write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
 960		write_scc(priv, R15, 0);
 961		start_timer(priv, priv->param.txdelay, 0);
 962	}
 963
 964	/* Turn interrupts back on and free buffer */
 965	spin_unlock_irqrestore(&priv->ring_lock, flags);
 966	dev_kfree_skb(skb);
 967
 968	return NETDEV_TX_OK;
 969}
 970
 971
 972static int scc_set_mac_address(struct net_device *dev, void *sa)
 973{
 974	memcpy(dev->dev_addr, ((struct sockaddr *) sa)->sa_data,
 975	       dev->addr_len);
 976	return 0;
 977}
 978
 979
 980static inline void tx_on(struct scc_priv *priv)
 981{
 982	int i, n;
 983	unsigned long flags;
 984
 985	if (priv->param.dma >= 0) {
 986		n = (priv->chip == Z85230) ? 3 : 1;
 987		/* Program DMA controller */
 988		flags = claim_dma_lock();
 989		set_dma_mode(priv->param.dma, DMA_MODE_WRITE);
 990		set_dma_addr(priv->param.dma,
 991			     (int) priv->tx_buf[priv->tx_tail] + n);
 992		set_dma_count(priv->param.dma,
 993			      priv->tx_len[priv->tx_tail] - n);
 994		release_dma_lock(flags);
 995		/* Enable TX underrun interrupt */
 996		write_scc(priv, R15, TxUIE);
 997		/* Configure DREQ */
 998		if (priv->type == TYPE_TWIN)
 999			outb((priv->param.dma ==
1000			      1) ? TWIN_DMA_HDX_T1 : TWIN_DMA_HDX_T3,
1001			     priv->card_base + TWIN_DMA_CFG);
1002		else
1003			write_scc(priv, R1,
1004				  EXT_INT_ENAB | WT_FN_RDYFN |
1005				  WT_RDY_ENAB);
1006		/* Write first byte(s) */
1007		spin_lock_irqsave(priv->register_lock, flags);
1008		for (i = 0; i < n; i++)
1009			write_scc_data(priv,
1010				       priv->tx_buf[priv->tx_tail][i], 1);
1011		enable_dma(priv->param.dma);
1012		spin_unlock_irqrestore(priv->register_lock, flags);
1013	} else {
1014		write_scc(priv, R15, TxUIE);
1015		write_scc(priv, R1,
1016			  EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB);
1017		tx_isr(priv);
1018	}
1019	/* Reset EOM latch if we do not have the AUTOEOM feature */
1020	if (priv->chip == Z8530)
1021		write_scc(priv, R0, RES_EOM_L);
1022}
1023
1024
1025static inline void rx_on(struct scc_priv *priv)
1026{
1027	unsigned long flags;
1028
1029	/* Clear RX FIFO */
1030	while (read_scc(priv, R0) & Rx_CH_AV)
1031		read_scc_data(priv);
1032	priv->rx_over = 0;
1033	if (priv->param.dma >= 0) {
1034		/* Program DMA controller */
1035		flags = claim_dma_lock();
1036		set_dma_mode(priv->param.dma, DMA_MODE_READ);
1037		set_dma_addr(priv->param.dma,
1038			     (int) priv->rx_buf[priv->rx_head]);
1039		set_dma_count(priv->param.dma, BUF_SIZE);
1040		release_dma_lock(flags);
1041		enable_dma(priv->param.dma);
1042		/* Configure PackeTwin DMA */
1043		if (priv->type == TYPE_TWIN) {
1044			outb((priv->param.dma ==
1045			      1) ? TWIN_DMA_HDX_R1 : TWIN_DMA_HDX_R3,
1046			     priv->card_base + TWIN_DMA_CFG);
1047		}
1048		/* Sp. cond. intr. only, ext int enable, RX DMA enable */
1049		write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |
1050			  WT_RDY_RT | WT_FN_RDYFN | WT_RDY_ENAB);
1051	} else {
1052		/* Reset current frame */
1053		priv->rx_ptr = 0;
1054		/* Intr. on all Rx characters and Sp. cond., ext int enable */
1055		write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
1056			  WT_FN_RDYFN);
1057	}
1058	write_scc(priv, R0, ERR_RES);
1059	write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1060}
1061
1062
1063static inline void rx_off(struct scc_priv *priv)
1064{
1065	/* Disable receiver */
1066	write_scc(priv, R3, Rx8);
1067	/* Disable DREQ / RX interrupt */
1068	if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1069		outb(0, priv->card_base + TWIN_DMA_CFG);
1070	else
1071		write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1072	/* Disable DMA */
1073	if (priv->param.dma >= 0)
1074		disable_dma(priv->param.dma);
1075}
1076
1077
1078static void start_timer(struct scc_priv *priv, int t, int r15)
1079{
1080	outb(priv->tmr_mode, priv->tmr_ctrl);
1081	if (t == 0) {
1082		tm_isr(priv);
1083	} else if (t > 0) {
1084		outb(t & 0xFF, priv->tmr_cnt);
1085		outb((t >> 8) & 0xFF, priv->tmr_cnt);
1086		if (priv->type != TYPE_TWIN) {
1087			write_scc(priv, R15, r15 | CTSIE);
1088			priv->rr0 |= CTS;
1089		}
1090	}
1091}
1092
1093
1094static inline unsigned char random(void)
1095{
1096	/* See "Numerical Recipes in C", second edition, p. 284 */
1097	rand = rand * 1664525L + 1013904223L;
1098	return (unsigned char) (rand >> 24);
1099}
1100
1101static inline void z8530_isr(struct scc_info *info)
1102{
1103	int is, i = 100;
1104
1105	while ((is = read_scc(&info->priv[0], R3)) && i--) {
1106		if (is & CHARxIP) {
1107			rx_isr(&info->priv[0]);
1108		} else if (is & CHATxIP) {
1109			tx_isr(&info->priv[0]);
1110		} else if (is & CHAEXT) {
1111			es_isr(&info->priv[0]);
1112		} else if (is & CHBRxIP) {
1113			rx_isr(&info->priv[1]);
1114		} else if (is & CHBTxIP) {
1115			tx_isr(&info->priv[1]);
1116		} else {
1117			es_isr(&info->priv[1]);
1118		}
1119		write_scc(&info->priv[0], R0, RES_H_IUS);
1120		i++;
1121	}
1122	if (i < 0) {
1123		printk(KERN_ERR "dmascc: stuck in ISR with RR3=0x%02x.\n",
1124		       is);
1125	}
1126	/* Ok, no interrupts pending from this 8530. The INT line should
1127	   be inactive now. */
1128}
1129
1130
1131static irqreturn_t scc_isr(int irq, void *dev_id)
1132{
1133	struct scc_info *info = dev_id;
1134
1135	spin_lock(info->priv[0].register_lock);
1136	/* At this point interrupts are enabled, and the interrupt under service
1137	   is already acknowledged, but masked off.
1138
1139	   Interrupt processing: We loop until we know that the IRQ line is
1140	   low. If another positive edge occurs afterwards during the ISR,
1141	   another interrupt will be triggered by the interrupt controller
1142	   as soon as the IRQ level is enabled again (see asm/irq.h).
1143
1144	   Bottom-half handlers will be processed after scc_isr(). This is
1145	   important, since we only have small ringbuffers and want new data
1146	   to be fetched/delivered immediately. */
1147
1148	if (info->priv[0].type == TYPE_TWIN) {
1149		int is, card_base = info->priv[0].card_base;
1150		while ((is = ~inb(card_base + TWIN_INT_REG)) &
1151		       TWIN_INT_MSK) {
1152			if (is & TWIN_SCC_MSK) {
1153				z8530_isr(info);
1154			} else if (is & TWIN_TMR1_MSK) {
1155				inb(card_base + TWIN_CLR_TMR1);
1156				tm_isr(&info->priv[0]);
1157			} else {
1158				inb(card_base + TWIN_CLR_TMR2);
1159				tm_isr(&info->priv[1]);
1160			}
1161		}
1162	} else
1163		z8530_isr(info);
1164	spin_unlock(info->priv[0].register_lock);
1165	return IRQ_HANDLED;
1166}
1167
1168
1169static void rx_isr(struct scc_priv *priv)
1170{
1171	if (priv->param.dma >= 0) {
1172		/* Check special condition and perform error reset. See 2.4.7.5. */
1173		special_condition(priv, read_scc(priv, R1));
1174		write_scc(priv, R0, ERR_RES);
1175	} else {
1176		/* Check special condition for each character. Error reset not necessary.
1177		   Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */
1178		int rc;
1179		while (read_scc(priv, R0) & Rx_CH_AV) {
1180			rc = read_scc(priv, R1);
1181			if (priv->rx_ptr < BUF_SIZE)
1182				priv->rx_buf[priv->rx_head][priv->
1183							    rx_ptr++] =
1184				    read_scc_data(priv);
1185			else {
1186				priv->rx_over = 2;
1187				read_scc_data(priv);
1188			}
1189			special_condition(priv, rc);
1190		}
1191	}
1192}
1193
1194
1195static void special_condition(struct scc_priv *priv, int rc)
1196{
1197	int cb;
1198	unsigned long flags;
1199
1200	/* See Figure 2-15. Only overrun and EOF need to be checked. */
1201
1202	if (rc & Rx_OVR) {
1203		/* Receiver overrun */
1204		priv->rx_over = 1;
1205		if (priv->param.dma < 0)
1206			write_scc(priv, R0, ERR_RES);
1207	} else if (rc & END_FR) {
1208		/* End of frame. Get byte count */
1209		if (priv->param.dma >= 0) {
1210			flags = claim_dma_lock();
1211			cb = BUF_SIZE - get_dma_residue(priv->param.dma) -
1212			    2;
1213			release_dma_lock(flags);
1214		} else {
1215			cb = priv->rx_ptr - 2;
1216		}
1217		if (priv->rx_over) {
1218			/* We had an overrun */
1219			priv->dev->stats.rx_errors++;
1220			if (priv->rx_over == 2)
1221				priv->dev->stats.rx_length_errors++;
1222			else
1223				priv->dev->stats.rx_fifo_errors++;
1224			priv->rx_over = 0;
1225		} else if (rc & CRC_ERR) {
1226			/* Count invalid CRC only if packet length >= minimum */
1227			if (cb >= 15) {
1228				priv->dev->stats.rx_errors++;
1229				priv->dev->stats.rx_crc_errors++;
1230			}
1231		} else {
1232			if (cb >= 15) {
1233				if (priv->rx_count < NUM_RX_BUF - 1) {
1234					/* Put good frame in FIFO */
1235					priv->rx_len[priv->rx_head] = cb;
1236					priv->rx_head =
1237					    (priv->rx_head +
1238					     1) % NUM_RX_BUF;
1239					priv->rx_count++;
1240					schedule_work(&priv->rx_work);
1241				} else {
1242					priv->dev->stats.rx_errors++;
1243					priv->dev->stats.rx_over_errors++;
1244				}
1245			}
1246		}
1247		/* Get ready for new frame */
1248		if (priv->param.dma >= 0) {
1249			flags = claim_dma_lock();
1250			set_dma_addr(priv->param.dma,
1251				     (int) priv->rx_buf[priv->rx_head]);
1252			set_dma_count(priv->param.dma, BUF_SIZE);
1253			release_dma_lock(flags);
1254		} else {
1255			priv->rx_ptr = 0;
1256		}
1257	}
1258}
1259
1260
1261static void rx_bh(struct work_struct *ugli_api)
1262{
1263	struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work);
1264	int i = priv->rx_tail;
1265	int cb;
1266	unsigned long flags;
1267	struct sk_buff *skb;
1268	unsigned char *data;
1269
1270	spin_lock_irqsave(&priv->ring_lock, flags);
1271	while (priv->rx_count) {
1272		spin_unlock_irqrestore(&priv->ring_lock, flags);
1273		cb = priv->rx_len[i];
1274		/* Allocate buffer */
1275		skb = dev_alloc_skb(cb + 1);
1276		if (skb == NULL) {
1277			/* Drop packet */
1278			priv->dev->stats.rx_dropped++;
1279		} else {
1280			/* Fill buffer */
1281			data = skb_put(skb, cb + 1);
1282			data[0] = 0;
1283			memcpy(&data[1], priv->rx_buf[i], cb);
1284			skb->protocol = ax25_type_trans(skb, priv->dev);
1285			netif_rx(skb);
1286			priv->dev->stats.rx_packets++;
1287			priv->dev->stats.rx_bytes += cb;
1288		}
1289		spin_lock_irqsave(&priv->ring_lock, flags);
1290		/* Move tail */
1291		priv->rx_tail = i = (i + 1) % NUM_RX_BUF;
1292		priv->rx_count--;
1293	}
1294	spin_unlock_irqrestore(&priv->ring_lock, flags);
1295}
1296
1297
1298static void tx_isr(struct scc_priv *priv)
1299{
1300	int i = priv->tx_tail, p = priv->tx_ptr;
1301
1302	/* Suspend TX interrupts if we don't want to send anything.
1303	   See Figure 2-22. */
1304	if (p == priv->tx_len[i]) {
1305		write_scc(priv, R0, RES_Tx_P);
1306		return;
1307	}
1308
1309	/* Write characters */
1310	while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) {
1311		write_scc_data(priv, priv->tx_buf[i][p++], 0);
1312	}
1313
1314	/* Reset EOM latch of Z8530 */
1315	if (!priv->tx_ptr && p && priv->chip == Z8530)
1316		write_scc(priv, R0, RES_EOM_L);
1317
1318	priv->tx_ptr = p;
1319}
1320
1321
1322static void es_isr(struct scc_priv *priv)
1323{
1324	int i, rr0, drr0, res;
1325	unsigned long flags;
1326
1327	/* Read status, reset interrupt bit (open latches) */
1328	rr0 = read_scc(priv, R0);
1329	write_scc(priv, R0, RES_EXT_INT);
1330	drr0 = priv->rr0 ^ rr0;
1331	priv->rr0 = rr0;
1332
1333	/* Transmit underrun (2.4.9.6). We can't check the TxEOM flag, since
1334	   it might have already been cleared again by AUTOEOM. */
1335	if (priv->state == TX_DATA) {
1336		/* Get remaining bytes */
1337		i = priv->tx_tail;
1338		if (priv->param.dma >= 0) {
1339			disable_dma(priv->param.dma);
1340			flags = claim_dma_lock();
1341			res = get_dma_residue(priv->param.dma);
1342			release_dma_lock(flags);
1343		} else {
1344			res = priv->tx_len[i] - priv->tx_ptr;
1345			priv->tx_ptr = 0;
1346		}
1347		/* Disable DREQ / TX interrupt */
1348		if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1349			outb(0, priv->card_base + TWIN_DMA_CFG);
1350		else
1351			write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1352		if (res) {
1353			/* Update packet statistics */
1354			priv->dev->stats.tx_errors++;
1355			priv->dev->stats.tx_fifo_errors++;
1356			/* Other underrun interrupts may already be waiting */
1357			write_scc(priv, R0, RES_EXT_INT);
1358			write_scc(priv, R0, RES_EXT_INT);
1359		} else {
1360			/* Update packet statistics */
1361			priv->dev->stats.tx_packets++;
1362			priv->dev->stats.tx_bytes += priv->tx_len[i];
1363			/* Remove frame from FIFO */
1364			priv->tx_tail = (i + 1) % NUM_TX_BUF;
1365			priv->tx_count--;
1366			/* Inform upper layers */
1367			netif_wake_queue(priv->dev);
1368		}
1369		/* Switch state */
1370		write_scc(priv, R15, 0);
1371		if (priv->tx_count &&
1372		    (jiffies - priv->tx_start) < priv->param.txtimeout) {
1373			priv->state = TX_PAUSE;
1374			start_timer(priv, priv->param.txpause, 0);
1375		} else {
1376			priv->state = TX_TAIL;
1377			start_timer(priv, priv->param.txtail, 0);
1378		}
1379	}
1380
1381	/* DCD transition */
1382	if (drr0 & DCD) {
1383		if (rr0 & DCD) {
1384			switch (priv->state) {
1385			case IDLE:
1386			case WAIT:
1387				priv->state = DCD_ON;
1388				write_scc(priv, R15, 0);
1389				start_timer(priv, priv->param.dcdon, 0);
1390			}
1391		} else {
1392			switch (priv->state) {
1393			case RX_ON:
1394				rx_off(priv);
1395				priv->state = DCD_OFF;
1396				write_scc(priv, R15, 0);
1397				start_timer(priv, priv->param.dcdoff, 0);
1398			}
1399		}
1400	}
1401
1402	/* CTS transition */
1403	if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN)
1404		tm_isr(priv);
1405
1406}
1407
1408
1409static void tm_isr(struct scc_priv *priv)
1410{
1411	switch (priv->state) {
1412	case TX_HEAD:
1413	case TX_PAUSE:
1414		tx_on(priv);
1415		priv->state = TX_DATA;
1416		break;
1417	case TX_TAIL:
1418		write_scc(priv, R5, TxCRC_ENAB | Tx8);
1419		priv->state = RTS_OFF;
1420		if (priv->type != TYPE_TWIN)
1421			write_scc(priv, R15, 0);
1422		start_timer(priv, priv->param.rtsoff, 0);
1423		break;
1424	case RTS_OFF:
1425		write_scc(priv, R15, DCDIE);
1426		priv->rr0 = read_scc(priv, R0);
1427		if (priv->rr0 & DCD) {
1428			priv->dev->stats.collisions++;
1429			rx_on(priv);
1430			priv->state = RX_ON;
1431		} else {
1432			priv->state = WAIT;
1433			start_timer(priv, priv->param.waittime, DCDIE);
1434		}
1435		break;
1436	case WAIT:
1437		if (priv->tx_count) {
1438			priv->state = TX_HEAD;
1439			priv->tx_start = jiffies;
1440			write_scc(priv, R5,
1441				  TxCRC_ENAB | RTS | TxENAB | Tx8);
1442			write_scc(priv, R15, 0);
1443			start_timer(priv, priv->param.txdelay, 0);
1444		} else {
1445			priv->state = IDLE;
1446			if (priv->type != TYPE_TWIN)
1447				write_scc(priv, R15, DCDIE);
1448		}
1449		break;
1450	case DCD_ON:
1451	case DCD_OFF:
1452		write_scc(priv, R15, DCDIE);
1453		priv->rr0 = read_scc(priv, R0);
1454		if (priv->rr0 & DCD) {
1455			rx_on(priv);
1456			priv->state = RX_ON;
1457		} else {
1458			priv->state = WAIT;
1459			start_timer(priv,
1460				    random() / priv->param.persist *
1461				    priv->param.slottime, DCDIE);
1462		}
1463		break;
1464	}
1465}