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1/*
2 * isp.h
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2009-2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#ifndef OMAP3_ISP_CORE_H
18#define OMAP3_ISP_CORE_H
19
20#include <media/media-entity.h>
21#include <media/v4l2-async.h>
22#include <media/v4l2-device.h>
23#include <linux/clk-provider.h>
24#include <linux/device.h>
25#include <linux/io.h>
26#include <linux/iommu.h>
27#include <linux/platform_device.h>
28#include <linux/wait.h>
29
30#include "omap3isp.h"
31#include "ispstat.h"
32#include "ispccdc.h"
33#include "ispreg.h"
34#include "ispresizer.h"
35#include "isppreview.h"
36#include "ispcsiphy.h"
37#include "ispcsi2.h"
38#include "ispccp2.h"
39
40#define ISP_TOK_TERM 0xFFFFFFFF /*
41 * terminating token for ISP
42 * modules reg list
43 */
44#define to_isp_device(ptr_module) \
45 container_of(ptr_module, struct isp_device, isp_##ptr_module)
46#define to_device(ptr_module) \
47 (to_isp_device(ptr_module)->dev)
48
49enum isp_mem_resources {
50 OMAP3_ISP_IOMEM_MAIN,
51 OMAP3_ISP_IOMEM_CCP2,
52 OMAP3_ISP_IOMEM_CCDC,
53 OMAP3_ISP_IOMEM_HIST,
54 OMAP3_ISP_IOMEM_H3A,
55 OMAP3_ISP_IOMEM_PREV,
56 OMAP3_ISP_IOMEM_RESZ,
57 OMAP3_ISP_IOMEM_SBL,
58 OMAP3_ISP_IOMEM_CSI2A_REGS1,
59 OMAP3_ISP_IOMEM_CSIPHY2,
60 OMAP3_ISP_IOMEM_CSI2A_REGS2,
61 OMAP3_ISP_IOMEM_CSI2C_REGS1,
62 OMAP3_ISP_IOMEM_CSIPHY1,
63 OMAP3_ISP_IOMEM_CSI2C_REGS2,
64 OMAP3_ISP_IOMEM_LAST
65};
66
67enum isp_sbl_resource {
68 OMAP3_ISP_SBL_CSI1_READ = 0x1,
69 OMAP3_ISP_SBL_CSI1_WRITE = 0x2,
70 OMAP3_ISP_SBL_CSI2A_WRITE = 0x4,
71 OMAP3_ISP_SBL_CSI2C_WRITE = 0x8,
72 OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10,
73 OMAP3_ISP_SBL_CCDC_WRITE = 0x20,
74 OMAP3_ISP_SBL_PREVIEW_READ = 0x40,
75 OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80,
76 OMAP3_ISP_SBL_RESIZER_READ = 0x100,
77 OMAP3_ISP_SBL_RESIZER_WRITE = 0x200,
78};
79
80enum isp_subclk_resource {
81 OMAP3_ISP_SUBCLK_CCDC = (1 << 0),
82 OMAP3_ISP_SUBCLK_AEWB = (1 << 1),
83 OMAP3_ISP_SUBCLK_AF = (1 << 2),
84 OMAP3_ISP_SUBCLK_HIST = (1 << 3),
85 OMAP3_ISP_SUBCLK_PREVIEW = (1 << 4),
86 OMAP3_ISP_SUBCLK_RESIZER = (1 << 5),
87};
88
89/* ISP: OMAP 34xx ES 1.0 */
90#define ISP_REVISION_1_0 0x10
91/* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
92#define ISP_REVISION_2_0 0x20
93/* ISP2P: OMAP 36xx */
94#define ISP_REVISION_15_0 0xF0
95
96#define ISP_PHY_TYPE_3430 0
97#define ISP_PHY_TYPE_3630 1
98
99struct regmap;
100
101/*
102 * struct isp_res_mapping - Map ISP io resources to ISP revision.
103 * @isp_rev: ISP_REVISION_x_x
104 * @offset: register offsets of various ISP sub-blocks
105 * @phy_type: ISP_PHY_TYPE_{3430,3630}
106 */
107struct isp_res_mapping {
108 u32 isp_rev;
109 u32 offset[OMAP3_ISP_IOMEM_LAST];
110 u32 phy_type;
111};
112
113/*
114 * struct isp_reg - Structure for ISP register values.
115 * @reg: 32-bit Register address.
116 * @val: 32-bit Register value.
117 */
118struct isp_reg {
119 enum isp_mem_resources mmio_range;
120 u32 reg;
121 u32 val;
122};
123
124enum isp_xclk_id {
125 ISP_XCLK_A,
126 ISP_XCLK_B,
127};
128
129struct isp_xclk {
130 struct isp_device *isp;
131 struct clk_hw hw;
132 struct clk *clk;
133 enum isp_xclk_id id;
134
135 spinlock_t lock; /* Protects enabled and divider */
136 bool enabled;
137 unsigned int divider;
138};
139
140/*
141 * struct isp_device - ISP device structure.
142 * @dev: Device pointer specific to the OMAP3 ISP.
143 * @revision: Stores current ISP module revision.
144 * @irq_num: Currently used IRQ number.
145 * @mmio_base: Array with kernel base addresses for ioremapped ISP register
146 * regions.
147 * @mmio_hist_base_phys: Physical L4 bus address for ISP hist block register
148 * region.
149 * @syscon: Regmap for the syscon register space
150 * @syscon_offset: Offset of the CSIPHY control register in syscon
151 * @phy_type: ISP_PHY_TYPE_{3430,3630}
152 * @mapping: IOMMU mapping
153 * @stat_lock: Spinlock for handling statistics
154 * @isp_mutex: Mutex for serializing requests to ISP.
155 * @stop_failure: Indicates that an entity failed to stop.
156 * @crashed: Crashed ent_enum
157 * @has_context: Context has been saved at least once and can be restored.
158 * @ref_count: Reference count for handling multiple ISP requests.
159 * @cam_ick: Pointer to camera interface clock structure.
160 * @cam_mclk: Pointer to camera functional clock structure.
161 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
162 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
163 * @xclks: External clocks provided by the ISP
164 * @irq: Currently attached ISP ISR callbacks information structure.
165 * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
166 * @isp_hist: Pointer to current settings for ISP Histogram SCM.
167 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
168 * White Balance SCM.
169 * @isp_res: Pointer to current settings for ISP Resizer.
170 * @isp_prev: Pointer to current settings for ISP Preview.
171 * @isp_ccdc: Pointer to current settings for ISP CCDC.
172 * @platform_cb: ISP driver callback function pointers for platform code
173 *
174 * This structure is used to store the OMAP ISP Information.
175 */
176struct isp_device {
177 struct v4l2_device v4l2_dev;
178 struct v4l2_async_notifier notifier;
179 struct media_device media_dev;
180 struct device *dev;
181 u32 revision;
182
183 /* platform HW resources */
184 unsigned int irq_num;
185
186 void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
187 unsigned long mmio_hist_base_phys;
188 struct regmap *syscon;
189 u32 syscon_offset;
190 u32 phy_type;
191
192 struct dma_iommu_mapping *mapping;
193
194 /* ISP Obj */
195 spinlock_t stat_lock; /* common lock for statistic drivers */
196 struct mutex isp_mutex; /* For handling ref_count field */
197 bool stop_failure;
198 struct media_entity_enum crashed;
199 int has_context;
200 int ref_count;
201 unsigned int autoidle;
202#define ISP_CLK_CAM_ICK 0
203#define ISP_CLK_CAM_MCLK 1
204#define ISP_CLK_CSI2_FCK 2
205#define ISP_CLK_L3_ICK 3
206 struct clk *clock[4];
207 struct isp_xclk xclks[2];
208
209 /* ISP modules */
210 struct ispstat isp_af;
211 struct ispstat isp_aewb;
212 struct ispstat isp_hist;
213 struct isp_res_device isp_res;
214 struct isp_prev_device isp_prev;
215 struct isp_ccdc_device isp_ccdc;
216 struct isp_csi2_device isp_csi2a;
217 struct isp_csi2_device isp_csi2c;
218 struct isp_ccp2_device isp_ccp2;
219 struct isp_csiphy isp_csiphy1;
220 struct isp_csiphy isp_csiphy2;
221
222 unsigned int sbl_resources;
223 unsigned int subclk_resources;
224
225#define ISP_MAX_SUBDEVS 8
226 struct v4l2_subdev *subdevs[ISP_MAX_SUBDEVS];
227};
228
229struct isp_async_subdev {
230 struct v4l2_subdev *sd;
231 struct isp_bus_cfg bus;
232 struct v4l2_async_subdev asd;
233};
234
235#define v4l2_dev_to_isp_device(dev) \
236 container_of(dev, struct isp_device, v4l2_dev)
237
238void omap3isp_hist_dma_done(struct isp_device *isp);
239
240void omap3isp_flush(struct isp_device *isp);
241
242int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
243 atomic_t *stopping);
244
245int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
246 atomic_t *stopping);
247
248int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
249 enum isp_pipeline_stream_state state);
250void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe);
251void omap3isp_configure_bridge(struct isp_device *isp,
252 enum ccdc_input_entity input,
253 const struct isp_parallel_cfg *buscfg,
254 unsigned int shift, unsigned int bridge);
255
256struct isp_device *omap3isp_get(struct isp_device *isp);
257void omap3isp_put(struct isp_device *isp);
258
259void omap3isp_print_status(struct isp_device *isp);
260
261void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
262void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
263
264void omap3isp_subclk_enable(struct isp_device *isp,
265 enum isp_subclk_resource res);
266void omap3isp_subclk_disable(struct isp_device *isp,
267 enum isp_subclk_resource res);
268
269int omap3isp_register_entities(struct platform_device *pdev,
270 struct v4l2_device *v4l2_dev);
271void omap3isp_unregister_entities(struct platform_device *pdev);
272
273/*
274 * isp_reg_readl - Read value of an OMAP3 ISP register
275 * @isp: Device pointer specific to the OMAP3 ISP.
276 * @isp_mmio_range: Range to which the register offset refers to.
277 * @reg_offset: Register offset to read from.
278 *
279 * Returns an unsigned 32 bit value with the required register contents.
280 */
281static inline
282u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
283 u32 reg_offset)
284{
285 return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
286}
287
288/*
289 * isp_reg_writel - Write value to an OMAP3 ISP register
290 * @isp: Device pointer specific to the OMAP3 ISP.
291 * @reg_value: 32 bit value to write to the register.
292 * @isp_mmio_range: Range to which the register offset refers to.
293 * @reg_offset: Register offset to write into.
294 */
295static inline
296void isp_reg_writel(struct isp_device *isp, u32 reg_value,
297 enum isp_mem_resources isp_mmio_range, u32 reg_offset)
298{
299 __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
300}
301
302/*
303 * isp_reg_clr - Clear individual bits in an OMAP3 ISP register
304 * @isp: Device pointer specific to the OMAP3 ISP.
305 * @mmio_range: Range to which the register offset refers to.
306 * @reg: Register offset to work on.
307 * @clr_bits: 32 bit value which would be cleared in the register.
308 */
309static inline
310void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
311 u32 reg, u32 clr_bits)
312{
313 u32 v = isp_reg_readl(isp, mmio_range, reg);
314
315 isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
316}
317
318/*
319 * isp_reg_set - Set individual bits in an OMAP3 ISP register
320 * @isp: Device pointer specific to the OMAP3 ISP.
321 * @mmio_range: Range to which the register offset refers to.
322 * @reg: Register offset to work on.
323 * @set_bits: 32 bit value which would be set in the register.
324 */
325static inline
326void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
327 u32 reg, u32 set_bits)
328{
329 u32 v = isp_reg_readl(isp, mmio_range, reg);
330
331 isp_reg_writel(isp, v | set_bits, mmio_range, reg);
332}
333
334/*
335 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
336 * @isp: Device pointer specific to the OMAP3 ISP.
337 * @mmio_range: Range to which the register offset refers to.
338 * @reg: Register offset to work on.
339 * @clr_bits: 32 bit value which would be cleared in the register.
340 * @set_bits: 32 bit value which would be set in the register.
341 *
342 * The clear operation is done first, and then the set operation.
343 */
344static inline
345void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
346 u32 reg, u32 clr_bits, u32 set_bits)
347{
348 u32 v = isp_reg_readl(isp, mmio_range, reg);
349
350 isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
351}
352
353static inline enum v4l2_buf_type
354isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
355{
356 if (pad >= subdev->entity.num_pads)
357 return 0;
358
359 if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
360 return V4L2_BUF_TYPE_VIDEO_OUTPUT;
361 else
362 return V4L2_BUF_TYPE_VIDEO_CAPTURE;
363}
364
365#endif /* OMAP3_ISP_CORE_H */