1/*
  2 * Copyright 2008 Advanced Micro Devices, Inc.
  3 * Copyright 2008 Red Hat Inc.
  4 * Copyright 2009 Jerome Glisse.
  5 *
  6 * Permission is hereby granted, free of charge, to any person obtaining a
  7 * copy of this software and associated documentation files (the "Software"),
  8 * to deal in the Software without restriction, including without limitation
  9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 10 * and/or sell copies of the Software, and to permit persons to whom the
 11 * Software is furnished to do so, subject to the following conditions:
 12 *
 13 * The above copyright notice and this permission notice shall be included in
 14 * all copies or substantial portions of the Software.
 15 *
 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 22 * OTHER DEALINGS IN THE SOFTWARE.
 23 *
 24 * Authors: Dave Airlie
 25 *          Alex Deucher
 26 *          Jerome Glisse
 27 *          Christian König
 28 */
 29#include <linux/seq_file.h>
 30#include <linux/slab.h>
 31#include <linux/debugfs.h>
 32#include <drm/drmP.h>
 33#include <drm/amdgpu_drm.h>
 34#include "amdgpu.h"
 35#include "atom.h"
 36
 37/*
 38 * Rings
 39 * Most engines on the GPU are fed via ring buffers.  Ring
 40 * buffers are areas of GPU accessible memory that the host
 41 * writes commands into and the GPU reads commands out of.
 42 * There is a rptr (read pointer) that determines where the
 43 * GPU is currently reading, and a wptr (write pointer)
 44 * which determines where the host has written.  When the
 45 * pointers are equal, the ring is idle.  When the host
 46 * writes commands to the ring buffer, it increments the
 47 * wptr.  The GPU then starts fetching commands and executes
 48 * them until the pointers are equal again.
 49 */
 50static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
 51				    struct amdgpu_ring *ring);
 52static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
 53
 54/**
 55 * amdgpu_ring_alloc - allocate space on the ring buffer
 56 *
 57 * @adev: amdgpu_device pointer
 58 * @ring: amdgpu_ring structure holding ring information
 59 * @ndw: number of dwords to allocate in the ring buffer
 60 *
 61 * Allocate @ndw dwords in the ring buffer (all asics).
 62 * Returns 0 on success, error on failure.
 63 */
 64int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
 65{
 66	/* Align requested size with padding so unlock_commit can
 67	 * pad safely */
 68	ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
 69
 70	/* Make sure we aren't trying to allocate more space
 71	 * than the maximum for one submission
 72	 */
 73	if (WARN_ON_ONCE(ndw > ring->max_dw))
 74		return -ENOMEM;
 75
 76	ring->count_dw = ndw;
 77	ring->wptr_old = ring->wptr;
 78
 79	if (ring->funcs->begin_use)
 80		ring->funcs->begin_use(ring);
 81
 82	return 0;
 83}
 84
 85/** amdgpu_ring_insert_nop - insert NOP packets
 86 *
 87 * @ring: amdgpu_ring structure holding ring information
 88 * @count: the number of NOP packets to insert
 89 *
 90 * This is the generic insert_nop function for rings except SDMA
 91 */
 92void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 93{
 94	int i;
 95
 96	for (i = 0; i < count; i++)
 97		amdgpu_ring_write(ring, ring->funcs->nop);
 98}
 99
100/** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
101 *
102 * @ring: amdgpu_ring structure holding ring information
103 * @ib: IB to add NOP packets to
104 *
105 * This is the generic pad_ib function for rings except SDMA
106 */
107void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
108{
109	while (ib->length_dw & ring->funcs->align_mask)
110		ib->ptr[ib->length_dw++] = ring->funcs->nop;
111}
112
113/**
114 * amdgpu_ring_commit - tell the GPU to execute the new
115 * commands on the ring buffer
116 *
117 * @adev: amdgpu_device pointer
118 * @ring: amdgpu_ring structure holding ring information
119 *
120 * Update the wptr (write pointer) to tell the GPU to
121 * execute new commands on the ring buffer (all asics).
122 */
123void amdgpu_ring_commit(struct amdgpu_ring *ring)
124{
125	uint32_t count;
126
127	/* We pad to match fetch size */
128	count = ring->funcs->align_mask + 1 -
129		(ring->wptr & ring->funcs->align_mask);
130	count %= ring->funcs->align_mask + 1;
131	ring->funcs->insert_nop(ring, count);
132
133	mb();
134	amdgpu_ring_set_wptr(ring);
135
136	if (ring->funcs->end_use)
137		ring->funcs->end_use(ring);
138}
139
140/**
141 * amdgpu_ring_undo - reset the wptr
142 *
143 * @ring: amdgpu_ring structure holding ring information
144 *
145 * Reset the driver's copy of the wptr (all asics).
146 */
147void amdgpu_ring_undo(struct amdgpu_ring *ring)
148{
149	ring->wptr = ring->wptr_old;
150
151	if (ring->funcs->end_use)
152		ring->funcs->end_use(ring);
153}
154
155/**
156 * amdgpu_ring_init - init driver ring struct.
157 *
158 * @adev: amdgpu_device pointer
159 * @ring: amdgpu_ring structure holding ring information
160 * @max_ndw: maximum number of dw for ring alloc
161 * @nop: nop packet for this ring
162 *
163 * Initialize the driver information for the selected ring (all asics).
164 * Returns 0 on success, error on failure.
165 */
166int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
167		     unsigned max_dw, struct amdgpu_irq_src *irq_src,
168		     unsigned irq_type)
169{
170	int r;
171
172	if (ring->adev == NULL) {
173		if (adev->num_rings >= AMDGPU_MAX_RINGS)
174			return -EINVAL;
175
176		ring->adev = adev;
177		ring->idx = adev->num_rings++;
178		adev->rings[ring->idx] = ring;
179		r = amdgpu_fence_driver_init_ring(ring,
180			amdgpu_sched_hw_submission);
181		if (r)
182			return r;
183	}
184
185	r = amdgpu_wb_get(adev, &ring->rptr_offs);
186	if (r) {
187		dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
188		return r;
189	}
190
191	r = amdgpu_wb_get(adev, &ring->wptr_offs);
192	if (r) {
193		dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
194		return r;
195	}
196
197	r = amdgpu_wb_get(adev, &ring->fence_offs);
198	if (r) {
199		dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
200		return r;
201	}
202
203	r = amdgpu_wb_get(adev, &ring->cond_exe_offs);
204	if (r) {
205		dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
206		return r;
207	}
208	ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
209	ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
210
211	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
212	if (r) {
213		dev_err(adev->dev, "failed initializing fences (%d).\n", r);
214		return r;
215	}
216
217	ring->ring_size = roundup_pow_of_two(max_dw * 4 *
218					     amdgpu_sched_hw_submission);
219
220	/* Allocate ring buffer */
221	if (ring->ring_obj == NULL) {
222		r = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
223					    AMDGPU_GEM_DOMAIN_GTT,
224					    &ring->ring_obj,
225					    &ring->gpu_addr,
226					    (void **)&ring->ring);
227		if (r) {
228			dev_err(adev->dev, "(%d) ring create failed\n", r);
229			return r;
230		}
231		memset((void *)ring->ring, 0, ring->ring_size);
232	}
233	ring->ptr_mask = (ring->ring_size / 4) - 1;
234	ring->max_dw = max_dw;
235
236	if (amdgpu_debugfs_ring_init(adev, ring)) {
237		DRM_ERROR("Failed to register debugfs file for rings !\n");
238	}
239	return 0;
240}
241
242/**
243 * amdgpu_ring_fini - tear down the driver ring struct.
244 *
245 * @adev: amdgpu_device pointer
246 * @ring: amdgpu_ring structure holding ring information
247 *
248 * Tear down the driver information for the selected ring (all asics).
249 */
250void amdgpu_ring_fini(struct amdgpu_ring *ring)
251{
252	ring->ready = false;
253
254	amdgpu_wb_free(ring->adev, ring->cond_exe_offs);
255	amdgpu_wb_free(ring->adev, ring->fence_offs);
256	amdgpu_wb_free(ring->adev, ring->rptr_offs);
257	amdgpu_wb_free(ring->adev, ring->wptr_offs);
258
259	amdgpu_bo_free_kernel(&ring->ring_obj,
260			      &ring->gpu_addr,
261			      (void **)&ring->ring);
262
263	amdgpu_debugfs_ring_fini(ring);
264
265	ring->adev->rings[ring->idx] = NULL;
266}
267
268/*
269 * Debugfs info
270 */
271#if defined(CONFIG_DEBUG_FS)
272
273/* Layout of file is 12 bytes consisting of
274 * - rptr
275 * - wptr
276 * - driver's copy of wptr
277 *
278 * followed by n-words of ring data
279 */
280static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
281					size_t size, loff_t *pos)
282{
283	struct amdgpu_ring *ring = file_inode(f)->i_private;
284	int r, i;
285	uint32_t value, result, early[3];
286
287	if (*pos & 3 || size & 3)
288		return -EINVAL;
289
290	result = 0;
291
292	if (*pos < 12) {
293		early[0] = amdgpu_ring_get_rptr(ring);
294		early[1] = amdgpu_ring_get_wptr(ring);
295		early[2] = ring->wptr;
296		for (i = *pos / 4; i < 3 && size; i++) {
297			r = put_user(early[i], (uint32_t *)buf);
298			if (r)
299				return r;
300			buf += 4;
301			result += 4;
302			size -= 4;
303			*pos += 4;
304		}
305	}
306
307	while (size) {
308		if (*pos >= (ring->ring_size + 12))
309			return result;
310			
311		value = ring->ring[(*pos - 12)/4];
312		r = put_user(value, (uint32_t*)buf);
313		if (r)
314			return r;
315		buf += 4;
316		result += 4;
317		size -= 4;
318		*pos += 4;
319	}
320
321	return result;
322}
323
324static const struct file_operations amdgpu_debugfs_ring_fops = {
325	.owner = THIS_MODULE,
326	.read = amdgpu_debugfs_ring_read,
327	.llseek = default_llseek
328};
329
330#endif
331
332static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
333				    struct amdgpu_ring *ring)
334{
335#if defined(CONFIG_DEBUG_FS)
336	struct drm_minor *minor = adev->ddev->primary;
337	struct dentry *ent, *root = minor->debugfs_root;
338	char name[32];
339
340	sprintf(name, "amdgpu_ring_%s", ring->name);
341
342	ent = debugfs_create_file(name,
343				  S_IFREG | S_IRUGO, root,
344				  ring, &amdgpu_debugfs_ring_fops);
345	if (!ent)
346		return -ENOMEM;
347
348	i_size_write(ent->d_inode, ring->ring_size + 12);
349	ring->ent = ent;
350#endif
351	return 0;
352}
353
354static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring)
355{
356#if defined(CONFIG_DEBUG_FS)
357	debugfs_remove(ring->ent);
358#endif
359}