1/*
  2 * Copyright (C) 2012,2013 - ARM Ltd
  3 * Author: Marc Zyngier <marc.zyngier@arm.com>
  4 *
  5 * Derived from arch/arm/include/uapi/asm/kvm.h:
  6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
  7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
  8 *
  9 * This program is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License version 2 as
 11 * published by the Free Software Foundation.
 12 *
 13 * This program is distributed in the hope that it will be useful,
 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16 * GNU General Public License for more details.
 17 *
 18 * You should have received a copy of the GNU General Public License
 19 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 20 */
 21
 22#ifndef __ARM_KVM_H__
 23#define __ARM_KVM_H__
 24
 25#define KVM_SPSR_EL1	0
 26#define KVM_SPSR_SVC	KVM_SPSR_EL1
 27#define KVM_SPSR_ABT	1
 28#define KVM_SPSR_UND	2
 29#define KVM_SPSR_IRQ	3
 30#define KVM_SPSR_FIQ	4
 31#define KVM_NR_SPSR	5
 32
 33#ifndef __ASSEMBLY__
 34#include <linux/psci.h>
 35#include <linux/types.h>
 36#include <asm/ptrace.h>
 37
 38#define __KVM_HAVE_GUEST_DEBUG
 39#define __KVM_HAVE_IRQ_LINE
 40#define __KVM_HAVE_READONLY_MEM
 41
 42#define KVM_REG_SIZE(id)						\
 43	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
 44
 45struct kvm_regs {
 46	struct user_pt_regs regs;	/* sp = sp_el0 */
 47
 48	__u64	sp_el1;
 49	__u64	elr_el1;
 50
 51	__u64	spsr[KVM_NR_SPSR];
 52
 53	struct user_fpsimd_state fp_regs;
 54};
 55
 56/*
 57 * Supported CPU Targets - Adding a new target type is not recommended,
 58 * unless there are some special registers not supported by the
 59 * genericv8 syreg table.
 60 */
 61#define KVM_ARM_TARGET_AEM_V8		0
 62#define KVM_ARM_TARGET_FOUNDATION_V8	1
 63#define KVM_ARM_TARGET_CORTEX_A57	2
 64#define KVM_ARM_TARGET_XGENE_POTENZA	3
 65#define KVM_ARM_TARGET_CORTEX_A53	4
 66/* Generic ARM v8 target */
 67#define KVM_ARM_TARGET_GENERIC_V8	5
 68
 69#define KVM_ARM_NUM_TARGETS		6
 70
 71/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
 72#define KVM_ARM_DEVICE_TYPE_SHIFT	0
 73#define KVM_ARM_DEVICE_TYPE_MASK	(0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
 74#define KVM_ARM_DEVICE_ID_SHIFT		16
 75#define KVM_ARM_DEVICE_ID_MASK		(0xffff << KVM_ARM_DEVICE_ID_SHIFT)
 76
 77/* Supported device IDs */
 78#define KVM_ARM_DEVICE_VGIC_V2		0
 79
 80/* Supported VGIC address types  */
 81#define KVM_VGIC_V2_ADDR_TYPE_DIST	0
 82#define KVM_VGIC_V2_ADDR_TYPE_CPU	1
 83
 84#define KVM_VGIC_V2_DIST_SIZE		0x1000
 85#define KVM_VGIC_V2_CPU_SIZE		0x2000
 86
 87/* Supported VGICv3 address types  */
 88#define KVM_VGIC_V3_ADDR_TYPE_DIST	2
 89#define KVM_VGIC_V3_ADDR_TYPE_REDIST	3
 90#define KVM_VGIC_ITS_ADDR_TYPE		4
 91
 92#define KVM_VGIC_V3_DIST_SIZE		SZ_64K
 93#define KVM_VGIC_V3_REDIST_SIZE		(2 * SZ_64K)
 94#define KVM_VGIC_V3_ITS_SIZE		(2 * SZ_64K)
 95
 96#define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */
 97#define KVM_ARM_VCPU_EL1_32BIT		1 /* CPU running a 32bit VM */
 98#define KVM_ARM_VCPU_PSCI_0_2		2 /* CPU uses PSCI v0.2 */
 99#define KVM_ARM_VCPU_PMU_V3		3 /* Support guest PMUv3 */
100
101struct kvm_vcpu_init {
102	__u32 target;
103	__u32 features[7];
104};
105
106struct kvm_sregs {
107};
108
109struct kvm_fpu {
110};
111
112/*
113 * See v8 ARM ARM D7.3: Debug Registers
114 *
115 * The architectural limit is 16 debug registers of each type although
116 * in practice there are usually less (see ID_AA64DFR0_EL1).
117 *
118 * Although the control registers are architecturally defined as 32
119 * bits wide we use a 64 bit structure here to keep parity with
120 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as
121 * 64 bit values. It also allows for the possibility of the
122 * architecture expanding the control registers without having to
123 * change the userspace ABI.
124 */
125#define KVM_ARM_MAX_DBG_REGS 16
126struct kvm_guest_debug_arch {
127	__u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
128	__u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
129	__u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
130	__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
131};
132
133struct kvm_debug_exit_arch {
134	__u32 hsr;
135	__u64 far;	/* used for watchpoints */
136};
137
138/*
139 * Architecture specific defines for kvm_guest_debug->control
140 */
141
142#define KVM_GUESTDBG_USE_SW_BP		(1 << 16)
143#define KVM_GUESTDBG_USE_HW		(1 << 17)
144
145struct kvm_sync_regs {
146};
147
148struct kvm_arch_memory_slot {
149};
150
151/* If you need to interpret the index values, here is the key: */
152#define KVM_REG_ARM_COPROC_MASK		0x000000000FFF0000
153#define KVM_REG_ARM_COPROC_SHIFT	16
154
155/* Normal registers are mapped as coprocessor 16. */
156#define KVM_REG_ARM_CORE		(0x0010 << KVM_REG_ARM_COPROC_SHIFT)
157#define KVM_REG_ARM_CORE_REG(name)	(offsetof(struct kvm_regs, name) / sizeof(__u32))
158
159/* Some registers need more space to represent values. */
160#define KVM_REG_ARM_DEMUX		(0x0011 << KVM_REG_ARM_COPROC_SHIFT)
161#define KVM_REG_ARM_DEMUX_ID_MASK	0x000000000000FF00
162#define KVM_REG_ARM_DEMUX_ID_SHIFT	8
163#define KVM_REG_ARM_DEMUX_ID_CCSIDR	(0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
164#define KVM_REG_ARM_DEMUX_VAL_MASK	0x00000000000000FF
165#define KVM_REG_ARM_DEMUX_VAL_SHIFT	0
166
167/* AArch64 system registers */
168#define KVM_REG_ARM64_SYSREG		(0x0013 << KVM_REG_ARM_COPROC_SHIFT)
169#define KVM_REG_ARM64_SYSREG_OP0_MASK	0x000000000000c000
170#define KVM_REG_ARM64_SYSREG_OP0_SHIFT	14
171#define KVM_REG_ARM64_SYSREG_OP1_MASK	0x0000000000003800
172#define KVM_REG_ARM64_SYSREG_OP1_SHIFT	11
173#define KVM_REG_ARM64_SYSREG_CRN_MASK	0x0000000000000780
174#define KVM_REG_ARM64_SYSREG_CRN_SHIFT	7
175#define KVM_REG_ARM64_SYSREG_CRM_MASK	0x0000000000000078
176#define KVM_REG_ARM64_SYSREG_CRM_SHIFT	3
177#define KVM_REG_ARM64_SYSREG_OP2_MASK	0x0000000000000007
178#define KVM_REG_ARM64_SYSREG_OP2_SHIFT	0
179
180#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
181	(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
182	KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
183
184#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
185	(KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
186	ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
187	ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
188	ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
189	ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
190	ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
191
192#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
193
194#define KVM_REG_ARM_TIMER_CTL		ARM64_SYS_REG(3, 3, 14, 3, 1)
195#define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)
196#define KVM_REG_ARM_TIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 0, 2)
197
198/* Device Control API: ARM VGIC */
199#define KVM_DEV_ARM_VGIC_GRP_ADDR	0
200#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1
201#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS	2
202#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT	32
203#define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
204#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0
205#define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
206#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS	3
207#define KVM_DEV_ARM_VGIC_GRP_CTRL	4
208#define   KVM_DEV_ARM_VGIC_CTRL_INIT	0
209
210/* Device Control API on vcpu fd */
211#define KVM_ARM_VCPU_PMU_V3_CTRL	0
212#define   KVM_ARM_VCPU_PMU_V3_IRQ	0
213#define   KVM_ARM_VCPU_PMU_V3_INIT	1
214
215/* KVM_IRQ_LINE irq field index values */
216#define KVM_ARM_IRQ_TYPE_SHIFT		24
217#define KVM_ARM_IRQ_TYPE_MASK		0xff
218#define KVM_ARM_IRQ_VCPU_SHIFT		16
219#define KVM_ARM_IRQ_VCPU_MASK		0xff
220#define KVM_ARM_IRQ_NUM_SHIFT		0
221#define KVM_ARM_IRQ_NUM_MASK		0xffff
222
223/* irq_type field */
224#define KVM_ARM_IRQ_TYPE_CPU		0
225#define KVM_ARM_IRQ_TYPE_SPI		1
226#define KVM_ARM_IRQ_TYPE_PPI		2
227
228/* out-of-kernel GIC cpu interrupt injection irq_number field */
229#define KVM_ARM_IRQ_CPU_IRQ		0
230#define KVM_ARM_IRQ_CPU_FIQ		1
231
232/*
233 * This used to hold the highest supported SPI, but it is now obsolete
234 * and only here to provide source code level compatibility with older
235 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
236 */
237#ifndef __KERNEL__
238#define KVM_ARM_IRQ_GIC_MAX		127
239#endif
240
241/* One single KVM irqchip, ie. the VGIC */
242#define KVM_NR_IRQCHIPS          1
243
244/* PSCI interface */
245#define KVM_PSCI_FN_BASE		0x95c1ba5e
246#define KVM_PSCI_FN(n)			(KVM_PSCI_FN_BASE + (n))
247
248#define KVM_PSCI_FN_CPU_SUSPEND		KVM_PSCI_FN(0)
249#define KVM_PSCI_FN_CPU_OFF		KVM_PSCI_FN(1)
250#define KVM_PSCI_FN_CPU_ON		KVM_PSCI_FN(2)
251#define KVM_PSCI_FN_MIGRATE		KVM_PSCI_FN(3)
252
253#define KVM_PSCI_RET_SUCCESS		PSCI_RET_SUCCESS
254#define KVM_PSCI_RET_NI			PSCI_RET_NOT_SUPPORTED
255#define KVM_PSCI_RET_INVAL		PSCI_RET_INVALID_PARAMS
256#define KVM_PSCI_RET_DENIED		PSCI_RET_DENIED
257
258#endif
259
260#endif /* __ARM_KVM_H__ */