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1/*
2 * ARC700 VIPT Cache Management
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
11 * -flush_cache_dup_mm (fork)
12 * -likewise for flush_cache_mm (exit/execve)
13 * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break)
14 *
15 * vineetg: Apr 2011
16 * -Now that MMU can support larger pg sz (16K), the determiniation of
17 * aliasing shd not be based on assumption of 8k pg
18 *
19 * vineetg: Mar 2011
20 * -optimised version of flush_icache_range( ) for making I/D coherent
21 * when vaddr is available (agnostic of num of aliases)
22 *
23 * vineetg: Mar 2011
24 * -Added documentation about I-cache aliasing on ARC700 and the way it
25 * was handled up until MMU V2.
26 * -Spotted a three year old bug when killing the 4 aliases, which needs
27 * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03}
28 * instead of paddr | {0x00, 0x01, 0x10, 0x11}
29 * (Rajesh you owe me one now)
30 *
31 * vineetg: Dec 2010
32 * -Off-by-one error when computing num_of_lines to flush
33 * This broke signal handling with bionic which uses synthetic sigret stub
34 *
35 * vineetg: Mar 2010
36 * -GCC can't generate ZOL for core cache flush loops.
37 * Conv them into iterations based as opposed to while (start < end) types
38 *
39 * Vineetg: July 2009
40 * -In I-cache flush routine we used to chk for aliasing for every line INV.
41 * Instead now we setup routines per cache geometry and invoke them
42 * via function pointers.
43 *
44 * Vineetg: Jan 2009
45 * -Cache Line flush routines used to flush an extra line beyond end addr
46 * because check was while (end >= start) instead of (end > start)
47 * =Some call sites had to work around by doing -1, -4 etc to end param
48 * =Some callers didnt care. This was spec bad in case of INV routines
49 * which would discard valid data (cause of the horrible ext2 bug
50 * in ARC IDE driver)
51 *
52 * vineetg: June 11th 2008: Fixed flush_icache_range( )
53 * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need
54 * to be flushed, which it was not doing.
55 * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API,
56 * however ARC cache maintenance OPs require PHY addr. Thus need to do
57 * vmalloc_to_phy.
58 * -Also added optimisation there, that for range > PAGE SIZE we flush the
59 * entire cache in one shot rather than line by line. For e.g. a module
60 * with Code sz 600k, old code flushed 600k worth of cache (line-by-line),
61 * while cache is only 16 or 32k.
62 */
63
64#include <linux/module.h>
65#include <linux/mm.h>
66#include <linux/sched.h>
67#include <linux/cache.h>
68#include <linux/mmu_context.h>
69#include <linux/syscalls.h>
70#include <linux/uaccess.h>
71#include <linux/pagemap.h>
72#include <asm/cacheflush.h>
73#include <asm/cachectl.h>
74#include <asm/setup.h>
75
76/* Instruction cache related Auxiliary registers */
77#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
78#define ARC_REG_IC_IVIC 0x10
79#define ARC_REG_IC_CTRL 0x11
80#define ARC_REG_IC_IVIL 0x19
81#if (CONFIG_ARC_MMU_VER > 2)
82#define ARC_REG_IC_PTAG 0x1E
83#endif
84
85/* Bit val in IC_CTRL */
86#define IC_CTRL_CACHE_DISABLE 0x1
87
88/* Data cache related Auxiliary registers */
89#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
90#define ARC_REG_DC_IVDC 0x47
91#define ARC_REG_DC_CTRL 0x48
92#define ARC_REG_DC_IVDL 0x4A
93#define ARC_REG_DC_FLSH 0x4B
94#define ARC_REG_DC_FLDL 0x4C
95#if (CONFIG_ARC_MMU_VER > 2)
96#define ARC_REG_DC_PTAG 0x5C
97#endif
98
99/* Bit val in DC_CTRL */
100#define DC_CTRL_INV_MODE_FLUSH 0x40
101#define DC_CTRL_FLUSH_STATUS 0x100
102
103char *arc_cache_mumbojumbo(int c, char *buf, int len)
104{
105 int n = 0;
106
107#define PR_CACHE(p, enb, str) \
108{ \
109 if (!(p)->ver) \
110 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
111 else \
112 n += scnprintf(buf + n, len - n, \
113 str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \
114 TO_KB((p)->sz), (p)->assoc, (p)->line_len, \
115 enb ? "" : "DISABLED (kernel-build)"); \
116}
117
118 PR_CACHE(&cpuinfo_arc700[c].icache, IS_ENABLED(CONFIG_ARC_HAS_ICACHE),
119 "I-Cache");
120 PR_CACHE(&cpuinfo_arc700[c].dcache, IS_ENABLED(CONFIG_ARC_HAS_DCACHE),
121 "D-Cache");
122
123 return buf;
124}
125
126/*
127 * Read the Cache Build Confuration Registers, Decode them and save into
128 * the cpuinfo structure for later use.
129 * No Validation done here, simply read/convert the BCRs
130 */
131void read_decode_cache_bcr(void)
132{
133 struct cpuinfo_arc_cache *p_ic, *p_dc;
134 unsigned int cpu = smp_processor_id();
135 struct bcr_cache {
136#ifdef CONFIG_CPU_BIG_ENDIAN
137 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
138#else
139 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
140#endif
141 } ibcr, dbcr;
142
143 p_ic = &cpuinfo_arc700[cpu].icache;
144 READ_BCR(ARC_REG_IC_BCR, ibcr);
145
146 BUG_ON(ibcr.config != 3);
147 p_ic->assoc = 2; /* Fixed to 2w set assoc */
148 p_ic->line_len = 8 << ibcr.line_len;
149 p_ic->sz = 0x200 << ibcr.sz;
150 p_ic->ver = ibcr.ver;
151
152 p_dc = &cpuinfo_arc700[cpu].dcache;
153 READ_BCR(ARC_REG_DC_BCR, dbcr);
154
155 BUG_ON(dbcr.config != 2);
156 p_dc->assoc = 4; /* Fixed to 4w set assoc */
157 p_dc->line_len = 16 << dbcr.line_len;
158 p_dc->sz = 0x200 << dbcr.sz;
159 p_dc->ver = dbcr.ver;
160}
161
162/*
163 * 1. Validate the Cache Geomtery (compile time config matches hardware)
164 * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn)
165 * (aliasing D-cache configurations are not supported YET)
166 * 3. Enable the Caches, setup default flush mode for D-Cache
167 * 3. Calculate the SHMLBA used by user space
168 */
169void arc_cache_init(void)
170{
171 unsigned int cpu = smp_processor_id();
172 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
173 struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
174 unsigned int dcache_does_alias, temp;
175 char str[256];
176
177 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
178
179 if (!ic->ver)
180 goto chk_dc;
181
182#ifdef CONFIG_ARC_HAS_ICACHE
183 /* 1. Confirm some of I-cache params which Linux assumes */
184 if (ic->line_len != L1_CACHE_BYTES)
185 panic("Cache H/W doesn't match kernel Config");
186
187 if (ic->ver != CONFIG_ARC_MMU_VER)
188 panic("Cache ver doesn't match MMU ver\n");
189#endif
190
191 /* Enable/disable I-Cache */
192 temp = read_aux_reg(ARC_REG_IC_CTRL);
193
194#ifdef CONFIG_ARC_HAS_ICACHE
195 temp &= ~IC_CTRL_CACHE_DISABLE;
196#else
197 temp |= IC_CTRL_CACHE_DISABLE;
198#endif
199
200 write_aux_reg(ARC_REG_IC_CTRL, temp);
201
202chk_dc:
203 if (!dc->ver)
204 return;
205
206#ifdef CONFIG_ARC_HAS_DCACHE
207 if (dc->line_len != L1_CACHE_BYTES)
208 panic("Cache H/W doesn't match kernel Config");
209
210 /* check for D-Cache aliasing */
211 dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
212
213 if (dcache_does_alias && !cache_is_vipt_aliasing())
214 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
215 else if (!dcache_does_alias && cache_is_vipt_aliasing())
216 panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
217#endif
218
219 /* Set the default Invalidate Mode to "simpy discard dirty lines"
220 * as this is more frequent then flush before invalidate
221 * Ofcourse we toggle this default behviour when desired
222 */
223 temp = read_aux_reg(ARC_REG_DC_CTRL);
224 temp &= ~DC_CTRL_INV_MODE_FLUSH;
225
226#ifdef CONFIG_ARC_HAS_DCACHE
227 /* Enable D-Cache: Clear Bit 0 */
228 write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE);
229#else
230 /* Flush D cache */
231 write_aux_reg(ARC_REG_DC_FLSH, 0x1);
232 /* Disable D cache */
233 write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE);
234#endif
235
236 return;
237}
238
239#define OP_INV 0x1
240#define OP_FLUSH 0x2
241#define OP_FLUSH_N_INV 0x3
242#define OP_INV_IC 0x4
243
244/*
245 * Common Helper for Line Operations on {I,D}-Cache
246 */
247static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr,
248 unsigned long sz, const int cacheop)
249{
250 unsigned int aux_cmd, aux_tag;
251 int num_lines;
252 const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE;
253
254 if (cacheop == OP_INV_IC) {
255 aux_cmd = ARC_REG_IC_IVIL;
256 aux_tag = ARC_REG_IC_PTAG;
257 }
258 else {
259 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
260 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
261 aux_tag = ARC_REG_DC_PTAG;
262 }
263
264 /* Ensure we properly floor/ceil the non-line aligned/sized requests
265 * and have @paddr - aligned to cache line and integral @num_lines.
266 * This however can be avoided for page sized since:
267 * -@paddr will be cache-line aligned already (being page aligned)
268 * -@sz will be integral multiple of line size (being page sized).
269 */
270 if (!full_page_op) {
271 sz += paddr & ~CACHE_LINE_MASK;
272 paddr &= CACHE_LINE_MASK;
273 vaddr &= CACHE_LINE_MASK;
274 }
275
276 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
277
278#if (CONFIG_ARC_MMU_VER <= 2)
279 /* MMUv2 and before: paddr contains stuffed vaddrs bits */
280 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
281#else
282 /* if V-P const for loop, PTAG can be written once outside loop */
283 if (full_page_op)
284 write_aux_reg(aux_tag, paddr);
285#endif
286
287 while (num_lines-- > 0) {
288#if (CONFIG_ARC_MMU_VER > 2)
289 /* MMUv3, cache ops require paddr seperately */
290 if (!full_page_op) {
291 write_aux_reg(aux_tag, paddr);
292 paddr += L1_CACHE_BYTES;
293 }
294
295 write_aux_reg(aux_cmd, vaddr);
296 vaddr += L1_CACHE_BYTES;
297#else
298 write_aux_reg(aux_cmd, paddr);
299 paddr += L1_CACHE_BYTES;
300#endif
301 }
302}
303
304#ifdef CONFIG_ARC_HAS_DCACHE
305
306/***************************************************************
307 * Machine specific helpers for Entire D-Cache or Per Line ops
308 */
309
310static inline void wait_for_flush(void)
311{
312 while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
313 ;
314}
315
316/*
317 * Operation on Entire D-Cache
318 * @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
319 * Note that constant propagation ensures all the checks are gone
320 * in generated code
321 */
322static inline void __dc_entire_op(const int cacheop)
323{
324 unsigned int tmp = tmp;
325 int aux;
326
327 if (cacheop == OP_FLUSH_N_INV) {
328 /* Dcache provides 2 cmd: FLUSH or INV
329 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
330 * flush-n-inv is achieved by INV cmd but with IM=1
331 * Default INV sub-mode is DISCARD, which needs to be toggled
332 */
333 tmp = read_aux_reg(ARC_REG_DC_CTRL);
334 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
335 }
336
337 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
338 aux = ARC_REG_DC_IVDC;
339 else
340 aux = ARC_REG_DC_FLSH;
341
342 write_aux_reg(aux, 0x1);
343
344 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
345 wait_for_flush();
346
347 /* Switch back the DISCARD ONLY Invalidate mode */
348 if (cacheop == OP_FLUSH_N_INV)
349 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
350}
351
352/* For kernel mappings cache operation: index is same as paddr */
353#define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
354
355/*
356 * D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback)
357 */
358static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr,
359 unsigned long sz, const int cacheop)
360{
361 unsigned long flags, tmp = tmp;
362
363 local_irq_save(flags);
364
365 if (cacheop == OP_FLUSH_N_INV) {
366 /*
367 * Dcache provides 2 cmd: FLUSH or INV
368 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
369 * flush-n-inv is achieved by INV cmd but with IM=1
370 * Default INV sub-mode is DISCARD, which needs to be toggled
371 */
372 tmp = read_aux_reg(ARC_REG_DC_CTRL);
373 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
374 }
375
376 __cache_line_loop(paddr, vaddr, sz, cacheop);
377
378 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
379 wait_for_flush();
380
381 /* Switch back the DISCARD ONLY Invalidate mode */
382 if (cacheop == OP_FLUSH_N_INV)
383 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
384
385 local_irq_restore(flags);
386}
387
388#else
389
390#define __dc_entire_op(cacheop)
391#define __dc_line_op(paddr, vaddr, sz, cacheop)
392#define __dc_line_op_k(paddr, sz, cacheop)
393
394#endif /* CONFIG_ARC_HAS_DCACHE */
395
396
397#ifdef CONFIG_ARC_HAS_ICACHE
398
399/*
400 * I-Cache Aliasing in ARC700 VIPT caches
401 *
402 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
403 * The orig Cache Management Module "CDU" only required paddr to invalidate a
404 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
405 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
406 * the exact same line.
407 *
408 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
409 * paddr alone could not be used to correctly index the cache.
410 *
411 * ------------------
412 * MMU v1/v2 (Fixed Page Size 8k)
413 * ------------------
414 * The solution was to provide CDU with these additonal vaddr bits. These
415 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
416 * standard page size of 8k.
417 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
418 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
419 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
420 * represent the offset within cache-line. The adv of using this "clumsy"
421 * interface for additional info was no new reg was needed in CDU programming
422 * model.
423 *
424 * 17:13 represented the max num of bits passable, actual bits needed were
425 * fewer, based on the num-of-aliases possible.
426 * -for 2 alias possibility, only bit 13 needed (32K cache)
427 * -for 4 alias possibility, bits 14:13 needed (64K cache)
428 *
429 * ------------------
430 * MMU v3
431 * ------------------
432 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
433 * only support 8k (default), 16k and 4k.
434 * However from hardware perspective, smaller page sizes aggrevate aliasing
435 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
436 * the existing scheme of piggybacking won't work for certain configurations.
437 * Two new registers IC_PTAG and DC_PTAG inttoduced.
438 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
439 */
440
441/***********************************************************
442 * Machine specific helper for per line I-Cache invalidate.
443 */
444static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr,
445 unsigned long sz)
446{
447 unsigned long flags;
448
449 local_irq_save(flags);
450 __cache_line_loop(paddr, vaddr, sz, OP_INV_IC);
451 local_irq_restore(flags);
452}
453
454static inline void __ic_entire_inv(void)
455{
456 write_aux_reg(ARC_REG_IC_IVIC, 1);
457 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */
458}
459
460#else
461
462#define __ic_entire_inv()
463#define __ic_line_inv_vaddr(pstart, vstart, sz)
464
465#endif /* CONFIG_ARC_HAS_ICACHE */
466
467
468/***********************************************************
469 * Exported APIs
470 */
471
472/*
473 * Handle cache congruency of kernel and userspace mappings of page when kernel
474 * writes-to/reads-from
475 *
476 * The idea is to defer flushing of kernel mapping after a WRITE, possible if:
477 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
478 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
479 * -In SMP, if hardware caches are coherent
480 *
481 * There's a corollary case, where kernel READs from a userspace mapped page.
482 * If the U-mapping is not congruent to to K-mapping, former needs flushing.
483 */
484void flush_dcache_page(struct page *page)
485{
486 struct address_space *mapping;
487
488 if (!cache_is_vipt_aliasing()) {
489 clear_bit(PG_dc_clean, &page->flags);
490 return;
491 }
492
493 /* don't handle anon pages here */
494 mapping = page_mapping(page);
495 if (!mapping)
496 return;
497
498 /*
499 * pagecache page, file not yet mapped to userspace
500 * Make a note that K-mapping is dirty
501 */
502 if (!mapping_mapped(mapping)) {
503 clear_bit(PG_dc_clean, &page->flags);
504 } else if (page_mapped(page)) {
505
506 /* kernel reading from page with U-mapping */
507 void *paddr = page_address(page);
508 unsigned long vaddr = page->index << PAGE_CACHE_SHIFT;
509
510 if (addr_not_cache_congruent(paddr, vaddr))
511 __flush_dcache_page(paddr, vaddr);
512 }
513}
514EXPORT_SYMBOL(flush_dcache_page);
515
516
517void dma_cache_wback_inv(unsigned long start, unsigned long sz)
518{
519 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
520}
521EXPORT_SYMBOL(dma_cache_wback_inv);
522
523void dma_cache_inv(unsigned long start, unsigned long sz)
524{
525 __dc_line_op_k(start, sz, OP_INV);
526}
527EXPORT_SYMBOL(dma_cache_inv);
528
529void dma_cache_wback(unsigned long start, unsigned long sz)
530{
531 __dc_line_op_k(start, sz, OP_FLUSH);
532}
533EXPORT_SYMBOL(dma_cache_wback);
534
535/*
536 * This is API for making I/D Caches consistent when modifying
537 * kernel code (loadable modules, kprobes, kgdb...)
538 * This is called on insmod, with kernel virtual address for CODE of
539 * the module. ARC cache maintenance ops require PHY address thus we
540 * need to convert vmalloc addr to PHY addr
541 */
542void flush_icache_range(unsigned long kstart, unsigned long kend)
543{
544 unsigned int tot_sz, off, sz;
545 unsigned long phy, pfn;
546
547 /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */
548
549 /* This is not the right API for user virtual address */
550 if (kstart < TASK_SIZE) {
551 BUG_ON("Flush icache range for user virtual addr space");
552 return;
553 }
554
555 /* Shortcut for bigger flush ranges.
556 * Here we don't care if this was kernel virtual or phy addr
557 */
558 tot_sz = kend - kstart;
559 if (tot_sz > PAGE_SIZE) {
560 flush_cache_all();
561 return;
562 }
563
564 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
565 if (likely(kstart > PAGE_OFFSET)) {
566 /*
567 * The 2nd arg despite being paddr will be used to index icache
568 * This is OK since no alternate virtual mappings will exist
569 * given the callers for this case: kprobe/kgdb in built-in
570 * kernel code only.
571 */
572 __sync_icache_dcache(kstart, kstart, kend - kstart);
573 return;
574 }
575
576 /*
577 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
578 * (1) ARC Cache Maintenance ops only take Phy addr, hence special
579 * handling of kernel vaddr.
580 *
581 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
582 * it still needs to handle a 2 page scenario, where the range
583 * straddles across 2 virtual pages and hence need for loop
584 */
585 while (tot_sz > 0) {
586 off = kstart % PAGE_SIZE;
587 pfn = vmalloc_to_pfn((void *)kstart);
588 phy = (pfn << PAGE_SHIFT) + off;
589 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
590 __sync_icache_dcache(phy, kstart, sz);
591 kstart += sz;
592 tot_sz -= sz;
593 }
594}
595
596/*
597 * General purpose helper to make I and D cache lines consistent.
598 * @paddr is phy addr of region
599 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
600 * However in one instance, when called by kprobe (for a breakpt in
601 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
602 * use a paddr to index the cache (despite VIPT). This is fine since since a
603 * builtin kernel page will not have any virtual mappings.
604 * kprobe on loadable module will be kernel vaddr.
605 */
606void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
607{
608 unsigned long flags;
609
610 local_irq_save(flags);
611 __ic_line_inv_vaddr(paddr, vaddr, len);
612 __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV);
613 local_irq_restore(flags);
614}
615
616/* wrapper to compile time eliminate alignment checks in flush loop */
617void __inv_icache_page(unsigned long paddr, unsigned long vaddr)
618{
619 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
620}
621
622/*
623 * wrapper to clearout kernel or userspace mappings of a page
624 * For kernel mappings @vaddr == @paddr
625 */
626void ___flush_dcache_page(unsigned long paddr, unsigned long vaddr)
627{
628 __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
629}
630
631noinline void flush_cache_all(void)
632{
633 unsigned long flags;
634
635 local_irq_save(flags);
636
637 __ic_entire_inv();
638 __dc_entire_op(OP_FLUSH_N_INV);
639
640 local_irq_restore(flags);
641
642}
643
644#ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
645
646void flush_cache_mm(struct mm_struct *mm)
647{
648 flush_cache_all();
649}
650
651void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
652 unsigned long pfn)
653{
654 unsigned int paddr = pfn << PAGE_SHIFT;
655
656 u_vaddr &= PAGE_MASK;
657
658 ___flush_dcache_page(paddr, u_vaddr);
659
660 if (vma->vm_flags & VM_EXEC)
661 __inv_icache_page(paddr, u_vaddr);
662}
663
664void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
665 unsigned long end)
666{
667 flush_cache_all();
668}
669
670void flush_anon_page(struct vm_area_struct *vma, struct page *page,
671 unsigned long u_vaddr)
672{
673 /* TBD: do we really need to clear the kernel mapping */
674 __flush_dcache_page(page_address(page), u_vaddr);
675 __flush_dcache_page(page_address(page), page_address(page));
676
677}
678
679#endif
680
681void copy_user_highpage(struct page *to, struct page *from,
682 unsigned long u_vaddr, struct vm_area_struct *vma)
683{
684 void *kfrom = page_address(from);
685 void *kto = page_address(to);
686 int clean_src_k_mappings = 0;
687
688 /*
689 * If SRC page was already mapped in userspace AND it's U-mapping is
690 * not congruent with K-mapping, sync former to physical page so that
691 * K-mapping in memcpy below, sees the right data
692 *
693 * Note that while @u_vaddr refers to DST page's userspace vaddr, it is
694 * equally valid for SRC page as well
695 */
696 if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) {
697 __flush_dcache_page(kfrom, u_vaddr);
698 clean_src_k_mappings = 1;
699 }
700
701 copy_page(kto, kfrom);
702
703 /*
704 * Mark DST page K-mapping as dirty for a later finalization by
705 * update_mmu_cache(). Although the finalization could have been done
706 * here as well (given that both vaddr/paddr are available).
707 * But update_mmu_cache() already has code to do that for other
708 * non copied user pages (e.g. read faults which wire in pagecache page
709 * directly).
710 */
711 clear_bit(PG_dc_clean, &to->flags);
712
713 /*
714 * if SRC was already usermapped and non-congruent to kernel mapping
715 * sync the kernel mapping back to physical page
716 */
717 if (clean_src_k_mappings) {
718 __flush_dcache_page(kfrom, kfrom);
719 set_bit(PG_dc_clean, &from->flags);
720 } else {
721 clear_bit(PG_dc_clean, &from->flags);
722 }
723}
724
725void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
726{
727 clear_page(to);
728 clear_bit(PG_dc_clean, &page->flags);
729}
730
731
732/**********************************************************************
733 * Explicit Cache flush request from user space via syscall
734 * Needed for JITs which generate code on the fly
735 */
736SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
737{
738 /* TBD: optimize this */
739 flush_cache_all();
740 return 0;
741}