1/*
   2 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
   3 *
   4 * Copyright (C) 2004-2013 Synopsys, Inc.
   5 *
   6 * Redistribution and use in source and binary forms, with or without
   7 * modification, are permitted provided that the following conditions
   8 * are met:
   9 * 1. Redistributions of source code must retain the above copyright
  10 *    notice, this list of conditions, and the following disclaimer,
  11 *    without modification.
  12 * 2. Redistributions in binary form must reproduce the above copyright
  13 *    notice, this list of conditions and the following disclaimer in the
  14 *    documentation and/or other materials provided with the distribution.
  15 * 3. The names of the above-listed copyright holders may not be used
  16 *    to endorse or promote products derived from this software without
  17 *    specific prior written permission.
  18 *
  19 * ALTERNATIVELY, this software may be distributed under the terms of the
  20 * GNU General Public License ("GPL") as published by the Free Software
  21 * Foundation; either version 2 of the License, or (at your option) any
  22 * later version.
  23 *
  24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 */
  36
  37/*
  38 * This file contains the interrupt handlers for Host mode
  39 */
  40#include <linux/kernel.h>
  41#include <linux/module.h>
  42#include <linux/spinlock.h>
  43#include <linux/interrupt.h>
  44#include <linux/dma-mapping.h>
  45#include <linux/io.h>
  46#include <linux/slab.h>
  47#include <linux/usb.h>
  48
  49#include <linux/usb/hcd.h>
  50#include <linux/usb/ch11.h>
  51
  52#include "core.h"
  53#include "hcd.h"
  54
  55/* This function is for debug only */
  56static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
  57{
 
  58	u16 curr_frame_number = hsotg->frame_number;
  59	u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
  60
  61	if (expected != curr_frame_number)
  62		dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
  63			expected, curr_frame_number);
  64
  65#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
  66	if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
  67		if (expected != curr_frame_number) {
 
  68			hsotg->frame_num_array[hsotg->frame_num_idx] =
  69					curr_frame_number;
  70			hsotg->last_frame_num_array[hsotg->frame_num_idx] =
  71					hsotg->last_frame_num;
  72			hsotg->frame_num_idx++;
  73		}
  74	} else if (!hsotg->dumped_frame_num_array) {
  75		int i;
  76
  77		dev_info(hsotg->dev, "Frame     Last Frame\n");
  78		dev_info(hsotg->dev, "-----     ----------\n");
  79		for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
  80			dev_info(hsotg->dev, "0x%04x    0x%04x\n",
  81				 hsotg->frame_num_array[i],
  82				 hsotg->last_frame_num_array[i]);
  83		}
  84		hsotg->dumped_frame_num_array = 1;
  85	}
  86#endif
  87	hsotg->last_frame_num = curr_frame_number;
 
  88}
  89
  90static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
  91				    struct dwc2_host_chan *chan,
  92				    struct dwc2_qtd *qtd)
  93{
  94	struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
  95	struct urb *usb_urb;
  96
  97	if (!chan->qh)
  98		return;
  99
 100	if (chan->qh->dev_speed == USB_SPEED_HIGH)
 101		return;
 102
 103	if (!qtd->urb)
 104		return;
 105
 106	usb_urb = qtd->urb->priv;
 107	if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
 108		return;
 109
 110	/*
 111	 * The root hub doesn't really have a TT, but Linux thinks it
 112	 * does because how could you have a "high speed hub" that
 113	 * directly talks directly to low speed devices without a TT?
 114	 * It's all lies.  Lies, I tell you.
 115	 */
 116	if (usb_urb->dev->tt->hub == root_hub)
 117		return;
 118
 119	if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
 120		chan->qh->tt_buffer_dirty = 1;
 121		if (usb_hub_clear_tt_buffer(usb_urb))
 122			/* Clear failed; let's hope things work anyway */
 123			chan->qh->tt_buffer_dirty = 0;
 124	}
 125}
 126
 127/*
 128 * Handles the start-of-frame interrupt in host mode. Non-periodic
 129 * transactions may be queued to the DWC_otg controller for the current
 130 * (micro)frame. Periodic transactions may be queued to the controller
 131 * for the next (micro)frame.
 132 */
 133static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
 134{
 135	struct list_head *qh_entry;
 136	struct dwc2_qh *qh;
 137	enum dwc2_transaction_type tr_type;
 138
 139	/* Clear interrupt */
 140	dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
 141
 142#ifdef DEBUG_SOF
 143	dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
 144#endif
 145
 146	hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
 147
 148	dwc2_track_missed_sofs(hsotg);
 149
 150	/* Determine whether any periodic QHs should be executed */
 151	qh_entry = hsotg->periodic_sched_inactive.next;
 152	while (qh_entry != &hsotg->periodic_sched_inactive) {
 153		qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
 154		qh_entry = qh_entry->next;
 155		if (dwc2_frame_num_le(qh->next_active_frame,
 156				      hsotg->frame_number)) {
 157			dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
 158				      qh, hsotg->frame_number,
 159				      qh->next_active_frame);
 160
 161			/*
 162			 * Move QH to the ready list to be executed next
 163			 * (micro)frame
 164			 */
 165			list_move_tail(&qh->qh_list_entry,
 166				  &hsotg->periodic_sched_ready);
 167		}
 168	}
 169	tr_type = dwc2_hcd_select_transactions(hsotg);
 170	if (tr_type != DWC2_TRANSACTION_NONE)
 171		dwc2_hcd_queue_transactions(hsotg, tr_type);
 
 
 
 172}
 173
 174/*
 175 * Handles the Rx FIFO Level Interrupt, which indicates that there is
 176 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
 177 * memory if the DWC_otg controller is operating in Slave mode.
 178 */
 179static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
 180{
 181	u32 grxsts, chnum, bcnt, dpid, pktsts;
 182	struct dwc2_host_chan *chan;
 183
 184	if (dbg_perio())
 185		dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
 186
 187	grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
 188	chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
 189	chan = hsotg->hc_ptr_array[chnum];
 190	if (!chan) {
 191		dev_err(hsotg->dev, "Unable to get corresponding channel\n");
 192		return;
 193	}
 194
 195	bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
 196	dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
 197	pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
 198
 199	/* Packet Status */
 200	if (dbg_perio()) {
 201		dev_vdbg(hsotg->dev, "    Ch num = %d\n", chnum);
 202		dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);
 203		dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,
 204			 chan->data_pid_start);
 205		dev_vdbg(hsotg->dev, "    PStatus = %d\n", pktsts);
 206	}
 207
 208	switch (pktsts) {
 209	case GRXSTS_PKTSTS_HCHIN:
 210		/* Read the data into the host buffer */
 211		if (bcnt > 0) {
 212			dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
 213
 214			/* Update the HC fields for the next packet received */
 215			chan->xfer_count += bcnt;
 216			chan->xfer_buf += bcnt;
 217		}
 218		break;
 219	case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
 220	case GRXSTS_PKTSTS_DATATOGGLEERR:
 221	case GRXSTS_PKTSTS_HCHHALTED:
 222		/* Handled in interrupt, just ignore data */
 223		break;
 224	default:
 225		dev_err(hsotg->dev,
 226			"RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
 227		break;
 228	}
 229}
 230
 231/*
 232 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 233 * data packets may be written to the FIFO for OUT transfers. More requests
 234 * may be written to the non-periodic request queue for IN transfers. This
 235 * interrupt is enabled only in Slave mode.
 236 */
 237static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 238{
 239	dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 240	dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
 241}
 242
 243/*
 244 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 245 * packets may be written to the FIFO for OUT transfers. More requests may be
 246 * written to the periodic request queue for IN transfers. This interrupt is
 247 * enabled only in Slave mode.
 248 */
 249static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 250{
 251	if (dbg_perio())
 252		dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
 253	dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
 254}
 255
 256static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
 257			      u32 *hprt0_modify)
 258{
 259	struct dwc2_core_params *params = &hsotg->params;
 260	int do_reset = 0;
 261	u32 usbcfg;
 262	u32 prtspd;
 263	u32 hcfg;
 264	u32 fslspclksel;
 265	u32 hfir;
 266
 267	dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 268
 269	/* Every time when port enables calculate HFIR.FrInterval */
 270	hfir = dwc2_readl(hsotg->regs + HFIR);
 271	hfir &= ~HFIR_FRINT_MASK;
 272	hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
 273		HFIR_FRINT_MASK;
 274	dwc2_writel(hfir, hsotg->regs + HFIR);
 275
 276	/* Check if we need to adjust the PHY clock speed for low power */
 277	if (!params->host_support_fs_ls_low_power) {
 278		/* Port has been enabled, set the reset change flag */
 279		hsotg->flags.b.port_reset_change = 1;
 280		return;
 281	}
 282
 283	usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 284	prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 285
 286	if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
 287		/* Low power */
 288		if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
 289			/* Set PHY low power clock select for FS/LS devices */
 290			usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
 291			dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 292			do_reset = 1;
 293		}
 294
 295		hcfg = dwc2_readl(hsotg->regs + HCFG);
 296		fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
 297			      HCFG_FSLSPCLKSEL_SHIFT;
 298
 299		if (prtspd == HPRT0_SPD_LOW_SPEED &&
 300		    params->host_ls_low_power_phy_clk ==
 301		    DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 302			/* 6 MHZ */
 303			dev_vdbg(hsotg->dev,
 304				 "FS_PHY programming HCFG to 6 MHz\n");
 305			if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
 306				fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
 307				hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 308				hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 309				dwc2_writel(hcfg, hsotg->regs + HCFG);
 310				do_reset = 1;
 311			}
 312		} else {
 313			/* 48 MHZ */
 314			dev_vdbg(hsotg->dev,
 315				 "FS_PHY programming HCFG to 48 MHz\n");
 316			if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
 317				fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
 318				hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 319				hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 320				dwc2_writel(hcfg, hsotg->regs + HCFG);
 321				do_reset = 1;
 322			}
 323		}
 324	} else {
 325		/* Not low power */
 326		if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
 327			usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
 328			dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 329			do_reset = 1;
 330		}
 331	}
 332
 333	if (do_reset) {
 334		*hprt0_modify |= HPRT0_RST;
 335		dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0);
 336		queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
 337				   msecs_to_jiffies(60));
 338	} else {
 339		/* Port has been enabled, set the reset change flag */
 340		hsotg->flags.b.port_reset_change = 1;
 341	}
 342}
 343
 344/*
 345 * There are multiple conditions that can cause a port interrupt. This function
 346 * determines which interrupt conditions have occurred and handles them
 347 * appropriately.
 348 */
 349static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 350{
 351	u32 hprt0;
 352	u32 hprt0_modify;
 353
 354	dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
 355
 356	hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 357	hprt0_modify = hprt0;
 358
 359	/*
 360	 * Clear appropriate bits in HPRT0 to clear the interrupt bit in
 361	 * GINTSTS
 362	 */
 363	hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
 364			  HPRT0_OVRCURRCHG);
 365
 366	/*
 367	 * Port Connect Detected
 368	 * Set flag and clear if detected
 369	 */
 370	if (hprt0 & HPRT0_CONNDET) {
 371		dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0);
 372
 373		dev_vdbg(hsotg->dev,
 374			 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
 375			 hprt0);
 376		dwc2_hcd_connect(hsotg);
 
 
 377
 378		/*
 379		 * The Hub driver asserts a reset when it sees port connect
 380		 * status change flag
 381		 */
 382	}
 383
 384	/*
 385	 * Port Enable Changed
 386	 * Clear if detected - Set internal flag if disabled
 387	 */
 388	if (hprt0 & HPRT0_ENACHG) {
 389		dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0);
 390		dev_vdbg(hsotg->dev,
 391			 "  --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
 392			 hprt0, !!(hprt0 & HPRT0_ENA));
 393		if (hprt0 & HPRT0_ENA) {
 394			hsotg->new_connection = true;
 395			dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
 396		} else {
 397			hsotg->flags.b.port_enable_change = 1;
 398			if (hsotg->params.dma_desc_fs_enable) {
 399				u32 hcfg;
 400
 401				hsotg->params.dma_desc_enable = 0;
 402				hsotg->new_connection = false;
 403				hcfg = dwc2_readl(hsotg->regs + HCFG);
 404				hcfg &= ~HCFG_DESCDMA;
 405				dwc2_writel(hcfg, hsotg->regs + HCFG);
 406			}
 407		}
 408	}
 409
 410	/* Overcurrent Change Interrupt */
 411	if (hprt0 & HPRT0_OVRCURRCHG) {
 412		dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG,
 413			    hsotg->regs + HPRT0);
 414		dev_vdbg(hsotg->dev,
 415			 "  --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
 416			 hprt0);
 417		hsotg->flags.b.port_over_current_change = 1;
 
 418	}
 
 
 
 419}
 420
 421/*
 422 * Gets the actual length of a transfer after the transfer halts. halt_status
 423 * holds the reason for the halt.
 424 *
 425 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
 426 * is set to 1 upon return if less than the requested number of bytes were
 427 * transferred. short_read may also be NULL on entry, in which case it remains
 428 * unchanged.
 429 */
 430static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
 431				       struct dwc2_host_chan *chan, int chnum,
 432				       struct dwc2_qtd *qtd,
 433				       enum dwc2_halt_status halt_status,
 434				       int *short_read)
 435{
 436	u32 hctsiz, count, length;
 437
 438	hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 439
 440	if (halt_status == DWC2_HC_XFER_COMPLETE) {
 441		if (chan->ep_is_in) {
 442			count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
 443				TSIZ_XFERSIZE_SHIFT;
 444			length = chan->xfer_len - count;
 445			if (short_read != NULL)
 446				*short_read = (count != 0);
 447		} else if (chan->qh->do_split) {
 448			length = qtd->ssplit_out_xfer_count;
 449		} else {
 450			length = chan->xfer_len;
 451		}
 452	} else {
 453		/*
 454		 * Must use the hctsiz.pktcnt field to determine how much data
 455		 * has been transferred. This field reflects the number of
 456		 * packets that have been transferred via the USB. This is
 457		 * always an integral number of packets if the transfer was
 458		 * halted before its normal completion. (Can't use the
 459		 * hctsiz.xfersize field because that reflects the number of
 460		 * bytes transferred via the AHB, not the USB).
 461		 */
 462		count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
 463		length = (chan->start_pkt_count - count) * chan->max_packet;
 464	}
 465
 466	return length;
 467}
 468
 469/**
 470 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
 471 * Complete interrupt on the host channel. Updates the actual_length field
 472 * of the URB based on the number of bytes transferred via the host channel.
 473 * Sets the URB status if the data transfer is finished.
 474 *
 475 * Return: 1 if the data transfer specified by the URB is completely finished,
 476 * 0 otherwise
 477 */
 478static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
 479				 struct dwc2_host_chan *chan, int chnum,
 480				 struct dwc2_hcd_urb *urb,
 481				 struct dwc2_qtd *qtd)
 482{
 483	u32 hctsiz;
 484	int xfer_done = 0;
 485	int short_read = 0;
 486	int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 487						      DWC2_HC_XFER_COMPLETE,
 488						      &short_read);
 489
 490	if (urb->actual_length + xfer_length > urb->length) {
 491		dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
 492		xfer_length = urb->length - urb->actual_length;
 493	}
 494
 
 
 
 
 
 
 
 
 
 
 
 495	dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
 496		 urb->actual_length, xfer_length);
 497	urb->actual_length += xfer_length;
 498
 499	if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
 500	    (urb->flags & URB_SEND_ZERO_PACKET) &&
 501	    urb->actual_length >= urb->length &&
 502	    !(urb->length % chan->max_packet)) {
 503		xfer_done = 0;
 504	} else if (short_read || urb->actual_length >= urb->length) {
 505		xfer_done = 1;
 506		urb->status = 0;
 507	}
 508
 509	hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 510	dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
 511		 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
 512	dev_vdbg(hsotg->dev, "  chan->xfer_len %d\n", chan->xfer_len);
 513	dev_vdbg(hsotg->dev, "  hctsiz.xfersize %d\n",
 514		 (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
 515	dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n", urb->length);
 516	dev_vdbg(hsotg->dev, "  urb->actual_length %d\n", urb->actual_length);
 517	dev_vdbg(hsotg->dev, "  short_read %d, xfer_done %d\n", short_read,
 518		 xfer_done);
 519
 520	return xfer_done;
 521}
 522
 523/*
 524 * Save the starting data toggle for the next transfer. The data toggle is
 525 * saved in the QH for non-control transfers and it's saved in the QTD for
 526 * control transfers.
 527 */
 528void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
 529			       struct dwc2_host_chan *chan, int chnum,
 530			       struct dwc2_qtd *qtd)
 531{
 532	u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 533	u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
 534
 535	if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
 536		if (WARN(!chan || !chan->qh,
 537			 "chan->qh must be specified for non-control eps\n"))
 538			return;
 539
 540		if (pid == TSIZ_SC_MC_PID_DATA0)
 541			chan->qh->data_toggle = DWC2_HC_PID_DATA0;
 542		else
 543			chan->qh->data_toggle = DWC2_HC_PID_DATA1;
 544	} else {
 545		if (WARN(!qtd,
 546			 "qtd must be specified for control eps\n"))
 547			return;
 548
 549		if (pid == TSIZ_SC_MC_PID_DATA0)
 550			qtd->data_toggle = DWC2_HC_PID_DATA0;
 551		else
 552			qtd->data_toggle = DWC2_HC_PID_DATA1;
 553	}
 554}
 555
 556/**
 557 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
 558 * the transfer is stopped for any reason. The fields of the current entry in
 559 * the frame descriptor array are set based on the transfer state and the input
 560 * halt_status. Completes the Isochronous URB if all the URB frames have been
 561 * completed.
 562 *
 563 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
 564 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
 565 */
 566static enum dwc2_halt_status dwc2_update_isoc_urb_state(
 567		struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 568		int chnum, struct dwc2_qtd *qtd,
 569		enum dwc2_halt_status halt_status)
 570{
 571	struct dwc2_hcd_iso_packet_desc *frame_desc;
 572	struct dwc2_hcd_urb *urb = qtd->urb;
 573
 574	if (!urb)
 575		return DWC2_HC_XFER_NO_HALT_STATUS;
 576
 577	frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 578
 579	switch (halt_status) {
 580	case DWC2_HC_XFER_COMPLETE:
 581		frame_desc->status = 0;
 582		frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 583					chan, chnum, qtd, halt_status, NULL);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 584		break;
 585	case DWC2_HC_XFER_FRAME_OVERRUN:
 586		urb->error_count++;
 587		if (chan->ep_is_in)
 588			frame_desc->status = -ENOSR;
 589		else
 590			frame_desc->status = -ECOMM;
 591		frame_desc->actual_length = 0;
 592		break;
 593	case DWC2_HC_XFER_BABBLE_ERR:
 594		urb->error_count++;
 595		frame_desc->status = -EOVERFLOW;
 596		/* Don't need to update actual_length in this case */
 597		break;
 598	case DWC2_HC_XFER_XACT_ERR:
 599		urb->error_count++;
 600		frame_desc->status = -EPROTO;
 601		frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 602					chan, chnum, qtd, halt_status, NULL);
 603
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 604		/* Skip whole frame */
 605		if (chan->qh->do_split &&
 606		    chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 607		    hsotg->params.host_dma > 0) {
 608			qtd->complete_split = 0;
 609			qtd->isoc_split_offset = 0;
 610		}
 611
 612		break;
 613	default:
 614		dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
 615			halt_status);
 616		break;
 617	}
 618
 619	if (++qtd->isoc_frame_index == urb->packet_count) {
 620		/*
 621		 * urb->status is not used for isoc transfers. The individual
 622		 * frame_desc statuses are used instead.
 623		 */
 624		dwc2_host_complete(hsotg, qtd, 0);
 625		halt_status = DWC2_HC_XFER_URB_COMPLETE;
 626	} else {
 627		halt_status = DWC2_HC_XFER_COMPLETE;
 628	}
 629
 630	return halt_status;
 631}
 632
 633/*
 634 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 635 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 636 * still linked to the QH, the QH is added to the end of the inactive
 637 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 638 * schedule if no more QTDs are linked to the QH.
 639 */
 640static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 641			       int free_qtd)
 642{
 643	int continue_split = 0;
 644	struct dwc2_qtd *qtd;
 645
 646	if (dbg_qh(qh))
 647		dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__,
 648			 hsotg, qh, free_qtd);
 649
 650	if (list_empty(&qh->qtd_list)) {
 651		dev_dbg(hsotg->dev, "## QTD list empty ##\n");
 652		goto no_qtd;
 653	}
 654
 655	qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 656
 657	if (qtd->complete_split)
 658		continue_split = 1;
 659	else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
 660		 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
 661		continue_split = 1;
 662
 663	if (free_qtd) {
 664		dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 665		continue_split = 0;
 666	}
 667
 668no_qtd:
 
 
 669	qh->channel = NULL;
 670	dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
 671}
 672
 673/**
 674 * dwc2_release_channel() - Releases a host channel for use by other transfers
 675 *
 676 * @hsotg:       The HCD state structure
 677 * @chan:        The host channel to release
 678 * @qtd:         The QTD associated with the host channel. This QTD may be
 679 *               freed if the transfer is complete or an error has occurred.
 680 * @halt_status: Reason the channel is being released. This status
 681 *               determines the actions taken by this function.
 682 *
 683 * Also attempts to select and queue more transactions since at least one host
 684 * channel is available.
 685 */
 686static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
 687				 struct dwc2_host_chan *chan,
 688				 struct dwc2_qtd *qtd,
 689				 enum dwc2_halt_status halt_status)
 690{
 691	enum dwc2_transaction_type tr_type;
 692	u32 haintmsk;
 693	int free_qtd = 0;
 694
 695	if (dbg_hc(chan))
 696		dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",
 697			 __func__, chan->hc_num, halt_status);
 698
 699	switch (halt_status) {
 700	case DWC2_HC_XFER_URB_COMPLETE:
 701		free_qtd = 1;
 702		break;
 703	case DWC2_HC_XFER_AHB_ERR:
 704	case DWC2_HC_XFER_STALL:
 705	case DWC2_HC_XFER_BABBLE_ERR:
 706		free_qtd = 1;
 707		break;
 708	case DWC2_HC_XFER_XACT_ERR:
 709		if (qtd && qtd->error_count >= 3) {
 710			dev_vdbg(hsotg->dev,
 711				 "  Complete URB with transaction error\n");
 712			free_qtd = 1;
 713			dwc2_host_complete(hsotg, qtd, -EPROTO);
 714		}
 715		break;
 716	case DWC2_HC_XFER_URB_DEQUEUE:
 717		/*
 718		 * The QTD has already been removed and the QH has been
 719		 * deactivated. Don't want to do anything except release the
 720		 * host channel and try to queue more transfers.
 721		 */
 722		goto cleanup;
 723	case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
 724		dev_vdbg(hsotg->dev, "  Complete URB with I/O error\n");
 725		free_qtd = 1;
 726		dwc2_host_complete(hsotg, qtd, -EIO);
 727		break;
 728	case DWC2_HC_XFER_NO_HALT_STATUS:
 729	default:
 730		break;
 731	}
 732
 733	dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
 734
 735cleanup:
 736	/*
 737	 * Release the host channel for use by other transfers. The cleanup
 738	 * function clears the channel interrupt enables and conditions, so
 739	 * there's no need to clear the Channel Halted interrupt separately.
 740	 */
 741	if (!list_empty(&chan->hc_list_entry))
 742		list_del(&chan->hc_list_entry);
 743	dwc2_hc_cleanup(hsotg, chan);
 744	list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 745
 746	if (hsotg->params.uframe_sched > 0) {
 747		hsotg->available_host_channels++;
 748	} else {
 749		switch (chan->ep_type) {
 750		case USB_ENDPOINT_XFER_CONTROL:
 751		case USB_ENDPOINT_XFER_BULK:
 752			hsotg->non_periodic_channels--;
 753			break;
 754		default:
 755			/*
 756			 * Don't release reservations for periodic channels
 757			 * here. That's done when a periodic transfer is
 758			 * descheduled (i.e. when the QH is removed from the
 759			 * periodic schedule).
 760			 */
 761			break;
 762		}
 763	}
 764
 765	haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
 766	haintmsk &= ~(1 << chan->hc_num);
 767	dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
 768
 769	/* Try to queue more transfers now that there's a free channel */
 770	tr_type = dwc2_hcd_select_transactions(hsotg);
 771	if (tr_type != DWC2_TRANSACTION_NONE)
 772		dwc2_hcd_queue_transactions(hsotg, tr_type);
 773}
 774
 775/*
 776 * Halts a host channel. If the channel cannot be halted immediately because
 777 * the request queue is full, this function ensures that the FIFO empty
 778 * interrupt for the appropriate queue is enabled so that the halt request can
 779 * be queued when there is space in the request queue.
 780 *
 781 * This function may also be called in DMA mode. In that case, the channel is
 782 * simply released since the core always halts the channel automatically in
 783 * DMA mode.
 784 */
 785static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
 786			      struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
 787			      enum dwc2_halt_status halt_status)
 788{
 789	if (dbg_hc(chan))
 790		dev_vdbg(hsotg->dev, "%s()\n", __func__);
 791
 792	if (hsotg->params.host_dma > 0) {
 793		if (dbg_hc(chan))
 794			dev_vdbg(hsotg->dev, "DMA enabled\n");
 795		dwc2_release_channel(hsotg, chan, qtd, halt_status);
 796		return;
 797	}
 798
 799	/* Slave mode processing */
 800	dwc2_hc_halt(hsotg, chan, halt_status);
 801
 802	if (chan->halt_on_queue) {
 803		u32 gintmsk;
 804
 805		dev_vdbg(hsotg->dev, "Halt on queue\n");
 806		if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 807		    chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 808			dev_vdbg(hsotg->dev, "control/bulk\n");
 809			/*
 810			 * Make sure the Non-periodic Tx FIFO empty interrupt
 811			 * is enabled so that the non-periodic schedule will
 812			 * be processed
 813			 */
 814			gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 815			gintmsk |= GINTSTS_NPTXFEMP;
 816			dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
 817		} else {
 818			dev_vdbg(hsotg->dev, "isoc/intr\n");
 819			/*
 820			 * Move the QH from the periodic queued schedule to
 821			 * the periodic assigned schedule. This allows the
 822			 * halt to be queued when the periodic schedule is
 823			 * processed.
 824			 */
 825			list_move_tail(&chan->qh->qh_list_entry,
 826				  &hsotg->periodic_sched_assigned);
 827
 828			/*
 829			 * Make sure the Periodic Tx FIFO Empty interrupt is
 830			 * enabled so that the periodic schedule will be
 831			 * processed
 832			 */
 833			gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 834			gintmsk |= GINTSTS_PTXFEMP;
 835			dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
 836		}
 837	}
 838}
 839
 840/*
 841 * Performs common cleanup for non-periodic transfers after a Transfer
 842 * Complete interrupt. This function should be called after any endpoint type
 843 * specific handling is finished to release the host channel.
 844 */
 845static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
 846					    struct dwc2_host_chan *chan,
 847					    int chnum, struct dwc2_qtd *qtd,
 848					    enum dwc2_halt_status halt_status)
 849{
 850	dev_vdbg(hsotg->dev, "%s()\n", __func__);
 851
 852	qtd->error_count = 0;
 853
 854	if (chan->hcint & HCINTMSK_NYET) {
 855		/*
 856		 * Got a NYET on the last transaction of the transfer. This
 857		 * means that the endpoint should be in the PING state at the
 858		 * beginning of the next transfer.
 859		 */
 860		dev_vdbg(hsotg->dev, "got NYET\n");
 861		chan->qh->ping_state = 1;
 862	}
 863
 864	/*
 865	 * Always halt and release the host channel to make it available for
 866	 * more transfers. There may still be more phases for a control
 867	 * transfer or more data packets for a bulk transfer at this point,
 868	 * but the host channel is still halted. A channel will be reassigned
 869	 * to the transfer when the non-periodic schedule is processed after
 870	 * the channel is released. This allows transactions to be queued
 871	 * properly via dwc2_hcd_queue_transactions, which also enables the
 872	 * Tx FIFO Empty interrupt if necessary.
 873	 */
 874	if (chan->ep_is_in) {
 875		/*
 876		 * IN transfers in Slave mode require an explicit disable to
 877		 * halt the channel. (In DMA mode, this call simply releases
 878		 * the channel.)
 879		 */
 880		dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 881	} else {
 882		/*
 883		 * The channel is automatically disabled by the core for OUT
 884		 * transfers in Slave mode
 885		 */
 886		dwc2_release_channel(hsotg, chan, qtd, halt_status);
 887	}
 888}
 889
 890/*
 891 * Performs common cleanup for periodic transfers after a Transfer Complete
 892 * interrupt. This function should be called after any endpoint type specific
 893 * handling is finished to release the host channel.
 894 */
 895static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
 896					struct dwc2_host_chan *chan, int chnum,
 897					struct dwc2_qtd *qtd,
 898					enum dwc2_halt_status halt_status)
 899{
 900	u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 901
 902	qtd->error_count = 0;
 903
 904	if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
 905		/* Core halts channel in these cases */
 906		dwc2_release_channel(hsotg, chan, qtd, halt_status);
 907	else
 908		/* Flush any outstanding requests from the Tx queue */
 909		dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 910}
 911
 912static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
 913				       struct dwc2_host_chan *chan, int chnum,
 914				       struct dwc2_qtd *qtd)
 915{
 916	struct dwc2_hcd_iso_packet_desc *frame_desc;
 917	u32 len;
 918	u32 hctsiz;
 919	u32 pid;
 920
 921	if (!qtd->urb)
 922		return 0;
 923
 924	frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
 925	len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 926					  DWC2_HC_XFER_COMPLETE, NULL);
 927	if (!len) {
 928		qtd->complete_split = 0;
 929		qtd->isoc_split_offset = 0;
 930		return 0;
 931	}
 932
 933	frame_desc->actual_length += len;
 934
 935	qtd->isoc_split_offset += len;
 
 
 
 
 
 
 
 
 936
 937	hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 938	pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
 939
 940	if (frame_desc->actual_length >= frame_desc->length || pid == 0) {
 941		frame_desc->status = 0;
 942		qtd->isoc_frame_index++;
 943		qtd->complete_split = 0;
 944		qtd->isoc_split_offset = 0;
 945	}
 946
 947	if (qtd->isoc_frame_index == qtd->urb->packet_count) {
 948		dwc2_host_complete(hsotg, qtd, 0);
 949		dwc2_release_channel(hsotg, chan, qtd,
 950				     DWC2_HC_XFER_URB_COMPLETE);
 951	} else {
 952		dwc2_release_channel(hsotg, chan, qtd,
 953				     DWC2_HC_XFER_NO_HALT_STATUS);
 954	}
 955
 956	return 1;	/* Indicates that channel released */
 957}
 958
 959/*
 960 * Handles a host channel Transfer Complete interrupt. This handler may be
 961 * called in either DMA mode or Slave mode.
 962 */
 963static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
 964				  struct dwc2_host_chan *chan, int chnum,
 965				  struct dwc2_qtd *qtd)
 966{
 967	struct dwc2_hcd_urb *urb = qtd->urb;
 968	enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
 969	int pipe_type;
 970	int urb_xfer_done;
 971
 972	if (dbg_hc(chan))
 973		dev_vdbg(hsotg->dev,
 974			 "--Host Channel %d Interrupt: Transfer Complete--\n",
 975			 chnum);
 976
 977	if (!urb)
 978		goto handle_xfercomp_done;
 979
 980	pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
 981
 982	if (hsotg->params.dma_desc_enable > 0) {
 983		dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
 984		if (pipe_type == USB_ENDPOINT_XFER_ISOC)
 985			/* Do not disable the interrupt, just clear it */
 986			return;
 987		goto handle_xfercomp_done;
 988	}
 989
 990	/* Handle xfer complete on CSPLIT */
 991	if (chan->qh->do_split) {
 992		if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 993		    hsotg->params.host_dma > 0) {
 994			if (qtd->complete_split &&
 995			    dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
 996							qtd))
 997				goto handle_xfercomp_done;
 998		} else {
 999			qtd->complete_split = 0;
1000		}
1001	}
1002
1003	/* Update the QTD and URB states */
1004	switch (pipe_type) {
1005	case USB_ENDPOINT_XFER_CONTROL:
1006		switch (qtd->control_phase) {
1007		case DWC2_CONTROL_SETUP:
1008			if (urb->length > 0)
1009				qtd->control_phase = DWC2_CONTROL_DATA;
1010			else
1011				qtd->control_phase = DWC2_CONTROL_STATUS;
1012			dev_vdbg(hsotg->dev,
1013				 "  Control setup transaction done\n");
1014			halt_status = DWC2_HC_XFER_COMPLETE;
1015			break;
1016		case DWC2_CONTROL_DATA:
1017			urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1018							      chnum, urb, qtd);
1019			if (urb_xfer_done) {
1020				qtd->control_phase = DWC2_CONTROL_STATUS;
1021				dev_vdbg(hsotg->dev,
1022					 "  Control data transfer done\n");
1023			} else {
1024				dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1025							  qtd);
1026			}
1027			halt_status = DWC2_HC_XFER_COMPLETE;
1028			break;
1029		case DWC2_CONTROL_STATUS:
1030			dev_vdbg(hsotg->dev, "  Control transfer complete\n");
1031			if (urb->status == -EINPROGRESS)
1032				urb->status = 0;
1033			dwc2_host_complete(hsotg, qtd, urb->status);
1034			halt_status = DWC2_HC_XFER_URB_COMPLETE;
1035			break;
1036		}
1037
1038		dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1039						halt_status);
1040		break;
1041	case USB_ENDPOINT_XFER_BULK:
1042		dev_vdbg(hsotg->dev, "  Bulk transfer complete\n");
1043		urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1044						      qtd);
1045		if (urb_xfer_done) {
1046			dwc2_host_complete(hsotg, qtd, urb->status);
1047			halt_status = DWC2_HC_XFER_URB_COMPLETE;
1048		} else {
1049			halt_status = DWC2_HC_XFER_COMPLETE;
1050		}
1051
1052		dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1053		dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1054						halt_status);
1055		break;
1056	case USB_ENDPOINT_XFER_INT:
1057		dev_vdbg(hsotg->dev, "  Interrupt transfer complete\n");
1058		urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1059						      qtd);
1060
1061		/*
1062		 * Interrupt URB is done on the first transfer complete
1063		 * interrupt
1064		 */
1065		if (urb_xfer_done) {
1066			dwc2_host_complete(hsotg, qtd, urb->status);
1067			halt_status = DWC2_HC_XFER_URB_COMPLETE;
1068		} else {
1069			halt_status = DWC2_HC_XFER_COMPLETE;
1070		}
1071
1072		dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1073		dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1074					    halt_status);
1075		break;
1076	case USB_ENDPOINT_XFER_ISOC:
1077		if (dbg_perio())
1078			dev_vdbg(hsotg->dev, "  Isochronous transfer complete\n");
1079		if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1080			halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1081					chnum, qtd, DWC2_HC_XFER_COMPLETE);
1082		dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1083					    halt_status);
1084		break;
1085	}
1086
1087handle_xfercomp_done:
1088	disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1089}
1090
1091/*
1092 * Handles a host channel STALL interrupt. This handler may be called in
1093 * either DMA mode or Slave mode.
1094 */
1095static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1096			       struct dwc2_host_chan *chan, int chnum,
1097			       struct dwc2_qtd *qtd)
1098{
1099	struct dwc2_hcd_urb *urb = qtd->urb;
1100	int pipe_type;
1101
1102	dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1103		chnum);
1104
1105	if (hsotg->params.dma_desc_enable > 0) {
1106		dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1107					    DWC2_HC_XFER_STALL);
1108		goto handle_stall_done;
1109	}
1110
1111	if (!urb)
1112		goto handle_stall_halt;
1113
1114	pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1115
1116	if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1117		dwc2_host_complete(hsotg, qtd, -EPIPE);
1118
1119	if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1120	    pipe_type == USB_ENDPOINT_XFER_INT) {
1121		dwc2_host_complete(hsotg, qtd, -EPIPE);
1122		/*
1123		 * USB protocol requires resetting the data toggle for bulk
1124		 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1125		 * setup command is issued to the endpoint. Anticipate the
1126		 * CLEAR_FEATURE command since a STALL has occurred and reset
1127		 * the data toggle now.
1128		 */
1129		chan->qh->data_toggle = 0;
1130	}
1131
1132handle_stall_halt:
1133	dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1134
1135handle_stall_done:
1136	disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1137}
1138
1139/*
1140 * Updates the state of the URB when a transfer has been stopped due to an
1141 * abnormal condition before the transfer completes. Modifies the
1142 * actual_length field of the URB to reflect the number of bytes that have
1143 * actually been transferred via the host channel.
1144 */
1145static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1146				      struct dwc2_host_chan *chan, int chnum,
1147				      struct dwc2_hcd_urb *urb,
1148				      struct dwc2_qtd *qtd,
1149				      enum dwc2_halt_status halt_status)
1150{
1151	u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1152						      qtd, halt_status, NULL);
1153	u32 hctsiz;
1154
1155	if (urb->actual_length + xfer_length > urb->length) {
1156		dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1157		xfer_length = urb->length - urb->actual_length;
1158	}
1159
 
 
 
 
 
 
 
 
 
 
 
1160	urb->actual_length += xfer_length;
1161
1162	hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1163	dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1164		 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1165	dev_vdbg(hsotg->dev, "  chan->start_pkt_count %d\n",
1166		 chan->start_pkt_count);
1167	dev_vdbg(hsotg->dev, "  hctsiz.pktcnt %d\n",
1168		 (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1169	dev_vdbg(hsotg->dev, "  chan->max_packet %d\n", chan->max_packet);
1170	dev_vdbg(hsotg->dev, "  bytes_transferred %d\n",
1171		 xfer_length);
1172	dev_vdbg(hsotg->dev, "  urb->actual_length %d\n",
1173		 urb->actual_length);
1174	dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n",
1175		 urb->length);
1176}
1177
1178/*
1179 * Handles a host channel NAK interrupt. This handler may be called in either
1180 * DMA mode or Slave mode.
1181 */
1182static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1183			     struct dwc2_host_chan *chan, int chnum,
1184			     struct dwc2_qtd *qtd)
1185{
1186	if (!qtd) {
1187		dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1188		return;
1189	}
1190
1191	if (!qtd->urb) {
1192		dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1193		return;
1194	}
1195
1196	if (dbg_hc(chan))
1197		dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1198			 chnum);
1199
1200	/*
1201	 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1202	 * interrupt. Re-start the SSPLIT transfer.
1203	 */
1204	if (chan->do_split) {
1205		if (chan->complete_split)
1206			qtd->error_count = 0;
1207		qtd->complete_split = 0;
1208		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1209		goto handle_nak_done;
1210	}
1211
1212	switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1213	case USB_ENDPOINT_XFER_CONTROL:
1214	case USB_ENDPOINT_XFER_BULK:
1215		if (hsotg->params.host_dma > 0 && chan->ep_is_in) {
1216			/*
1217			 * NAK interrupts are enabled on bulk/control IN
1218			 * transfers in DMA mode for the sole purpose of
1219			 * resetting the error count after a transaction error
1220			 * occurs. The core will continue transferring data.
1221			 */
1222			qtd->error_count = 0;
1223			break;
1224		}
1225
1226		/*
1227		 * NAK interrupts normally occur during OUT transfers in DMA
1228		 * or Slave mode. For IN transfers, more requests will be
1229		 * queued as request queue space is available.
1230		 */
1231		qtd->error_count = 0;
1232
1233		if (!chan->qh->ping_state) {
1234			dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1235						  qtd, DWC2_HC_XFER_NAK);
1236			dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1237
1238			if (chan->speed == USB_SPEED_HIGH)
1239				chan->qh->ping_state = 1;
1240		}
1241
1242		/*
1243		 * Halt the channel so the transfer can be re-started from
1244		 * the appropriate point or the PING protocol will
1245		 * start/continue
1246		 */
1247		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1248		break;
1249	case USB_ENDPOINT_XFER_INT:
1250		qtd->error_count = 0;
1251		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1252		break;
1253	case USB_ENDPOINT_XFER_ISOC:
1254		/* Should never get called for isochronous transfers */
1255		dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1256		break;
1257	}
1258
1259handle_nak_done:
1260	disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1261}
1262
1263/*
1264 * Handles a host channel ACK interrupt. This interrupt is enabled when
1265 * performing the PING protocol in Slave mode, when errors occur during
1266 * either Slave mode or DMA mode, and during Start Split transactions.
1267 */
1268static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1269			     struct dwc2_host_chan *chan, int chnum,
1270			     struct dwc2_qtd *qtd)
1271{
1272	struct dwc2_hcd_iso_packet_desc *frame_desc;
1273
1274	if (dbg_hc(chan))
1275		dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1276			 chnum);
1277
1278	if (chan->do_split) {
1279		/* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1280		if (!chan->ep_is_in &&
1281		    chan->data_pid_start != DWC2_HC_PID_SETUP)
1282			qtd->ssplit_out_xfer_count = chan->xfer_len;
1283
1284		if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1285			qtd->complete_split = 1;
1286			dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1287		} else {
1288			/* ISOC OUT */
1289			switch (chan->xact_pos) {
1290			case DWC2_HCSPLT_XACTPOS_ALL:
1291				break;
1292			case DWC2_HCSPLT_XACTPOS_END:
1293				qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1294				qtd->isoc_split_offset = 0;
1295				break;
1296			case DWC2_HCSPLT_XACTPOS_BEGIN:
1297			case DWC2_HCSPLT_XACTPOS_MID:
1298				/*
1299				 * For BEGIN or MID, calculate the length for
1300				 * the next microframe to determine the correct
1301				 * SSPLIT token, either MID or END
1302				 */
1303				frame_desc = &qtd->urb->iso_descs[
1304						qtd->isoc_frame_index];
1305				qtd->isoc_split_offset += 188;
1306
1307				if (frame_desc->length - qtd->isoc_split_offset
1308							<= 188)
1309					qtd->isoc_split_pos =
1310							DWC2_HCSPLT_XACTPOS_END;
1311				else
1312					qtd->isoc_split_pos =
1313							DWC2_HCSPLT_XACTPOS_MID;
1314				break;
1315			}
1316		}
1317	} else {
1318		qtd->error_count = 0;
1319
1320		if (chan->qh->ping_state) {
1321			chan->qh->ping_state = 0;
1322			/*
1323			 * Halt the channel so the transfer can be re-started
1324			 * from the appropriate point. This only happens in
1325			 * Slave mode. In DMA mode, the ping_state is cleared
1326			 * when the transfer is started because the core
1327			 * automatically executes the PING, then the transfer.
1328			 */
1329			dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1330		}
1331	}
1332
1333	/*
1334	 * If the ACK occurred when _not_ in the PING state, let the channel
1335	 * continue transferring data after clearing the error count
1336	 */
1337	disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1338}
1339
1340/*
1341 * Handles a host channel NYET interrupt. This interrupt should only occur on
1342 * Bulk and Control OUT endpoints and for complete split transactions. If a
1343 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1344 * handled in the xfercomp interrupt handler, not here. This handler may be
1345 * called in either DMA mode or Slave mode.
1346 */
1347static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1348			      struct dwc2_host_chan *chan, int chnum,
1349			      struct dwc2_qtd *qtd)
1350{
1351	if (dbg_hc(chan))
1352		dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1353			 chnum);
1354
1355	/*
1356	 * NYET on CSPLIT
1357	 * re-do the CSPLIT immediately on non-periodic
1358	 */
1359	if (chan->do_split && chan->complete_split) {
1360		if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1361		    hsotg->params.host_dma > 0) {
1362			qtd->complete_split = 0;
1363			qtd->isoc_split_offset = 0;
1364			qtd->isoc_frame_index++;
1365			if (qtd->urb &&
1366			    qtd->isoc_frame_index == qtd->urb->packet_count) {
1367				dwc2_host_complete(hsotg, qtd, 0);
1368				dwc2_release_channel(hsotg, chan, qtd,
1369						     DWC2_HC_XFER_URB_COMPLETE);
1370			} else {
1371				dwc2_release_channel(hsotg, chan, qtd,
1372						DWC2_HC_XFER_NO_HALT_STATUS);
1373			}
1374			goto handle_nyet_done;
1375		}
1376
1377		if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1378		    chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1379			struct dwc2_qh *qh = chan->qh;
1380			bool past_end;
1381
1382			if (hsotg->params.uframe_sched <= 0) {
1383				int frnum = dwc2_hcd_get_frame_number(hsotg);
1384
1385				/* Don't have num_hs_transfers; simple logic */
1386				past_end = dwc2_full_frame_num(frnum) !=
1387				     dwc2_full_frame_num(qh->next_active_frame);
1388			} else {
1389				int end_frnum;
1390
 
 
1391				/*
1392				* Figure out the end frame based on schedule.
1393				*
1394				* We don't want to go on trying again and again
1395				* forever.  Let's stop when we've done all the
1396				* transfers that were scheduled.
1397				*
1398				* We're going to be comparing start_active_frame
1399				* and next_active_frame, both of which are 1
1400				* before the time the packet goes on the wire,
1401				* so that cancels out.  Basically if had 1
1402				* transfer and we saw 1 NYET then we're done.
1403				* We're getting a NYET here so if next >=
1404				* (start + num_transfers) we're done. The
1405				* complexity is that for all but ISOC_OUT we
1406				* skip one slot.
1407				*/
1408				end_frnum = dwc2_frame_num_inc(
1409					qh->start_active_frame,
1410					qh->num_hs_transfers);
1411
1412				if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
1413				    qh->ep_is_in)
1414					end_frnum =
1415					       dwc2_frame_num_inc(end_frnum, 1);
1416
1417				past_end = dwc2_frame_num_le(
1418					end_frnum, qh->next_active_frame);
1419			}
1420
1421			if (past_end) {
1422				/* Treat this as a transaction error. */
1423#if 0
1424				/*
1425				 * Todo: Fix system performance so this can
1426				 * be treated as an error. Right now complete
1427				 * splits cannot be scheduled precisely enough
1428				 * due to other system activity, so this error
1429				 * occurs regularly in Slave mode.
1430				 */
1431				qtd->error_count++;
1432#endif
1433				qtd->complete_split = 0;
1434				dwc2_halt_channel(hsotg, chan, qtd,
1435						  DWC2_HC_XFER_XACT_ERR);
1436				/* Todo: add support for isoc release */
1437				goto handle_nyet_done;
1438			}
1439		}
1440
1441		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1442		goto handle_nyet_done;
1443	}
1444
1445	chan->qh->ping_state = 1;
1446	qtd->error_count = 0;
1447
1448	dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1449				  DWC2_HC_XFER_NYET);
1450	dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1451
1452	/*
1453	 * Halt the channel and re-start the transfer so the PING protocol
1454	 * will start
1455	 */
1456	dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1457
1458handle_nyet_done:
1459	disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1460}
1461
1462/*
1463 * Handles a host channel babble interrupt. This handler may be called in
1464 * either DMA mode or Slave mode.
1465 */
1466static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1467				struct dwc2_host_chan *chan, int chnum,
1468				struct dwc2_qtd *qtd)
1469{
1470	dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1471		chnum);
1472
1473	dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1474
1475	if (hsotg->params.dma_desc_enable > 0) {
1476		dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1477					    DWC2_HC_XFER_BABBLE_ERR);
1478		goto disable_int;
1479	}
1480
1481	if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1482		dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1483		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1484	} else {
1485		enum dwc2_halt_status halt_status;
1486
1487		halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1488						qtd, DWC2_HC_XFER_BABBLE_ERR);
1489		dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1490	}
1491
1492disable_int:
1493	disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1494}
1495
1496/*
1497 * Handles a host channel AHB error interrupt. This handler is only called in
1498 * DMA mode.
1499 */
1500static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1501				struct dwc2_host_chan *chan, int chnum,
1502				struct dwc2_qtd *qtd)
1503{
1504	struct dwc2_hcd_urb *urb = qtd->urb;
1505	char *pipetype, *speed;
1506	u32 hcchar;
1507	u32 hcsplt;
1508	u32 hctsiz;
1509	u32 hc_dma;
1510
1511	dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1512		chnum);
1513
1514	if (!urb)
1515		goto handle_ahberr_halt;
1516
1517	dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1518
1519	hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1520	hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1521	hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1522	hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
1523
1524	dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1525	dev_err(hsotg->dev, "  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1526	dev_err(hsotg->dev, "  hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1527	dev_err(hsotg->dev, "  Device address: %d\n",
1528		dwc2_hcd_get_dev_addr(&urb->pipe_info));
1529	dev_err(hsotg->dev, "  Endpoint: %d, %s\n",
1530		dwc2_hcd_get_ep_num(&urb->pipe_info),
1531		dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1532
1533	switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1534	case USB_ENDPOINT_XFER_CONTROL:
1535		pipetype = "CONTROL";
1536		break;
1537	case USB_ENDPOINT_XFER_BULK:
1538		pipetype = "BULK";
1539		break;
1540	case USB_ENDPOINT_XFER_INT:
1541		pipetype = "INTERRUPT";
1542		break;
1543	case USB_ENDPOINT_XFER_ISOC:
1544		pipetype = "ISOCHRONOUS";
1545		break;
1546	default:
1547		pipetype = "UNKNOWN";
1548		break;
1549	}
1550
1551	dev_err(hsotg->dev, "  Endpoint type: %s\n", pipetype);
1552
1553	switch (chan->speed) {
1554	case USB_SPEED_HIGH:
1555		speed = "HIGH";
1556		break;
1557	case USB_SPEED_FULL:
1558		speed = "FULL";
1559		break;
1560	case USB_SPEED_LOW:
1561		speed = "LOW";
1562		break;
1563	default:
1564		speed = "UNKNOWN";
1565		break;
1566	}
1567
1568	dev_err(hsotg->dev, "  Speed: %s\n", speed);
1569
1570	dev_err(hsotg->dev, "  Max packet size: %d\n",
1571		dwc2_hcd_get_mps(&urb->pipe_info));
1572	dev_err(hsotg->dev, "  Data buffer length: %d\n", urb->length);
1573	dev_err(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
1574		urb->buf, (unsigned long)urb->dma);
1575	dev_err(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
1576		urb->setup_packet, (unsigned long)urb->setup_dma);
1577	dev_err(hsotg->dev, "  Interval: %d\n", urb->interval);
1578
1579	/* Core halts the channel for Descriptor DMA mode */
1580	if (hsotg->params.dma_desc_enable > 0) {
1581		dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1582					    DWC2_HC_XFER_AHB_ERR);
1583		goto handle_ahberr_done;
1584	}
1585
1586	dwc2_host_complete(hsotg, qtd, -EIO);
1587
1588handle_ahberr_halt:
1589	/*
1590	 * Force a channel halt. Don't call dwc2_halt_channel because that won't
1591	 * write to the HCCHARn register in DMA mode to force the halt.
1592	 */
1593	dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1594
1595handle_ahberr_done:
1596	disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1597}
1598
1599/*
1600 * Handles a host channel transaction error interrupt. This handler may be
1601 * called in either DMA mode or Slave mode.
1602 */
1603static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1604				 struct dwc2_host_chan *chan, int chnum,
1605				 struct dwc2_qtd *qtd)
1606{
1607	dev_dbg(hsotg->dev,
1608		"--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1609
1610	dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1611
1612	if (hsotg->params.dma_desc_enable > 0) {
1613		dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1614					    DWC2_HC_XFER_XACT_ERR);
1615		goto handle_xacterr_done;
1616	}
1617
1618	switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1619	case USB_ENDPOINT_XFER_CONTROL:
1620	case USB_ENDPOINT_XFER_BULK:
1621		qtd->error_count++;
1622		if (!chan->qh->ping_state) {
1623
1624			dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1625						  qtd, DWC2_HC_XFER_XACT_ERR);
1626			dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1627			if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1628				chan->qh->ping_state = 1;
1629		}
1630
1631		/*
1632		 * Halt the channel so the transfer can be re-started from
1633		 * the appropriate point or the PING protocol will start
1634		 */
1635		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1636		break;
1637	case USB_ENDPOINT_XFER_INT:
1638		qtd->error_count++;
1639		if (chan->do_split && chan->complete_split)
1640			qtd->complete_split = 0;
1641		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1642		break;
1643	case USB_ENDPOINT_XFER_ISOC:
1644		{
1645			enum dwc2_halt_status halt_status;
1646
1647			halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1648					chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1649			dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1650		}
1651		break;
1652	}
1653
1654handle_xacterr_done:
1655	disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1656}
1657
1658/*
1659 * Handles a host channel frame overrun interrupt. This handler may be called
1660 * in either DMA mode or Slave mode.
1661 */
1662static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1663				  struct dwc2_host_chan *chan, int chnum,
1664				  struct dwc2_qtd *qtd)
1665{
1666	enum dwc2_halt_status halt_status;
1667
1668	if (dbg_hc(chan))
1669		dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1670			chnum);
1671
1672	dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1673
1674	switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1675	case USB_ENDPOINT_XFER_CONTROL:
1676	case USB_ENDPOINT_XFER_BULK:
1677		break;
1678	case USB_ENDPOINT_XFER_INT:
1679		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1680		break;
1681	case USB_ENDPOINT_XFER_ISOC:
1682		halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1683					qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1684		dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1685		break;
1686	}
1687
1688	disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1689}
1690
1691/*
1692 * Handles a host channel data toggle error interrupt. This handler may be
1693 * called in either DMA mode or Slave mode.
1694 */
1695static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1696				    struct dwc2_host_chan *chan, int chnum,
1697				    struct dwc2_qtd *qtd)
1698{
1699	dev_dbg(hsotg->dev,
1700		"--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1701
1702	if (chan->ep_is_in)
1703		qtd->error_count = 0;
1704	else
1705		dev_err(hsotg->dev,
1706			"Data Toggle Error on OUT transfer, channel %d\n",
1707			chnum);
1708
1709	dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1710	disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1711}
1712
1713/*
1714 * For debug only. It checks that a valid halt status is set and that
1715 * HCCHARn.chdis is clear. If there's a problem, corrective action is
1716 * taken and a warning is issued.
1717 *
1718 * Return: true if halt status is ok, false otherwise
1719 */
1720static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1721				struct dwc2_host_chan *chan, int chnum,
1722				struct dwc2_qtd *qtd)
1723{
1724#ifdef DEBUG
1725	u32 hcchar;
1726	u32 hctsiz;
1727	u32 hcintmsk;
1728	u32 hcsplt;
1729
1730	if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1731		/*
1732		 * This code is here only as a check. This condition should
1733		 * never happen. Ignore the halt if it does occur.
1734		 */
1735		hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1736		hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1737		hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1738		hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1739		dev_dbg(hsotg->dev,
1740			"%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1741			 __func__);
1742		dev_dbg(hsotg->dev,
1743			"channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1744			chnum, hcchar, hctsiz);
1745		dev_dbg(hsotg->dev,
1746			"hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1747			chan->hcint, hcintmsk, hcsplt);
1748		if (qtd)
1749			dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1750				qtd->complete_split);
1751		dev_warn(hsotg->dev,
1752			 "%s: no halt status, channel %d, ignoring interrupt\n",
1753			 __func__, chnum);
1754		return false;
1755	}
1756
1757	/*
1758	 * This code is here only as a check. hcchar.chdis should never be set
1759	 * when the halt interrupt occurs. Halt the channel again if it does
1760	 * occur.
1761	 */
1762	hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1763	if (hcchar & HCCHAR_CHDIS) {
1764		dev_warn(hsotg->dev,
1765			 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1766			 __func__, hcchar);
1767		chan->halt_pending = 0;
1768		dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1769		return false;
1770	}
1771#endif
1772
1773	return true;
1774}
1775
1776/*
1777 * Handles a host Channel Halted interrupt in DMA mode. This handler
1778 * determines the reason the channel halted and proceeds accordingly.
1779 */
1780static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1781				    struct dwc2_host_chan *chan, int chnum,
1782				    struct dwc2_qtd *qtd)
1783{
1784	u32 hcintmsk;
1785	int out_nak_enh = 0;
1786
1787	if (dbg_hc(chan))
1788		dev_vdbg(hsotg->dev,
1789			 "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1790			 chnum);
1791
1792	/*
1793	 * For core with OUT NAK enhancement, the flow for high-speed
1794	 * CONTROL/BULK OUT is handled a little differently
1795	 */
1796	if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1797		if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1798		    (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1799		     chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1800			out_nak_enh = 1;
1801		}
1802	}
1803
1804	if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1805	    (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1806	     hsotg->params.dma_desc_enable <= 0)) {
1807		if (hsotg->params.dma_desc_enable > 0)
1808			dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1809						    chan->halt_status);
1810		else
1811			/*
1812			 * Just release the channel. A dequeue can happen on a
1813			 * transfer timeout. In the case of an AHB Error, the
1814			 * channel was forced to halt because there's no way to
1815			 * gracefully recover.
1816			 */
1817			dwc2_release_channel(hsotg, chan, qtd,
1818					     chan->halt_status);
1819		return;
1820	}
1821
1822	hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1823
1824	if (chan->hcint & HCINTMSK_XFERCOMPL) {
1825		/*
1826		 * Todo: This is here because of a possible hardware bug. Spec
1827		 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1828		 * interrupt w/ACK bit set should occur, but I only see the
1829		 * XFERCOMP bit, even with it masked out. This is a workaround
1830		 * for that behavior. Should fix this when hardware is fixed.
1831		 */
1832		if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1833			dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1834		dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1835	} else if (chan->hcint & HCINTMSK_STALL) {
1836		dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1837	} else if ((chan->hcint & HCINTMSK_XACTERR) &&
1838		   hsotg->params.dma_desc_enable <= 0) {
1839		if (out_nak_enh) {
1840			if (chan->hcint &
1841			    (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1842				dev_vdbg(hsotg->dev,
1843					 "XactErr with NYET/NAK/ACK\n");
1844				qtd->error_count = 0;
1845			} else {
1846				dev_vdbg(hsotg->dev,
1847					 "XactErr without NYET/NAK/ACK\n");
1848			}
1849		}
1850
1851		/*
1852		 * Must handle xacterr before nak or ack. Could get a xacterr
1853		 * at the same time as either of these on a BULK/CONTROL OUT
1854		 * that started with a PING. The xacterr takes precedence.
1855		 */
1856		dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1857	} else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1858		   hsotg->params.dma_desc_enable > 0) {
1859		dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1860	} else if ((chan->hcint & HCINTMSK_AHBERR) &&
1861		   hsotg->params.dma_desc_enable > 0) {
1862		dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1863	} else if (chan->hcint & HCINTMSK_BBLERR) {
1864		dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1865	} else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1866		dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1867	} else if (!out_nak_enh) {
1868		if (chan->hcint & HCINTMSK_NYET) {
1869			/*
1870			 * Must handle nyet before nak or ack. Could get a nyet
1871			 * at the same time as either of those on a BULK/CONTROL
1872			 * OUT that started with a PING. The nyet takes
1873			 * precedence.
1874			 */
1875			dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1876		} else if ((chan->hcint & HCINTMSK_NAK) &&
1877			   !(hcintmsk & HCINTMSK_NAK)) {
1878			/*
1879			 * If nak is not masked, it's because a non-split IN
1880			 * transfer is in an error state. In that case, the nak
1881			 * is handled by the nak interrupt handler, not here.
1882			 * Handle nak here for BULK/CONTROL OUT transfers, which
1883			 * halt on a NAK to allow rewinding the buffer pointer.
1884			 */
1885			dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1886		} else if ((chan->hcint & HCINTMSK_ACK) &&
1887			   !(hcintmsk & HCINTMSK_ACK)) {
1888			/*
1889			 * If ack is not masked, it's because a non-split IN
1890			 * transfer is in an error state. In that case, the ack
1891			 * is handled by the ack interrupt handler, not here.
1892			 * Handle ack here for split transfers. Start splits
1893			 * halt on ACK.
1894			 */
1895			dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1896		} else {
1897			if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1898			    chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1899				/*
1900				 * A periodic transfer halted with no other
1901				 * channel interrupts set. Assume it was halted
1902				 * by the core because it could not be completed
1903				 * in its scheduled (micro)frame.
1904				 */
1905				dev_dbg(hsotg->dev,
1906					"%s: Halt channel %d (assume incomplete periodic transfer)\n",
1907					__func__, chnum);
1908				dwc2_halt_channel(hsotg, chan, qtd,
1909					DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1910			} else {
1911				dev_err(hsotg->dev,
1912					"%s: Channel %d - ChHltd set, but reason is unknown\n",
1913					__func__, chnum);
1914				dev_err(hsotg->dev,
1915					"hcint 0x%08x, intsts 0x%08x\n",
1916					chan->hcint,
1917					dwc2_readl(hsotg->regs + GINTSTS));
1918				goto error;
1919			}
1920		}
1921	} else {
1922		dev_info(hsotg->dev,
1923			 "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1924			 chan->hcint);
1925error:
1926		/* Failthrough: use 3-strikes rule */
1927		qtd->error_count++;
1928		dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1929					  qtd, DWC2_HC_XFER_XACT_ERR);
1930		dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1931		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1932	}
1933}
1934
1935/*
1936 * Handles a host channel Channel Halted interrupt
1937 *
1938 * In slave mode, this handler is called only when the driver specifically
1939 * requests a halt. This occurs during handling other host channel interrupts
1940 * (e.g. nak, xacterr, stall, nyet, etc.).
1941 *
1942 * In DMA mode, this is the interrupt that occurs when the core has finished
1943 * processing a transfer on a channel. Other host channel interrupts (except
1944 * ahberr) are disabled in DMA mode.
1945 */
1946static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1947				struct dwc2_host_chan *chan, int chnum,
1948				struct dwc2_qtd *qtd)
1949{
1950	if (dbg_hc(chan))
1951		dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1952			 chnum);
1953
1954	if (hsotg->params.host_dma > 0) {
1955		dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1956	} else {
1957		if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1958			return;
1959		dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1960	}
1961}
1962
1963/*
1964 * Check if the given qtd is still the top of the list (and thus valid).
1965 *
1966 * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
1967 * the qtd from the top of the list, this will return false (otherwise true).
1968 */
1969static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1970{
1971	struct dwc2_qtd *cur_head;
1972
1973	if (qh == NULL)
1974		return false;
1975
1976	cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
1977				    qtd_list_entry);
1978	return (cur_head == qtd);
1979}
1980
1981/* Handles interrupt for a specific Host Channel */
1982static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1983{
1984	struct dwc2_qtd *qtd;
1985	struct dwc2_host_chan *chan;
1986	u32 hcint, hcintmsk;
1987
1988	chan = hsotg->hc_ptr_array[chnum];
1989
1990	hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
1991	hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1992	if (!chan) {
1993		dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1994		dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
1995		return;
1996	}
1997
1998	if (dbg_hc(chan)) {
1999		dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2000			 chnum);
2001		dev_vdbg(hsotg->dev,
2002			 "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2003			 hcint, hcintmsk, hcint & hcintmsk);
2004	}
2005
2006	dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2007
2008	/*
2009	 * If we got an interrupt after someone called
2010	 * dwc2_hcd_endpoint_disable() we don't want to crash below
2011	 */
2012	if (!chan->qh) {
2013		dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
2014		return;
2015	}
2016
2017	chan->hcint = hcint;
2018	hcint &= hcintmsk;
2019
2020	/*
2021	 * If the channel was halted due to a dequeue, the qtd list might
2022	 * be empty or at least the first entry will not be the active qtd.
2023	 * In this case, take a shortcut and just release the channel.
2024	 */
2025	if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2026		/*
2027		 * If the channel was halted, this should be the only
2028		 * interrupt unmasked
2029		 */
2030		WARN_ON(hcint != HCINTMSK_CHHLTD);
2031		if (hsotg->params.dma_desc_enable > 0)
2032			dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2033						    chan->halt_status);
2034		else
2035			dwc2_release_channel(hsotg, chan, NULL,
2036					     chan->halt_status);
2037		return;
2038	}
2039
2040	if (list_empty(&chan->qh->qtd_list)) {
2041		/*
2042		 * TODO: Will this ever happen with the
2043		 * DWC2_HC_XFER_URB_DEQUEUE handling above?
2044		 */
2045		dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2046			chnum);
2047		dev_dbg(hsotg->dev,
2048			"  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2049			chan->hcint, hcintmsk, hcint);
2050		chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2051		disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2052		chan->hcint = 0;
2053		return;
2054	}
2055
2056	qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2057			       qtd_list_entry);
2058
2059	if (hsotg->params.host_dma <= 0) {
2060		if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2061			hcint &= ~HCINTMSK_CHHLTD;
2062	}
2063
2064	if (hcint & HCINTMSK_XFERCOMPL) {
2065		dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2066		/*
2067		 * If NYET occurred at same time as Xfer Complete, the NYET is
2068		 * handled by the Xfer Complete interrupt handler. Don't want
2069		 * to call the NYET interrupt handler in this case.
2070		 */
2071		hcint &= ~HCINTMSK_NYET;
2072	}
2073
2074	if (hcint & HCINTMSK_CHHLTD) {
2075		dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2076		if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2077			goto exit;
2078	}
2079	if (hcint & HCINTMSK_AHBERR) {
2080		dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2081		if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2082			goto exit;
2083	}
2084	if (hcint & HCINTMSK_STALL) {
2085		dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2086		if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2087			goto exit;
2088	}
2089	if (hcint & HCINTMSK_NAK) {
2090		dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2091		if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2092			goto exit;
2093	}
2094	if (hcint & HCINTMSK_ACK) {
2095		dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2096		if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2097			goto exit;
2098	}
2099	if (hcint & HCINTMSK_NYET) {
2100		dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2101		if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2102			goto exit;
2103	}
2104	if (hcint & HCINTMSK_XACTERR) {
2105		dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2106		if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2107			goto exit;
2108	}
2109	if (hcint & HCINTMSK_BBLERR) {
2110		dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2111		if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2112			goto exit;
2113	}
2114	if (hcint & HCINTMSK_FRMOVRUN) {
2115		dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2116		if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2117			goto exit;
2118	}
2119	if (hcint & HCINTMSK_DATATGLERR) {
2120		dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2121		if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2122			goto exit;
2123	}
2124
2125exit:
2126	chan->hcint = 0;
2127}
2128
2129/*
2130 * This interrupt indicates that one or more host channels has a pending
2131 * interrupt. There are multiple conditions that can cause each host channel
2132 * interrupt. This function determines which conditions have occurred for each
2133 * host channel interrupt and handles them appropriately.
2134 */
2135static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2136{
2137	u32 haint;
2138	int i;
2139	struct dwc2_host_chan *chan, *chan_tmp;
2140
2141	haint = dwc2_readl(hsotg->regs + HAINT);
2142	if (dbg_perio()) {
2143		dev_vdbg(hsotg->dev, "%s()\n", __func__);
2144
2145		dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2146	}
2147
2148	/*
2149	 * According to USB 2.0 spec section 11.18.8, a host must
2150	 * issue complete-split transactions in a microframe for a
2151	 * set of full-/low-speed endpoints in the same relative
2152	 * order as the start-splits were issued in a microframe for.
2153	 */
2154	list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
2155				 split_order_list_entry) {
2156		int hc_num = chan->hc_num;
2157
2158		if (haint & (1 << hc_num)) {
2159			dwc2_hc_n_intr(hsotg, hc_num);
2160			haint &= ~(1 << hc_num);
2161		}
2162	}
2163
2164	for (i = 0; i < hsotg->params.host_channels; i++) {
2165		if (haint & (1 << i))
2166			dwc2_hc_n_intr(hsotg, i);
2167	}
2168}
2169
2170/* This function handles interrupts for the HCD */
2171irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2172{
2173	u32 gintsts, dbg_gintsts;
2174	irqreturn_t retval = IRQ_NONE;
2175
2176	if (!dwc2_is_controller_alive(hsotg)) {
2177		dev_warn(hsotg->dev, "Controller is dead\n");
2178		return retval;
2179	}
2180
2181	spin_lock(&hsotg->lock);
2182
2183	/* Check if HOST Mode */
2184	if (dwc2_is_host_mode(hsotg)) {
2185		gintsts = dwc2_read_core_intr(hsotg);
2186		if (!gintsts) {
2187			spin_unlock(&hsotg->lock);
2188			return retval;
2189		}
2190
2191		retval = IRQ_HANDLED;
2192
2193		dbg_gintsts = gintsts;
2194#ifndef DEBUG_SOF
2195		dbg_gintsts &= ~GINTSTS_SOF;
2196#endif
2197		if (!dbg_perio())
2198			dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2199					 GINTSTS_PTXFEMP);
2200
2201		/* Only print if there are any non-suppressed interrupts left */
2202		if (dbg_gintsts)
2203			dev_vdbg(hsotg->dev,
2204				 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2205				 gintsts);
2206
2207		if (gintsts & GINTSTS_SOF)
2208			dwc2_sof_intr(hsotg);
2209		if (gintsts & GINTSTS_RXFLVL)
2210			dwc2_rx_fifo_level_intr(hsotg);
2211		if (gintsts & GINTSTS_NPTXFEMP)
2212			dwc2_np_tx_fifo_empty_intr(hsotg);
2213		if (gintsts & GINTSTS_PRTINT)
2214			dwc2_port_intr(hsotg);
2215		if (gintsts & GINTSTS_HCHINT)
2216			dwc2_hc_intr(hsotg);
2217		if (gintsts & GINTSTS_PTXFEMP)
2218			dwc2_perio_tx_fifo_empty_intr(hsotg);
2219
2220		if (dbg_gintsts) {
2221			dev_vdbg(hsotg->dev,
2222				 "DWC OTG HCD Finished Servicing Interrupts\n");
2223			dev_vdbg(hsotg->dev,
2224				 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2225				 dwc2_readl(hsotg->regs + GINTSTS),
2226				 dwc2_readl(hsotg->regs + GINTMSK));
2227		}
2228	}
2229
2230	spin_unlock(&hsotg->lock);
2231
2232	return retval;
2233}