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v4.10.11
  1/*
  2 * Shared Atheros AR9170 Header
  3 *
  4 * Firmware command interface definitions
  5 *
  6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
  7 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
  8 *
  9 * This program is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License as published by
 11 * the Free Software Foundation; either version 2 of the License.
 12 *
 13 * This program is distributed in the hope that it will be useful,
 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16 * GNU General Public License for more details.
 17 *
 18 * You should have received a copy of the GNU General Public License
 19 * along with this program; see the file COPYING.  If not, see
 20 * http://www.gnu.org/licenses/.
 21 *
 22 * This file incorporates work covered by the following copyright and
 23 * permission notice:
 24 *    Copyright (c) 2007-2008 Atheros Communications, Inc.
 25 *
 26 *    Permission to use, copy, modify, and/or distribute this software for any
 27 *    purpose with or without fee is hereby granted, provided that the above
 28 *    copyright notice and this permission notice appear in all copies.
 29 *
 30 *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 31 *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 32 *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 33 *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 34 *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 35 *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 36 *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 37 */
 38
 39#ifndef __CARL9170_SHARED_FWCMD_H
 40#define __CARL9170_SHARED_FWCMD_H
 41
 42#define	CARL9170_MAX_CMD_LEN		64
 43#define	CARL9170_MAX_CMD_PAYLOAD_LEN	60
 44
 45#define CARL9170FW_API_MIN_VER		1
 46#define CARL9170FW_API_MAX_VER		1
 47
 48enum carl9170_cmd_oids {
 49	CARL9170_CMD_RREG		= 0x00,
 50	CARL9170_CMD_WREG		= 0x01,
 51	CARL9170_CMD_ECHO		= 0x02,
 52	CARL9170_CMD_SWRST		= 0x03,
 53	CARL9170_CMD_REBOOT		= 0x04,
 54	CARL9170_CMD_BCN_CTRL		= 0x05,
 55	CARL9170_CMD_READ_TSF		= 0x06,
 56	CARL9170_CMD_RX_FILTER		= 0x07,
 57	CARL9170_CMD_WOL		= 0x08,
 58	CARL9170_CMD_TALLY		= 0x09,
 59	CARL9170_CMD_WREGB		= 0x0a,
 60
 61	/* CAM */
 62	CARL9170_CMD_EKEY		= 0x10,
 63	CARL9170_CMD_DKEY		= 0x11,
 64
 65	/* RF / PHY */
 66	CARL9170_CMD_FREQUENCY		= 0x20,
 67	CARL9170_CMD_RF_INIT		= 0x21,
 68	CARL9170_CMD_SYNTH		= 0x22,
 69	CARL9170_CMD_FREQ_START		= 0x23,
 70	CARL9170_CMD_PSM		= 0x24,
 71
 72	/* Asychronous command flag */
 73	CARL9170_CMD_ASYNC_FLAG		= 0x40,
 74	CARL9170_CMD_WREG_ASYNC		= (CARL9170_CMD_WREG |
 75					   CARL9170_CMD_ASYNC_FLAG),
 76	CARL9170_CMD_REBOOT_ASYNC	= (CARL9170_CMD_REBOOT |
 77					   CARL9170_CMD_ASYNC_FLAG),
 78	CARL9170_CMD_BCN_CTRL_ASYNC	= (CARL9170_CMD_BCN_CTRL |
 79					   CARL9170_CMD_ASYNC_FLAG),
 80	CARL9170_CMD_PSM_ASYNC		= (CARL9170_CMD_PSM |
 81					   CARL9170_CMD_ASYNC_FLAG),
 82
 83	/* responses and traps */
 84	CARL9170_RSP_FLAG		= 0xc0,
 85	CARL9170_RSP_PRETBTT		= 0xc0,
 86	CARL9170_RSP_TXCOMP		= 0xc1,
 87	CARL9170_RSP_BEACON_CONFIG	= 0xc2,
 88	CARL9170_RSP_ATIM		= 0xc3,
 89	CARL9170_RSP_WATCHDOG		= 0xc6,
 90	CARL9170_RSP_TEXT		= 0xca,
 91	CARL9170_RSP_HEXDUMP		= 0xcc,
 92	CARL9170_RSP_RADAR		= 0xcd,
 93	CARL9170_RSP_GPIO		= 0xce,
 94	CARL9170_RSP_BOOT		= 0xcf,
 95};
 96
 97struct carl9170_set_key_cmd {
 98	__le16		user;
 99	__le16		keyId;
100	__le16		type;
101	u8		macAddr[6];
102	u32		key[4];
103} __packed __aligned(4);
104#define CARL9170_SET_KEY_CMD_SIZE		28
105
106struct carl9170_disable_key_cmd {
107	__le16		user;
108	__le16		padding;
109} __packed __aligned(4);
110#define CARL9170_DISABLE_KEY_CMD_SIZE		4
111
112struct carl9170_u32_list {
113	u32	vals[0];
114} __packed;
115
116struct carl9170_reg_list {
117	__le32		regs[0];
118} __packed;
119
120struct carl9170_write_reg {
121	struct {
122		__le32		addr;
123		__le32		val;
124	} regs[0] __packed;
125} __packed;
126
127struct carl9170_write_reg_byte {
128	__le32	addr;
129	__le32  count;
130	u8	val[0];
131} __packed;
132
133#define	CARL9170FW_PHY_HT_ENABLE		0x4
134#define	CARL9170FW_PHY_HT_DYN2040		0x8
135#define	CARL9170FW_PHY_HT_EXT_CHAN_OFF		0x3
136#define	CARL9170FW_PHY_HT_EXT_CHAN_OFF_S	2
137
138struct carl9170_rf_init {
139	__le32		freq;
140	u8		ht_settings;
141	u8		padding2[3];
142	__le32		delta_slope_coeff_exp;
143	__le32		delta_slope_coeff_man;
144	__le32		delta_slope_coeff_exp_shgi;
145	__le32		delta_slope_coeff_man_shgi;
146	__le32		finiteLoopCount;
147} __packed;
148#define CARL9170_RF_INIT_SIZE		28
149
150struct carl9170_rf_init_result {
151	__le32		ret;		/* AR9170_PHY_REG_AGC_CONTROL */
152} __packed;
153#define	CARL9170_RF_INIT_RESULT_SIZE	4
154
155#define	CARL9170_PSM_SLEEP		0x1000
156#define	CARL9170_PSM_SOFTWARE		0
157#define	CARL9170_PSM_WAKE		0 /* internally used. */
158#define	CARL9170_PSM_COUNTER		0xfff
159#define	CARL9170_PSM_COUNTER_S		0
160
161struct carl9170_psm {
162	__le32		state;
163} __packed;
164#define CARL9170_PSM_SIZE		4
165
166/*
167 * Note: If a bit in rx_filter is set, then it
168 * means that the particular frames which matches
169 * the condition are FILTERED/REMOVED/DISCARDED!
170 * (This is can be a bit confusing, especially
171 * because someone people think it's the exact
172 * opposite way, so watch out!)
173 */
174struct carl9170_rx_filter_cmd {
175	__le32		rx_filter;
176} __packed;
177#define CARL9170_RX_FILTER_CMD_SIZE	4
178
179#define CARL9170_RX_FILTER_BAD		0x01
180#define CARL9170_RX_FILTER_OTHER_RA	0x02
181#define CARL9170_RX_FILTER_DECRY_FAIL	0x04
182#define CARL9170_RX_FILTER_CTL_OTHER	0x08
183#define CARL9170_RX_FILTER_CTL_PSPOLL	0x10
184#define CARL9170_RX_FILTER_CTL_BACKR	0x20
185#define CARL9170_RX_FILTER_MGMT		0x40
186#define CARL9170_RX_FILTER_DATA		0x80
187#define CARL9170_RX_FILTER_EVERYTHING	(~0)
188
189struct carl9170_bcn_ctrl_cmd {
190	__le32		vif_id;
191	__le32		mode;
192	__le32		bcn_addr;
193	__le32		bcn_len;
194} __packed;
195#define CARL9170_BCN_CTRL_CMD_SIZE	16
196
197#define CARL9170_BCN_CTRL_DRAIN	0
198#define CARL9170_BCN_CTRL_CAB_TRIGGER	1
199
200struct carl9170_wol_cmd {
201	__le32		flags;
202	u8		mac[6];
203	u8		bssid[6];
204	__le32		null_interval;
205	__le32		free_for_use2;
206	__le32		mask;
207	u8		pattern[32];
208} __packed;
209
210#define CARL9170_WOL_CMD_SIZE		60
211
212#define CARL9170_WOL_DISCONNECT		1
213#define CARL9170_WOL_MAGIC_PKT		2
214
215struct carl9170_cmd_head {
216	union {
217		struct {
218			u8	len;
219			u8	cmd;
220			u8	seq;
221			u8	ext;
222		} __packed;
223
224		u32 hdr_data;
225	} __packed;
226} __packed;
227
228struct carl9170_cmd {
229	struct carl9170_cmd_head hdr;
230	union {
231		struct carl9170_set_key_cmd	setkey;
232		struct carl9170_disable_key_cmd	disablekey;
233		struct carl9170_u32_list	echo;
234		struct carl9170_reg_list	rreg;
235		struct carl9170_write_reg	wreg;
236		struct carl9170_write_reg_byte	wregb;
237		struct carl9170_rf_init		rf_init;
238		struct carl9170_psm		psm;
239		struct carl9170_wol_cmd		wol;
240		struct carl9170_bcn_ctrl_cmd	bcn_ctrl;
241		struct carl9170_rx_filter_cmd	rx_filter;
242		u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
243	} __packed;
244} __packed __aligned(4);
245
246#define	CARL9170_TX_STATUS_QUEUE	3
247#define	CARL9170_TX_STATUS_QUEUE_S	0
248#define	CARL9170_TX_STATUS_RIX_S	2
249#define	CARL9170_TX_STATUS_RIX		(3 << CARL9170_TX_STATUS_RIX_S)
250#define	CARL9170_TX_STATUS_TRIES_S	4
251#define	CARL9170_TX_STATUS_TRIES	(7 << CARL9170_TX_STATUS_TRIES_S)
252#define	CARL9170_TX_STATUS_SUCCESS	0x80
253
254#ifdef __CARL9170FW__
255/*
256 * NOTE:
257 * Both structs [carl9170_tx_status and _carl9170_tx_status]
258 * need to be "bit for bit" in sync.
259 */
260struct carl9170_tx_status {
261	/*
262	 * Beware of compiler bugs in all gcc pre 4.4!
263	 */
264
265	u8 cookie;
266	u8 queue:2;
267	u8 rix:2;
268	u8 tries:3;
269	u8 success:1;
270} __packed;
271#endif /* __CARL9170FW__ */
272
273struct _carl9170_tx_status {
274	/*
275	 * This version should be immune to all alignment bugs.
276	 */
277
278	u8 cookie;
279	u8 info;
280} __packed;
281#define CARL9170_TX_STATUS_SIZE		2
282
283#define	CARL9170_RSP_TX_STATUS_NUM	(CARL9170_MAX_CMD_PAYLOAD_LEN /	\
284					 sizeof(struct _carl9170_tx_status))
285
286#define	CARL9170_TX_MAX_RATE_TRIES	7
287
288#define	CARL9170_TX_MAX_RATES		4
289#define	CARL9170_TX_MAX_RETRY_RATES	(CARL9170_TX_MAX_RATES - 1)
290#define	CARL9170_ERR_MAGIC		"ERR:"
291#define	CARL9170_BUG_MAGIC		"BUG:"
292
293struct carl9170_gpio {
294	__le32 gpio;
295} __packed;
296#define CARL9170_GPIO_SIZE		4
297
298struct carl9170_tsf_rsp {
299	union {
300		__le32 tsf[2];
301		__le64 tsf_64;
302	} __packed;
303} __packed;
304#define CARL9170_TSF_RSP_SIZE		8
305
306struct carl9170_tally_rsp {
307	__le32 active;
308	__le32 cca;
309	__le32 tx_time;
310	__le32 rx_total;
311	__le32 rx_overrun;
312	__le32 tick;
313} __packed;
314
315struct carl9170_rsp {
316	struct carl9170_cmd_head hdr;
317
318	union {
319		struct carl9170_rf_init_result	rf_init_res;
320		struct carl9170_u32_list	rreg_res;
321		struct carl9170_u32_list	echo;
322#ifdef __CARL9170FW__
323		struct carl9170_tx_status	tx_status[0];
324#endif /* __CARL9170FW__ */
325		struct _carl9170_tx_status	_tx_status[0];
326		struct carl9170_gpio		gpio;
327		struct carl9170_tsf_rsp		tsf;
328		struct carl9170_psm		psm;
329		struct carl9170_tally_rsp	tally;
330		u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
331	} __packed;
332} __packed __aligned(4);
333
334#endif /* __CARL9170_SHARED_FWCMD_H */
v3.15
  1/*
  2 * Shared Atheros AR9170 Header
  3 *
  4 * Firmware command interface definitions
  5 *
  6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
  7 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
  8 *
  9 * This program is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License as published by
 11 * the Free Software Foundation; either version 2 of the License.
 12 *
 13 * This program is distributed in the hope that it will be useful,
 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16 * GNU General Public License for more details.
 17 *
 18 * You should have received a copy of the GNU General Public License
 19 * along with this program; see the file COPYING.  If not, see
 20 * http://www.gnu.org/licenses/.
 21 *
 22 * This file incorporates work covered by the following copyright and
 23 * permission notice:
 24 *    Copyright (c) 2007-2008 Atheros Communications, Inc.
 25 *
 26 *    Permission to use, copy, modify, and/or distribute this software for any
 27 *    purpose with or without fee is hereby granted, provided that the above
 28 *    copyright notice and this permission notice appear in all copies.
 29 *
 30 *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 31 *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 32 *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 33 *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 34 *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 35 *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 36 *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 37 */
 38
 39#ifndef __CARL9170_SHARED_FWCMD_H
 40#define __CARL9170_SHARED_FWCMD_H
 41
 42#define	CARL9170_MAX_CMD_LEN		64
 43#define	CARL9170_MAX_CMD_PAYLOAD_LEN	60
 44
 45#define CARL9170FW_API_MIN_VER		1
 46#define CARL9170FW_API_MAX_VER		1
 47
 48enum carl9170_cmd_oids {
 49	CARL9170_CMD_RREG		= 0x00,
 50	CARL9170_CMD_WREG		= 0x01,
 51	CARL9170_CMD_ECHO		= 0x02,
 52	CARL9170_CMD_SWRST		= 0x03,
 53	CARL9170_CMD_REBOOT		= 0x04,
 54	CARL9170_CMD_BCN_CTRL		= 0x05,
 55	CARL9170_CMD_READ_TSF		= 0x06,
 56	CARL9170_CMD_RX_FILTER		= 0x07,
 57	CARL9170_CMD_WOL		= 0x08,
 58	CARL9170_CMD_TALLY		= 0x09,
 
 59
 60	/* CAM */
 61	CARL9170_CMD_EKEY		= 0x10,
 62	CARL9170_CMD_DKEY		= 0x11,
 63
 64	/* RF / PHY */
 65	CARL9170_CMD_FREQUENCY		= 0x20,
 66	CARL9170_CMD_RF_INIT		= 0x21,
 67	CARL9170_CMD_SYNTH		= 0x22,
 68	CARL9170_CMD_FREQ_START		= 0x23,
 69	CARL9170_CMD_PSM		= 0x24,
 70
 71	/* Asychronous command flag */
 72	CARL9170_CMD_ASYNC_FLAG		= 0x40,
 73	CARL9170_CMD_WREG_ASYNC		= (CARL9170_CMD_WREG |
 74					   CARL9170_CMD_ASYNC_FLAG),
 75	CARL9170_CMD_REBOOT_ASYNC	= (CARL9170_CMD_REBOOT |
 76					   CARL9170_CMD_ASYNC_FLAG),
 77	CARL9170_CMD_BCN_CTRL_ASYNC	= (CARL9170_CMD_BCN_CTRL |
 78					   CARL9170_CMD_ASYNC_FLAG),
 79	CARL9170_CMD_PSM_ASYNC		= (CARL9170_CMD_PSM |
 80					   CARL9170_CMD_ASYNC_FLAG),
 81
 82	/* responses and traps */
 83	CARL9170_RSP_FLAG		= 0xc0,
 84	CARL9170_RSP_PRETBTT		= 0xc0,
 85	CARL9170_RSP_TXCOMP		= 0xc1,
 86	CARL9170_RSP_BEACON_CONFIG	= 0xc2,
 87	CARL9170_RSP_ATIM		= 0xc3,
 88	CARL9170_RSP_WATCHDOG		= 0xc6,
 89	CARL9170_RSP_TEXT		= 0xca,
 90	CARL9170_RSP_HEXDUMP		= 0xcc,
 91	CARL9170_RSP_RADAR		= 0xcd,
 92	CARL9170_RSP_GPIO		= 0xce,
 93	CARL9170_RSP_BOOT		= 0xcf,
 94};
 95
 96struct carl9170_set_key_cmd {
 97	__le16		user;
 98	__le16		keyId;
 99	__le16		type;
100	u8		macAddr[6];
101	u32		key[4];
102} __packed __aligned(4);
103#define CARL9170_SET_KEY_CMD_SIZE		28
104
105struct carl9170_disable_key_cmd {
106	__le16		user;
107	__le16		padding;
108} __packed __aligned(4);
109#define CARL9170_DISABLE_KEY_CMD_SIZE		4
110
111struct carl9170_u32_list {
112	u32	vals[0];
113} __packed;
114
115struct carl9170_reg_list {
116	__le32		regs[0];
117} __packed;
118
119struct carl9170_write_reg {
120	struct {
121		__le32		addr;
122		__le32		val;
123	} regs[0] __packed;
124} __packed;
125
 
 
 
 
 
 
126#define	CARL9170FW_PHY_HT_ENABLE		0x4
127#define	CARL9170FW_PHY_HT_DYN2040		0x8
128#define	CARL9170FW_PHY_HT_EXT_CHAN_OFF		0x3
129#define	CARL9170FW_PHY_HT_EXT_CHAN_OFF_S	2
130
131struct carl9170_rf_init {
132	__le32		freq;
133	u8		ht_settings;
134	u8		padding2[3];
135	__le32		delta_slope_coeff_exp;
136	__le32		delta_slope_coeff_man;
137	__le32		delta_slope_coeff_exp_shgi;
138	__le32		delta_slope_coeff_man_shgi;
139	__le32		finiteLoopCount;
140} __packed;
141#define CARL9170_RF_INIT_SIZE		28
142
143struct carl9170_rf_init_result {
144	__le32		ret;		/* AR9170_PHY_REG_AGC_CONTROL */
145} __packed;
146#define	CARL9170_RF_INIT_RESULT_SIZE	4
147
148#define	CARL9170_PSM_SLEEP		0x1000
149#define	CARL9170_PSM_SOFTWARE		0
150#define	CARL9170_PSM_WAKE		0 /* internally used. */
151#define	CARL9170_PSM_COUNTER		0xfff
152#define	CARL9170_PSM_COUNTER_S		0
153
154struct carl9170_psm {
155	__le32		state;
156} __packed;
157#define CARL9170_PSM_SIZE		4
158
159/*
160 * Note: If a bit in rx_filter is set, then it
161 * means that the particular frames which matches
162 * the condition are FILTERED/REMOVED/DISCARDED!
163 * (This is can be a bit confusing, especially
164 * because someone people think it's the exact
165 * opposite way, so watch out!)
166 */
167struct carl9170_rx_filter_cmd {
168	__le32		rx_filter;
169} __packed;
170#define CARL9170_RX_FILTER_CMD_SIZE	4
171
172#define CARL9170_RX_FILTER_BAD		0x01
173#define CARL9170_RX_FILTER_OTHER_RA	0x02
174#define CARL9170_RX_FILTER_DECRY_FAIL	0x04
175#define CARL9170_RX_FILTER_CTL_OTHER	0x08
176#define CARL9170_RX_FILTER_CTL_PSPOLL	0x10
177#define CARL9170_RX_FILTER_CTL_BACKR	0x20
178#define CARL9170_RX_FILTER_MGMT		0x40
179#define CARL9170_RX_FILTER_DATA		0x80
180#define CARL9170_RX_FILTER_EVERYTHING	(~0)
181
182struct carl9170_bcn_ctrl_cmd {
183	__le32		vif_id;
184	__le32		mode;
185	__le32		bcn_addr;
186	__le32		bcn_len;
187} __packed;
188#define CARL9170_BCN_CTRL_CMD_SIZE	16
189
190#define CARL9170_BCN_CTRL_DRAIN	0
191#define CARL9170_BCN_CTRL_CAB_TRIGGER	1
192
193struct carl9170_wol_cmd {
194	__le32		flags;
195	u8		mac[6];
196	u8		bssid[6];
197	__le32		null_interval;
198	__le32		free_for_use2;
199	__le32		mask;
200	u8		pattern[32];
201} __packed;
202
203#define CARL9170_WOL_CMD_SIZE		60
204
205#define CARL9170_WOL_DISCONNECT		1
206#define CARL9170_WOL_MAGIC_PKT		2
207
208struct carl9170_cmd_head {
209	union {
210		struct {
211			u8	len;
212			u8	cmd;
213			u8	seq;
214			u8	ext;
215		} __packed;
216
217		u32 hdr_data;
218	} __packed;
219} __packed;
220
221struct carl9170_cmd {
222	struct carl9170_cmd_head hdr;
223	union {
224		struct carl9170_set_key_cmd	setkey;
225		struct carl9170_disable_key_cmd	disablekey;
226		struct carl9170_u32_list	echo;
227		struct carl9170_reg_list	rreg;
228		struct carl9170_write_reg	wreg;
 
229		struct carl9170_rf_init		rf_init;
230		struct carl9170_psm		psm;
231		struct carl9170_wol_cmd		wol;
232		struct carl9170_bcn_ctrl_cmd	bcn_ctrl;
233		struct carl9170_rx_filter_cmd	rx_filter;
234		u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
235	} __packed;
236} __packed __aligned(4);
237
238#define	CARL9170_TX_STATUS_QUEUE	3
239#define	CARL9170_TX_STATUS_QUEUE_S	0
240#define	CARL9170_TX_STATUS_RIX_S	2
241#define	CARL9170_TX_STATUS_RIX		(3 << CARL9170_TX_STATUS_RIX_S)
242#define	CARL9170_TX_STATUS_TRIES_S	4
243#define	CARL9170_TX_STATUS_TRIES	(7 << CARL9170_TX_STATUS_TRIES_S)
244#define	CARL9170_TX_STATUS_SUCCESS	0x80
245
246#ifdef __CARL9170FW__
247/*
248 * NOTE:
249 * Both structs [carl9170_tx_status and _carl9170_tx_status]
250 * need to be "bit for bit" in sync.
251 */
252struct carl9170_tx_status {
253	/*
254	 * Beware of compiler bugs in all gcc pre 4.4!
255	 */
256
257	u8 cookie;
258	u8 queue:2;
259	u8 rix:2;
260	u8 tries:3;
261	u8 success:1;
262} __packed;
263#endif /* __CARL9170FW__ */
264
265struct _carl9170_tx_status {
266	/*
267	 * This version should be immune to all alignment bugs.
268	 */
269
270	u8 cookie;
271	u8 info;
272} __packed;
273#define CARL9170_TX_STATUS_SIZE		2
274
275#define	CARL9170_RSP_TX_STATUS_NUM	(CARL9170_MAX_CMD_PAYLOAD_LEN /	\
276					 sizeof(struct _carl9170_tx_status))
277
278#define	CARL9170_TX_MAX_RATE_TRIES	7
279
280#define	CARL9170_TX_MAX_RATES		4
281#define	CARL9170_TX_MAX_RETRY_RATES	(CARL9170_TX_MAX_RATES - 1)
282#define	CARL9170_ERR_MAGIC		"ERR:"
283#define	CARL9170_BUG_MAGIC		"BUG:"
284
285struct carl9170_gpio {
286	__le32 gpio;
287} __packed;
288#define CARL9170_GPIO_SIZE		4
289
290struct carl9170_tsf_rsp {
291	union {
292		__le32 tsf[2];
293		__le64 tsf_64;
294	} __packed;
295} __packed;
296#define CARL9170_TSF_RSP_SIZE		8
297
298struct carl9170_tally_rsp {
299	__le32 active;
300	__le32 cca;
301	__le32 tx_time;
302	__le32 rx_total;
303	__le32 rx_overrun;
304	__le32 tick;
305} __packed;
306
307struct carl9170_rsp {
308	struct carl9170_cmd_head hdr;
309
310	union {
311		struct carl9170_rf_init_result	rf_init_res;
312		struct carl9170_u32_list	rreg_res;
313		struct carl9170_u32_list	echo;
314#ifdef __CARL9170FW__
315		struct carl9170_tx_status	tx_status[0];
316#endif /* __CARL9170FW__ */
317		struct _carl9170_tx_status	_tx_status[0];
318		struct carl9170_gpio		gpio;
319		struct carl9170_tsf_rsp		tsf;
320		struct carl9170_psm		psm;
321		struct carl9170_tally_rsp	tally;
322		u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
323	} __packed;
324} __packed __aligned(4);
325
326#endif /* __CARL9170_SHARED_FWCMD_H */