Loading...
1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/component.h>
19#include <linux/hdmi.h>
20#include <linux/module.h>
21#include <linux/irq.h>
22#include <sound/asoundef.h>
23#include <sound/hdmi-codec.h>
24
25#include <drm/drmP.h>
26#include <drm/drm_atomic_helper.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/drm_edid.h>
29#include <drm/drm_of.h>
30#include <drm/i2c/tda998x.h>
31
32#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
33
34struct tda998x_audio_port {
35 u8 format; /* AFMT_xxx */
36 u8 config; /* AP value */
37};
38
39struct tda998x_priv {
40 struct i2c_client *cec;
41 struct i2c_client *hdmi;
42 struct mutex mutex;
43 u16 rev;
44 u8 cec_addr;
45 u8 current_page;
46 bool is_on;
47 bool supports_infoframes;
48 bool sink_has_audio;
49 u8 vip_cntrl_0;
50 u8 vip_cntrl_1;
51 u8 vip_cntrl_2;
52 unsigned long tmds_clock;
53 struct tda998x_audio_params audio_params;
54
55 struct platform_device *audio_pdev;
56 struct mutex audio_mutex;
57
58 wait_queue_head_t wq_edid;
59 volatile int wq_edid_wait;
60
61 struct work_struct detect_work;
62 struct timer_list edid_delay_timer;
63 wait_queue_head_t edid_delay_waitq;
64 bool edid_delay_active;
65
66 struct drm_encoder encoder;
67 struct drm_connector connector;
68
69 struct tda998x_audio_port audio_port[2];
70};
71
72#define conn_to_tda998x_priv(x) \
73 container_of(x, struct tda998x_priv, connector)
74
75#define enc_to_tda998x_priv(x) \
76 container_of(x, struct tda998x_priv, encoder)
77
78/* The TDA9988 series of devices use a paged register scheme.. to simplify
79 * things we encode the page # in upper bits of the register #. To read/
80 * write a given register, we need to make sure CURPAGE register is set
81 * appropriately. Which implies reads/writes are not atomic. Fun!
82 */
83
84#define REG(page, addr) (((page) << 8) | (addr))
85#define REG2ADDR(reg) ((reg) & 0xff)
86#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
87
88#define REG_CURPAGE 0xff /* write */
89
90
91/* Page 00h: General Control */
92#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
93#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
94# define MAIN_CNTRL0_SR (1 << 0)
95# define MAIN_CNTRL0_DECS (1 << 1)
96# define MAIN_CNTRL0_DEHS (1 << 2)
97# define MAIN_CNTRL0_CECS (1 << 3)
98# define MAIN_CNTRL0_CEHS (1 << 4)
99# define MAIN_CNTRL0_SCALER (1 << 7)
100#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
101#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
102# define SOFTRESET_AUDIO (1 << 0)
103# define SOFTRESET_I2C_MASTER (1 << 1)
104#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
105#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
106#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
107# define I2C_MASTER_DIS_MM (1 << 0)
108# define I2C_MASTER_DIS_FILT (1 << 1)
109# define I2C_MASTER_APP_STRT_LAT (1 << 2)
110#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
111# define FEAT_POWERDOWN_PREFILT BIT(0)
112# define FEAT_POWERDOWN_CSC BIT(1)
113# define FEAT_POWERDOWN_SPDIF (1 << 3)
114#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
115#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
116#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
117# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
118#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
119#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
120#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
121#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
122#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
123#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
124# define VIP_CNTRL_0_MIRR_A (1 << 7)
125# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
126# define VIP_CNTRL_0_MIRR_B (1 << 3)
127# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
128#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
129# define VIP_CNTRL_1_MIRR_C (1 << 7)
130# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
131# define VIP_CNTRL_1_MIRR_D (1 << 3)
132# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
133#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
134# define VIP_CNTRL_2_MIRR_E (1 << 7)
135# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
136# define VIP_CNTRL_2_MIRR_F (1 << 3)
137# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
138#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
139# define VIP_CNTRL_3_X_TGL (1 << 0)
140# define VIP_CNTRL_3_H_TGL (1 << 1)
141# define VIP_CNTRL_3_V_TGL (1 << 2)
142# define VIP_CNTRL_3_EMB (1 << 3)
143# define VIP_CNTRL_3_SYNC_DE (1 << 4)
144# define VIP_CNTRL_3_SYNC_HS (1 << 5)
145# define VIP_CNTRL_3_DE_INT (1 << 6)
146# define VIP_CNTRL_3_EDGE (1 << 7)
147#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
148# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
149# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
150# define VIP_CNTRL_4_CCIR656 (1 << 4)
151# define VIP_CNTRL_4_656_ALT (1 << 5)
152# define VIP_CNTRL_4_TST_656 (1 << 6)
153# define VIP_CNTRL_4_TST_PAT (1 << 7)
154#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
155# define VIP_CNTRL_5_CKCASE (1 << 0)
156# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
157#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
158# define MUX_AP_SELECT_I2S 0x64
159# define MUX_AP_SELECT_SPDIF 0x40
160#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
161#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
162# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
163# define MAT_CONTRL_MAT_BP (1 << 2)
164#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
165#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
166#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
167#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
168#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
169#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
170#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
171#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
172#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
173#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
174#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
175#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
176#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
177#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
178#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
179#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
180#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
181#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
182#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
183#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
184#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
185#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
186#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
187#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
188#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
189#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
190#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
191#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
192#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
193#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
194#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
195#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
196#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
197#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
198#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
199#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
200#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
201#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
202#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
203#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
204#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
205#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
206# define TBG_CNTRL_0_TOP_TGL (1 << 0)
207# define TBG_CNTRL_0_TOP_SEL (1 << 1)
208# define TBG_CNTRL_0_DE_EXT (1 << 2)
209# define TBG_CNTRL_0_TOP_EXT (1 << 3)
210# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
211# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
212# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
213#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
214# define TBG_CNTRL_1_H_TGL (1 << 0)
215# define TBG_CNTRL_1_V_TGL (1 << 1)
216# define TBG_CNTRL_1_TGL_EN (1 << 2)
217# define TBG_CNTRL_1_X_EXT (1 << 3)
218# define TBG_CNTRL_1_H_EXT (1 << 4)
219# define TBG_CNTRL_1_V_EXT (1 << 5)
220# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
221#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
222#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
223# define HVF_CNTRL_0_SM (1 << 7)
224# define HVF_CNTRL_0_RWB (1 << 6)
225# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
226# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
227#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
228# define HVF_CNTRL_1_FOR (1 << 0)
229# define HVF_CNTRL_1_YUVBLK (1 << 1)
230# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
231# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
232# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
233#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
234#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
235# define I2S_FORMAT(x) (((x) & 3) << 0)
236#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
237# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
238# define AIP_CLKSEL_AIP_I2S (1 << 3)
239# define AIP_CLKSEL_FS_ACLK (0 << 0)
240# define AIP_CLKSEL_FS_MCLK (1 << 0)
241# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
242
243/* Page 02h: PLL settings */
244#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
245# define PLL_SERIAL_1_SRL_FDN (1 << 0)
246# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
247# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
248#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
249# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
250# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
251#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
252# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
253# define PLL_SERIAL_3_SRL_DE (1 << 2)
254# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
255#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
256#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
257#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
258#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
259#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
260#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
261#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
262#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
263#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
264# define AUDIO_DIV_SERCLK_1 0
265# define AUDIO_DIV_SERCLK_2 1
266# define AUDIO_DIV_SERCLK_4 2
267# define AUDIO_DIV_SERCLK_8 3
268# define AUDIO_DIV_SERCLK_16 4
269# define AUDIO_DIV_SERCLK_32 5
270#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
271# define SEL_CLK_SEL_CLK1 (1 << 0)
272# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
273# define SEL_CLK_ENA_SC_CLK (1 << 3)
274#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
275
276
277/* Page 09h: EDID Control */
278#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
279/* next 127 successive registers are the EDID block */
280#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
281#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
282#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
283#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
284#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
285
286
287/* Page 10h: information frames and packets */
288#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
289#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
290#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
291#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
292#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
293
294
295/* Page 11h: audio settings and content info packets */
296#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
297# define AIP_CNTRL_0_RST_FIFO (1 << 0)
298# define AIP_CNTRL_0_SWAP (1 << 1)
299# define AIP_CNTRL_0_LAYOUT (1 << 2)
300# define AIP_CNTRL_0_ACR_MAN (1 << 5)
301# define AIP_CNTRL_0_RST_CTS (1 << 6)
302#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
303# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
304# define CA_I2S_HBR_CHSTAT (1 << 6)
305#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
306#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
307#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
308#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
309#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
310#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
311#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
312#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
313# define CTS_N_K(x) (((x) & 7) << 0)
314# define CTS_N_M(x) (((x) & 3) << 4)
315#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
316# define ENC_CNTRL_RST_ENC (1 << 0)
317# define ENC_CNTRL_RST_SEL (1 << 1)
318# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
319#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
320# define DIP_FLAGS_ACR (1 << 0)
321# define DIP_FLAGS_GC (1 << 1)
322#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
323# define DIP_IF_FLAGS_IF1 (1 << 1)
324# define DIP_IF_FLAGS_IF2 (1 << 2)
325# define DIP_IF_FLAGS_IF3 (1 << 3)
326# define DIP_IF_FLAGS_IF4 (1 << 4)
327# define DIP_IF_FLAGS_IF5 (1 << 5)
328#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
329
330
331/* Page 12h: HDCP and OTP */
332#define REG_TX3 REG(0x12, 0x9a) /* read/write */
333#define REG_TX4 REG(0x12, 0x9b) /* read/write */
334# define TX4_PD_RAM (1 << 1)
335#define REG_TX33 REG(0x12, 0xb8) /* read/write */
336# define TX33_HDMI (1 << 1)
337
338
339/* Page 13h: Gamut related metadata packets */
340
341
342
343/* CEC registers: (not paged)
344 */
345#define REG_CEC_INTSTATUS 0xee /* read */
346# define CEC_INTSTATUS_CEC (1 << 0)
347# define CEC_INTSTATUS_HDMI (1 << 1)
348#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
349# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
350# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
351# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
352# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
353#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
354#define REG_CEC_RXSHPDINT 0xfd /* read */
355# define CEC_RXSHPDINT_RXSENS BIT(0)
356# define CEC_RXSHPDINT_HPD BIT(1)
357#define REG_CEC_RXSHPDLEV 0xfe /* read */
358# define CEC_RXSHPDLEV_RXSENS (1 << 0)
359# define CEC_RXSHPDLEV_HPD (1 << 1)
360
361#define REG_CEC_ENAMODS 0xff /* read/write */
362# define CEC_ENAMODS_DIS_FRO (1 << 6)
363# define CEC_ENAMODS_DIS_CCLK (1 << 5)
364# define CEC_ENAMODS_EN_RXSENS (1 << 2)
365# define CEC_ENAMODS_EN_HDMI (1 << 1)
366# define CEC_ENAMODS_EN_CEC (1 << 0)
367
368
369/* Device versions: */
370#define TDA9989N2 0x0101
371#define TDA19989 0x0201
372#define TDA19989N2 0x0202
373#define TDA19988 0x0301
374
375static void
376cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
377{
378 u8 buf[] = {addr, val};
379 struct i2c_msg msg = {
380 .addr = priv->cec_addr,
381 .len = 2,
382 .buf = buf,
383 };
384 int ret;
385
386 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
387 if (ret < 0)
388 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
389 ret, addr);
390}
391
392static u8
393cec_read(struct tda998x_priv *priv, u8 addr)
394{
395 u8 val;
396 struct i2c_msg msg[2] = {
397 {
398 .addr = priv->cec_addr,
399 .len = 1,
400 .buf = &addr,
401 }, {
402 .addr = priv->cec_addr,
403 .flags = I2C_M_RD,
404 .len = 1,
405 .buf = &val,
406 },
407 };
408 int ret;
409
410 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
411 if (ret < 0) {
412 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
413 ret, addr);
414 val = 0;
415 }
416
417 return val;
418}
419
420static int
421set_page(struct tda998x_priv *priv, u16 reg)
422{
423 if (REG2PAGE(reg) != priv->current_page) {
424 struct i2c_client *client = priv->hdmi;
425 u8 buf[] = {
426 REG_CURPAGE, REG2PAGE(reg)
427 };
428 int ret = i2c_master_send(client, buf, sizeof(buf));
429 if (ret < 0) {
430 dev_err(&client->dev, "%s %04x err %d\n", __func__,
431 reg, ret);
432 return ret;
433 }
434
435 priv->current_page = REG2PAGE(reg);
436 }
437 return 0;
438}
439
440static int
441reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
442{
443 struct i2c_client *client = priv->hdmi;
444 u8 addr = REG2ADDR(reg);
445 int ret;
446
447 mutex_lock(&priv->mutex);
448 ret = set_page(priv, reg);
449 if (ret < 0)
450 goto out;
451
452 ret = i2c_master_send(client, &addr, sizeof(addr));
453 if (ret < 0)
454 goto fail;
455
456 ret = i2c_master_recv(client, buf, cnt);
457 if (ret < 0)
458 goto fail;
459
460 goto out;
461
462fail:
463 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
464out:
465 mutex_unlock(&priv->mutex);
466 return ret;
467}
468
469static void
470reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
471{
472 struct i2c_client *client = priv->hdmi;
473 u8 buf[cnt+1];
474 int ret;
475
476 buf[0] = REG2ADDR(reg);
477 memcpy(&buf[1], p, cnt);
478
479 mutex_lock(&priv->mutex);
480 ret = set_page(priv, reg);
481 if (ret < 0)
482 goto out;
483
484 ret = i2c_master_send(client, buf, cnt + 1);
485 if (ret < 0)
486 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
487out:
488 mutex_unlock(&priv->mutex);
489}
490
491static int
492reg_read(struct tda998x_priv *priv, u16 reg)
493{
494 u8 val = 0;
495 int ret;
496
497 ret = reg_read_range(priv, reg, &val, sizeof(val));
498 if (ret < 0)
499 return ret;
500 return val;
501}
502
503static void
504reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
505{
506 struct i2c_client *client = priv->hdmi;
507 u8 buf[] = {REG2ADDR(reg), val};
508 int ret;
509
510 mutex_lock(&priv->mutex);
511 ret = set_page(priv, reg);
512 if (ret < 0)
513 goto out;
514
515 ret = i2c_master_send(client, buf, sizeof(buf));
516 if (ret < 0)
517 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
518out:
519 mutex_unlock(&priv->mutex);
520}
521
522static void
523reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
524{
525 struct i2c_client *client = priv->hdmi;
526 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
527 int ret;
528
529 mutex_lock(&priv->mutex);
530 ret = set_page(priv, reg);
531 if (ret < 0)
532 goto out;
533
534 ret = i2c_master_send(client, buf, sizeof(buf));
535 if (ret < 0)
536 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
537out:
538 mutex_unlock(&priv->mutex);
539}
540
541static void
542reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
543{
544 int old_val;
545
546 old_val = reg_read(priv, reg);
547 if (old_val >= 0)
548 reg_write(priv, reg, old_val | val);
549}
550
551static void
552reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
553{
554 int old_val;
555
556 old_val = reg_read(priv, reg);
557 if (old_val >= 0)
558 reg_write(priv, reg, old_val & ~val);
559}
560
561static void
562tda998x_reset(struct tda998x_priv *priv)
563{
564 /* reset audio and i2c master: */
565 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
566 msleep(50);
567 reg_write(priv, REG_SOFTRESET, 0);
568 msleep(50);
569
570 /* reset transmitter: */
571 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
572 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
573
574 /* PLL registers common configuration */
575 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
576 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
577 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
578 reg_write(priv, REG_SERIALIZER, 0x00);
579 reg_write(priv, REG_BUFFER_OUT, 0x00);
580 reg_write(priv, REG_PLL_SCG1, 0x00);
581 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
582 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
583 reg_write(priv, REG_PLL_SCGN1, 0xfa);
584 reg_write(priv, REG_PLL_SCGN2, 0x00);
585 reg_write(priv, REG_PLL_SCGR1, 0x5b);
586 reg_write(priv, REG_PLL_SCGR2, 0x00);
587 reg_write(priv, REG_PLL_SCG2, 0x10);
588
589 /* Write the default value MUX register */
590 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
591}
592
593/*
594 * The TDA998x has a problem when trying to read the EDID close to a
595 * HPD assertion: it needs a delay of 100ms to avoid timing out while
596 * trying to read EDID data.
597 *
598 * However, tda998x_connector_get_modes() may be called at any moment
599 * after tda998x_connector_detect() indicates that we are connected, so
600 * we need to delay probing modes in tda998x_connector_get_modes() after
601 * we have seen a HPD inactive->active transition. This code implements
602 * that delay.
603 */
604static void tda998x_edid_delay_done(unsigned long data)
605{
606 struct tda998x_priv *priv = (struct tda998x_priv *)data;
607
608 priv->edid_delay_active = false;
609 wake_up(&priv->edid_delay_waitq);
610 schedule_work(&priv->detect_work);
611}
612
613static void tda998x_edid_delay_start(struct tda998x_priv *priv)
614{
615 priv->edid_delay_active = true;
616 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
617}
618
619static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
620{
621 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
622}
623
624/*
625 * We need to run the KMS hotplug event helper outside of our threaded
626 * interrupt routine as this can call back into our get_modes method,
627 * which will want to make use of interrupts.
628 */
629static void tda998x_detect_work(struct work_struct *work)
630{
631 struct tda998x_priv *priv =
632 container_of(work, struct tda998x_priv, detect_work);
633 struct drm_device *dev = priv->encoder.dev;
634
635 if (dev)
636 drm_kms_helper_hotplug_event(dev);
637}
638
639/*
640 * only 2 interrupts may occur: screen plug/unplug and EDID read
641 */
642static irqreturn_t tda998x_irq_thread(int irq, void *data)
643{
644 struct tda998x_priv *priv = data;
645 u8 sta, cec, lvl, flag0, flag1, flag2;
646 bool handled = false;
647
648 sta = cec_read(priv, REG_CEC_INTSTATUS);
649 if (sta & CEC_INTSTATUS_HDMI) {
650 cec = cec_read(priv, REG_CEC_RXSHPDINT);
651 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
652 flag0 = reg_read(priv, REG_INT_FLAGS_0);
653 flag1 = reg_read(priv, REG_INT_FLAGS_1);
654 flag2 = reg_read(priv, REG_INT_FLAGS_2);
655 DRM_DEBUG_DRIVER(
656 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
657 sta, cec, lvl, flag0, flag1, flag2);
658
659 if (cec & CEC_RXSHPDINT_HPD) {
660 if (lvl & CEC_RXSHPDLEV_HPD)
661 tda998x_edid_delay_start(priv);
662 else
663 schedule_work(&priv->detect_work);
664
665 handled = true;
666 }
667
668 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
669 priv->wq_edid_wait = 0;
670 wake_up(&priv->wq_edid);
671 handled = true;
672 }
673 }
674
675 return IRQ_RETVAL(handled);
676}
677
678static void
679tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
680 union hdmi_infoframe *frame)
681{
682 u8 buf[32];
683 ssize_t len;
684
685 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
686 if (len < 0) {
687 dev_err(&priv->hdmi->dev,
688 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
689 frame->any.type, len);
690 return;
691 }
692
693 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
694 reg_write_range(priv, addr, buf, len);
695 reg_set(priv, REG_DIP_IF_FLAGS, bit);
696}
697
698static int tda998x_write_aif(struct tda998x_priv *priv,
699 struct hdmi_audio_infoframe *cea)
700{
701 union hdmi_infoframe frame;
702
703 frame.audio = *cea;
704
705 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
706
707 return 0;
708}
709
710static void
711tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
712{
713 union hdmi_infoframe frame;
714
715 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
716 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
717
718 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
719}
720
721/* Audio support */
722
723static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
724{
725 if (on) {
726 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
727 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
728 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
729 } else {
730 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
731 }
732}
733
734static int
735tda998x_configure_audio(struct tda998x_priv *priv,
736 struct tda998x_audio_params *params)
737{
738 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
739 u32 n;
740
741 /* Enable audio ports */
742 reg_write(priv, REG_ENA_AP, params->config);
743
744 /* Set audio input source */
745 switch (params->format) {
746 case AFMT_SPDIF:
747 reg_write(priv, REG_ENA_ACLK, 0);
748 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
749 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
750 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
751 cts_n = CTS_N_M(3) | CTS_N_K(3);
752 break;
753
754 case AFMT_I2S:
755 reg_write(priv, REG_ENA_ACLK, 1);
756 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
757 clksel_aip = AIP_CLKSEL_AIP_I2S;
758 clksel_fs = AIP_CLKSEL_FS_ACLK;
759 switch (params->sample_width) {
760 case 16:
761 cts_n = CTS_N_M(3) | CTS_N_K(1);
762 break;
763 case 18:
764 case 20:
765 case 24:
766 cts_n = CTS_N_M(3) | CTS_N_K(2);
767 break;
768 default:
769 case 32:
770 cts_n = CTS_N_M(3) | CTS_N_K(3);
771 break;
772 }
773 break;
774
775 default:
776 dev_err(&priv->hdmi->dev, "Unsupported I2S format\n");
777 return -EINVAL;
778 }
779
780 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
781 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
782 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
783 reg_write(priv, REG_CTS_N, cts_n);
784
785 /*
786 * Audio input somehow depends on HDMI line rate which is
787 * related to pixclk. Testing showed that modes with pixclk
788 * >100MHz need a larger divider while <40MHz need the default.
789 * There is no detailed info in the datasheet, so we just
790 * assume 100MHz requires larger divider.
791 */
792 adiv = AUDIO_DIV_SERCLK_8;
793 if (priv->tmds_clock > 100000)
794 adiv++; /* AUDIO_DIV_SERCLK_16 */
795
796 /* S/PDIF asks for a larger divider */
797 if (params->format == AFMT_SPDIF)
798 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
799
800 reg_write(priv, REG_AUDIO_DIV, adiv);
801
802 /*
803 * This is the approximate value of N, which happens to be
804 * the recommended values for non-coherent clocks.
805 */
806 n = 128 * params->sample_rate / 1000;
807
808 /* Write the CTS and N values */
809 buf[0] = 0x44;
810 buf[1] = 0x42;
811 buf[2] = 0x01;
812 buf[3] = n;
813 buf[4] = n >> 8;
814 buf[5] = n >> 16;
815 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
816
817 /* Set CTS clock reference */
818 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
819
820 /* Reset CTS generator */
821 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
822 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
823
824 /* Write the channel status
825 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
826 * there is a separate register for each I2S wire.
827 */
828 buf[0] = params->status[0];
829 buf[1] = params->status[1];
830 buf[2] = params->status[3];
831 buf[3] = params->status[4];
832 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
833
834 tda998x_audio_mute(priv, true);
835 msleep(20);
836 tda998x_audio_mute(priv, false);
837
838 return tda998x_write_aif(priv, ¶ms->cea);
839}
840
841static int tda998x_audio_hw_params(struct device *dev, void *data,
842 struct hdmi_codec_daifmt *daifmt,
843 struct hdmi_codec_params *params)
844{
845 struct tda998x_priv *priv = dev_get_drvdata(dev);
846 int i, ret;
847 struct tda998x_audio_params audio = {
848 .sample_width = params->sample_width,
849 .sample_rate = params->sample_rate,
850 .cea = params->cea,
851 };
852
853 memcpy(audio.status, params->iec.status,
854 min(sizeof(audio.status), sizeof(params->iec.status)));
855
856 switch (daifmt->fmt) {
857 case HDMI_I2S:
858 if (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
859 daifmt->bit_clk_master || daifmt->frame_clk_master) {
860 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
861 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
862 daifmt->bit_clk_master,
863 daifmt->frame_clk_master);
864 return -EINVAL;
865 }
866 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
867 if (priv->audio_port[i].format == AFMT_I2S)
868 audio.config = priv->audio_port[i].config;
869 audio.format = AFMT_I2S;
870 break;
871 case HDMI_SPDIF:
872 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
873 if (priv->audio_port[i].format == AFMT_SPDIF)
874 audio.config = priv->audio_port[i].config;
875 audio.format = AFMT_SPDIF;
876 break;
877 default:
878 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
879 return -EINVAL;
880 }
881
882 if (audio.config == 0) {
883 dev_err(dev, "%s: No audio configuration found\n", __func__);
884 return -EINVAL;
885 }
886
887 mutex_lock(&priv->audio_mutex);
888 if (priv->supports_infoframes && priv->sink_has_audio)
889 ret = tda998x_configure_audio(priv, &audio);
890 else
891 ret = 0;
892
893 if (ret == 0)
894 priv->audio_params = audio;
895 mutex_unlock(&priv->audio_mutex);
896
897 return ret;
898}
899
900static void tda998x_audio_shutdown(struct device *dev, void *data)
901{
902 struct tda998x_priv *priv = dev_get_drvdata(dev);
903
904 mutex_lock(&priv->audio_mutex);
905
906 reg_write(priv, REG_ENA_AP, 0);
907
908 priv->audio_params.format = AFMT_UNUSED;
909
910 mutex_unlock(&priv->audio_mutex);
911}
912
913int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
914{
915 struct tda998x_priv *priv = dev_get_drvdata(dev);
916
917 mutex_lock(&priv->audio_mutex);
918
919 tda998x_audio_mute(priv, enable);
920
921 mutex_unlock(&priv->audio_mutex);
922 return 0;
923}
924
925static int tda998x_audio_get_eld(struct device *dev, void *data,
926 uint8_t *buf, size_t len)
927{
928 struct tda998x_priv *priv = dev_get_drvdata(dev);
929
930 mutex_lock(&priv->audio_mutex);
931 memcpy(buf, priv->connector.eld,
932 min(sizeof(priv->connector.eld), len));
933 mutex_unlock(&priv->audio_mutex);
934
935 return 0;
936}
937
938static const struct hdmi_codec_ops audio_codec_ops = {
939 .hw_params = tda998x_audio_hw_params,
940 .audio_shutdown = tda998x_audio_shutdown,
941 .digital_mute = tda998x_audio_digital_mute,
942 .get_eld = tda998x_audio_get_eld,
943};
944
945static int tda998x_audio_codec_init(struct tda998x_priv *priv,
946 struct device *dev)
947{
948 struct hdmi_codec_pdata codec_data = {
949 .ops = &audio_codec_ops,
950 .max_i2s_channels = 2,
951 };
952 int i;
953
954 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) {
955 if (priv->audio_port[i].format == AFMT_I2S &&
956 priv->audio_port[i].config != 0)
957 codec_data.i2s = 1;
958 if (priv->audio_port[i].format == AFMT_SPDIF &&
959 priv->audio_port[i].config != 0)
960 codec_data.spdif = 1;
961 }
962
963 priv->audio_pdev = platform_device_register_data(
964 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
965 &codec_data, sizeof(codec_data));
966
967 return PTR_ERR_OR_ZERO(priv->audio_pdev);
968}
969
970/* DRM connector functions */
971
972static int tda998x_connector_dpms(struct drm_connector *connector, int mode)
973{
974 if (drm_core_check_feature(connector->dev, DRIVER_ATOMIC))
975 return drm_atomic_helper_connector_dpms(connector, mode);
976 else
977 return drm_helper_connector_dpms(connector, mode);
978}
979
980static int tda998x_connector_fill_modes(struct drm_connector *connector,
981 uint32_t maxX, uint32_t maxY)
982{
983 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
984 int ret;
985
986 mutex_lock(&priv->audio_mutex);
987 ret = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
988
989 if (connector->edid_blob_ptr) {
990 struct edid *edid = (void *)connector->edid_blob_ptr->data;
991
992 priv->sink_has_audio = drm_detect_monitor_audio(edid);
993 } else {
994 priv->sink_has_audio = false;
995 }
996 mutex_unlock(&priv->audio_mutex);
997
998 return ret;
999}
1000
1001static enum drm_connector_status
1002tda998x_connector_detect(struct drm_connector *connector, bool force)
1003{
1004 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1005 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1006
1007 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1008 connector_status_disconnected;
1009}
1010
1011static void tda998x_connector_destroy(struct drm_connector *connector)
1012{
1013 drm_connector_cleanup(connector);
1014}
1015
1016static const struct drm_connector_funcs tda998x_connector_funcs = {
1017 .dpms = tda998x_connector_dpms,
1018 .reset = drm_atomic_helper_connector_reset,
1019 .fill_modes = tda998x_connector_fill_modes,
1020 .detect = tda998x_connector_detect,
1021 .destroy = tda998x_connector_destroy,
1022 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1023 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1024};
1025
1026static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1027{
1028 struct tda998x_priv *priv = data;
1029 u8 offset, segptr;
1030 int ret, i;
1031
1032 offset = (blk & 1) ? 128 : 0;
1033 segptr = blk / 2;
1034
1035 reg_write(priv, REG_DDC_ADDR, 0xa0);
1036 reg_write(priv, REG_DDC_OFFS, offset);
1037 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1038 reg_write(priv, REG_DDC_SEGM, segptr);
1039
1040 /* enable reading EDID: */
1041 priv->wq_edid_wait = 1;
1042 reg_write(priv, REG_EDID_CTRL, 0x1);
1043
1044 /* flag must be cleared by sw: */
1045 reg_write(priv, REG_EDID_CTRL, 0x0);
1046
1047 /* wait for block read to complete: */
1048 if (priv->hdmi->irq) {
1049 i = wait_event_timeout(priv->wq_edid,
1050 !priv->wq_edid_wait,
1051 msecs_to_jiffies(100));
1052 if (i < 0) {
1053 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1054 return i;
1055 }
1056 } else {
1057 for (i = 100; i > 0; i--) {
1058 msleep(1);
1059 ret = reg_read(priv, REG_INT_FLAGS_2);
1060 if (ret < 0)
1061 return ret;
1062 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1063 break;
1064 }
1065 }
1066
1067 if (i == 0) {
1068 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1069 return -ETIMEDOUT;
1070 }
1071
1072 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1073 if (ret != length) {
1074 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1075 blk, ret);
1076 return ret;
1077 }
1078
1079 return 0;
1080}
1081
1082static int tda998x_connector_get_modes(struct drm_connector *connector)
1083{
1084 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1085 struct edid *edid;
1086 int n;
1087
1088 /*
1089 * If we get killed while waiting for the HPD timeout, return
1090 * no modes found: we are not in a restartable path, so we
1091 * can't handle signals gracefully.
1092 */
1093 if (tda998x_edid_delay_wait(priv))
1094 return 0;
1095
1096 if (priv->rev == TDA19988)
1097 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1098
1099 edid = drm_do_get_edid(connector, read_edid_block, priv);
1100
1101 if (priv->rev == TDA19988)
1102 reg_set(priv, REG_TX4, TX4_PD_RAM);
1103
1104 if (!edid) {
1105 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1106 return 0;
1107 }
1108
1109 drm_mode_connector_update_edid_property(connector, edid);
1110 n = drm_add_edid_modes(connector, edid);
1111 drm_edid_to_eld(connector, edid);
1112
1113 kfree(edid);
1114
1115 return n;
1116}
1117
1118static int tda998x_connector_mode_valid(struct drm_connector *connector,
1119 struct drm_display_mode *mode)
1120{
1121 /* TDA19988 dotclock can go up to 165MHz */
1122 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1123
1124 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1125 return MODE_CLOCK_HIGH;
1126 if (mode->htotal >= BIT(13))
1127 return MODE_BAD_HVALUE;
1128 if (mode->vtotal >= BIT(11))
1129 return MODE_BAD_VVALUE;
1130 return MODE_OK;
1131}
1132
1133static struct drm_encoder *
1134tda998x_connector_best_encoder(struct drm_connector *connector)
1135{
1136 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1137
1138 return &priv->encoder;
1139}
1140
1141static
1142const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1143 .get_modes = tda998x_connector_get_modes,
1144 .mode_valid = tda998x_connector_mode_valid,
1145 .best_encoder = tda998x_connector_best_encoder,
1146};
1147
1148static int tda998x_connector_init(struct tda998x_priv *priv,
1149 struct drm_device *drm)
1150{
1151 struct drm_connector *connector = &priv->connector;
1152 int ret;
1153
1154 connector->interlace_allowed = 1;
1155
1156 if (priv->hdmi->irq)
1157 connector->polled = DRM_CONNECTOR_POLL_HPD;
1158 else
1159 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1160 DRM_CONNECTOR_POLL_DISCONNECT;
1161
1162 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1163 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1164 DRM_MODE_CONNECTOR_HDMIA);
1165 if (ret)
1166 return ret;
1167
1168 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1169
1170 return 0;
1171}
1172
1173/* DRM encoder functions */
1174
1175static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
1176{
1177 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1178 bool on;
1179
1180 /* we only care about on or off: */
1181 on = mode == DRM_MODE_DPMS_ON;
1182
1183 if (on == priv->is_on)
1184 return;
1185
1186 if (on) {
1187 /* enable video ports, audio will be enabled later */
1188 reg_write(priv, REG_ENA_VP_0, 0xff);
1189 reg_write(priv, REG_ENA_VP_1, 0xff);
1190 reg_write(priv, REG_ENA_VP_2, 0xff);
1191 /* set muxing after enabling ports: */
1192 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1193 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1194 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1195
1196 priv->is_on = true;
1197 } else {
1198 /* disable video ports */
1199 reg_write(priv, REG_ENA_VP_0, 0x00);
1200 reg_write(priv, REG_ENA_VP_1, 0x00);
1201 reg_write(priv, REG_ENA_VP_2, 0x00);
1202
1203 priv->is_on = false;
1204 }
1205}
1206
1207static void
1208tda998x_encoder_mode_set(struct drm_encoder *encoder,
1209 struct drm_display_mode *mode,
1210 struct drm_display_mode *adjusted_mode)
1211{
1212 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1213 u16 ref_pix, ref_line, n_pix, n_line;
1214 u16 hs_pix_s, hs_pix_e;
1215 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1216 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1217 u16 vwin1_line_s, vwin1_line_e;
1218 u16 vwin2_line_s, vwin2_line_e;
1219 u16 de_pix_s, de_pix_e;
1220 u8 reg, div, rep;
1221
1222 /*
1223 * Internally TDA998x is using ITU-R BT.656 style sync but
1224 * we get VESA style sync. TDA998x is using a reference pixel
1225 * relative to ITU to sync to the input frame and for output
1226 * sync generation. Currently, we are using reference detection
1227 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1228 * which is position of rising VS with coincident rising HS.
1229 *
1230 * Now there is some issues to take care of:
1231 * - HDMI data islands require sync-before-active
1232 * - TDA998x register values must be > 0 to be enabled
1233 * - REFLINE needs an additional offset of +1
1234 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1235 *
1236 * So we add +1 to all horizontal and vertical register values,
1237 * plus an additional +3 for REFPIX as we are using RGB input only.
1238 */
1239 n_pix = mode->htotal;
1240 n_line = mode->vtotal;
1241
1242 hs_pix_e = mode->hsync_end - mode->hdisplay;
1243 hs_pix_s = mode->hsync_start - mode->hdisplay;
1244 de_pix_e = mode->htotal;
1245 de_pix_s = mode->htotal - mode->hdisplay;
1246 ref_pix = 3 + hs_pix_s;
1247
1248 /*
1249 * Attached LCD controllers may generate broken sync. Allow
1250 * those to adjust the position of the rising VS edge by adding
1251 * HSKEW to ref_pix.
1252 */
1253 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1254 ref_pix += adjusted_mode->hskew;
1255
1256 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1257 ref_line = 1 + mode->vsync_start - mode->vdisplay;
1258 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1259 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1260 vs1_pix_s = vs1_pix_e = hs_pix_s;
1261 vs1_line_s = mode->vsync_start - mode->vdisplay;
1262 vs1_line_e = vs1_line_s +
1263 mode->vsync_end - mode->vsync_start;
1264 vwin2_line_s = vwin2_line_e = 0;
1265 vs2_pix_s = vs2_pix_e = 0;
1266 vs2_line_s = vs2_line_e = 0;
1267 } else {
1268 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
1269 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1270 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1271 vs1_pix_s = vs1_pix_e = hs_pix_s;
1272 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
1273 vs1_line_e = vs1_line_s +
1274 (mode->vsync_end - mode->vsync_start)/2;
1275 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1276 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1277 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
1278 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
1279 vs2_line_e = vs2_line_s +
1280 (mode->vsync_end - mode->vsync_start)/2;
1281 }
1282
1283 div = 148500 / mode->clock;
1284 if (div != 0) {
1285 div--;
1286 if (div > 3)
1287 div = 3;
1288 }
1289
1290 mutex_lock(&priv->audio_mutex);
1291
1292 /* mute the audio FIFO: */
1293 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1294
1295 /* set HDMI HDCP mode off: */
1296 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1297 reg_clear(priv, REG_TX33, TX33_HDMI);
1298 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1299
1300 /* no pre-filter or interpolator: */
1301 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1302 HVF_CNTRL_0_INTPOL(0));
1303 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1304 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1305 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1306 VIP_CNTRL_4_BLC(0));
1307
1308 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1309 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1310 PLL_SERIAL_3_SRL_DE);
1311 reg_write(priv, REG_SERIALIZER, 0);
1312 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1313
1314 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
1315 rep = 0;
1316 reg_write(priv, REG_RPT_CNTRL, 0);
1317 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
1318 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1319
1320 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1321 PLL_SERIAL_2_SRL_PR(rep));
1322
1323 /* set color matrix bypass flag: */
1324 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1325 MAT_CONTRL_MAT_SC(1));
1326 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1327
1328 /* set BIAS tmds value: */
1329 reg_write(priv, REG_ANA_GENERAL, 0x09);
1330
1331 /*
1332 * Sync on rising HSYNC/VSYNC
1333 */
1334 reg = VIP_CNTRL_3_SYNC_HS;
1335
1336 /*
1337 * TDA19988 requires high-active sync at input stage,
1338 * so invert low-active sync provided by master encoder here
1339 */
1340 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1341 reg |= VIP_CNTRL_3_H_TGL;
1342 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1343 reg |= VIP_CNTRL_3_V_TGL;
1344 reg_write(priv, REG_VIP_CNTRL_3, reg);
1345
1346 reg_write(priv, REG_VIDFORMAT, 0x00);
1347 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1348 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1349 reg_write16(priv, REG_NPIX_MSB, n_pix);
1350 reg_write16(priv, REG_NLINE_MSB, n_line);
1351 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1352 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1353 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1354 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1355 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1356 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1357 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1358 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1359 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1360 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1361 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1362 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1363 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1364 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1365 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1366 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1367
1368 if (priv->rev == TDA19988) {
1369 /* let incoming pixels fill the active space (if any) */
1370 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1371 }
1372
1373 /*
1374 * Always generate sync polarity relative to input sync and
1375 * revert input stage toggled sync at output stage
1376 */
1377 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1378 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1379 reg |= TBG_CNTRL_1_H_TGL;
1380 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1381 reg |= TBG_CNTRL_1_V_TGL;
1382 reg_write(priv, REG_TBG_CNTRL_1, reg);
1383
1384 /* must be last register set: */
1385 reg_write(priv, REG_TBG_CNTRL_0, 0);
1386
1387 priv->tmds_clock = adjusted_mode->clock;
1388
1389 /* CEA-861B section 6 says that:
1390 * CEA version 1 (CEA-861) has no support for infoframes.
1391 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1392 * and optional basic audio.
1393 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1394 * and optional digital audio, with audio infoframes.
1395 *
1396 * Since we only support generation of version 2 AVI infoframes,
1397 * ignore CEA version 2 and below (iow, behave as if we're a
1398 * CEA-861 source.)
1399 */
1400 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1401
1402 if (priv->supports_infoframes) {
1403 /* We need to turn HDMI HDCP stuff on to get audio through */
1404 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1405 reg_write(priv, REG_TBG_CNTRL_1, reg);
1406 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1407 reg_set(priv, REG_TX33, TX33_HDMI);
1408
1409 tda998x_write_avi(priv, adjusted_mode);
1410
1411 if (priv->audio_params.format != AFMT_UNUSED &&
1412 priv->sink_has_audio)
1413 tda998x_configure_audio(priv, &priv->audio_params);
1414 }
1415
1416 mutex_unlock(&priv->audio_mutex);
1417}
1418
1419static void tda998x_destroy(struct tda998x_priv *priv)
1420{
1421 /* disable all IRQs and free the IRQ handler */
1422 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1423 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1424
1425 if (priv->audio_pdev)
1426 platform_device_unregister(priv->audio_pdev);
1427
1428 if (priv->hdmi->irq)
1429 free_irq(priv->hdmi->irq, priv);
1430
1431 del_timer_sync(&priv->edid_delay_timer);
1432 cancel_work_sync(&priv->detect_work);
1433
1434 i2c_unregister_device(priv->cec);
1435}
1436
1437/* I2C driver functions */
1438
1439static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1440 struct device_node *np)
1441{
1442 const u32 *port_data;
1443 u32 size;
1444 int i;
1445
1446 port_data = of_get_property(np, "audio-ports", &size);
1447 if (!port_data)
1448 return 0;
1449
1450 size /= sizeof(u32);
1451 if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) {
1452 dev_err(&priv->hdmi->dev,
1453 "Bad number of elements in audio-ports dt-property\n");
1454 return -EINVAL;
1455 }
1456
1457 size /= 2;
1458
1459 for (i = 0; i < size; i++) {
1460 u8 afmt = be32_to_cpup(&port_data[2*i]);
1461 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1462
1463 if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) {
1464 dev_err(&priv->hdmi->dev,
1465 "Bad audio format %u\n", afmt);
1466 return -EINVAL;
1467 }
1468
1469 priv->audio_port[i].format = afmt;
1470 priv->audio_port[i].config = ena_ap;
1471 }
1472
1473 if (priv->audio_port[0].format == priv->audio_port[1].format) {
1474 dev_err(&priv->hdmi->dev,
1475 "There can only be on I2S port and one SPDIF port\n");
1476 return -EINVAL;
1477 }
1478 return 0;
1479}
1480
1481static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1482{
1483 struct device_node *np = client->dev.of_node;
1484 u32 video;
1485 int rev_lo, rev_hi, ret;
1486
1487 mutex_init(&priv->audio_mutex); /* Protect access from audio thread */
1488
1489 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1490 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1491 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1492
1493 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1494 priv->cec_addr = 0x34 + (client->addr & 0x03);
1495 priv->current_page = 0xff;
1496 priv->hdmi = client;
1497 priv->cec = i2c_new_dummy(client->adapter, priv->cec_addr);
1498 if (!priv->cec)
1499 return -ENODEV;
1500
1501 mutex_init(&priv->mutex); /* protect the page access */
1502 init_waitqueue_head(&priv->edid_delay_waitq);
1503 setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1504 (unsigned long)priv);
1505 INIT_WORK(&priv->detect_work, tda998x_detect_work);
1506
1507 /* wake up the device: */
1508 cec_write(priv, REG_CEC_ENAMODS,
1509 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1510
1511 tda998x_reset(priv);
1512
1513 /* read version: */
1514 rev_lo = reg_read(priv, REG_VERSION_LSB);
1515 rev_hi = reg_read(priv, REG_VERSION_MSB);
1516 if (rev_lo < 0 || rev_hi < 0) {
1517 ret = rev_lo < 0 ? rev_lo : rev_hi;
1518 goto fail;
1519 }
1520
1521 priv->rev = rev_lo | rev_hi << 8;
1522
1523 /* mask off feature bits: */
1524 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1525
1526 switch (priv->rev) {
1527 case TDA9989N2:
1528 dev_info(&client->dev, "found TDA9989 n2");
1529 break;
1530 case TDA19989:
1531 dev_info(&client->dev, "found TDA19989");
1532 break;
1533 case TDA19989N2:
1534 dev_info(&client->dev, "found TDA19989 n2");
1535 break;
1536 case TDA19988:
1537 dev_info(&client->dev, "found TDA19988");
1538 break;
1539 default:
1540 dev_err(&client->dev, "found unsupported device: %04x\n",
1541 priv->rev);
1542 goto fail;
1543 }
1544
1545 /* after reset, enable DDC: */
1546 reg_write(priv, REG_DDC_DISABLE, 0x00);
1547
1548 /* set clock on DDC channel: */
1549 reg_write(priv, REG_TX3, 39);
1550
1551 /* if necessary, disable multi-master: */
1552 if (priv->rev == TDA19989)
1553 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1554
1555 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1556 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1557
1558 /* initialize the optional IRQ */
1559 if (client->irq) {
1560 unsigned long irq_flags;
1561
1562 /* init read EDID waitqueue and HDP work */
1563 init_waitqueue_head(&priv->wq_edid);
1564
1565 /* clear pending interrupts */
1566 reg_read(priv, REG_INT_FLAGS_0);
1567 reg_read(priv, REG_INT_FLAGS_1);
1568 reg_read(priv, REG_INT_FLAGS_2);
1569
1570 irq_flags =
1571 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1572 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1573 ret = request_threaded_irq(client->irq, NULL,
1574 tda998x_irq_thread, irq_flags,
1575 "tda998x", priv);
1576 if (ret) {
1577 dev_err(&client->dev,
1578 "failed to request IRQ#%u: %d\n",
1579 client->irq, ret);
1580 goto fail;
1581 }
1582
1583 /* enable HPD irq */
1584 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1585 }
1586
1587 /* enable EDID read irq: */
1588 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1589
1590 if (!np)
1591 return 0; /* non-DT */
1592
1593 /* get the device tree parameters */
1594 ret = of_property_read_u32(np, "video-ports", &video);
1595 if (ret == 0) {
1596 priv->vip_cntrl_0 = video >> 16;
1597 priv->vip_cntrl_1 = video >> 8;
1598 priv->vip_cntrl_2 = video;
1599 }
1600
1601 ret = tda998x_get_audio_ports(priv, np);
1602 if (ret)
1603 goto fail;
1604
1605 if (priv->audio_port[0].format != AFMT_UNUSED)
1606 tda998x_audio_codec_init(priv, &client->dev);
1607
1608 return 0;
1609fail:
1610 /* if encoder_init fails, the encoder slave is never registered,
1611 * so cleanup here:
1612 */
1613 if (priv->cec)
1614 i2c_unregister_device(priv->cec);
1615 return -ENXIO;
1616}
1617
1618static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1619{
1620 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1621}
1622
1623static void tda998x_encoder_commit(struct drm_encoder *encoder)
1624{
1625 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1626}
1627
1628static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1629 .dpms = tda998x_encoder_dpms,
1630 .prepare = tda998x_encoder_prepare,
1631 .commit = tda998x_encoder_commit,
1632 .mode_set = tda998x_encoder_mode_set,
1633};
1634
1635static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1636{
1637 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1638
1639 tda998x_destroy(priv);
1640 drm_encoder_cleanup(encoder);
1641}
1642
1643static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1644 .destroy = tda998x_encoder_destroy,
1645};
1646
1647static void tda998x_set_config(struct tda998x_priv *priv,
1648 const struct tda998x_encoder_params *p)
1649{
1650 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1651 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1652 VIP_CNTRL_0_SWAP_B(p->swap_b) |
1653 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1654 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1655 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1656 VIP_CNTRL_1_SWAP_D(p->swap_d) |
1657 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1658 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1659 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1660 VIP_CNTRL_2_SWAP_F(p->swap_f) |
1661 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1662
1663 priv->audio_params = p->audio_params;
1664}
1665
1666static int tda998x_bind(struct device *dev, struct device *master, void *data)
1667{
1668 struct tda998x_encoder_params *params = dev->platform_data;
1669 struct i2c_client *client = to_i2c_client(dev);
1670 struct drm_device *drm = data;
1671 struct tda998x_priv *priv;
1672 u32 crtcs = 0;
1673 int ret;
1674
1675 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1676 if (!priv)
1677 return -ENOMEM;
1678
1679 dev_set_drvdata(dev, priv);
1680
1681 if (dev->of_node)
1682 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1683
1684 /* If no CRTCs were found, fall back to our old behaviour */
1685 if (crtcs == 0) {
1686 dev_warn(dev, "Falling back to first CRTC\n");
1687 crtcs = 1 << 0;
1688 }
1689
1690 priv->encoder.possible_crtcs = crtcs;
1691
1692 ret = tda998x_create(client, priv);
1693 if (ret)
1694 return ret;
1695
1696 if (!dev->of_node && params)
1697 tda998x_set_config(priv, params);
1698
1699 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1700 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1701 DRM_MODE_ENCODER_TMDS, NULL);
1702 if (ret)
1703 goto err_encoder;
1704
1705 ret = tda998x_connector_init(priv, drm);
1706 if (ret)
1707 goto err_connector;
1708
1709 return 0;
1710
1711err_connector:
1712 drm_encoder_cleanup(&priv->encoder);
1713err_encoder:
1714 tda998x_destroy(priv);
1715 return ret;
1716}
1717
1718static void tda998x_unbind(struct device *dev, struct device *master,
1719 void *data)
1720{
1721 struct tda998x_priv *priv = dev_get_drvdata(dev);
1722
1723 drm_connector_cleanup(&priv->connector);
1724 drm_encoder_cleanup(&priv->encoder);
1725 tda998x_destroy(priv);
1726}
1727
1728static const struct component_ops tda998x_ops = {
1729 .bind = tda998x_bind,
1730 .unbind = tda998x_unbind,
1731};
1732
1733static int
1734tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1735{
1736 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1737 dev_warn(&client->dev, "adapter does not support I2C\n");
1738 return -EIO;
1739 }
1740 return component_add(&client->dev, &tda998x_ops);
1741}
1742
1743static int tda998x_remove(struct i2c_client *client)
1744{
1745 component_del(&client->dev, &tda998x_ops);
1746 return 0;
1747}
1748
1749#ifdef CONFIG_OF
1750static const struct of_device_id tda998x_dt_ids[] = {
1751 { .compatible = "nxp,tda998x", },
1752 { }
1753};
1754MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1755#endif
1756
1757static struct i2c_device_id tda998x_ids[] = {
1758 { "tda998x", 0 },
1759 { }
1760};
1761MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1762
1763static struct i2c_driver tda998x_driver = {
1764 .probe = tda998x_probe,
1765 .remove = tda998x_remove,
1766 .driver = {
1767 .name = "tda998x",
1768 .of_match_table = of_match_ptr(tda998x_dt_ids),
1769 },
1770 .id_table = tda998x_ids,
1771};
1772
1773module_i2c_driver(tda998x_driver);
1774
1775MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1776MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1777MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18
19
20#include <linux/hdmi.h>
21#include <linux/module.h>
22#include <linux/irq.h>
23#include <sound/asoundef.h>
24
25#include <drm/drmP.h>
26#include <drm/drm_crtc_helper.h>
27#include <drm/drm_encoder_slave.h>
28#include <drm/drm_edid.h>
29#include <drm/i2c/tda998x.h>
30
31#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
32
33struct tda998x_priv {
34 struct i2c_client *cec;
35 struct i2c_client *hdmi;
36 uint16_t rev;
37 uint8_t current_page;
38 int dpms;
39 bool is_hdmi_sink;
40 u8 vip_cntrl_0;
41 u8 vip_cntrl_1;
42 u8 vip_cntrl_2;
43 struct tda998x_encoder_params params;
44
45 wait_queue_head_t wq_edid;
46 volatile int wq_edid_wait;
47 struct drm_encoder *encoder;
48};
49
50#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
51
52/* The TDA9988 series of devices use a paged register scheme.. to simplify
53 * things we encode the page # in upper bits of the register #. To read/
54 * write a given register, we need to make sure CURPAGE register is set
55 * appropriately. Which implies reads/writes are not atomic. Fun!
56 */
57
58#define REG(page, addr) (((page) << 8) | (addr))
59#define REG2ADDR(reg) ((reg) & 0xff)
60#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
61
62#define REG_CURPAGE 0xff /* write */
63
64
65/* Page 00h: General Control */
66#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
67#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
68# define MAIN_CNTRL0_SR (1 << 0)
69# define MAIN_CNTRL0_DECS (1 << 1)
70# define MAIN_CNTRL0_DEHS (1 << 2)
71# define MAIN_CNTRL0_CECS (1 << 3)
72# define MAIN_CNTRL0_CEHS (1 << 4)
73# define MAIN_CNTRL0_SCALER (1 << 7)
74#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
75#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
76# define SOFTRESET_AUDIO (1 << 0)
77# define SOFTRESET_I2C_MASTER (1 << 1)
78#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
79#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
80#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
81# define I2C_MASTER_DIS_MM (1 << 0)
82# define I2C_MASTER_DIS_FILT (1 << 1)
83# define I2C_MASTER_APP_STRT_LAT (1 << 2)
84#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
85# define FEAT_POWERDOWN_SPDIF (1 << 3)
86#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
87#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
88#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
89# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
90#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
91#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
92#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
93#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
94#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
95#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
96# define VIP_CNTRL_0_MIRR_A (1 << 7)
97# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
98# define VIP_CNTRL_0_MIRR_B (1 << 3)
99# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
100#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
101# define VIP_CNTRL_1_MIRR_C (1 << 7)
102# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
103# define VIP_CNTRL_1_MIRR_D (1 << 3)
104# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
105#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
106# define VIP_CNTRL_2_MIRR_E (1 << 7)
107# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
108# define VIP_CNTRL_2_MIRR_F (1 << 3)
109# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
110#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
111# define VIP_CNTRL_3_X_TGL (1 << 0)
112# define VIP_CNTRL_3_H_TGL (1 << 1)
113# define VIP_CNTRL_3_V_TGL (1 << 2)
114# define VIP_CNTRL_3_EMB (1 << 3)
115# define VIP_CNTRL_3_SYNC_DE (1 << 4)
116# define VIP_CNTRL_3_SYNC_HS (1 << 5)
117# define VIP_CNTRL_3_DE_INT (1 << 6)
118# define VIP_CNTRL_3_EDGE (1 << 7)
119#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
120# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
121# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
122# define VIP_CNTRL_4_CCIR656 (1 << 4)
123# define VIP_CNTRL_4_656_ALT (1 << 5)
124# define VIP_CNTRL_4_TST_656 (1 << 6)
125# define VIP_CNTRL_4_TST_PAT (1 << 7)
126#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
127# define VIP_CNTRL_5_CKCASE (1 << 0)
128# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
129#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
130# define MUX_AP_SELECT_I2S 0x64
131# define MUX_AP_SELECT_SPDIF 0x40
132#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
133#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
134# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
135# define MAT_CONTRL_MAT_BP (1 << 2)
136#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
137#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
138#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
139#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
140#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
141#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
142#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
143#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
144#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
145#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
146#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
147#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
148#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
149#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
150#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
151#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
152#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
153#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
154#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
155#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
156#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
157#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
158#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
159#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
160#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
161#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
162#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
163#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
164#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
165#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
166#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
167#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
168#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
169#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
170#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
171#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
172#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
173#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
174#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
175#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
176#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
177#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
178# define TBG_CNTRL_0_TOP_TGL (1 << 0)
179# define TBG_CNTRL_0_TOP_SEL (1 << 1)
180# define TBG_CNTRL_0_DE_EXT (1 << 2)
181# define TBG_CNTRL_0_TOP_EXT (1 << 3)
182# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
183# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
184# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
185#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
186# define TBG_CNTRL_1_H_TGL (1 << 0)
187# define TBG_CNTRL_1_V_TGL (1 << 1)
188# define TBG_CNTRL_1_TGL_EN (1 << 2)
189# define TBG_CNTRL_1_X_EXT (1 << 3)
190# define TBG_CNTRL_1_H_EXT (1 << 4)
191# define TBG_CNTRL_1_V_EXT (1 << 5)
192# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
193#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
194#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
195# define HVF_CNTRL_0_SM (1 << 7)
196# define HVF_CNTRL_0_RWB (1 << 6)
197# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
198# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
199#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
200# define HVF_CNTRL_1_FOR (1 << 0)
201# define HVF_CNTRL_1_YUVBLK (1 << 1)
202# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
203# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
204# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
205#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
206#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
207# define I2S_FORMAT(x) (((x) & 3) << 0)
208#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
209# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
210# define AIP_CLKSEL_AIP_I2S (1 << 3)
211# define AIP_CLKSEL_FS_ACLK (0 << 0)
212# define AIP_CLKSEL_FS_MCLK (1 << 0)
213# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
214
215/* Page 02h: PLL settings */
216#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
217# define PLL_SERIAL_1_SRL_FDN (1 << 0)
218# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
219# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
220#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
221# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
222# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
223#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
224# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
225# define PLL_SERIAL_3_SRL_DE (1 << 2)
226# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
227#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
228#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
229#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
230#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
231#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
232#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
233#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
234#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
235#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
236# define AUDIO_DIV_SERCLK_1 0
237# define AUDIO_DIV_SERCLK_2 1
238# define AUDIO_DIV_SERCLK_4 2
239# define AUDIO_DIV_SERCLK_8 3
240# define AUDIO_DIV_SERCLK_16 4
241# define AUDIO_DIV_SERCLK_32 5
242#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
243# define SEL_CLK_SEL_CLK1 (1 << 0)
244# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
245# define SEL_CLK_ENA_SC_CLK (1 << 3)
246#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
247
248
249/* Page 09h: EDID Control */
250#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
251/* next 127 successive registers are the EDID block */
252#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
253#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
254#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
255#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
256#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
257
258
259/* Page 10h: information frames and packets */
260#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
261#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
262#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
263#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
264#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
265
266
267/* Page 11h: audio settings and content info packets */
268#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
269# define AIP_CNTRL_0_RST_FIFO (1 << 0)
270# define AIP_CNTRL_0_SWAP (1 << 1)
271# define AIP_CNTRL_0_LAYOUT (1 << 2)
272# define AIP_CNTRL_0_ACR_MAN (1 << 5)
273# define AIP_CNTRL_0_RST_CTS (1 << 6)
274#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
275# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
276# define CA_I2S_HBR_CHSTAT (1 << 6)
277#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
278#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
279#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
280#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
281#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
282#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
283#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
284#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
285# define CTS_N_K(x) (((x) & 7) << 0)
286# define CTS_N_M(x) (((x) & 3) << 4)
287#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
288# define ENC_CNTRL_RST_ENC (1 << 0)
289# define ENC_CNTRL_RST_SEL (1 << 1)
290# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
291#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
292# define DIP_FLAGS_ACR (1 << 0)
293# define DIP_FLAGS_GC (1 << 1)
294#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
295# define DIP_IF_FLAGS_IF1 (1 << 1)
296# define DIP_IF_FLAGS_IF2 (1 << 2)
297# define DIP_IF_FLAGS_IF3 (1 << 3)
298# define DIP_IF_FLAGS_IF4 (1 << 4)
299# define DIP_IF_FLAGS_IF5 (1 << 5)
300#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
301
302
303/* Page 12h: HDCP and OTP */
304#define REG_TX3 REG(0x12, 0x9a) /* read/write */
305#define REG_TX4 REG(0x12, 0x9b) /* read/write */
306# define TX4_PD_RAM (1 << 1)
307#define REG_TX33 REG(0x12, 0xb8) /* read/write */
308# define TX33_HDMI (1 << 1)
309
310
311/* Page 13h: Gamut related metadata packets */
312
313
314
315/* CEC registers: (not paged)
316 */
317#define REG_CEC_INTSTATUS 0xee /* read */
318# define CEC_INTSTATUS_CEC (1 << 0)
319# define CEC_INTSTATUS_HDMI (1 << 1)
320#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
321# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
322# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
323# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
324# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
325#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
326#define REG_CEC_RXSHPDINT 0xfd /* read */
327#define REG_CEC_RXSHPDLEV 0xfe /* read */
328# define CEC_RXSHPDLEV_RXSENS (1 << 0)
329# define CEC_RXSHPDLEV_HPD (1 << 1)
330
331#define REG_CEC_ENAMODS 0xff /* read/write */
332# define CEC_ENAMODS_DIS_FRO (1 << 6)
333# define CEC_ENAMODS_DIS_CCLK (1 << 5)
334# define CEC_ENAMODS_EN_RXSENS (1 << 2)
335# define CEC_ENAMODS_EN_HDMI (1 << 1)
336# define CEC_ENAMODS_EN_CEC (1 << 0)
337
338
339/* Device versions: */
340#define TDA9989N2 0x0101
341#define TDA19989 0x0201
342#define TDA19989N2 0x0202
343#define TDA19988 0x0301
344
345static void
346cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val)
347{
348 struct i2c_client *client = priv->cec;
349 uint8_t buf[] = {addr, val};
350 int ret;
351
352 ret = i2c_master_send(client, buf, sizeof(buf));
353 if (ret < 0)
354 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
355}
356
357static uint8_t
358cec_read(struct tda998x_priv *priv, uint8_t addr)
359{
360 struct i2c_client *client = priv->cec;
361 uint8_t val;
362 int ret;
363
364 ret = i2c_master_send(client, &addr, sizeof(addr));
365 if (ret < 0)
366 goto fail;
367
368 ret = i2c_master_recv(client, &val, sizeof(val));
369 if (ret < 0)
370 goto fail;
371
372 return val;
373
374fail:
375 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
376 return 0;
377}
378
379static int
380set_page(struct tda998x_priv *priv, uint16_t reg)
381{
382 if (REG2PAGE(reg) != priv->current_page) {
383 struct i2c_client *client = priv->hdmi;
384 uint8_t buf[] = {
385 REG_CURPAGE, REG2PAGE(reg)
386 };
387 int ret = i2c_master_send(client, buf, sizeof(buf));
388 if (ret < 0) {
389 dev_err(&client->dev, "setpage %04x err %d\n",
390 reg, ret);
391 return ret;
392 }
393
394 priv->current_page = REG2PAGE(reg);
395 }
396 return 0;
397}
398
399static int
400reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt)
401{
402 struct i2c_client *client = priv->hdmi;
403 uint8_t addr = REG2ADDR(reg);
404 int ret;
405
406 ret = set_page(priv, reg);
407 if (ret < 0)
408 return ret;
409
410 ret = i2c_master_send(client, &addr, sizeof(addr));
411 if (ret < 0)
412 goto fail;
413
414 ret = i2c_master_recv(client, buf, cnt);
415 if (ret < 0)
416 goto fail;
417
418 return ret;
419
420fail:
421 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
422 return ret;
423}
424
425static void
426reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt)
427{
428 struct i2c_client *client = priv->hdmi;
429 uint8_t buf[cnt+1];
430 int ret;
431
432 buf[0] = REG2ADDR(reg);
433 memcpy(&buf[1], p, cnt);
434
435 ret = set_page(priv, reg);
436 if (ret < 0)
437 return;
438
439 ret = i2c_master_send(client, buf, cnt + 1);
440 if (ret < 0)
441 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
442}
443
444static int
445reg_read(struct tda998x_priv *priv, uint16_t reg)
446{
447 uint8_t val = 0;
448 int ret;
449
450 ret = reg_read_range(priv, reg, &val, sizeof(val));
451 if (ret < 0)
452 return ret;
453 return val;
454}
455
456static void
457reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
458{
459 struct i2c_client *client = priv->hdmi;
460 uint8_t buf[] = {REG2ADDR(reg), val};
461 int ret;
462
463 ret = set_page(priv, reg);
464 if (ret < 0)
465 return;
466
467 ret = i2c_master_send(client, buf, sizeof(buf));
468 if (ret < 0)
469 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
470}
471
472static void
473reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val)
474{
475 struct i2c_client *client = priv->hdmi;
476 uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
477 int ret;
478
479 ret = set_page(priv, reg);
480 if (ret < 0)
481 return;
482
483 ret = i2c_master_send(client, buf, sizeof(buf));
484 if (ret < 0)
485 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
486}
487
488static void
489reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
490{
491 int old_val;
492
493 old_val = reg_read(priv, reg);
494 if (old_val >= 0)
495 reg_write(priv, reg, old_val | val);
496}
497
498static void
499reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
500{
501 int old_val;
502
503 old_val = reg_read(priv, reg);
504 if (old_val >= 0)
505 reg_write(priv, reg, old_val & ~val);
506}
507
508static void
509tda998x_reset(struct tda998x_priv *priv)
510{
511 /* reset audio and i2c master: */
512 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
513 msleep(50);
514 reg_write(priv, REG_SOFTRESET, 0);
515 msleep(50);
516
517 /* reset transmitter: */
518 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
519 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
520
521 /* PLL registers common configuration */
522 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
523 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
524 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
525 reg_write(priv, REG_SERIALIZER, 0x00);
526 reg_write(priv, REG_BUFFER_OUT, 0x00);
527 reg_write(priv, REG_PLL_SCG1, 0x00);
528 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
529 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
530 reg_write(priv, REG_PLL_SCGN1, 0xfa);
531 reg_write(priv, REG_PLL_SCGN2, 0x00);
532 reg_write(priv, REG_PLL_SCGR1, 0x5b);
533 reg_write(priv, REG_PLL_SCGR2, 0x00);
534 reg_write(priv, REG_PLL_SCG2, 0x10);
535
536 /* Write the default value MUX register */
537 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
538}
539
540/*
541 * only 2 interrupts may occur: screen plug/unplug and EDID read
542 */
543static irqreturn_t tda998x_irq_thread(int irq, void *data)
544{
545 struct tda998x_priv *priv = data;
546 u8 sta, cec, lvl, flag0, flag1, flag2;
547
548 if (!priv)
549 return IRQ_HANDLED;
550 sta = cec_read(priv, REG_CEC_INTSTATUS);
551 cec = cec_read(priv, REG_CEC_RXSHPDINT);
552 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
553 flag0 = reg_read(priv, REG_INT_FLAGS_0);
554 flag1 = reg_read(priv, REG_INT_FLAGS_1);
555 flag2 = reg_read(priv, REG_INT_FLAGS_2);
556 DRM_DEBUG_DRIVER(
557 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
558 sta, cec, lvl, flag0, flag1, flag2);
559 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
560 priv->wq_edid_wait = 0;
561 wake_up(&priv->wq_edid);
562 } else if (cec != 0) { /* HPD change */
563 if (priv->encoder && priv->encoder->dev)
564 drm_helper_hpd_irq_event(priv->encoder->dev);
565 }
566 return IRQ_HANDLED;
567}
568
569static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
570{
571 uint8_t sum = 0;
572
573 while (bytes--)
574 sum += *buf++;
575 return (255 - sum) + 1;
576}
577
578#define HB(x) (x)
579#define PB(x) (HB(2) + 1 + (x))
580
581static void
582tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr,
583 uint8_t *buf, size_t size)
584{
585 buf[PB(0)] = tda998x_cksum(buf, size);
586
587 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
588 reg_write_range(priv, addr, buf, size);
589 reg_set(priv, REG_DIP_IF_FLAGS, bit);
590}
591
592static void
593tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
594{
595 u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
596
597 memset(buf, 0, sizeof(buf));
598 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO;
599 buf[HB(1)] = 0x01;
600 buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE;
601 buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
602 buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
603 buf[PB(4)] = p->audio_frame[4];
604 buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
605
606 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
607 sizeof(buf));
608}
609
610static void
611tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
612{
613 u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1];
614
615 memset(buf, 0, sizeof(buf));
616 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AVI;
617 buf[HB(1)] = 0x02;
618 buf[HB(2)] = HDMI_AVI_INFOFRAME_SIZE;
619 buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN;
620 buf[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE;
621 buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2;
622 buf[PB(4)] = drm_match_cea_mode(mode);
623
624 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf,
625 sizeof(buf));
626}
627
628static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
629{
630 if (on) {
631 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
632 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
633 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
634 } else {
635 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
636 }
637}
638
639static void
640tda998x_configure_audio(struct tda998x_priv *priv,
641 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
642{
643 uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv;
644 uint32_t n;
645
646 /* Enable audio ports */
647 reg_write(priv, REG_ENA_AP, p->audio_cfg);
648 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
649
650 /* Set audio input source */
651 switch (p->audio_format) {
652 case AFMT_SPDIF:
653 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
654 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
655 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
656 cts_n = CTS_N_M(3) | CTS_N_K(3);
657 break;
658
659 case AFMT_I2S:
660 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
661 clksel_aip = AIP_CLKSEL_AIP_I2S;
662 clksel_fs = AIP_CLKSEL_FS_ACLK;
663 cts_n = CTS_N_M(3) | CTS_N_K(3);
664 break;
665
666 default:
667 BUG();
668 return;
669 }
670
671 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
672 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
673 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
674 reg_write(priv, REG_CTS_N, cts_n);
675
676 /*
677 * Audio input somehow depends on HDMI line rate which is
678 * related to pixclk. Testing showed that modes with pixclk
679 * >100MHz need a larger divider while <40MHz need the default.
680 * There is no detailed info in the datasheet, so we just
681 * assume 100MHz requires larger divider.
682 */
683 adiv = AUDIO_DIV_SERCLK_8;
684 if (mode->clock > 100000)
685 adiv++; /* AUDIO_DIV_SERCLK_16 */
686
687 /* S/PDIF asks for a larger divider */
688 if (p->audio_format == AFMT_SPDIF)
689 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
690
691 reg_write(priv, REG_AUDIO_DIV, adiv);
692
693 /*
694 * This is the approximate value of N, which happens to be
695 * the recommended values for non-coherent clocks.
696 */
697 n = 128 * p->audio_sample_rate / 1000;
698
699 /* Write the CTS and N values */
700 buf[0] = 0x44;
701 buf[1] = 0x42;
702 buf[2] = 0x01;
703 buf[3] = n;
704 buf[4] = n >> 8;
705 buf[5] = n >> 16;
706 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
707
708 /* Set CTS clock reference */
709 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
710
711 /* Reset CTS generator */
712 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
713 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
714
715 /* Write the channel status */
716 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
717 buf[1] = 0x00;
718 buf[2] = IEC958_AES3_CON_FS_NOTID;
719 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
720 IEC958_AES4_CON_MAX_WORDLEN_24;
721 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
722
723 tda998x_audio_mute(priv, true);
724 msleep(20);
725 tda998x_audio_mute(priv, false);
726
727 /* Write the audio information packet */
728 tda998x_write_aif(priv, p);
729}
730
731/* DRM encoder functions */
732
733static void
734tda998x_encoder_set_config(struct drm_encoder *encoder, void *params)
735{
736 struct tda998x_priv *priv = to_tda998x_priv(encoder);
737 struct tda998x_encoder_params *p = params;
738
739 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
740 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
741 VIP_CNTRL_0_SWAP_B(p->swap_b) |
742 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
743 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
744 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
745 VIP_CNTRL_1_SWAP_D(p->swap_d) |
746 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
747 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
748 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
749 VIP_CNTRL_2_SWAP_F(p->swap_f) |
750 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
751
752 priv->params = *p;
753}
754
755static void
756tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
757{
758 struct tda998x_priv *priv = to_tda998x_priv(encoder);
759
760 /* we only care about on or off: */
761 if (mode != DRM_MODE_DPMS_ON)
762 mode = DRM_MODE_DPMS_OFF;
763
764 if (mode == priv->dpms)
765 return;
766
767 switch (mode) {
768 case DRM_MODE_DPMS_ON:
769 /* enable video ports, audio will be enabled later */
770 reg_write(priv, REG_ENA_VP_0, 0xff);
771 reg_write(priv, REG_ENA_VP_1, 0xff);
772 reg_write(priv, REG_ENA_VP_2, 0xff);
773 /* set muxing after enabling ports: */
774 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
775 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
776 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
777 break;
778 case DRM_MODE_DPMS_OFF:
779 /* disable video ports */
780 reg_write(priv, REG_ENA_VP_0, 0x00);
781 reg_write(priv, REG_ENA_VP_1, 0x00);
782 reg_write(priv, REG_ENA_VP_2, 0x00);
783 break;
784 }
785
786 priv->dpms = mode;
787}
788
789static void
790tda998x_encoder_save(struct drm_encoder *encoder)
791{
792 DBG("");
793}
794
795static void
796tda998x_encoder_restore(struct drm_encoder *encoder)
797{
798 DBG("");
799}
800
801static bool
802tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
803 const struct drm_display_mode *mode,
804 struct drm_display_mode *adjusted_mode)
805{
806 return true;
807}
808
809static int
810tda998x_encoder_mode_valid(struct drm_encoder *encoder,
811 struct drm_display_mode *mode)
812{
813 return MODE_OK;
814}
815
816static void
817tda998x_encoder_mode_set(struct drm_encoder *encoder,
818 struct drm_display_mode *mode,
819 struct drm_display_mode *adjusted_mode)
820{
821 struct tda998x_priv *priv = to_tda998x_priv(encoder);
822 uint16_t ref_pix, ref_line, n_pix, n_line;
823 uint16_t hs_pix_s, hs_pix_e;
824 uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
825 uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
826 uint16_t vwin1_line_s, vwin1_line_e;
827 uint16_t vwin2_line_s, vwin2_line_e;
828 uint16_t de_pix_s, de_pix_e;
829 uint8_t reg, div, rep;
830
831 /*
832 * Internally TDA998x is using ITU-R BT.656 style sync but
833 * we get VESA style sync. TDA998x is using a reference pixel
834 * relative to ITU to sync to the input frame and for output
835 * sync generation. Currently, we are using reference detection
836 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
837 * which is position of rising VS with coincident rising HS.
838 *
839 * Now there is some issues to take care of:
840 * - HDMI data islands require sync-before-active
841 * - TDA998x register values must be > 0 to be enabled
842 * - REFLINE needs an additional offset of +1
843 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
844 *
845 * So we add +1 to all horizontal and vertical register values,
846 * plus an additional +3 for REFPIX as we are using RGB input only.
847 */
848 n_pix = mode->htotal;
849 n_line = mode->vtotal;
850
851 hs_pix_e = mode->hsync_end - mode->hdisplay;
852 hs_pix_s = mode->hsync_start - mode->hdisplay;
853 de_pix_e = mode->htotal;
854 de_pix_s = mode->htotal - mode->hdisplay;
855 ref_pix = 3 + hs_pix_s;
856
857 /*
858 * Attached LCD controllers may generate broken sync. Allow
859 * those to adjust the position of the rising VS edge by adding
860 * HSKEW to ref_pix.
861 */
862 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
863 ref_pix += adjusted_mode->hskew;
864
865 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
866 ref_line = 1 + mode->vsync_start - mode->vdisplay;
867 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
868 vwin1_line_e = vwin1_line_s + mode->vdisplay;
869 vs1_pix_s = vs1_pix_e = hs_pix_s;
870 vs1_line_s = mode->vsync_start - mode->vdisplay;
871 vs1_line_e = vs1_line_s +
872 mode->vsync_end - mode->vsync_start;
873 vwin2_line_s = vwin2_line_e = 0;
874 vs2_pix_s = vs2_pix_e = 0;
875 vs2_line_s = vs2_line_e = 0;
876 } else {
877 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
878 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
879 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
880 vs1_pix_s = vs1_pix_e = hs_pix_s;
881 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
882 vs1_line_e = vs1_line_s +
883 (mode->vsync_end - mode->vsync_start)/2;
884 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
885 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
886 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
887 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
888 vs2_line_e = vs2_line_s +
889 (mode->vsync_end - mode->vsync_start)/2;
890 }
891
892 div = 148500 / mode->clock;
893 if (div != 0) {
894 div--;
895 if (div > 3)
896 div = 3;
897 }
898
899 /* mute the audio FIFO: */
900 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
901
902 /* set HDMI HDCP mode off: */
903 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
904 reg_clear(priv, REG_TX33, TX33_HDMI);
905 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
906
907 /* no pre-filter or interpolator: */
908 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
909 HVF_CNTRL_0_INTPOL(0));
910 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
911 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
912 VIP_CNTRL_4_BLC(0));
913
914 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
915 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
916 PLL_SERIAL_3_SRL_DE);
917 reg_write(priv, REG_SERIALIZER, 0);
918 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
919
920 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
921 rep = 0;
922 reg_write(priv, REG_RPT_CNTRL, 0);
923 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
924 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
925
926 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
927 PLL_SERIAL_2_SRL_PR(rep));
928
929 /* set color matrix bypass flag: */
930 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
931 MAT_CONTRL_MAT_SC(1));
932
933 /* set BIAS tmds value: */
934 reg_write(priv, REG_ANA_GENERAL, 0x09);
935
936 /*
937 * Sync on rising HSYNC/VSYNC
938 */
939 reg = VIP_CNTRL_3_SYNC_HS;
940
941 /*
942 * TDA19988 requires high-active sync at input stage,
943 * so invert low-active sync provided by master encoder here
944 */
945 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
946 reg |= VIP_CNTRL_3_H_TGL;
947 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
948 reg |= VIP_CNTRL_3_V_TGL;
949 reg_write(priv, REG_VIP_CNTRL_3, reg);
950
951 reg_write(priv, REG_VIDFORMAT, 0x00);
952 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
953 reg_write16(priv, REG_REFLINE_MSB, ref_line);
954 reg_write16(priv, REG_NPIX_MSB, n_pix);
955 reg_write16(priv, REG_NLINE_MSB, n_line);
956 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
957 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
958 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
959 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
960 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
961 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
962 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
963 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
964 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
965 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
966 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
967 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
968 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
969 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
970 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
971 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
972
973 if (priv->rev == TDA19988) {
974 /* let incoming pixels fill the active space (if any) */
975 reg_write(priv, REG_ENABLE_SPACE, 0x00);
976 }
977
978 /*
979 * Always generate sync polarity relative to input sync and
980 * revert input stage toggled sync at output stage
981 */
982 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
983 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
984 reg |= TBG_CNTRL_1_H_TGL;
985 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
986 reg |= TBG_CNTRL_1_V_TGL;
987 reg_write(priv, REG_TBG_CNTRL_1, reg);
988
989 /* must be last register set: */
990 reg_write(priv, REG_TBG_CNTRL_0, 0);
991
992 /* Only setup the info frames if the sink is HDMI */
993 if (priv->is_hdmi_sink) {
994 /* We need to turn HDMI HDCP stuff on to get audio through */
995 reg &= ~TBG_CNTRL_1_DWIN_DIS;
996 reg_write(priv, REG_TBG_CNTRL_1, reg);
997 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
998 reg_set(priv, REG_TX33, TX33_HDMI);
999
1000 tda998x_write_avi(priv, adjusted_mode);
1001
1002 if (priv->params.audio_cfg)
1003 tda998x_configure_audio(priv, adjusted_mode,
1004 &priv->params);
1005 }
1006}
1007
1008static enum drm_connector_status
1009tda998x_encoder_detect(struct drm_encoder *encoder,
1010 struct drm_connector *connector)
1011{
1012 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1013 uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV);
1014
1015 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1016 connector_status_disconnected;
1017}
1018
1019static int
1020read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk)
1021{
1022 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1023 uint8_t offset, segptr;
1024 int ret, i;
1025
1026 offset = (blk & 1) ? 128 : 0;
1027 segptr = blk / 2;
1028
1029 reg_write(priv, REG_DDC_ADDR, 0xa0);
1030 reg_write(priv, REG_DDC_OFFS, offset);
1031 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1032 reg_write(priv, REG_DDC_SEGM, segptr);
1033
1034 /* enable reading EDID: */
1035 priv->wq_edid_wait = 1;
1036 reg_write(priv, REG_EDID_CTRL, 0x1);
1037
1038 /* flag must be cleared by sw: */
1039 reg_write(priv, REG_EDID_CTRL, 0x0);
1040
1041 /* wait for block read to complete: */
1042 if (priv->hdmi->irq) {
1043 i = wait_event_timeout(priv->wq_edid,
1044 !priv->wq_edid_wait,
1045 msecs_to_jiffies(100));
1046 if (i < 0) {
1047 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1048 return i;
1049 }
1050 } else {
1051 for (i = 10; i > 0; i--) {
1052 msleep(10);
1053 ret = reg_read(priv, REG_INT_FLAGS_2);
1054 if (ret < 0)
1055 return ret;
1056 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1057 break;
1058 }
1059 }
1060
1061 if (i == 0) {
1062 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1063 return -ETIMEDOUT;
1064 }
1065
1066 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, EDID_LENGTH);
1067 if (ret != EDID_LENGTH) {
1068 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1069 blk, ret);
1070 return ret;
1071 }
1072
1073 return 0;
1074}
1075
1076static uint8_t *
1077do_get_edid(struct drm_encoder *encoder)
1078{
1079 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1080 int j, valid_extensions = 0;
1081 uint8_t *block, *new;
1082 bool print_bad_edid = drm_debug & DRM_UT_KMS;
1083
1084 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1085 return NULL;
1086
1087 if (priv->rev == TDA19988)
1088 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1089
1090 /* base block fetch */
1091 if (read_edid_block(encoder, block, 0))
1092 goto fail;
1093
1094 if (!drm_edid_block_valid(block, 0, print_bad_edid))
1095 goto fail;
1096
1097 /* if there's no extensions, we're done */
1098 if (block[0x7e] == 0)
1099 goto done;
1100
1101 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1102 if (!new)
1103 goto fail;
1104 block = new;
1105
1106 for (j = 1; j <= block[0x7e]; j++) {
1107 uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH;
1108 if (read_edid_block(encoder, ext_block, j))
1109 goto fail;
1110
1111 if (!drm_edid_block_valid(ext_block, j, print_bad_edid))
1112 goto fail;
1113
1114 valid_extensions++;
1115 }
1116
1117 if (valid_extensions != block[0x7e]) {
1118 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1119 block[0x7e] = valid_extensions;
1120 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1121 if (!new)
1122 goto fail;
1123 block = new;
1124 }
1125
1126done:
1127 if (priv->rev == TDA19988)
1128 reg_set(priv, REG_TX4, TX4_PD_RAM);
1129
1130 return block;
1131
1132fail:
1133 if (priv->rev == TDA19988)
1134 reg_set(priv, REG_TX4, TX4_PD_RAM);
1135 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1136 kfree(block);
1137 return NULL;
1138}
1139
1140static int
1141tda998x_encoder_get_modes(struct drm_encoder *encoder,
1142 struct drm_connector *connector)
1143{
1144 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1145 struct edid *edid = (struct edid *)do_get_edid(encoder);
1146 int n = 0;
1147
1148 if (edid) {
1149 drm_mode_connector_update_edid_property(connector, edid);
1150 n = drm_add_edid_modes(connector, edid);
1151 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1152 kfree(edid);
1153 }
1154
1155 return n;
1156}
1157
1158static int
1159tda998x_encoder_create_resources(struct drm_encoder *encoder,
1160 struct drm_connector *connector)
1161{
1162 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1163
1164 if (priv->hdmi->irq)
1165 connector->polled = DRM_CONNECTOR_POLL_HPD;
1166 else
1167 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1168 DRM_CONNECTOR_POLL_DISCONNECT;
1169 return 0;
1170}
1171
1172static int
1173tda998x_encoder_set_property(struct drm_encoder *encoder,
1174 struct drm_connector *connector,
1175 struct drm_property *property,
1176 uint64_t val)
1177{
1178 DBG("");
1179 return 0;
1180}
1181
1182static void
1183tda998x_encoder_destroy(struct drm_encoder *encoder)
1184{
1185 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1186 drm_i2c_encoder_destroy(encoder);
1187
1188 /* disable all IRQs and free the IRQ handler */
1189 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1190 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1191 if (priv->hdmi->irq)
1192 free_irq(priv->hdmi->irq, priv);
1193
1194 if (priv->cec)
1195 i2c_unregister_device(priv->cec);
1196 kfree(priv);
1197}
1198
1199static struct drm_encoder_slave_funcs tda998x_encoder_funcs = {
1200 .set_config = tda998x_encoder_set_config,
1201 .destroy = tda998x_encoder_destroy,
1202 .dpms = tda998x_encoder_dpms,
1203 .save = tda998x_encoder_save,
1204 .restore = tda998x_encoder_restore,
1205 .mode_fixup = tda998x_encoder_mode_fixup,
1206 .mode_valid = tda998x_encoder_mode_valid,
1207 .mode_set = tda998x_encoder_mode_set,
1208 .detect = tda998x_encoder_detect,
1209 .get_modes = tda998x_encoder_get_modes,
1210 .create_resources = tda998x_encoder_create_resources,
1211 .set_property = tda998x_encoder_set_property,
1212};
1213
1214/* I2C driver functions */
1215
1216static int
1217tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1218{
1219 return 0;
1220}
1221
1222static int
1223tda998x_remove(struct i2c_client *client)
1224{
1225 return 0;
1226}
1227
1228static int
1229tda998x_encoder_init(struct i2c_client *client,
1230 struct drm_device *dev,
1231 struct drm_encoder_slave *encoder_slave)
1232{
1233 struct tda998x_priv *priv;
1234 struct device_node *np = client->dev.of_node;
1235 u32 video;
1236 int rev_lo, rev_hi, ret;
1237
1238 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1239 if (!priv)
1240 return -ENOMEM;
1241
1242 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1243 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1244 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1245
1246 priv->current_page = 0xff;
1247 priv->hdmi = client;
1248 priv->cec = i2c_new_dummy(client->adapter, 0x34);
1249 if (!priv->cec) {
1250 kfree(priv);
1251 return -ENODEV;
1252 }
1253
1254 priv->encoder = &encoder_slave->base;
1255 priv->dpms = DRM_MODE_DPMS_OFF;
1256
1257 encoder_slave->slave_priv = priv;
1258 encoder_slave->slave_funcs = &tda998x_encoder_funcs;
1259
1260 /* wake up the device: */
1261 cec_write(priv, REG_CEC_ENAMODS,
1262 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1263
1264 tda998x_reset(priv);
1265
1266 /* read version: */
1267 rev_lo = reg_read(priv, REG_VERSION_LSB);
1268 rev_hi = reg_read(priv, REG_VERSION_MSB);
1269 if (rev_lo < 0 || rev_hi < 0) {
1270 ret = rev_lo < 0 ? rev_lo : rev_hi;
1271 goto fail;
1272 }
1273
1274 priv->rev = rev_lo | rev_hi << 8;
1275
1276 /* mask off feature bits: */
1277 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1278
1279 switch (priv->rev) {
1280 case TDA9989N2:
1281 dev_info(&client->dev, "found TDA9989 n2");
1282 break;
1283 case TDA19989:
1284 dev_info(&client->dev, "found TDA19989");
1285 break;
1286 case TDA19989N2:
1287 dev_info(&client->dev, "found TDA19989 n2");
1288 break;
1289 case TDA19988:
1290 dev_info(&client->dev, "found TDA19988");
1291 break;
1292 default:
1293 dev_err(&client->dev, "found unsupported device: %04x\n",
1294 priv->rev);
1295 goto fail;
1296 }
1297
1298 /* after reset, enable DDC: */
1299 reg_write(priv, REG_DDC_DISABLE, 0x00);
1300
1301 /* set clock on DDC channel: */
1302 reg_write(priv, REG_TX3, 39);
1303
1304 /* if necessary, disable multi-master: */
1305 if (priv->rev == TDA19989)
1306 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1307
1308 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1309 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1310
1311 /* initialize the optional IRQ */
1312 if (client->irq) {
1313 int irqf_trigger;
1314
1315 /* init read EDID waitqueue */
1316 init_waitqueue_head(&priv->wq_edid);
1317
1318 /* clear pending interrupts */
1319 reg_read(priv, REG_INT_FLAGS_0);
1320 reg_read(priv, REG_INT_FLAGS_1);
1321 reg_read(priv, REG_INT_FLAGS_2);
1322
1323 irqf_trigger =
1324 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1325 ret = request_threaded_irq(client->irq, NULL,
1326 tda998x_irq_thread,
1327 irqf_trigger | IRQF_ONESHOT,
1328 "tda998x", priv);
1329 if (ret) {
1330 dev_err(&client->dev,
1331 "failed to request IRQ#%u: %d\n",
1332 client->irq, ret);
1333 goto fail;
1334 }
1335
1336 /* enable HPD irq */
1337 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1338 }
1339
1340 /* enable EDID read irq: */
1341 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1342
1343 if (!np)
1344 return 0; /* non-DT */
1345
1346 /* get the optional video properties */
1347 ret = of_property_read_u32(np, "video-ports", &video);
1348 if (ret == 0) {
1349 priv->vip_cntrl_0 = video >> 16;
1350 priv->vip_cntrl_1 = video >> 8;
1351 priv->vip_cntrl_2 = video;
1352 }
1353
1354 return 0;
1355
1356fail:
1357 /* if encoder_init fails, the encoder slave is never registered,
1358 * so cleanup here:
1359 */
1360 if (priv->cec)
1361 i2c_unregister_device(priv->cec);
1362 kfree(priv);
1363 encoder_slave->slave_priv = NULL;
1364 encoder_slave->slave_funcs = NULL;
1365 return -ENXIO;
1366}
1367
1368#ifdef CONFIG_OF
1369static const struct of_device_id tda998x_dt_ids[] = {
1370 { .compatible = "nxp,tda998x", },
1371 { }
1372};
1373MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1374#endif
1375
1376static struct i2c_device_id tda998x_ids[] = {
1377 { "tda998x", 0 },
1378 { }
1379};
1380MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1381
1382static struct drm_i2c_encoder_driver tda998x_driver = {
1383 .i2c_driver = {
1384 .probe = tda998x_probe,
1385 .remove = tda998x_remove,
1386 .driver = {
1387 .name = "tda998x",
1388 .of_match_table = of_match_ptr(tda998x_dt_ids),
1389 },
1390 .id_table = tda998x_ids,
1391 },
1392 .encoder_init = tda998x_encoder_init,
1393};
1394
1395/* Module initialization */
1396
1397static int __init
1398tda998x_init(void)
1399{
1400 DBG("");
1401 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
1402}
1403
1404static void __exit
1405tda998x_exit(void)
1406{
1407 DBG("");
1408 drm_i2c_encoder_unregister(&tda998x_driver);
1409}
1410
1411MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1412MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1413MODULE_LICENSE("GPL");
1414
1415module_init(tda998x_init);
1416module_exit(tda998x_exit);