Loading...
1/*
2 * Copyright IBM Corp. 2004, 2011
3 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
4 * Holger Smolinski <Holger.Smolinski@de.ibm.com>,
5 * Thomas Spatzier <tspat@de.ibm.com>,
6 *
7 * This file contains interrupt related functions.
8 */
9
10#include <linux/kernel_stat.h>
11#include <linux/interrupt.h>
12#include <linux/seq_file.h>
13#include <linux/proc_fs.h>
14#include <linux/profile.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/ftrace.h>
18#include <linux/errno.h>
19#include <linux/slab.h>
20#include <linux/cpu.h>
21#include <linux/irq.h>
22#include <asm/irq_regs.h>
23#include <asm/cputime.h>
24#include <asm/lowcore.h>
25#include <asm/irq.h>
26#include <asm/hw_irq.h>
27#include "entry.h"
28
29DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
30EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
31
32struct irq_class {
33 int irq;
34 char *name;
35 char *desc;
36};
37
38/*
39 * The list of "main" irq classes on s390. This is the list of interrupts
40 * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
41 * Historically only external and I/O interrupts have been part of /proc/stat.
42 * We can't add the split external and I/O sub classes since the first field
43 * in the "intr" line in /proc/stat is supposed to be the sum of all other
44 * fields.
45 * Since the external and I/O interrupt fields are already sums we would end
46 * up with having a sum which accounts each interrupt twice.
47 */
48static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
49 {.irq = EXT_INTERRUPT, .name = "EXT"},
50 {.irq = IO_INTERRUPT, .name = "I/O"},
51 {.irq = THIN_INTERRUPT, .name = "AIO"},
52};
53
54/*
55 * The list of split external and I/O interrupts that appear only in
56 * /proc/interrupts.
57 * In addition this list contains non external / I/O events like NMIs.
58 */
59static const struct irq_class irqclass_sub_desc[] = {
60 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
61 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
62 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
63 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
64 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
65 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
66 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
67 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
68 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
69 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
70 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
71 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
72 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
73 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
74 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"},
75 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"},
76 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"},
77 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"},
78 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"},
79 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"},
80 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"},
81 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"},
82 {.irq = IRQIO_APB, .name = "APB", .desc = "[I/O] AP Bus"},
83 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"},
84 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
85 {.irq = IRQIO_PCI, .name = "PCI", .desc = "[I/O] PCI Interrupt" },
86 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[I/O] MSI Interrupt" },
87 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
88 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"},
89 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"},
90 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"},
91};
92
93void __init init_IRQ(void)
94{
95 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
96 init_cio_interrupts();
97 init_airq_interrupts();
98 init_ext_interrupts();
99}
100
101void do_IRQ(struct pt_regs *regs, int irq)
102{
103 struct pt_regs *old_regs;
104
105 old_regs = set_irq_regs(regs);
106 irq_enter();
107 if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)
108 /* Serve timer interrupts first. */
109 clock_comparator_work();
110 generic_handle_irq(irq);
111 irq_exit();
112 set_irq_regs(old_regs);
113}
114
115/*
116 * show_interrupts is needed by /proc/interrupts.
117 */
118int show_interrupts(struct seq_file *p, void *v)
119{
120 int index = *(loff_t *) v;
121 int cpu, irq;
122
123 get_online_cpus();
124 if (index == 0) {
125 seq_puts(p, " ");
126 for_each_online_cpu(cpu)
127 seq_printf(p, "CPU%d ", cpu);
128 seq_putc(p, '\n');
129 }
130 if (index < NR_IRQS_BASE) {
131 seq_printf(p, "%s: ", irqclass_main_desc[index].name);
132 irq = irqclass_main_desc[index].irq;
133 for_each_online_cpu(cpu)
134 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
135 seq_putc(p, '\n');
136 goto out;
137 }
138 if (index > NR_IRQS_BASE)
139 goto out;
140
141 for (index = 0; index < NR_ARCH_IRQS; index++) {
142 seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
143 irq = irqclass_sub_desc[index].irq;
144 for_each_online_cpu(cpu)
145 seq_printf(p, "%10u ",
146 per_cpu(irq_stat, cpu).irqs[irq]);
147 if (irqclass_sub_desc[index].desc)
148 seq_printf(p, " %s", irqclass_sub_desc[index].desc);
149 seq_putc(p, '\n');
150 }
151out:
152 put_online_cpus();
153 return 0;
154}
155
156unsigned int arch_dynirq_lower_bound(unsigned int from)
157{
158 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
159}
160
161/*
162 * Switch to the asynchronous interrupt stack for softirq execution.
163 */
164void do_softirq_own_stack(void)
165{
166 unsigned long old, new;
167
168 old = current_stack_pointer();
169 /* Check against async. stack address range. */
170 new = S390_lowcore.async_stack;
171 if (((new - old) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)) != 0) {
172 /* Need to switch to the async. stack. */
173 new -= STACK_FRAME_OVERHEAD;
174 ((struct stack_frame *) new)->back_chain = old;
175 asm volatile(" la 15,0(%0)\n"
176 " basr 14,%2\n"
177 " la 15,0(%1)\n"
178 : : "a" (new), "a" (old),
179 "a" (__do_softirq)
180 : "0", "1", "2", "3", "4", "5", "14",
181 "cc", "memory" );
182 } else {
183 /* We are already on the async stack. */
184 __do_softirq();
185 }
186}
187
188/*
189 * ext_int_hash[index] is the list head for all external interrupts that hash
190 * to this index.
191 */
192static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
193
194struct ext_int_info {
195 ext_int_handler_t handler;
196 struct hlist_node entry;
197 struct rcu_head rcu;
198 u16 code;
199};
200
201/* ext_int_hash_lock protects the handler lists for external interrupts */
202static DEFINE_SPINLOCK(ext_int_hash_lock);
203
204static inline int ext_hash(u16 code)
205{
206 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
207
208 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
209}
210
211int register_external_irq(u16 code, ext_int_handler_t handler)
212{
213 struct ext_int_info *p;
214 unsigned long flags;
215 int index;
216
217 p = kmalloc(sizeof(*p), GFP_ATOMIC);
218 if (!p)
219 return -ENOMEM;
220 p->code = code;
221 p->handler = handler;
222 index = ext_hash(code);
223
224 spin_lock_irqsave(&ext_int_hash_lock, flags);
225 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
226 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
227 return 0;
228}
229EXPORT_SYMBOL(register_external_irq);
230
231int unregister_external_irq(u16 code, ext_int_handler_t handler)
232{
233 struct ext_int_info *p;
234 unsigned long flags;
235 int index = ext_hash(code);
236
237 spin_lock_irqsave(&ext_int_hash_lock, flags);
238 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
239 if (p->code == code && p->handler == handler) {
240 hlist_del_rcu(&p->entry);
241 kfree_rcu(p, rcu);
242 }
243 }
244 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
245 return 0;
246}
247EXPORT_SYMBOL(unregister_external_irq);
248
249static irqreturn_t do_ext_interrupt(int irq, void *dummy)
250{
251 struct pt_regs *regs = get_irq_regs();
252 struct ext_code ext_code;
253 struct ext_int_info *p;
254 int index;
255
256 ext_code = *(struct ext_code *) ®s->int_code;
257 if (ext_code.code != EXT_IRQ_CLK_COMP)
258 set_cpu_flag(CIF_NOHZ_DELAY);
259
260 index = ext_hash(ext_code.code);
261 rcu_read_lock();
262 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
263 if (unlikely(p->code != ext_code.code))
264 continue;
265 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
266 }
267 rcu_read_unlock();
268 return IRQ_HANDLED;
269}
270
271static struct irqaction external_interrupt = {
272 .name = "EXT",
273 .handler = do_ext_interrupt,
274};
275
276void __init init_ext_interrupts(void)
277{
278 int idx;
279
280 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
281 INIT_HLIST_HEAD(&ext_int_hash[idx]);
282
283 irq_set_chip_and_handler(EXT_INTERRUPT,
284 &dummy_irq_chip, handle_percpu_irq);
285 setup_irq(EXT_INTERRUPT, &external_interrupt);
286}
287
288static DEFINE_SPINLOCK(irq_subclass_lock);
289static unsigned char irq_subclass_refcount[64];
290
291void irq_subclass_register(enum irq_subclass subclass)
292{
293 spin_lock(&irq_subclass_lock);
294 if (!irq_subclass_refcount[subclass])
295 ctl_set_bit(0, subclass);
296 irq_subclass_refcount[subclass]++;
297 spin_unlock(&irq_subclass_lock);
298}
299EXPORT_SYMBOL(irq_subclass_register);
300
301void irq_subclass_unregister(enum irq_subclass subclass)
302{
303 spin_lock(&irq_subclass_lock);
304 irq_subclass_refcount[subclass]--;
305 if (!irq_subclass_refcount[subclass])
306 ctl_clear_bit(0, subclass);
307 spin_unlock(&irq_subclass_lock);
308}
309EXPORT_SYMBOL(irq_subclass_unregister);
1/*
2 * Copyright IBM Corp. 2004, 2011
3 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
4 * Holger Smolinski <Holger.Smolinski@de.ibm.com>,
5 * Thomas Spatzier <tspat@de.ibm.com>,
6 *
7 * This file contains interrupt related functions.
8 */
9
10#include <linux/kernel_stat.h>
11#include <linux/interrupt.h>
12#include <linux/seq_file.h>
13#include <linux/proc_fs.h>
14#include <linux/profile.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/ftrace.h>
18#include <linux/errno.h>
19#include <linux/slab.h>
20#include <linux/cpu.h>
21#include <linux/irq.h>
22#include <asm/irq_regs.h>
23#include <asm/cputime.h>
24#include <asm/lowcore.h>
25#include <asm/irq.h>
26#include <asm/hw_irq.h>
27#include "entry.h"
28
29DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
30EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
31
32struct irq_class {
33 char *name;
34 char *desc;
35};
36
37/*
38 * The list of "main" irq classes on s390. This is the list of interrupts
39 * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
40 * Historically only external and I/O interrupts have been part of /proc/stat.
41 * We can't add the split external and I/O sub classes since the first field
42 * in the "intr" line in /proc/stat is supposed to be the sum of all other
43 * fields.
44 * Since the external and I/O interrupt fields are already sums we would end
45 * up with having a sum which accounts each interrupt twice.
46 */
47static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
48 [EXT_INTERRUPT] = {.name = "EXT"},
49 [IO_INTERRUPT] = {.name = "I/O"},
50 [THIN_INTERRUPT] = {.name = "AIO"},
51};
52
53/*
54 * The list of split external and I/O interrupts that appear only in
55 * /proc/interrupts.
56 * In addition this list contains non external / I/O events like NMIs.
57 */
58static const struct irq_class irqclass_sub_desc[NR_ARCH_IRQS] = {
59 [IRQEXT_CLK] = {.name = "CLK", .desc = "[EXT] Clock Comparator"},
60 [IRQEXT_EXC] = {.name = "EXC", .desc = "[EXT] External Call"},
61 [IRQEXT_EMS] = {.name = "EMS", .desc = "[EXT] Emergency Signal"},
62 [IRQEXT_TMR] = {.name = "TMR", .desc = "[EXT] CPU Timer"},
63 [IRQEXT_TLA] = {.name = "TAL", .desc = "[EXT] Timing Alert"},
64 [IRQEXT_PFL] = {.name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
65 [IRQEXT_DSD] = {.name = "DSD", .desc = "[EXT] DASD Diag"},
66 [IRQEXT_VRT] = {.name = "VRT", .desc = "[EXT] Virtio"},
67 [IRQEXT_SCP] = {.name = "SCP", .desc = "[EXT] Service Call"},
68 [IRQEXT_IUC] = {.name = "IUC", .desc = "[EXT] IUCV"},
69 [IRQEXT_CMS] = {.name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
70 [IRQEXT_CMC] = {.name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
71 [IRQEXT_CMR] = {.name = "CMR", .desc = "[EXT] CPU-Measurement: RI"},
72 [IRQIO_CIO] = {.name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
73 [IRQIO_QAI] = {.name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"},
74 [IRQIO_DAS] = {.name = "DAS", .desc = "[I/O] DASD"},
75 [IRQIO_C15] = {.name = "C15", .desc = "[I/O] 3215"},
76 [IRQIO_C70] = {.name = "C70", .desc = "[I/O] 3270"},
77 [IRQIO_TAP] = {.name = "TAP", .desc = "[I/O] Tape"},
78 [IRQIO_VMR] = {.name = "VMR", .desc = "[I/O] Unit Record Devices"},
79 [IRQIO_LCS] = {.name = "LCS", .desc = "[I/O] LCS"},
80 [IRQIO_CLW] = {.name = "CLW", .desc = "[I/O] CLAW"},
81 [IRQIO_CTC] = {.name = "CTC", .desc = "[I/O] CTC"},
82 [IRQIO_APB] = {.name = "APB", .desc = "[I/O] AP Bus"},
83 [IRQIO_ADM] = {.name = "ADM", .desc = "[I/O] EADM Subchannel"},
84 [IRQIO_CSC] = {.name = "CSC", .desc = "[I/O] CHSC Subchannel"},
85 [IRQIO_PCI] = {.name = "PCI", .desc = "[I/O] PCI Interrupt" },
86 [IRQIO_MSI] = {.name = "MSI", .desc = "[I/O] MSI Interrupt" },
87 [IRQIO_VIR] = {.name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
88 [IRQIO_VAI] = {.name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"},
89 [NMI_NMI] = {.name = "NMI", .desc = "[NMI] Machine Check"},
90 [CPU_RST] = {.name = "RST", .desc = "[CPU] CPU Restart"},
91};
92
93void __init init_IRQ(void)
94{
95 irq_reserve_irqs(0, THIN_INTERRUPT);
96 init_cio_interrupts();
97 init_airq_interrupts();
98 init_ext_interrupts();
99}
100
101void do_IRQ(struct pt_regs *regs, int irq)
102{
103 struct pt_regs *old_regs;
104
105 old_regs = set_irq_regs(regs);
106 irq_enter();
107 if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)
108 /* Serve timer interrupts first. */
109 clock_comparator_work();
110 generic_handle_irq(irq);
111 irq_exit();
112 set_irq_regs(old_regs);
113}
114
115/*
116 * show_interrupts is needed by /proc/interrupts.
117 */
118int show_interrupts(struct seq_file *p, void *v)
119{
120 int irq = *(loff_t *) v;
121 int cpu;
122
123 get_online_cpus();
124 if (irq == 0) {
125 seq_puts(p, " ");
126 for_each_online_cpu(cpu)
127 seq_printf(p, "CPU%d ", cpu);
128 seq_putc(p, '\n');
129 goto out;
130 }
131 if (irq < NR_IRQS) {
132 if (irq >= NR_IRQS_BASE)
133 goto out;
134 seq_printf(p, "%s: ", irqclass_main_desc[irq].name);
135 for_each_online_cpu(cpu)
136 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
137 seq_putc(p, '\n');
138 goto out;
139 }
140 for (irq = 0; irq < NR_ARCH_IRQS; irq++) {
141 seq_printf(p, "%s: ", irqclass_sub_desc[irq].name);
142 for_each_online_cpu(cpu)
143 seq_printf(p, "%10u ",
144 per_cpu(irq_stat, cpu).irqs[irq]);
145 if (irqclass_sub_desc[irq].desc)
146 seq_printf(p, " %s", irqclass_sub_desc[irq].desc);
147 seq_putc(p, '\n');
148 }
149out:
150 put_online_cpus();
151 return 0;
152}
153
154int arch_show_interrupts(struct seq_file *p, int prec)
155{
156 return 0;
157}
158
159/*
160 * Switch to the asynchronous interrupt stack for softirq execution.
161 */
162void do_softirq_own_stack(void)
163{
164 unsigned long old, new;
165
166 /* Get current stack pointer. */
167 asm volatile("la %0,0(15)" : "=a" (old));
168 /* Check against async. stack address range. */
169 new = S390_lowcore.async_stack;
170 if (((new - old) >> (PAGE_SHIFT + THREAD_ORDER)) != 0) {
171 /* Need to switch to the async. stack. */
172 new -= STACK_FRAME_OVERHEAD;
173 ((struct stack_frame *) new)->back_chain = old;
174 asm volatile(" la 15,0(%0)\n"
175 " basr 14,%2\n"
176 " la 15,0(%1)\n"
177 : : "a" (new), "a" (old),
178 "a" (__do_softirq)
179 : "0", "1", "2", "3", "4", "5", "14",
180 "cc", "memory" );
181 } else {
182 /* We are already on the async stack. */
183 __do_softirq();
184 }
185}
186
187/*
188 * ext_int_hash[index] is the list head for all external interrupts that hash
189 * to this index.
190 */
191static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
192
193struct ext_int_info {
194 ext_int_handler_t handler;
195 struct hlist_node entry;
196 struct rcu_head rcu;
197 u16 code;
198};
199
200/* ext_int_hash_lock protects the handler lists for external interrupts */
201static DEFINE_SPINLOCK(ext_int_hash_lock);
202
203static inline int ext_hash(u16 code)
204{
205 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
206
207 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
208}
209
210int register_external_irq(u16 code, ext_int_handler_t handler)
211{
212 struct ext_int_info *p;
213 unsigned long flags;
214 int index;
215
216 p = kmalloc(sizeof(*p), GFP_ATOMIC);
217 if (!p)
218 return -ENOMEM;
219 p->code = code;
220 p->handler = handler;
221 index = ext_hash(code);
222
223 spin_lock_irqsave(&ext_int_hash_lock, flags);
224 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
225 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
226 return 0;
227}
228EXPORT_SYMBOL(register_external_irq);
229
230int unregister_external_irq(u16 code, ext_int_handler_t handler)
231{
232 struct ext_int_info *p;
233 unsigned long flags;
234 int index = ext_hash(code);
235
236 spin_lock_irqsave(&ext_int_hash_lock, flags);
237 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
238 if (p->code == code && p->handler == handler) {
239 hlist_del_rcu(&p->entry);
240 kfree_rcu(p, rcu);
241 }
242 }
243 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
244 return 0;
245}
246EXPORT_SYMBOL(unregister_external_irq);
247
248static irqreturn_t do_ext_interrupt(int irq, void *dummy)
249{
250 struct pt_regs *regs = get_irq_regs();
251 struct ext_code ext_code;
252 struct ext_int_info *p;
253 int index;
254
255 ext_code = *(struct ext_code *) ®s->int_code;
256 if (ext_code.code != EXT_IRQ_CLK_COMP)
257 __get_cpu_var(s390_idle).nohz_delay = 1;
258
259 index = ext_hash(ext_code.code);
260 rcu_read_lock();
261 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
262 if (unlikely(p->code != ext_code.code))
263 continue;
264 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
265 }
266 rcu_read_unlock();
267 return IRQ_HANDLED;
268}
269
270static struct irqaction external_interrupt = {
271 .name = "EXT",
272 .handler = do_ext_interrupt,
273};
274
275void __init init_ext_interrupts(void)
276{
277 int idx;
278
279 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
280 INIT_HLIST_HEAD(&ext_int_hash[idx]);
281
282 irq_set_chip_and_handler(EXT_INTERRUPT,
283 &dummy_irq_chip, handle_percpu_irq);
284 setup_irq(EXT_INTERRUPT, &external_interrupt);
285}
286
287static DEFINE_SPINLOCK(irq_subclass_lock);
288static unsigned char irq_subclass_refcount[64];
289
290void irq_subclass_register(enum irq_subclass subclass)
291{
292 spin_lock(&irq_subclass_lock);
293 if (!irq_subclass_refcount[subclass])
294 ctl_set_bit(0, subclass);
295 irq_subclass_refcount[subclass]++;
296 spin_unlock(&irq_subclass_lock);
297}
298EXPORT_SYMBOL(irq_subclass_register);
299
300void irq_subclass_unregister(enum irq_subclass subclass)
301{
302 spin_lock(&irq_subclass_lock);
303 irq_subclass_refcount[subclass]--;
304 if (!irq_subclass_refcount[subclass])
305 ctl_clear_bit(0, subclass);
306 spin_unlock(&irq_subclass_lock);
307}
308EXPORT_SYMBOL(irq_subclass_unregister);