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1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <linux/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
35#include <linux/module.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/initval.h>
41/* for 440MX workaround */
42#include <asm/pgtable.h>
43#include <asm/cacheflush.h>
44
45MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
46MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
47MODULE_LICENSE("GPL");
48MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
49 "{Intel,82901AB-ICH0},"
50 "{Intel,82801BA-ICH2},"
51 "{Intel,82801CA-ICH3},"
52 "{Intel,82801DB-ICH4},"
53 "{Intel,ICH5},"
54 "{Intel,ICH6},"
55 "{Intel,ICH7},"
56 "{Intel,6300ESB},"
57 "{Intel,ESB2},"
58 "{Intel,MX440},"
59 "{SiS,SI7012},"
60 "{NVidia,nForce Audio},"
61 "{NVidia,nForce2 Audio},"
62 "{NVidia,nForce3 Audio},"
63 "{NVidia,MCP04},"
64 "{NVidia,MCP501},"
65 "{NVidia,CK804},"
66 "{NVidia,CK8},"
67 "{NVidia,CK8S},"
68 "{AMD,AMD768},"
69 "{AMD,AMD8111},"
70 "{ALI,M5455}}");
71
72static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
73static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
74static int ac97_clock;
75static char *ac97_quirk;
76static bool buggy_semaphore;
77static int buggy_irq = -1; /* auto-check */
78static bool xbox;
79static int spdif_aclink = -1;
80static int inside_vm = -1;
81
82module_param(index, int, 0444);
83MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
84module_param(id, charp, 0444);
85MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
86module_param(ac97_clock, int, 0444);
87MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
88module_param(ac97_quirk, charp, 0444);
89MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
90module_param(buggy_semaphore, bool, 0444);
91MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
92module_param(buggy_irq, bint, 0444);
93MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
94module_param(xbox, bool, 0444);
95MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
96module_param(spdif_aclink, int, 0444);
97MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
98module_param(inside_vm, bint, 0444);
99MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
100
101/* just for backward compatibility */
102static bool enable;
103module_param(enable, bool, 0444);
104static int joystick;
105module_param(joystick, int, 0444);
106
107/*
108 * Direct registers
109 */
110enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
111
112#define ICHREG(x) ICH_REG_##x
113
114#define DEFINE_REGSET(name,base) \
115enum { \
116 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
117 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
118 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
119 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
120 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
121 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
122 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
123};
124
125/* busmaster blocks */
126DEFINE_REGSET(OFF, 0); /* offset */
127DEFINE_REGSET(PI, 0x00); /* PCM in */
128DEFINE_REGSET(PO, 0x10); /* PCM out */
129DEFINE_REGSET(MC, 0x20); /* Mic in */
130
131/* ICH4 busmaster blocks */
132DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
133DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
134DEFINE_REGSET(SP, 0x60); /* SPDIF out */
135
136/* values for each busmaster block */
137
138/* LVI */
139#define ICH_REG_LVI_MASK 0x1f
140
141/* SR */
142#define ICH_FIFOE 0x10 /* FIFO error */
143#define ICH_BCIS 0x08 /* buffer completion interrupt status */
144#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
145#define ICH_CELV 0x02 /* current equals last valid */
146#define ICH_DCH 0x01 /* DMA controller halted */
147
148/* PIV */
149#define ICH_REG_PIV_MASK 0x1f /* mask */
150
151/* CR */
152#define ICH_IOCE 0x10 /* interrupt on completion enable */
153#define ICH_FEIE 0x08 /* fifo error interrupt enable */
154#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
155#define ICH_RESETREGS 0x02 /* reset busmaster registers */
156#define ICH_STARTBM 0x01 /* start busmaster operation */
157
158
159/* global block */
160#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
161#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
162#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
163#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
164#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
165#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
166#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
167#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
168#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
169#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
170#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
171#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
172#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
173#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
174#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
175#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
176#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
177#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
178#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
179#define ICH_ACLINK 0x00000008 /* AClink shut off */
180#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
181#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
182#define ICH_GIE 0x00000001 /* GPI interrupt enable */
183#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
184#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
185#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
186#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
187#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
188#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
189#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
190#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
191#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
192#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
193#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
194#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
195#define ICH_MD3 0x00020000 /* modem power down semaphore */
196#define ICH_AD3 0x00010000 /* audio power down semaphore */
197#define ICH_RCS 0x00008000 /* read completion status */
198#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
199#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
200#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
201#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
202#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
203#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
204#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
205#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
206#define ICH_POINT 0x00000040 /* playback interrupt */
207#define ICH_PIINT 0x00000020 /* capture interrupt */
208#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
209#define ICH_MOINT 0x00000004 /* modem playback interrupt */
210#define ICH_MIINT 0x00000002 /* modem capture interrupt */
211#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
212#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
213#define ICH_CAS 0x01 /* codec access semaphore */
214#define ICH_REG_SDM 0x80
215#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
216#define ICH_DI2L_SHIFT 6
217#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
218#define ICH_DI1L_SHIFT 4
219#define ICH_SE 0x00000008 /* steer enable */
220#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
221
222#define ICH_MAX_FRAGS 32 /* max hw frags */
223
224
225/*
226 * registers for Ali5455
227 */
228
229/* ALi 5455 busmaster blocks */
230DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
231DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
232DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
233DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
234DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
235DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
236DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
237DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
238DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
239DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
240DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
241
242enum {
243 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
244 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
245 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
246 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
247 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
248 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
249 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
250 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
251 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
252 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
253 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
254 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
255 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
256 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
257 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
258 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
259 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
260 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
261 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
262 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
263 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
264};
265
266#define ALI_CAS_SEM_BUSY 0x80000000
267#define ALI_CPR_ADDR_SECONDARY 0x100
268#define ALI_CPR_ADDR_READ 0x80
269#define ALI_CSPSR_CODEC_READY 0x08
270#define ALI_CSPSR_READ_OK 0x02
271#define ALI_CSPSR_WRITE_OK 0x01
272
273/* interrupts for the whole chip by interrupt status register finish */
274
275#define ALI_INT_MICIN2 (1<<26)
276#define ALI_INT_PCMIN2 (1<<25)
277#define ALI_INT_I2SIN (1<<24)
278#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
279#define ALI_INT_SPDIFIN (1<<22)
280#define ALI_INT_LFEOUT (1<<21)
281#define ALI_INT_CENTEROUT (1<<20)
282#define ALI_INT_CODECSPDIFOUT (1<<19)
283#define ALI_INT_MICIN (1<<18)
284#define ALI_INT_PCMOUT (1<<17)
285#define ALI_INT_PCMIN (1<<16)
286#define ALI_INT_CPRAIS (1<<7) /* command port available */
287#define ALI_INT_SPRAIS (1<<5) /* status port available */
288#define ALI_INT_GPIO (1<<1)
289#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
290 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
291
292#define ICH_ALI_SC_RESET (1<<31) /* master reset */
293#define ICH_ALI_SC_AC97_DBL (1<<30)
294#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
295#define ICH_ALI_SC_IN_BITS (3<<18)
296#define ICH_ALI_SC_OUT_BITS (3<<16)
297#define ICH_ALI_SC_6CH_CFG (3<<14)
298#define ICH_ALI_SC_PCM_4 (1<<8)
299#define ICH_ALI_SC_PCM_6 (2<<8)
300#define ICH_ALI_SC_PCM_246_MASK (3<<8)
301
302#define ICH_ALI_SS_SEC_ID (3<<5)
303#define ICH_ALI_SS_PRI_ID (3<<3)
304
305#define ICH_ALI_IF_AC97SP (1<<21)
306#define ICH_ALI_IF_MC (1<<20)
307#define ICH_ALI_IF_PI (1<<19)
308#define ICH_ALI_IF_MC2 (1<<18)
309#define ICH_ALI_IF_PI2 (1<<17)
310#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
311#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
312#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
313#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
314#define ICH_ALI_IF_PO_SPDF (1<<3)
315#define ICH_ALI_IF_PO (1<<1)
316
317/*
318 *
319 */
320
321enum {
322 ICHD_PCMIN,
323 ICHD_PCMOUT,
324 ICHD_MIC,
325 ICHD_MIC2,
326 ICHD_PCM2IN,
327 ICHD_SPBAR,
328 ICHD_LAST = ICHD_SPBAR
329};
330enum {
331 NVD_PCMIN,
332 NVD_PCMOUT,
333 NVD_MIC,
334 NVD_SPBAR,
335 NVD_LAST = NVD_SPBAR
336};
337enum {
338 ALID_PCMIN,
339 ALID_PCMOUT,
340 ALID_MIC,
341 ALID_AC97SPDIFOUT,
342 ALID_SPDIFIN,
343 ALID_SPDIFOUT,
344 ALID_LAST = ALID_SPDIFOUT
345};
346
347#define get_ichdev(substream) (substream->runtime->private_data)
348
349struct ichdev {
350 unsigned int ichd; /* ich device number */
351 unsigned long reg_offset; /* offset to bmaddr */
352 u32 *bdbar; /* CPU address (32bit) */
353 unsigned int bdbar_addr; /* PCI bus address (32bit) */
354 struct snd_pcm_substream *substream;
355 unsigned int physbuf; /* physical address (32bit) */
356 unsigned int size;
357 unsigned int fragsize;
358 unsigned int fragsize1;
359 unsigned int position;
360 unsigned int pos_shift;
361 unsigned int last_pos;
362 int frags;
363 int lvi;
364 int lvi_frag;
365 int civ;
366 int ack;
367 int ack_reload;
368 unsigned int ack_bit;
369 unsigned int roff_sr;
370 unsigned int roff_picb;
371 unsigned int int_sta_mask; /* interrupt status mask */
372 unsigned int ali_slot; /* ALI DMA slot */
373 struct ac97_pcm *pcm;
374 int pcm_open_flag;
375 unsigned int page_attr_changed: 1;
376 unsigned int suspended: 1;
377};
378
379struct intel8x0 {
380 unsigned int device_type;
381
382 int irq;
383
384 void __iomem *addr;
385 void __iomem *bmaddr;
386
387 struct pci_dev *pci;
388 struct snd_card *card;
389
390 int pcm_devs;
391 struct snd_pcm *pcm[6];
392 struct ichdev ichd[6];
393
394 unsigned multi4: 1,
395 multi6: 1,
396 multi8 :1,
397 dra: 1,
398 smp20bit: 1;
399 unsigned in_ac97_init: 1,
400 in_sdin_init: 1;
401 unsigned in_measurement: 1; /* during ac97 clock measurement */
402 unsigned fix_nocache: 1; /* workaround for 440MX */
403 unsigned buggy_irq: 1; /* workaround for buggy mobos */
404 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
405 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
406 unsigned inside_vm: 1; /* enable VM optimization */
407
408 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
409 unsigned int sdm_saved; /* SDM reg value */
410
411 struct snd_ac97_bus *ac97_bus;
412 struct snd_ac97 *ac97[3];
413 unsigned int ac97_sdin[3];
414 unsigned int max_codecs, ncodecs;
415 unsigned int *codec_bit;
416 unsigned int codec_isr_bits;
417 unsigned int codec_ready_bits;
418
419 spinlock_t reg_lock;
420
421 u32 bdbars_count;
422 struct snd_dma_buffer bdbars;
423 u32 int_sta_reg; /* interrupt status register */
424 u32 int_sta_mask; /* interrupt status mask */
425};
426
427static const struct pci_device_id snd_intel8x0_ids[] = {
428 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
429 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
430 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
431 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
432 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
433 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
434 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
435 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
436 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
437 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
438 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
439 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
440 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
441 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
442 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
443 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
444 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
445 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
446 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
447 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
448 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
449 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
450 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
451 { 0, }
452};
453
454MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
455
456/*
457 * Lowlevel I/O - busmaster
458 */
459
460static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
461{
462 return ioread8(chip->bmaddr + offset);
463}
464
465static inline u16 igetword(struct intel8x0 *chip, u32 offset)
466{
467 return ioread16(chip->bmaddr + offset);
468}
469
470static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
471{
472 return ioread32(chip->bmaddr + offset);
473}
474
475static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
476{
477 iowrite8(val, chip->bmaddr + offset);
478}
479
480static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
481{
482 iowrite16(val, chip->bmaddr + offset);
483}
484
485static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
486{
487 iowrite32(val, chip->bmaddr + offset);
488}
489
490/*
491 * Lowlevel I/O - AC'97 registers
492 */
493
494static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
495{
496 return ioread16(chip->addr + offset);
497}
498
499static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
500{
501 iowrite16(val, chip->addr + offset);
502}
503
504/*
505 * Basic I/O
506 */
507
508/*
509 * access to AC97 codec via normal i/o (for ICH and SIS7012)
510 */
511
512static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
513{
514 int time;
515
516 if (codec > 2)
517 return -EIO;
518 if (chip->in_sdin_init) {
519 /* we don't know the ready bit assignment at the moment */
520 /* so we check any */
521 codec = chip->codec_isr_bits;
522 } else {
523 codec = chip->codec_bit[chip->ac97_sdin[codec]];
524 }
525
526 /* codec ready ? */
527 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
528 return -EIO;
529
530 if (chip->buggy_semaphore)
531 return 0; /* just ignore ... */
532
533 /* Anyone holding a semaphore for 1 msec should be shot... */
534 time = 100;
535 do {
536 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
537 return 0;
538 udelay(10);
539 } while (time--);
540
541 /* access to some forbidden (non existent) ac97 registers will not
542 * reset the semaphore. So even if you don't get the semaphore, still
543 * continue the access. We don't need the semaphore anyway. */
544 dev_err(chip->card->dev,
545 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
546 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
547 iagetword(chip, 0); /* clear semaphore flag */
548 /* I don't care about the semaphore */
549 return -EBUSY;
550}
551
552static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
553 unsigned short reg,
554 unsigned short val)
555{
556 struct intel8x0 *chip = ac97->private_data;
557
558 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
559 if (! chip->in_ac97_init)
560 dev_err(chip->card->dev,
561 "codec_write %d: semaphore is not ready for register 0x%x\n",
562 ac97->num, reg);
563 }
564 iaputword(chip, reg + ac97->num * 0x80, val);
565}
566
567static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
568 unsigned short reg)
569{
570 struct intel8x0 *chip = ac97->private_data;
571 unsigned short res;
572 unsigned int tmp;
573
574 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
575 if (! chip->in_ac97_init)
576 dev_err(chip->card->dev,
577 "codec_read %d: semaphore is not ready for register 0x%x\n",
578 ac97->num, reg);
579 res = 0xffff;
580 } else {
581 res = iagetword(chip, reg + ac97->num * 0x80);
582 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
583 /* reset RCS and preserve other R/WC bits */
584 iputdword(chip, ICHREG(GLOB_STA), tmp &
585 ~(chip->codec_ready_bits | ICH_GSCI));
586 if (! chip->in_ac97_init)
587 dev_err(chip->card->dev,
588 "codec_read %d: read timeout for register 0x%x\n",
589 ac97->num, reg);
590 res = 0xffff;
591 }
592 }
593 return res;
594}
595
596static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
597 unsigned int codec)
598{
599 unsigned int tmp;
600
601 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
602 iagetword(chip, codec * 0x80);
603 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
604 /* reset RCS and preserve other R/WC bits */
605 iputdword(chip, ICHREG(GLOB_STA), tmp &
606 ~(chip->codec_ready_bits | ICH_GSCI));
607 }
608 }
609}
610
611/*
612 * access to AC97 for Ali5455
613 */
614static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
615{
616 int count = 0;
617 for (count = 0; count < 0x7f; count++) {
618 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
619 if (val & mask)
620 return 0;
621 }
622 if (! chip->in_ac97_init)
623 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
624 return -EBUSY;
625}
626
627static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
628{
629 int time = 100;
630 if (chip->buggy_semaphore)
631 return 0; /* just ignore ... */
632 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
633 udelay(1);
634 if (! time && ! chip->in_ac97_init)
635 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
636 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
637}
638
639static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
640{
641 struct intel8x0 *chip = ac97->private_data;
642 unsigned short data = 0xffff;
643
644 if (snd_intel8x0_ali_codec_semaphore(chip))
645 goto __err;
646 reg |= ALI_CPR_ADDR_READ;
647 if (ac97->num)
648 reg |= ALI_CPR_ADDR_SECONDARY;
649 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
650 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
651 goto __err;
652 data = igetword(chip, ICHREG(ALI_SPR));
653 __err:
654 return data;
655}
656
657static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
658 unsigned short val)
659{
660 struct intel8x0 *chip = ac97->private_data;
661
662 if (snd_intel8x0_ali_codec_semaphore(chip))
663 return;
664 iputword(chip, ICHREG(ALI_CPR), val);
665 if (ac97->num)
666 reg |= ALI_CPR_ADDR_SECONDARY;
667 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
668 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
669}
670
671
672/*
673 * DMA I/O
674 */
675static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
676{
677 int idx;
678 u32 *bdbar = ichdev->bdbar;
679 unsigned long port = ichdev->reg_offset;
680
681 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
682 if (ichdev->size == ichdev->fragsize) {
683 ichdev->ack_reload = ichdev->ack = 2;
684 ichdev->fragsize1 = ichdev->fragsize >> 1;
685 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
686 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
687 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
688 ichdev->fragsize1 >> ichdev->pos_shift);
689 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
690 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
691 ichdev->fragsize1 >> ichdev->pos_shift);
692 }
693 ichdev->frags = 2;
694 } else {
695 ichdev->ack_reload = ichdev->ack = 1;
696 ichdev->fragsize1 = ichdev->fragsize;
697 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
698 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
699 (((idx >> 1) * ichdev->fragsize) %
700 ichdev->size));
701 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
702 ichdev->fragsize >> ichdev->pos_shift);
703#if 0
704 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
705 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
706#endif
707 }
708 ichdev->frags = ichdev->size / ichdev->fragsize;
709 }
710 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
711 ichdev->civ = 0;
712 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
713 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
714 ichdev->position = 0;
715#if 0
716 dev_dbg(chip->card->dev,
717 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
718 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
719 ichdev->fragsize1);
720#endif
721 /* clear interrupts */
722 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
723}
724
725#ifdef __i386__
726/*
727 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
728 * which aborts PCI busmaster for audio transfer. A workaround is to set
729 * the pages as non-cached. For details, see the errata in
730 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
731 */
732static void fill_nocache(void *buf, int size, int nocache)
733{
734 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
735 if (nocache)
736 set_pages_uc(virt_to_page(buf), size);
737 else
738 set_pages_wb(virt_to_page(buf), size);
739}
740#else
741#define fill_nocache(buf, size, nocache) do { ; } while (0)
742#endif
743
744/*
745 * Interrupt handler
746 */
747
748static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
749{
750 unsigned long port = ichdev->reg_offset;
751 unsigned long flags;
752 int status, civ, i, step;
753 int ack = 0;
754
755 spin_lock_irqsave(&chip->reg_lock, flags);
756 status = igetbyte(chip, port + ichdev->roff_sr);
757 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
758 if (!(status & ICH_BCIS)) {
759 step = 0;
760 } else if (civ == ichdev->civ) {
761 // snd_printd("civ same %d\n", civ);
762 step = 1;
763 ichdev->civ++;
764 ichdev->civ &= ICH_REG_LVI_MASK;
765 } else {
766 step = civ - ichdev->civ;
767 if (step < 0)
768 step += ICH_REG_LVI_MASK + 1;
769 // if (step != 1)
770 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
771 ichdev->civ = civ;
772 }
773
774 ichdev->position += step * ichdev->fragsize1;
775 if (! chip->in_measurement)
776 ichdev->position %= ichdev->size;
777 ichdev->lvi += step;
778 ichdev->lvi &= ICH_REG_LVI_MASK;
779 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
780 for (i = 0; i < step; i++) {
781 ichdev->lvi_frag++;
782 ichdev->lvi_frag %= ichdev->frags;
783 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
784#if 0
785 dev_dbg(chip->card->dev,
786 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
787 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
788 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
789 inl(port + 4), inb(port + ICH_REG_OFF_CR));
790#endif
791 if (--ichdev->ack == 0) {
792 ichdev->ack = ichdev->ack_reload;
793 ack = 1;
794 }
795 }
796 spin_unlock_irqrestore(&chip->reg_lock, flags);
797 if (ack && ichdev->substream) {
798 snd_pcm_period_elapsed(ichdev->substream);
799 }
800 iputbyte(chip, port + ichdev->roff_sr,
801 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
802}
803
804static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
805{
806 struct intel8x0 *chip = dev_id;
807 struct ichdev *ichdev;
808 unsigned int status;
809 unsigned int i;
810
811 status = igetdword(chip, chip->int_sta_reg);
812 if (status == 0xffffffff) /* we are not yet resumed */
813 return IRQ_NONE;
814
815 if ((status & chip->int_sta_mask) == 0) {
816 if (status) {
817 /* ack */
818 iputdword(chip, chip->int_sta_reg, status);
819 if (! chip->buggy_irq)
820 status = 0;
821 }
822 return IRQ_RETVAL(status);
823 }
824
825 for (i = 0; i < chip->bdbars_count; i++) {
826 ichdev = &chip->ichd[i];
827 if (status & ichdev->int_sta_mask)
828 snd_intel8x0_update(chip, ichdev);
829 }
830
831 /* ack them */
832 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
833
834 return IRQ_HANDLED;
835}
836
837/*
838 * PCM part
839 */
840
841static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
842{
843 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
844 struct ichdev *ichdev = get_ichdev(substream);
845 unsigned char val = 0;
846 unsigned long port = ichdev->reg_offset;
847
848 switch (cmd) {
849 case SNDRV_PCM_TRIGGER_RESUME:
850 ichdev->suspended = 0;
851 /* fallthru */
852 case SNDRV_PCM_TRIGGER_START:
853 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
854 val = ICH_IOCE | ICH_STARTBM;
855 ichdev->last_pos = ichdev->position;
856 break;
857 case SNDRV_PCM_TRIGGER_SUSPEND:
858 ichdev->suspended = 1;
859 /* fallthru */
860 case SNDRV_PCM_TRIGGER_STOP:
861 val = 0;
862 break;
863 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
864 val = ICH_IOCE;
865 break;
866 default:
867 return -EINVAL;
868 }
869 iputbyte(chip, port + ICH_REG_OFF_CR, val);
870 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
871 /* wait until DMA stopped */
872 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
873 /* reset whole DMA things */
874 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
875 }
876 return 0;
877}
878
879static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
880{
881 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
882 struct ichdev *ichdev = get_ichdev(substream);
883 unsigned long port = ichdev->reg_offset;
884 static int fiforeg[] = {
885 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
886 };
887 unsigned int val, fifo;
888
889 val = igetdword(chip, ICHREG(ALI_DMACR));
890 switch (cmd) {
891 case SNDRV_PCM_TRIGGER_RESUME:
892 ichdev->suspended = 0;
893 /* fallthru */
894 case SNDRV_PCM_TRIGGER_START:
895 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
896 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
897 /* clear FIFO for synchronization of channels */
898 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
899 fifo &= ~(0xff << (ichdev->ali_slot % 4));
900 fifo |= 0x83 << (ichdev->ali_slot % 4);
901 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
902 }
903 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
904 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
905 /* start DMA */
906 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
907 break;
908 case SNDRV_PCM_TRIGGER_SUSPEND:
909 ichdev->suspended = 1;
910 /* fallthru */
911 case SNDRV_PCM_TRIGGER_STOP:
912 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
913 /* pause */
914 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
915 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
916 while (igetbyte(chip, port + ICH_REG_OFF_CR))
917 ;
918 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
919 break;
920 /* reset whole DMA things */
921 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
922 /* clear interrupts */
923 iputbyte(chip, port + ICH_REG_OFF_SR,
924 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
925 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
926 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
927 break;
928 default:
929 return -EINVAL;
930 }
931 return 0;
932}
933
934static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
935 struct snd_pcm_hw_params *hw_params)
936{
937 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
938 struct ichdev *ichdev = get_ichdev(substream);
939 struct snd_pcm_runtime *runtime = substream->runtime;
940 int dbl = params_rate(hw_params) > 48000;
941 int err;
942
943 if (chip->fix_nocache && ichdev->page_attr_changed) {
944 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
945 ichdev->page_attr_changed = 0;
946 }
947 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
948 if (err < 0)
949 return err;
950 if (chip->fix_nocache) {
951 if (runtime->dma_area && ! ichdev->page_attr_changed) {
952 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
953 ichdev->page_attr_changed = 1;
954 }
955 }
956 if (ichdev->pcm_open_flag) {
957 snd_ac97_pcm_close(ichdev->pcm);
958 ichdev->pcm_open_flag = 0;
959 }
960 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
961 params_channels(hw_params),
962 ichdev->pcm->r[dbl].slots);
963 if (err >= 0) {
964 ichdev->pcm_open_flag = 1;
965 /* Force SPDIF setting */
966 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
967 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
968 params_rate(hw_params));
969 }
970 return err;
971}
972
973static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
974{
975 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
976 struct ichdev *ichdev = get_ichdev(substream);
977
978 if (ichdev->pcm_open_flag) {
979 snd_ac97_pcm_close(ichdev->pcm);
980 ichdev->pcm_open_flag = 0;
981 }
982 if (chip->fix_nocache && ichdev->page_attr_changed) {
983 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
984 ichdev->page_attr_changed = 0;
985 }
986 return snd_pcm_lib_free_pages(substream);
987}
988
989static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
990 struct snd_pcm_runtime *runtime)
991{
992 unsigned int cnt;
993 int dbl = runtime->rate > 48000;
994
995 spin_lock_irq(&chip->reg_lock);
996 switch (chip->device_type) {
997 case DEVICE_ALI:
998 cnt = igetdword(chip, ICHREG(ALI_SCR));
999 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1000 if (runtime->channels == 4 || dbl)
1001 cnt |= ICH_ALI_SC_PCM_4;
1002 else if (runtime->channels == 6)
1003 cnt |= ICH_ALI_SC_PCM_6;
1004 iputdword(chip, ICHREG(ALI_SCR), cnt);
1005 break;
1006 case DEVICE_SIS:
1007 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1008 cnt &= ~ICH_SIS_PCM_246_MASK;
1009 if (runtime->channels == 4 || dbl)
1010 cnt |= ICH_SIS_PCM_4;
1011 else if (runtime->channels == 6)
1012 cnt |= ICH_SIS_PCM_6;
1013 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1014 break;
1015 default:
1016 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1017 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1018 if (runtime->channels == 4 || dbl)
1019 cnt |= ICH_PCM_4;
1020 else if (runtime->channels == 6)
1021 cnt |= ICH_PCM_6;
1022 else if (runtime->channels == 8)
1023 cnt |= ICH_PCM_8;
1024 if (chip->device_type == DEVICE_NFORCE) {
1025 /* reset to 2ch once to keep the 6 channel data in alignment,
1026 * to start from Front Left always
1027 */
1028 if (cnt & ICH_PCM_246_MASK) {
1029 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1030 spin_unlock_irq(&chip->reg_lock);
1031 msleep(50); /* grrr... */
1032 spin_lock_irq(&chip->reg_lock);
1033 }
1034 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1035 if (runtime->sample_bits > 16)
1036 cnt |= ICH_PCM_20BIT;
1037 }
1038 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1039 break;
1040 }
1041 spin_unlock_irq(&chip->reg_lock);
1042}
1043
1044static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1045{
1046 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1047 struct snd_pcm_runtime *runtime = substream->runtime;
1048 struct ichdev *ichdev = get_ichdev(substream);
1049
1050 ichdev->physbuf = runtime->dma_addr;
1051 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1052 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1053 if (ichdev->ichd == ICHD_PCMOUT) {
1054 snd_intel8x0_setup_pcm_out(chip, runtime);
1055 if (chip->device_type == DEVICE_INTEL_ICH4)
1056 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1057 }
1058 snd_intel8x0_setup_periods(chip, ichdev);
1059 return 0;
1060}
1061
1062static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1063{
1064 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1065 struct ichdev *ichdev = get_ichdev(substream);
1066 size_t ptr1, ptr;
1067 int civ, timeout = 10;
1068 unsigned int position;
1069
1070 spin_lock(&chip->reg_lock);
1071 do {
1072 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1073 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1074 position = ichdev->position;
1075 if (ptr1 == 0) {
1076 udelay(10);
1077 continue;
1078 }
1079 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1080 continue;
1081
1082 /* IO read operation is very expensive inside virtual machine
1083 * as it is emulated. The probability that subsequent PICB read
1084 * will return different result is high enough to loop till
1085 * timeout here.
1086 * Same CIV is strict enough condition to be sure that PICB
1087 * is valid inside VM on emulated card. */
1088 if (chip->inside_vm)
1089 break;
1090 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1091 break;
1092 } while (timeout--);
1093 ptr = ichdev->last_pos;
1094 if (ptr1 != 0) {
1095 ptr1 <<= ichdev->pos_shift;
1096 ptr = ichdev->fragsize1 - ptr1;
1097 ptr += position;
1098 if (ptr < ichdev->last_pos) {
1099 unsigned int pos_base, last_base;
1100 pos_base = position / ichdev->fragsize1;
1101 last_base = ichdev->last_pos / ichdev->fragsize1;
1102 /* another sanity check; ptr1 can go back to full
1103 * before the base position is updated
1104 */
1105 if (pos_base == last_base)
1106 ptr = ichdev->last_pos;
1107 }
1108 }
1109 ichdev->last_pos = ptr;
1110 spin_unlock(&chip->reg_lock);
1111 if (ptr >= ichdev->size)
1112 return 0;
1113 return bytes_to_frames(substream->runtime, ptr);
1114}
1115
1116static struct snd_pcm_hardware snd_intel8x0_stream =
1117{
1118 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1119 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1120 SNDRV_PCM_INFO_MMAP_VALID |
1121 SNDRV_PCM_INFO_PAUSE |
1122 SNDRV_PCM_INFO_RESUME),
1123 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1124 .rates = SNDRV_PCM_RATE_48000,
1125 .rate_min = 48000,
1126 .rate_max = 48000,
1127 .channels_min = 2,
1128 .channels_max = 2,
1129 .buffer_bytes_max = 128 * 1024,
1130 .period_bytes_min = 32,
1131 .period_bytes_max = 128 * 1024,
1132 .periods_min = 1,
1133 .periods_max = 1024,
1134 .fifo_size = 0,
1135};
1136
1137static unsigned int channels4[] = {
1138 2, 4,
1139};
1140
1141static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1142 .count = ARRAY_SIZE(channels4),
1143 .list = channels4,
1144 .mask = 0,
1145};
1146
1147static unsigned int channels6[] = {
1148 2, 4, 6,
1149};
1150
1151static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1152 .count = ARRAY_SIZE(channels6),
1153 .list = channels6,
1154 .mask = 0,
1155};
1156
1157static unsigned int channels8[] = {
1158 2, 4, 6, 8,
1159};
1160
1161static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1162 .count = ARRAY_SIZE(channels8),
1163 .list = channels8,
1164 .mask = 0,
1165};
1166
1167static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1168{
1169 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1170 struct snd_pcm_runtime *runtime = substream->runtime;
1171 int err;
1172
1173 ichdev->substream = substream;
1174 runtime->hw = snd_intel8x0_stream;
1175 runtime->hw.rates = ichdev->pcm->rates;
1176 snd_pcm_limit_hw_rates(runtime);
1177 if (chip->device_type == DEVICE_SIS) {
1178 runtime->hw.buffer_bytes_max = 64*1024;
1179 runtime->hw.period_bytes_max = 64*1024;
1180 }
1181 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1182 return err;
1183 runtime->private_data = ichdev;
1184 return 0;
1185}
1186
1187static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1188{
1189 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1190 struct snd_pcm_runtime *runtime = substream->runtime;
1191 int err;
1192
1193 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1194 if (err < 0)
1195 return err;
1196
1197 if (chip->multi8) {
1198 runtime->hw.channels_max = 8;
1199 snd_pcm_hw_constraint_list(runtime, 0,
1200 SNDRV_PCM_HW_PARAM_CHANNELS,
1201 &hw_constraints_channels8);
1202 } else if (chip->multi6) {
1203 runtime->hw.channels_max = 6;
1204 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1205 &hw_constraints_channels6);
1206 } else if (chip->multi4) {
1207 runtime->hw.channels_max = 4;
1208 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1209 &hw_constraints_channels4);
1210 }
1211 if (chip->dra) {
1212 snd_ac97_pcm_double_rate_rules(runtime);
1213 }
1214 if (chip->smp20bit) {
1215 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1216 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1217 }
1218 return 0;
1219}
1220
1221static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1222{
1223 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1224
1225 chip->ichd[ICHD_PCMOUT].substream = NULL;
1226 return 0;
1227}
1228
1229static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1230{
1231 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1232
1233 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1234}
1235
1236static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1237{
1238 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1239
1240 chip->ichd[ICHD_PCMIN].substream = NULL;
1241 return 0;
1242}
1243
1244static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1245{
1246 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1247
1248 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1249}
1250
1251static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1252{
1253 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1254
1255 chip->ichd[ICHD_MIC].substream = NULL;
1256 return 0;
1257}
1258
1259static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1260{
1261 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1262
1263 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1264}
1265
1266static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1267{
1268 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1269
1270 chip->ichd[ICHD_MIC2].substream = NULL;
1271 return 0;
1272}
1273
1274static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1275{
1276 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1277
1278 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1279}
1280
1281static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1282{
1283 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1284
1285 chip->ichd[ICHD_PCM2IN].substream = NULL;
1286 return 0;
1287}
1288
1289static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1290{
1291 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1292 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1293
1294 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1295}
1296
1297static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1298{
1299 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1300 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1301
1302 chip->ichd[idx].substream = NULL;
1303 return 0;
1304}
1305
1306static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1307{
1308 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1309 unsigned int val;
1310
1311 spin_lock_irq(&chip->reg_lock);
1312 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1313 val |= ICH_ALI_IF_AC97SP;
1314 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1315 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1316 spin_unlock_irq(&chip->reg_lock);
1317
1318 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1319}
1320
1321static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1322{
1323 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1324 unsigned int val;
1325
1326 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1327 spin_lock_irq(&chip->reg_lock);
1328 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1329 val &= ~ICH_ALI_IF_AC97SP;
1330 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1331 spin_unlock_irq(&chip->reg_lock);
1332
1333 return 0;
1334}
1335
1336#if 0 // NYI
1337static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1338{
1339 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1340
1341 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1342}
1343
1344static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1345{
1346 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1347
1348 chip->ichd[ALID_SPDIFIN].substream = NULL;
1349 return 0;
1350}
1351
1352static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1353{
1354 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1355
1356 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1357}
1358
1359static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1360{
1361 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1362
1363 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1364 return 0;
1365}
1366#endif
1367
1368static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1369 .open = snd_intel8x0_playback_open,
1370 .close = snd_intel8x0_playback_close,
1371 .ioctl = snd_pcm_lib_ioctl,
1372 .hw_params = snd_intel8x0_hw_params,
1373 .hw_free = snd_intel8x0_hw_free,
1374 .prepare = snd_intel8x0_pcm_prepare,
1375 .trigger = snd_intel8x0_pcm_trigger,
1376 .pointer = snd_intel8x0_pcm_pointer,
1377};
1378
1379static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1380 .open = snd_intel8x0_capture_open,
1381 .close = snd_intel8x0_capture_close,
1382 .ioctl = snd_pcm_lib_ioctl,
1383 .hw_params = snd_intel8x0_hw_params,
1384 .hw_free = snd_intel8x0_hw_free,
1385 .prepare = snd_intel8x0_pcm_prepare,
1386 .trigger = snd_intel8x0_pcm_trigger,
1387 .pointer = snd_intel8x0_pcm_pointer,
1388};
1389
1390static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1391 .open = snd_intel8x0_mic_open,
1392 .close = snd_intel8x0_mic_close,
1393 .ioctl = snd_pcm_lib_ioctl,
1394 .hw_params = snd_intel8x0_hw_params,
1395 .hw_free = snd_intel8x0_hw_free,
1396 .prepare = snd_intel8x0_pcm_prepare,
1397 .trigger = snd_intel8x0_pcm_trigger,
1398 .pointer = snd_intel8x0_pcm_pointer,
1399};
1400
1401static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1402 .open = snd_intel8x0_mic2_open,
1403 .close = snd_intel8x0_mic2_close,
1404 .ioctl = snd_pcm_lib_ioctl,
1405 .hw_params = snd_intel8x0_hw_params,
1406 .hw_free = snd_intel8x0_hw_free,
1407 .prepare = snd_intel8x0_pcm_prepare,
1408 .trigger = snd_intel8x0_pcm_trigger,
1409 .pointer = snd_intel8x0_pcm_pointer,
1410};
1411
1412static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1413 .open = snd_intel8x0_capture2_open,
1414 .close = snd_intel8x0_capture2_close,
1415 .ioctl = snd_pcm_lib_ioctl,
1416 .hw_params = snd_intel8x0_hw_params,
1417 .hw_free = snd_intel8x0_hw_free,
1418 .prepare = snd_intel8x0_pcm_prepare,
1419 .trigger = snd_intel8x0_pcm_trigger,
1420 .pointer = snd_intel8x0_pcm_pointer,
1421};
1422
1423static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1424 .open = snd_intel8x0_spdif_open,
1425 .close = snd_intel8x0_spdif_close,
1426 .ioctl = snd_pcm_lib_ioctl,
1427 .hw_params = snd_intel8x0_hw_params,
1428 .hw_free = snd_intel8x0_hw_free,
1429 .prepare = snd_intel8x0_pcm_prepare,
1430 .trigger = snd_intel8x0_pcm_trigger,
1431 .pointer = snd_intel8x0_pcm_pointer,
1432};
1433
1434static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1435 .open = snd_intel8x0_playback_open,
1436 .close = snd_intel8x0_playback_close,
1437 .ioctl = snd_pcm_lib_ioctl,
1438 .hw_params = snd_intel8x0_hw_params,
1439 .hw_free = snd_intel8x0_hw_free,
1440 .prepare = snd_intel8x0_pcm_prepare,
1441 .trigger = snd_intel8x0_ali_trigger,
1442 .pointer = snd_intel8x0_pcm_pointer,
1443};
1444
1445static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1446 .open = snd_intel8x0_capture_open,
1447 .close = snd_intel8x0_capture_close,
1448 .ioctl = snd_pcm_lib_ioctl,
1449 .hw_params = snd_intel8x0_hw_params,
1450 .hw_free = snd_intel8x0_hw_free,
1451 .prepare = snd_intel8x0_pcm_prepare,
1452 .trigger = snd_intel8x0_ali_trigger,
1453 .pointer = snd_intel8x0_pcm_pointer,
1454};
1455
1456static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1457 .open = snd_intel8x0_mic_open,
1458 .close = snd_intel8x0_mic_close,
1459 .ioctl = snd_pcm_lib_ioctl,
1460 .hw_params = snd_intel8x0_hw_params,
1461 .hw_free = snd_intel8x0_hw_free,
1462 .prepare = snd_intel8x0_pcm_prepare,
1463 .trigger = snd_intel8x0_ali_trigger,
1464 .pointer = snd_intel8x0_pcm_pointer,
1465};
1466
1467static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1468 .open = snd_intel8x0_ali_ac97spdifout_open,
1469 .close = snd_intel8x0_ali_ac97spdifout_close,
1470 .ioctl = snd_pcm_lib_ioctl,
1471 .hw_params = snd_intel8x0_hw_params,
1472 .hw_free = snd_intel8x0_hw_free,
1473 .prepare = snd_intel8x0_pcm_prepare,
1474 .trigger = snd_intel8x0_ali_trigger,
1475 .pointer = snd_intel8x0_pcm_pointer,
1476};
1477
1478#if 0 // NYI
1479static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1480 .open = snd_intel8x0_ali_spdifin_open,
1481 .close = snd_intel8x0_ali_spdifin_close,
1482 .ioctl = snd_pcm_lib_ioctl,
1483 .hw_params = snd_intel8x0_hw_params,
1484 .hw_free = snd_intel8x0_hw_free,
1485 .prepare = snd_intel8x0_pcm_prepare,
1486 .trigger = snd_intel8x0_pcm_trigger,
1487 .pointer = snd_intel8x0_pcm_pointer,
1488};
1489
1490static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1491 .open = snd_intel8x0_ali_spdifout_open,
1492 .close = snd_intel8x0_ali_spdifout_close,
1493 .ioctl = snd_pcm_lib_ioctl,
1494 .hw_params = snd_intel8x0_hw_params,
1495 .hw_free = snd_intel8x0_hw_free,
1496 .prepare = snd_intel8x0_pcm_prepare,
1497 .trigger = snd_intel8x0_pcm_trigger,
1498 .pointer = snd_intel8x0_pcm_pointer,
1499};
1500#endif // NYI
1501
1502struct ich_pcm_table {
1503 char *suffix;
1504 struct snd_pcm_ops *playback_ops;
1505 struct snd_pcm_ops *capture_ops;
1506 size_t prealloc_size;
1507 size_t prealloc_max_size;
1508 int ac97_idx;
1509};
1510
1511static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1512 struct ich_pcm_table *rec)
1513{
1514 struct snd_pcm *pcm;
1515 int err;
1516 char name[32];
1517
1518 if (rec->suffix)
1519 sprintf(name, "Intel ICH - %s", rec->suffix);
1520 else
1521 strcpy(name, "Intel ICH");
1522 err = snd_pcm_new(chip->card, name, device,
1523 rec->playback_ops ? 1 : 0,
1524 rec->capture_ops ? 1 : 0, &pcm);
1525 if (err < 0)
1526 return err;
1527
1528 if (rec->playback_ops)
1529 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1530 if (rec->capture_ops)
1531 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1532
1533 pcm->private_data = chip;
1534 pcm->info_flags = 0;
1535 if (rec->suffix)
1536 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1537 else
1538 strcpy(pcm->name, chip->card->shortname);
1539 chip->pcm[device] = pcm;
1540
1541 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1542 snd_dma_pci_data(chip->pci),
1543 rec->prealloc_size, rec->prealloc_max_size);
1544
1545 if (rec->playback_ops &&
1546 rec->playback_ops->open == snd_intel8x0_playback_open) {
1547 struct snd_pcm_chmap *chmap;
1548 int chs = 2;
1549 if (chip->multi8)
1550 chs = 8;
1551 else if (chip->multi6)
1552 chs = 6;
1553 else if (chip->multi4)
1554 chs = 4;
1555 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1556 snd_pcm_alt_chmaps, chs, 0,
1557 &chmap);
1558 if (err < 0)
1559 return err;
1560 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1561 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1562 }
1563
1564 return 0;
1565}
1566
1567static struct ich_pcm_table intel_pcms[] = {
1568 {
1569 .playback_ops = &snd_intel8x0_playback_ops,
1570 .capture_ops = &snd_intel8x0_capture_ops,
1571 .prealloc_size = 64 * 1024,
1572 .prealloc_max_size = 128 * 1024,
1573 },
1574 {
1575 .suffix = "MIC ADC",
1576 .capture_ops = &snd_intel8x0_capture_mic_ops,
1577 .prealloc_size = 0,
1578 .prealloc_max_size = 128 * 1024,
1579 .ac97_idx = ICHD_MIC,
1580 },
1581 {
1582 .suffix = "MIC2 ADC",
1583 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1584 .prealloc_size = 0,
1585 .prealloc_max_size = 128 * 1024,
1586 .ac97_idx = ICHD_MIC2,
1587 },
1588 {
1589 .suffix = "ADC2",
1590 .capture_ops = &snd_intel8x0_capture2_ops,
1591 .prealloc_size = 0,
1592 .prealloc_max_size = 128 * 1024,
1593 .ac97_idx = ICHD_PCM2IN,
1594 },
1595 {
1596 .suffix = "IEC958",
1597 .playback_ops = &snd_intel8x0_spdif_ops,
1598 .prealloc_size = 64 * 1024,
1599 .prealloc_max_size = 128 * 1024,
1600 .ac97_idx = ICHD_SPBAR,
1601 },
1602};
1603
1604static struct ich_pcm_table nforce_pcms[] = {
1605 {
1606 .playback_ops = &snd_intel8x0_playback_ops,
1607 .capture_ops = &snd_intel8x0_capture_ops,
1608 .prealloc_size = 64 * 1024,
1609 .prealloc_max_size = 128 * 1024,
1610 },
1611 {
1612 .suffix = "MIC ADC",
1613 .capture_ops = &snd_intel8x0_capture_mic_ops,
1614 .prealloc_size = 0,
1615 .prealloc_max_size = 128 * 1024,
1616 .ac97_idx = NVD_MIC,
1617 },
1618 {
1619 .suffix = "IEC958",
1620 .playback_ops = &snd_intel8x0_spdif_ops,
1621 .prealloc_size = 64 * 1024,
1622 .prealloc_max_size = 128 * 1024,
1623 .ac97_idx = NVD_SPBAR,
1624 },
1625};
1626
1627static struct ich_pcm_table ali_pcms[] = {
1628 {
1629 .playback_ops = &snd_intel8x0_ali_playback_ops,
1630 .capture_ops = &snd_intel8x0_ali_capture_ops,
1631 .prealloc_size = 64 * 1024,
1632 .prealloc_max_size = 128 * 1024,
1633 },
1634 {
1635 .suffix = "MIC ADC",
1636 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1637 .prealloc_size = 0,
1638 .prealloc_max_size = 128 * 1024,
1639 .ac97_idx = ALID_MIC,
1640 },
1641 {
1642 .suffix = "IEC958",
1643 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1644 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1645 .prealloc_size = 64 * 1024,
1646 .prealloc_max_size = 128 * 1024,
1647 .ac97_idx = ALID_AC97SPDIFOUT,
1648 },
1649#if 0 // NYI
1650 {
1651 .suffix = "HW IEC958",
1652 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1653 .prealloc_size = 64 * 1024,
1654 .prealloc_max_size = 128 * 1024,
1655 },
1656#endif
1657};
1658
1659static int snd_intel8x0_pcm(struct intel8x0 *chip)
1660{
1661 int i, tblsize, device, err;
1662 struct ich_pcm_table *tbl, *rec;
1663
1664 switch (chip->device_type) {
1665 case DEVICE_INTEL_ICH4:
1666 tbl = intel_pcms;
1667 tblsize = ARRAY_SIZE(intel_pcms);
1668 if (spdif_aclink)
1669 tblsize--;
1670 break;
1671 case DEVICE_NFORCE:
1672 tbl = nforce_pcms;
1673 tblsize = ARRAY_SIZE(nforce_pcms);
1674 if (spdif_aclink)
1675 tblsize--;
1676 break;
1677 case DEVICE_ALI:
1678 tbl = ali_pcms;
1679 tblsize = ARRAY_SIZE(ali_pcms);
1680 break;
1681 default:
1682 tbl = intel_pcms;
1683 tblsize = 2;
1684 break;
1685 }
1686
1687 device = 0;
1688 for (i = 0; i < tblsize; i++) {
1689 rec = tbl + i;
1690 if (i > 0 && rec->ac97_idx) {
1691 /* activate PCM only when associated AC'97 codec */
1692 if (! chip->ichd[rec->ac97_idx].pcm)
1693 continue;
1694 }
1695 err = snd_intel8x0_pcm1(chip, device, rec);
1696 if (err < 0)
1697 return err;
1698 device++;
1699 }
1700
1701 chip->pcm_devs = device;
1702 return 0;
1703}
1704
1705
1706/*
1707 * Mixer part
1708 */
1709
1710static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1711{
1712 struct intel8x0 *chip = bus->private_data;
1713 chip->ac97_bus = NULL;
1714}
1715
1716static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1717{
1718 struct intel8x0 *chip = ac97->private_data;
1719 chip->ac97[ac97->num] = NULL;
1720}
1721
1722static struct ac97_pcm ac97_pcm_defs[] = {
1723 /* front PCM */
1724 {
1725 .exclusive = 1,
1726 .r = { {
1727 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1728 (1 << AC97_SLOT_PCM_RIGHT) |
1729 (1 << AC97_SLOT_PCM_CENTER) |
1730 (1 << AC97_SLOT_PCM_SLEFT) |
1731 (1 << AC97_SLOT_PCM_SRIGHT) |
1732 (1 << AC97_SLOT_LFE)
1733 },
1734 {
1735 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1736 (1 << AC97_SLOT_PCM_RIGHT) |
1737 (1 << AC97_SLOT_PCM_LEFT_0) |
1738 (1 << AC97_SLOT_PCM_RIGHT_0)
1739 }
1740 }
1741 },
1742 /* PCM IN #1 */
1743 {
1744 .stream = 1,
1745 .exclusive = 1,
1746 .r = { {
1747 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1748 (1 << AC97_SLOT_PCM_RIGHT)
1749 }
1750 }
1751 },
1752 /* MIC IN #1 */
1753 {
1754 .stream = 1,
1755 .exclusive = 1,
1756 .r = { {
1757 .slots = (1 << AC97_SLOT_MIC)
1758 }
1759 }
1760 },
1761 /* S/PDIF PCM */
1762 {
1763 .exclusive = 1,
1764 .spdif = 1,
1765 .r = { {
1766 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1767 (1 << AC97_SLOT_SPDIF_RIGHT2)
1768 }
1769 }
1770 },
1771 /* PCM IN #2 */
1772 {
1773 .stream = 1,
1774 .exclusive = 1,
1775 .r = { {
1776 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1777 (1 << AC97_SLOT_PCM_RIGHT)
1778 }
1779 }
1780 },
1781 /* MIC IN #2 */
1782 {
1783 .stream = 1,
1784 .exclusive = 1,
1785 .r = { {
1786 .slots = (1 << AC97_SLOT_MIC)
1787 }
1788 }
1789 },
1790};
1791
1792static const struct ac97_quirk ac97_quirks[] = {
1793 {
1794 .subvendor = 0x0e11,
1795 .subdevice = 0x000e,
1796 .name = "Compaq Deskpro EN", /* AD1885 */
1797 .type = AC97_TUNE_HP_ONLY
1798 },
1799 {
1800 .subvendor = 0x0e11,
1801 .subdevice = 0x008a,
1802 .name = "Compaq Evo W4000", /* AD1885 */
1803 .type = AC97_TUNE_HP_ONLY
1804 },
1805 {
1806 .subvendor = 0x0e11,
1807 .subdevice = 0x00b8,
1808 .name = "Compaq Evo D510C",
1809 .type = AC97_TUNE_HP_ONLY
1810 },
1811 {
1812 .subvendor = 0x0e11,
1813 .subdevice = 0x0860,
1814 .name = "HP/Compaq nx7010",
1815 .type = AC97_TUNE_MUTE_LED
1816 },
1817 {
1818 .subvendor = 0x1014,
1819 .subdevice = 0x0534,
1820 .name = "ThinkPad X31",
1821 .type = AC97_TUNE_INV_EAPD
1822 },
1823 {
1824 .subvendor = 0x1014,
1825 .subdevice = 0x1f00,
1826 .name = "MS-9128",
1827 .type = AC97_TUNE_ALC_JACK
1828 },
1829 {
1830 .subvendor = 0x1014,
1831 .subdevice = 0x0267,
1832 .name = "IBM NetVista A30p", /* AD1981B */
1833 .type = AC97_TUNE_HP_ONLY
1834 },
1835 {
1836 .subvendor = 0x1025,
1837 .subdevice = 0x0082,
1838 .name = "Acer Travelmate 2310",
1839 .type = AC97_TUNE_HP_ONLY
1840 },
1841 {
1842 .subvendor = 0x1025,
1843 .subdevice = 0x0083,
1844 .name = "Acer Aspire 3003LCi",
1845 .type = AC97_TUNE_HP_ONLY
1846 },
1847 {
1848 .subvendor = 0x1028,
1849 .subdevice = 0x00d8,
1850 .name = "Dell Precision 530", /* AD1885 */
1851 .type = AC97_TUNE_HP_ONLY
1852 },
1853 {
1854 .subvendor = 0x1028,
1855 .subdevice = 0x010d,
1856 .name = "Dell", /* which model? AD1885 */
1857 .type = AC97_TUNE_HP_ONLY
1858 },
1859 {
1860 .subvendor = 0x1028,
1861 .subdevice = 0x0126,
1862 .name = "Dell Optiplex GX260", /* AD1981A */
1863 .type = AC97_TUNE_HP_ONLY
1864 },
1865 {
1866 .subvendor = 0x1028,
1867 .subdevice = 0x012c,
1868 .name = "Dell Precision 650", /* AD1981A */
1869 .type = AC97_TUNE_HP_ONLY
1870 },
1871 {
1872 .subvendor = 0x1028,
1873 .subdevice = 0x012d,
1874 .name = "Dell Precision 450", /* AD1981B*/
1875 .type = AC97_TUNE_HP_ONLY
1876 },
1877 {
1878 .subvendor = 0x1028,
1879 .subdevice = 0x0147,
1880 .name = "Dell", /* which model? AD1981B*/
1881 .type = AC97_TUNE_HP_ONLY
1882 },
1883 {
1884 .subvendor = 0x1028,
1885 .subdevice = 0x0151,
1886 .name = "Dell Optiplex GX270", /* AD1981B */
1887 .type = AC97_TUNE_HP_ONLY
1888 },
1889 {
1890 .subvendor = 0x1028,
1891 .subdevice = 0x014e,
1892 .name = "Dell D800", /* STAC9750/51 */
1893 .type = AC97_TUNE_HP_ONLY
1894 },
1895 {
1896 .subvendor = 0x1028,
1897 .subdevice = 0x0163,
1898 .name = "Dell Unknown", /* STAC9750/51 */
1899 .type = AC97_TUNE_HP_ONLY
1900 },
1901 {
1902 .subvendor = 0x1028,
1903 .subdevice = 0x016a,
1904 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1905 .type = AC97_TUNE_HP_ONLY
1906 },
1907 {
1908 .subvendor = 0x1028,
1909 .subdevice = 0x0182,
1910 .name = "Dell Latitude D610", /* STAC9750/51 */
1911 .type = AC97_TUNE_HP_ONLY
1912 },
1913 {
1914 .subvendor = 0x1028,
1915 .subdevice = 0x0186,
1916 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1917 .type = AC97_TUNE_HP_MUTE_LED
1918 },
1919 {
1920 .subvendor = 0x1028,
1921 .subdevice = 0x0188,
1922 .name = "Dell Inspiron 6000",
1923 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1924 },
1925 {
1926 .subvendor = 0x1028,
1927 .subdevice = 0x0189,
1928 .name = "Dell Inspiron 9300",
1929 .type = AC97_TUNE_HP_MUTE_LED
1930 },
1931 {
1932 .subvendor = 0x1028,
1933 .subdevice = 0x0191,
1934 .name = "Dell Inspiron 8600",
1935 .type = AC97_TUNE_HP_ONLY
1936 },
1937 {
1938 .subvendor = 0x103c,
1939 .subdevice = 0x006d,
1940 .name = "HP zv5000",
1941 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1942 },
1943 { /* FIXME: which codec? */
1944 .subvendor = 0x103c,
1945 .subdevice = 0x00c3,
1946 .name = "HP xw6000",
1947 .type = AC97_TUNE_HP_ONLY
1948 },
1949 {
1950 .subvendor = 0x103c,
1951 .subdevice = 0x088c,
1952 .name = "HP nc8000",
1953 .type = AC97_TUNE_HP_MUTE_LED
1954 },
1955 {
1956 .subvendor = 0x103c,
1957 .subdevice = 0x0890,
1958 .name = "HP nc6000",
1959 .type = AC97_TUNE_MUTE_LED
1960 },
1961 {
1962 .subvendor = 0x103c,
1963 .subdevice = 0x129d,
1964 .name = "HP xw8000",
1965 .type = AC97_TUNE_HP_ONLY
1966 },
1967 {
1968 .subvendor = 0x103c,
1969 .subdevice = 0x0938,
1970 .name = "HP nc4200",
1971 .type = AC97_TUNE_HP_MUTE_LED
1972 },
1973 {
1974 .subvendor = 0x103c,
1975 .subdevice = 0x099c,
1976 .name = "HP nx6110/nc6120",
1977 .type = AC97_TUNE_HP_MUTE_LED
1978 },
1979 {
1980 .subvendor = 0x103c,
1981 .subdevice = 0x0944,
1982 .name = "HP nc6220",
1983 .type = AC97_TUNE_HP_MUTE_LED
1984 },
1985 {
1986 .subvendor = 0x103c,
1987 .subdevice = 0x0934,
1988 .name = "HP nc8220",
1989 .type = AC97_TUNE_HP_MUTE_LED
1990 },
1991 {
1992 .subvendor = 0x103c,
1993 .subdevice = 0x12f1,
1994 .name = "HP xw8200", /* AD1981B*/
1995 .type = AC97_TUNE_HP_ONLY
1996 },
1997 {
1998 .subvendor = 0x103c,
1999 .subdevice = 0x12f2,
2000 .name = "HP xw6200",
2001 .type = AC97_TUNE_HP_ONLY
2002 },
2003 {
2004 .subvendor = 0x103c,
2005 .subdevice = 0x3008,
2006 .name = "HP xw4200", /* AD1981B*/
2007 .type = AC97_TUNE_HP_ONLY
2008 },
2009 {
2010 .subvendor = 0x104d,
2011 .subdevice = 0x8144,
2012 .name = "Sony",
2013 .type = AC97_TUNE_INV_EAPD
2014 },
2015 {
2016 .subvendor = 0x104d,
2017 .subdevice = 0x8197,
2018 .name = "Sony S1XP",
2019 .type = AC97_TUNE_INV_EAPD
2020 },
2021 {
2022 .subvendor = 0x104d,
2023 .subdevice = 0x81c0,
2024 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
2025 .type = AC97_TUNE_INV_EAPD
2026 },
2027 {
2028 .subvendor = 0x104d,
2029 .subdevice = 0x81c5,
2030 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
2031 .type = AC97_TUNE_INV_EAPD
2032 },
2033 {
2034 .subvendor = 0x1043,
2035 .subdevice = 0x80f3,
2036 .name = "ASUS ICH5/AD1985",
2037 .type = AC97_TUNE_AD_SHARING
2038 },
2039 {
2040 .subvendor = 0x10cf,
2041 .subdevice = 0x11c3,
2042 .name = "Fujitsu-Siemens E4010",
2043 .type = AC97_TUNE_HP_ONLY
2044 },
2045 {
2046 .subvendor = 0x10cf,
2047 .subdevice = 0x1225,
2048 .name = "Fujitsu-Siemens T3010",
2049 .type = AC97_TUNE_HP_ONLY
2050 },
2051 {
2052 .subvendor = 0x10cf,
2053 .subdevice = 0x1253,
2054 .name = "Fujitsu S6210", /* STAC9750/51 */
2055 .type = AC97_TUNE_HP_ONLY
2056 },
2057 {
2058 .subvendor = 0x10cf,
2059 .subdevice = 0x127d,
2060 .name = "Fujitsu Lifebook P7010",
2061 .type = AC97_TUNE_HP_ONLY
2062 },
2063 {
2064 .subvendor = 0x10cf,
2065 .subdevice = 0x127e,
2066 .name = "Fujitsu Lifebook C1211D",
2067 .type = AC97_TUNE_HP_ONLY
2068 },
2069 {
2070 .subvendor = 0x10cf,
2071 .subdevice = 0x12ec,
2072 .name = "Fujitsu-Siemens 4010",
2073 .type = AC97_TUNE_HP_ONLY
2074 },
2075 {
2076 .subvendor = 0x10cf,
2077 .subdevice = 0x12f2,
2078 .name = "Fujitsu-Siemens Celsius H320",
2079 .type = AC97_TUNE_SWAP_HP
2080 },
2081 {
2082 .subvendor = 0x10f1,
2083 .subdevice = 0x2665,
2084 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2085 .type = AC97_TUNE_HP_ONLY
2086 },
2087 {
2088 .subvendor = 0x10f1,
2089 .subdevice = 0x2885,
2090 .name = "AMD64 Mobo", /* ALC650 */
2091 .type = AC97_TUNE_HP_ONLY
2092 },
2093 {
2094 .subvendor = 0x10f1,
2095 .subdevice = 0x2895,
2096 .name = "Tyan Thunder K8WE",
2097 .type = AC97_TUNE_HP_ONLY
2098 },
2099 {
2100 .subvendor = 0x10f7,
2101 .subdevice = 0x834c,
2102 .name = "Panasonic CF-R4",
2103 .type = AC97_TUNE_HP_ONLY,
2104 },
2105 {
2106 .subvendor = 0x110a,
2107 .subdevice = 0x0056,
2108 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2109 .type = AC97_TUNE_HP_ONLY
2110 },
2111 {
2112 .subvendor = 0x11d4,
2113 .subdevice = 0x5375,
2114 .name = "ADI AD1985 (discrete)",
2115 .type = AC97_TUNE_HP_ONLY
2116 },
2117 {
2118 .subvendor = 0x1462,
2119 .subdevice = 0x5470,
2120 .name = "MSI P4 ATX 645 Ultra",
2121 .type = AC97_TUNE_HP_ONLY
2122 },
2123 {
2124 .subvendor = 0x161f,
2125 .subdevice = 0x202f,
2126 .name = "Gateway M520",
2127 .type = AC97_TUNE_INV_EAPD
2128 },
2129 {
2130 .subvendor = 0x161f,
2131 .subdevice = 0x203a,
2132 .name = "Gateway 4525GZ", /* AD1981B */
2133 .type = AC97_TUNE_INV_EAPD
2134 },
2135 {
2136 .subvendor = 0x1734,
2137 .subdevice = 0x0088,
2138 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2139 .type = AC97_TUNE_HP_ONLY
2140 },
2141 {
2142 .subvendor = 0x8086,
2143 .subdevice = 0x2000,
2144 .mask = 0xfff0,
2145 .name = "Intel ICH5/AD1985",
2146 .type = AC97_TUNE_AD_SHARING
2147 },
2148 {
2149 .subvendor = 0x8086,
2150 .subdevice = 0x4000,
2151 .mask = 0xfff0,
2152 .name = "Intel ICH5/AD1985",
2153 .type = AC97_TUNE_AD_SHARING
2154 },
2155 {
2156 .subvendor = 0x8086,
2157 .subdevice = 0x4856,
2158 .name = "Intel D845WN (82801BA)",
2159 .type = AC97_TUNE_SWAP_HP
2160 },
2161 {
2162 .subvendor = 0x8086,
2163 .subdevice = 0x4d44,
2164 .name = "Intel D850EMV2", /* AD1885 */
2165 .type = AC97_TUNE_HP_ONLY
2166 },
2167 {
2168 .subvendor = 0x8086,
2169 .subdevice = 0x4d56,
2170 .name = "Intel ICH/AD1885",
2171 .type = AC97_TUNE_HP_ONLY
2172 },
2173 {
2174 .subvendor = 0x8086,
2175 .subdevice = 0x6000,
2176 .mask = 0xfff0,
2177 .name = "Intel ICH5/AD1985",
2178 .type = AC97_TUNE_AD_SHARING
2179 },
2180 {
2181 .subvendor = 0x8086,
2182 .subdevice = 0xe000,
2183 .mask = 0xfff0,
2184 .name = "Intel ICH5/AD1985",
2185 .type = AC97_TUNE_AD_SHARING
2186 },
2187#if 0 /* FIXME: this seems wrong on most boards */
2188 {
2189 .subvendor = 0x8086,
2190 .subdevice = 0xa000,
2191 .mask = 0xfff0,
2192 .name = "Intel ICH5/AD1985",
2193 .type = AC97_TUNE_HP_ONLY
2194 },
2195#endif
2196 { } /* terminator */
2197};
2198
2199static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2200 const char *quirk_override)
2201{
2202 struct snd_ac97_bus *pbus;
2203 struct snd_ac97_template ac97;
2204 int err;
2205 unsigned int i, codecs;
2206 unsigned int glob_sta = 0;
2207 struct snd_ac97_bus_ops *ops;
2208 static struct snd_ac97_bus_ops standard_bus_ops = {
2209 .write = snd_intel8x0_codec_write,
2210 .read = snd_intel8x0_codec_read,
2211 };
2212 static struct snd_ac97_bus_ops ali_bus_ops = {
2213 .write = snd_intel8x0_ali_codec_write,
2214 .read = snd_intel8x0_ali_codec_read,
2215 };
2216
2217 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2218 if (!spdif_aclink) {
2219 switch (chip->device_type) {
2220 case DEVICE_NFORCE:
2221 chip->spdif_idx = NVD_SPBAR;
2222 break;
2223 case DEVICE_ALI:
2224 chip->spdif_idx = ALID_AC97SPDIFOUT;
2225 break;
2226 case DEVICE_INTEL_ICH4:
2227 chip->spdif_idx = ICHD_SPBAR;
2228 break;
2229 }
2230 }
2231
2232 chip->in_ac97_init = 1;
2233
2234 memset(&ac97, 0, sizeof(ac97));
2235 ac97.private_data = chip;
2236 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2237 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2238 if (chip->xbox)
2239 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2240 if (chip->device_type != DEVICE_ALI) {
2241 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2242 ops = &standard_bus_ops;
2243 chip->in_sdin_init = 1;
2244 codecs = 0;
2245 for (i = 0; i < chip->max_codecs; i++) {
2246 if (! (glob_sta & chip->codec_bit[i]))
2247 continue;
2248 if (chip->device_type == DEVICE_INTEL_ICH4) {
2249 snd_intel8x0_codec_read_test(chip, codecs);
2250 chip->ac97_sdin[codecs] =
2251 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2252 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2253 chip->ac97_sdin[codecs] = 0;
2254 } else
2255 chip->ac97_sdin[codecs] = i;
2256 codecs++;
2257 }
2258 chip->in_sdin_init = 0;
2259 if (! codecs)
2260 codecs = 1;
2261 } else {
2262 ops = &ali_bus_ops;
2263 codecs = 1;
2264 /* detect the secondary codec */
2265 for (i = 0; i < 100; i++) {
2266 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2267 if (reg & 0x40) {
2268 codecs = 2;
2269 break;
2270 }
2271 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2272 udelay(1);
2273 }
2274 }
2275 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2276 goto __err;
2277 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2278 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2279 pbus->clock = ac97_clock;
2280 /* FIXME: my test board doesn't work well with VRA... */
2281 if (chip->device_type == DEVICE_ALI)
2282 pbus->no_vra = 1;
2283 else
2284 pbus->dra = 1;
2285 chip->ac97_bus = pbus;
2286 chip->ncodecs = codecs;
2287
2288 ac97.pci = chip->pci;
2289 for (i = 0; i < codecs; i++) {
2290 ac97.num = i;
2291 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2292 if (err != -EACCES)
2293 dev_err(chip->card->dev,
2294 "Unable to initialize codec #%d\n", i);
2295 if (i == 0)
2296 goto __err;
2297 }
2298 }
2299 /* tune up the primary codec */
2300 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2301 /* enable separate SDINs for ICH4 */
2302 if (chip->device_type == DEVICE_INTEL_ICH4)
2303 pbus->isdin = 1;
2304 /* find the available PCM streams */
2305 i = ARRAY_SIZE(ac97_pcm_defs);
2306 if (chip->device_type != DEVICE_INTEL_ICH4)
2307 i -= 2; /* do not allocate PCM2IN and MIC2 */
2308 if (chip->spdif_idx < 0)
2309 i--; /* do not allocate S/PDIF */
2310 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2311 if (err < 0)
2312 goto __err;
2313 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2314 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2315 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2316 if (chip->spdif_idx >= 0)
2317 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2318 if (chip->device_type == DEVICE_INTEL_ICH4) {
2319 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2320 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2321 }
2322 /* enable separate SDINs for ICH4 */
2323 if (chip->device_type == DEVICE_INTEL_ICH4) {
2324 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2325 u8 tmp = igetbyte(chip, ICHREG(SDM));
2326 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2327 if (pcm) {
2328 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2329 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2330 for (i = 1; i < 4; i++) {
2331 if (pcm->r[0].codec[i]) {
2332 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2333 break;
2334 }
2335 }
2336 } else {
2337 tmp &= ~ICH_SE; /* steer disable */
2338 }
2339 iputbyte(chip, ICHREG(SDM), tmp);
2340 }
2341 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2342 chip->multi4 = 1;
2343 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2344 chip->multi6 = 1;
2345 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2346 chip->multi8 = 1;
2347 }
2348 }
2349 if (pbus->pcms[0].r[1].rslots[0]) {
2350 chip->dra = 1;
2351 }
2352 if (chip->device_type == DEVICE_INTEL_ICH4) {
2353 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2354 chip->smp20bit = 1;
2355 }
2356 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2357 /* 48kHz only */
2358 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2359 }
2360 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2361 /* use slot 10/11 for SPDIF */
2362 u32 val;
2363 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2364 val |= ICH_PCM_SPDIF_1011;
2365 iputdword(chip, ICHREG(GLOB_CNT), val);
2366 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2367 }
2368 chip->in_ac97_init = 0;
2369 return 0;
2370
2371 __err:
2372 /* clear the cold-reset bit for the next chance */
2373 if (chip->device_type != DEVICE_ALI)
2374 iputdword(chip, ICHREG(GLOB_CNT),
2375 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2376 return err;
2377}
2378
2379
2380/*
2381 *
2382 */
2383
2384static void do_ali_reset(struct intel8x0 *chip)
2385{
2386 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2387 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2388 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2389 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2390 iputdword(chip, ICHREG(ALI_INTERFACECR),
2391 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2392 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2393 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2394}
2395
2396#ifdef CONFIG_SND_AC97_POWER_SAVE
2397static struct snd_pci_quirk ich_chip_reset_mode[] = {
2398 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2399 { } /* end */
2400};
2401
2402static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2403{
2404 unsigned int cnt;
2405 /* ACLink on, 2 channels */
2406
2407 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2408 return -EIO;
2409
2410 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2411 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2412
2413 /* do cold reset - the full ac97 powerdown may leave the controller
2414 * in a warm state but actually it cannot communicate with the codec.
2415 */
2416 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2417 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2418 udelay(10);
2419 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2420 msleep(1);
2421 return 0;
2422}
2423#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2424 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2425#else
2426#define snd_intel8x0_ich_chip_cold_reset(chip) 0
2427#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2428#endif
2429
2430static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2431{
2432 unsigned long end_time;
2433 unsigned int cnt;
2434 /* ACLink on, 2 channels */
2435 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2436 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2437 /* finish cold or do warm reset */
2438 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2439 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2440 end_time = (jiffies + (HZ / 4)) + 1;
2441 do {
2442 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2443 return 0;
2444 schedule_timeout_uninterruptible(1);
2445 } while (time_after_eq(end_time, jiffies));
2446 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2447 igetdword(chip, ICHREG(GLOB_CNT)));
2448 return -EIO;
2449}
2450
2451static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2452{
2453 unsigned long end_time;
2454 unsigned int status, nstatus;
2455 unsigned int cnt;
2456 int err;
2457
2458 /* put logic to right state */
2459 /* first clear status bits */
2460 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2461 if (chip->device_type == DEVICE_NFORCE)
2462 status |= ICH_NVSPINT;
2463 cnt = igetdword(chip, ICHREG(GLOB_STA));
2464 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2465
2466 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2467 err = snd_intel8x0_ich_chip_cold_reset(chip);
2468 else
2469 err = snd_intel8x0_ich_chip_reset(chip);
2470 if (err < 0)
2471 return err;
2472
2473 if (probing) {
2474 /* wait for any codec ready status.
2475 * Once it becomes ready it should remain ready
2476 * as long as we do not disable the ac97 link.
2477 */
2478 end_time = jiffies + HZ;
2479 do {
2480 status = igetdword(chip, ICHREG(GLOB_STA)) &
2481 chip->codec_isr_bits;
2482 if (status)
2483 break;
2484 schedule_timeout_uninterruptible(1);
2485 } while (time_after_eq(end_time, jiffies));
2486 if (! status) {
2487 /* no codec is found */
2488 dev_err(chip->card->dev,
2489 "codec_ready: codec is not ready [0x%x]\n",
2490 igetdword(chip, ICHREG(GLOB_STA)));
2491 return -EIO;
2492 }
2493
2494 /* wait for other codecs ready status. */
2495 end_time = jiffies + HZ / 4;
2496 while (status != chip->codec_isr_bits &&
2497 time_after_eq(end_time, jiffies)) {
2498 schedule_timeout_uninterruptible(1);
2499 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2500 chip->codec_isr_bits;
2501 }
2502
2503 } else {
2504 /* resume phase */
2505 int i;
2506 status = 0;
2507 for (i = 0; i < chip->ncodecs; i++)
2508 if (chip->ac97[i])
2509 status |= chip->codec_bit[chip->ac97_sdin[i]];
2510 /* wait until all the probed codecs are ready */
2511 end_time = jiffies + HZ;
2512 do {
2513 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2514 chip->codec_isr_bits;
2515 if (status == nstatus)
2516 break;
2517 schedule_timeout_uninterruptible(1);
2518 } while (time_after_eq(end_time, jiffies));
2519 }
2520
2521 if (chip->device_type == DEVICE_SIS) {
2522 /* unmute the output on SIS7012 */
2523 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2524 }
2525 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2526 /* enable SPDIF interrupt */
2527 unsigned int val;
2528 pci_read_config_dword(chip->pci, 0x4c, &val);
2529 val |= 0x1000000;
2530 pci_write_config_dword(chip->pci, 0x4c, val);
2531 }
2532 return 0;
2533}
2534
2535static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2536{
2537 u32 reg;
2538 int i = 0;
2539
2540 reg = igetdword(chip, ICHREG(ALI_SCR));
2541 if ((reg & 2) == 0) /* Cold required */
2542 reg |= 2;
2543 else
2544 reg |= 1; /* Warm */
2545 reg &= ~0x80000000; /* ACLink on */
2546 iputdword(chip, ICHREG(ALI_SCR), reg);
2547
2548 for (i = 0; i < HZ / 2; i++) {
2549 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2550 goto __ok;
2551 schedule_timeout_uninterruptible(1);
2552 }
2553 dev_err(chip->card->dev, "AC'97 reset failed.\n");
2554 if (probing)
2555 return -EIO;
2556
2557 __ok:
2558 for (i = 0; i < HZ / 2; i++) {
2559 reg = igetdword(chip, ICHREG(ALI_RTSR));
2560 if (reg & 0x80) /* primary codec */
2561 break;
2562 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2563 schedule_timeout_uninterruptible(1);
2564 }
2565
2566 do_ali_reset(chip);
2567 return 0;
2568}
2569
2570static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2571{
2572 unsigned int i, timeout;
2573 int err;
2574
2575 if (chip->device_type != DEVICE_ALI) {
2576 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2577 return err;
2578 iagetword(chip, 0); /* clear semaphore flag */
2579 } else {
2580 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2581 return err;
2582 }
2583
2584 /* disable interrupts */
2585 for (i = 0; i < chip->bdbars_count; i++)
2586 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2587 /* reset channels */
2588 for (i = 0; i < chip->bdbars_count; i++)
2589 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2590 for (i = 0; i < chip->bdbars_count; i++) {
2591 timeout = 100000;
2592 while (--timeout != 0) {
2593 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2594 break;
2595 }
2596 if (timeout == 0)
2597 dev_err(chip->card->dev, "reset of registers failed?\n");
2598 }
2599 /* initialize Buffer Descriptor Lists */
2600 for (i = 0; i < chip->bdbars_count; i++)
2601 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2602 chip->ichd[i].bdbar_addr);
2603 return 0;
2604}
2605
2606static int snd_intel8x0_free(struct intel8x0 *chip)
2607{
2608 unsigned int i;
2609
2610 if (chip->irq < 0)
2611 goto __hw_end;
2612 /* disable interrupts */
2613 for (i = 0; i < chip->bdbars_count; i++)
2614 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2615 /* reset channels */
2616 for (i = 0; i < chip->bdbars_count; i++)
2617 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2618 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2619 /* stop the spdif interrupt */
2620 unsigned int val;
2621 pci_read_config_dword(chip->pci, 0x4c, &val);
2622 val &= ~0x1000000;
2623 pci_write_config_dword(chip->pci, 0x4c, val);
2624 }
2625 /* --- */
2626
2627 __hw_end:
2628 if (chip->irq >= 0)
2629 free_irq(chip->irq, chip);
2630 if (chip->bdbars.area) {
2631 if (chip->fix_nocache)
2632 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2633 snd_dma_free_pages(&chip->bdbars);
2634 }
2635 if (chip->addr)
2636 pci_iounmap(chip->pci, chip->addr);
2637 if (chip->bmaddr)
2638 pci_iounmap(chip->pci, chip->bmaddr);
2639 pci_release_regions(chip->pci);
2640 pci_disable_device(chip->pci);
2641 kfree(chip);
2642 return 0;
2643}
2644
2645#ifdef CONFIG_PM_SLEEP
2646/*
2647 * power management
2648 */
2649static int intel8x0_suspend(struct device *dev)
2650{
2651 struct snd_card *card = dev_get_drvdata(dev);
2652 struct intel8x0 *chip = card->private_data;
2653 int i;
2654
2655 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2656 for (i = 0; i < chip->pcm_devs; i++)
2657 snd_pcm_suspend_all(chip->pcm[i]);
2658 /* clear nocache */
2659 if (chip->fix_nocache) {
2660 for (i = 0; i < chip->bdbars_count; i++) {
2661 struct ichdev *ichdev = &chip->ichd[i];
2662 if (ichdev->substream && ichdev->page_attr_changed) {
2663 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2664 if (runtime->dma_area)
2665 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2666 }
2667 }
2668 }
2669 for (i = 0; i < chip->ncodecs; i++)
2670 snd_ac97_suspend(chip->ac97[i]);
2671 if (chip->device_type == DEVICE_INTEL_ICH4)
2672 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2673
2674 if (chip->irq >= 0) {
2675 free_irq(chip->irq, chip);
2676 chip->irq = -1;
2677 }
2678 return 0;
2679}
2680
2681static int intel8x0_resume(struct device *dev)
2682{
2683 struct pci_dev *pci = to_pci_dev(dev);
2684 struct snd_card *card = dev_get_drvdata(dev);
2685 struct intel8x0 *chip = card->private_data;
2686 int i;
2687
2688 snd_intel8x0_chip_init(chip, 0);
2689 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2690 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2691 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2692 pci->irq);
2693 snd_card_disconnect(card);
2694 return -EIO;
2695 }
2696 chip->irq = pci->irq;
2697 synchronize_irq(chip->irq);
2698
2699 /* re-initialize mixer stuff */
2700 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2701 /* enable separate SDINs for ICH4 */
2702 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2703 /* use slot 10/11 for SPDIF */
2704 iputdword(chip, ICHREG(GLOB_CNT),
2705 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2706 ICH_PCM_SPDIF_1011);
2707 }
2708
2709 /* refill nocache */
2710 if (chip->fix_nocache)
2711 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2712
2713 for (i = 0; i < chip->ncodecs; i++)
2714 snd_ac97_resume(chip->ac97[i]);
2715
2716 /* refill nocache */
2717 if (chip->fix_nocache) {
2718 for (i = 0; i < chip->bdbars_count; i++) {
2719 struct ichdev *ichdev = &chip->ichd[i];
2720 if (ichdev->substream && ichdev->page_attr_changed) {
2721 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2722 if (runtime->dma_area)
2723 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2724 }
2725 }
2726 }
2727
2728 /* resume status */
2729 for (i = 0; i < chip->bdbars_count; i++) {
2730 struct ichdev *ichdev = &chip->ichd[i];
2731 unsigned long port = ichdev->reg_offset;
2732 if (! ichdev->substream || ! ichdev->suspended)
2733 continue;
2734 if (ichdev->ichd == ICHD_PCMOUT)
2735 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2736 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2737 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2738 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2739 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2740 }
2741
2742 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2743 return 0;
2744}
2745
2746static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2747#define INTEL8X0_PM_OPS &intel8x0_pm
2748#else
2749#define INTEL8X0_PM_OPS NULL
2750#endif /* CONFIG_PM_SLEEP */
2751
2752#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2753
2754static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2755{
2756 struct snd_pcm_substream *subs;
2757 struct ichdev *ichdev;
2758 unsigned long port;
2759 unsigned long pos, pos1, t;
2760 int civ, timeout = 1000, attempt = 1;
2761 ktime_t start_time, stop_time;
2762
2763 if (chip->ac97_bus->clock != 48000)
2764 return; /* specified in module option */
2765
2766 __again:
2767 subs = chip->pcm[0]->streams[0].substream;
2768 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2769 dev_warn(chip->card->dev,
2770 "no playback buffer allocated - aborting measure ac97 clock\n");
2771 return;
2772 }
2773 ichdev = &chip->ichd[ICHD_PCMOUT];
2774 ichdev->physbuf = subs->dma_buffer.addr;
2775 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2776 ichdev->substream = NULL; /* don't process interrupts */
2777
2778 /* set rate */
2779 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2780 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2781 chip->ac97_bus->clock);
2782 return;
2783 }
2784 snd_intel8x0_setup_periods(chip, ichdev);
2785 port = ichdev->reg_offset;
2786 spin_lock_irq(&chip->reg_lock);
2787 chip->in_measurement = 1;
2788 /* trigger */
2789 if (chip->device_type != DEVICE_ALI)
2790 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2791 else {
2792 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2793 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2794 }
2795 start_time = ktime_get();
2796 spin_unlock_irq(&chip->reg_lock);
2797 msleep(50);
2798 spin_lock_irq(&chip->reg_lock);
2799 /* check the position */
2800 do {
2801 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2802 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2803 if (pos1 == 0) {
2804 udelay(10);
2805 continue;
2806 }
2807 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2808 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2809 break;
2810 } while (timeout--);
2811 if (pos1 == 0) { /* oops, this value is not reliable */
2812 pos = 0;
2813 } else {
2814 pos = ichdev->fragsize1;
2815 pos -= pos1 << ichdev->pos_shift;
2816 pos += ichdev->position;
2817 }
2818 chip->in_measurement = 0;
2819 stop_time = ktime_get();
2820 /* stop */
2821 if (chip->device_type == DEVICE_ALI) {
2822 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2823 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2824 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2825 ;
2826 } else {
2827 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2828 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2829 ;
2830 }
2831 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2832 spin_unlock_irq(&chip->reg_lock);
2833
2834 if (pos == 0) {
2835 dev_err(chip->card->dev,
2836 "measure - unreliable DMA position..\n");
2837 __retry:
2838 if (attempt < 3) {
2839 msleep(300);
2840 attempt++;
2841 goto __again;
2842 }
2843 goto __end;
2844 }
2845
2846 pos /= 4;
2847 t = ktime_us_delta(stop_time, start_time);
2848 dev_info(chip->card->dev,
2849 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2850 if (t == 0) {
2851 dev_err(chip->card->dev, "?? calculation error..\n");
2852 goto __retry;
2853 }
2854 pos *= 1000;
2855 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2856 if (pos < 40000 || pos >= 60000) {
2857 /* abnormal value. hw problem? */
2858 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2859 goto __retry;
2860 } else if (pos > 40500 && pos < 41500)
2861 /* first exception - 41000Hz reference clock */
2862 chip->ac97_bus->clock = 41000;
2863 else if (pos > 43600 && pos < 44600)
2864 /* second exception - 44100HZ reference clock */
2865 chip->ac97_bus->clock = 44100;
2866 else if (pos < 47500 || pos > 48500)
2867 /* not 48000Hz, tuning the clock.. */
2868 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2869 __end:
2870 dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2871 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2872}
2873
2874static struct snd_pci_quirk intel8x0_clock_list[] = {
2875 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2876 SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2877 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2878 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2879 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2880 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2881 { } /* terminator */
2882};
2883
2884static int intel8x0_in_clock_list(struct intel8x0 *chip)
2885{
2886 struct pci_dev *pci = chip->pci;
2887 const struct snd_pci_quirk *wl;
2888
2889 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2890 if (!wl)
2891 return 0;
2892 dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n",
2893 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2894 chip->ac97_bus->clock = wl->value;
2895 return 1;
2896}
2897
2898static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2899 struct snd_info_buffer *buffer)
2900{
2901 struct intel8x0 *chip = entry->private_data;
2902 unsigned int tmp;
2903
2904 snd_iprintf(buffer, "Intel8x0\n\n");
2905 if (chip->device_type == DEVICE_ALI)
2906 return;
2907 tmp = igetdword(chip, ICHREG(GLOB_STA));
2908 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2909 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2910 if (chip->device_type == DEVICE_INTEL_ICH4)
2911 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2912 snd_iprintf(buffer, "AC'97 codecs ready :");
2913 if (tmp & chip->codec_isr_bits) {
2914 int i;
2915 static const char *codecs[3] = {
2916 "primary", "secondary", "tertiary"
2917 };
2918 for (i = 0; i < chip->max_codecs; i++)
2919 if (tmp & chip->codec_bit[i])
2920 snd_iprintf(buffer, " %s", codecs[i]);
2921 } else
2922 snd_iprintf(buffer, " none");
2923 snd_iprintf(buffer, "\n");
2924 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2925 chip->device_type == DEVICE_SIS)
2926 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2927 chip->ac97_sdin[0],
2928 chip->ac97_sdin[1],
2929 chip->ac97_sdin[2]);
2930}
2931
2932static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2933{
2934 struct snd_info_entry *entry;
2935
2936 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2937 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2938}
2939
2940static int snd_intel8x0_dev_free(struct snd_device *device)
2941{
2942 struct intel8x0 *chip = device->device_data;
2943 return snd_intel8x0_free(chip);
2944}
2945
2946struct ich_reg_info {
2947 unsigned int int_sta_mask;
2948 unsigned int offset;
2949};
2950
2951static unsigned int ich_codec_bits[3] = {
2952 ICH_PCR, ICH_SCR, ICH_TCR
2953};
2954static unsigned int sis_codec_bits[3] = {
2955 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2956};
2957
2958static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2959{
2960 int result = inside_vm;
2961 char *msg = NULL;
2962
2963 /* check module parameter first (override detection) */
2964 if (result >= 0) {
2965 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2966 goto fini;
2967 }
2968
2969 /* check for known (emulated) devices */
2970 result = 0;
2971 if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2972 pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2973 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2974 msg = "enable KVM";
2975 result = 1;
2976 } else if (pci->subsystem_vendor == 0x1ab8) {
2977 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2978 msg = "enable Parallels VM";
2979 result = 1;
2980 }
2981
2982fini:
2983 if (msg != NULL)
2984 dev_info(&pci->dev, "%s optimization\n", msg);
2985
2986 return result;
2987}
2988
2989static int snd_intel8x0_create(struct snd_card *card,
2990 struct pci_dev *pci,
2991 unsigned long device_type,
2992 struct intel8x0 **r_intel8x0)
2993{
2994 struct intel8x0 *chip;
2995 int err;
2996 unsigned int i;
2997 unsigned int int_sta_masks;
2998 struct ichdev *ichdev;
2999 static struct snd_device_ops ops = {
3000 .dev_free = snd_intel8x0_dev_free,
3001 };
3002
3003 static unsigned int bdbars[] = {
3004 3, /* DEVICE_INTEL */
3005 6, /* DEVICE_INTEL_ICH4 */
3006 3, /* DEVICE_SIS */
3007 6, /* DEVICE_ALI */
3008 4, /* DEVICE_NFORCE */
3009 };
3010 static struct ich_reg_info intel_regs[6] = {
3011 { ICH_PIINT, 0 },
3012 { ICH_POINT, 0x10 },
3013 { ICH_MCINT, 0x20 },
3014 { ICH_M2INT, 0x40 },
3015 { ICH_P2INT, 0x50 },
3016 { ICH_SPINT, 0x60 },
3017 };
3018 static struct ich_reg_info nforce_regs[4] = {
3019 { ICH_PIINT, 0 },
3020 { ICH_POINT, 0x10 },
3021 { ICH_MCINT, 0x20 },
3022 { ICH_NVSPINT, 0x70 },
3023 };
3024 static struct ich_reg_info ali_regs[6] = {
3025 { ALI_INT_PCMIN, 0x40 },
3026 { ALI_INT_PCMOUT, 0x50 },
3027 { ALI_INT_MICIN, 0x60 },
3028 { ALI_INT_CODECSPDIFOUT, 0x70 },
3029 { ALI_INT_SPDIFIN, 0xa0 },
3030 { ALI_INT_SPDIFOUT, 0xb0 },
3031 };
3032 struct ich_reg_info *tbl;
3033
3034 *r_intel8x0 = NULL;
3035
3036 if ((err = pci_enable_device(pci)) < 0)
3037 return err;
3038
3039 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3040 if (chip == NULL) {
3041 pci_disable_device(pci);
3042 return -ENOMEM;
3043 }
3044 spin_lock_init(&chip->reg_lock);
3045 chip->device_type = device_type;
3046 chip->card = card;
3047 chip->pci = pci;
3048 chip->irq = -1;
3049
3050 /* module parameters */
3051 chip->buggy_irq = buggy_irq;
3052 chip->buggy_semaphore = buggy_semaphore;
3053 if (xbox)
3054 chip->xbox = 1;
3055
3056 chip->inside_vm = snd_intel8x0_inside_vm(pci);
3057
3058 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
3059 pci->device == PCI_DEVICE_ID_INTEL_440MX)
3060 chip->fix_nocache = 1; /* enable workaround */
3061
3062 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
3063 kfree(chip);
3064 pci_disable_device(pci);
3065 return err;
3066 }
3067
3068 if (device_type == DEVICE_ALI) {
3069 /* ALI5455 has no ac97 region */
3070 chip->bmaddr = pci_iomap(pci, 0, 0);
3071 goto port_inited;
3072 }
3073
3074 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3075 chip->addr = pci_iomap(pci, 2, 0);
3076 else
3077 chip->addr = pci_iomap(pci, 0, 0);
3078 if (!chip->addr) {
3079 dev_err(card->dev, "AC'97 space ioremap problem\n");
3080 snd_intel8x0_free(chip);
3081 return -EIO;
3082 }
3083 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3084 chip->bmaddr = pci_iomap(pci, 3, 0);
3085 else
3086 chip->bmaddr = pci_iomap(pci, 1, 0);
3087
3088 port_inited:
3089 if (!chip->bmaddr) {
3090 dev_err(card->dev, "Controller space ioremap problem\n");
3091 snd_intel8x0_free(chip);
3092 return -EIO;
3093 }
3094 chip->bdbars_count = bdbars[device_type];
3095
3096 /* initialize offsets */
3097 switch (device_type) {
3098 case DEVICE_NFORCE:
3099 tbl = nforce_regs;
3100 break;
3101 case DEVICE_ALI:
3102 tbl = ali_regs;
3103 break;
3104 default:
3105 tbl = intel_regs;
3106 break;
3107 }
3108 for (i = 0; i < chip->bdbars_count; i++) {
3109 ichdev = &chip->ichd[i];
3110 ichdev->ichd = i;
3111 ichdev->reg_offset = tbl[i].offset;
3112 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3113 if (device_type == DEVICE_SIS) {
3114 /* SiS 7012 swaps the registers */
3115 ichdev->roff_sr = ICH_REG_OFF_PICB;
3116 ichdev->roff_picb = ICH_REG_OFF_SR;
3117 } else {
3118 ichdev->roff_sr = ICH_REG_OFF_SR;
3119 ichdev->roff_picb = ICH_REG_OFF_PICB;
3120 }
3121 if (device_type == DEVICE_ALI)
3122 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3123 /* SIS7012 handles the pcm data in bytes, others are in samples */
3124 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3125 }
3126
3127 /* allocate buffer descriptor lists */
3128 /* the start of each lists must be aligned to 8 bytes */
3129 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3130 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3131 &chip->bdbars) < 0) {
3132 snd_intel8x0_free(chip);
3133 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3134 return -ENOMEM;
3135 }
3136 /* tables must be aligned to 8 bytes here, but the kernel pages
3137 are much bigger, so we don't care (on i386) */
3138 /* workaround for 440MX */
3139 if (chip->fix_nocache)
3140 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3141 int_sta_masks = 0;
3142 for (i = 0; i < chip->bdbars_count; i++) {
3143 ichdev = &chip->ichd[i];
3144 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3145 (i * ICH_MAX_FRAGS * 2);
3146 ichdev->bdbar_addr = chip->bdbars.addr +
3147 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3148 int_sta_masks |= ichdev->int_sta_mask;
3149 }
3150 chip->int_sta_reg = device_type == DEVICE_ALI ?
3151 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3152 chip->int_sta_mask = int_sta_masks;
3153
3154 pci_set_master(pci);
3155
3156 switch(chip->device_type) {
3157 case DEVICE_INTEL_ICH4:
3158 /* ICH4 can have three codecs */
3159 chip->max_codecs = 3;
3160 chip->codec_bit = ich_codec_bits;
3161 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3162 break;
3163 case DEVICE_SIS:
3164 /* recent SIS7012 can have three codecs */
3165 chip->max_codecs = 3;
3166 chip->codec_bit = sis_codec_bits;
3167 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3168 break;
3169 default:
3170 /* others up to two codecs */
3171 chip->max_codecs = 2;
3172 chip->codec_bit = ich_codec_bits;
3173 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3174 break;
3175 }
3176 for (i = 0; i < chip->max_codecs; i++)
3177 chip->codec_isr_bits |= chip->codec_bit[i];
3178
3179 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3180 snd_intel8x0_free(chip);
3181 return err;
3182 }
3183
3184 /* request irq after initializaing int_sta_mask, etc */
3185 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3186 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3187 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3188 snd_intel8x0_free(chip);
3189 return -EBUSY;
3190 }
3191 chip->irq = pci->irq;
3192
3193 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3194 snd_intel8x0_free(chip);
3195 return err;
3196 }
3197
3198 *r_intel8x0 = chip;
3199 return 0;
3200}
3201
3202static struct shortname_table {
3203 unsigned int id;
3204 const char *s;
3205} shortnames[] = {
3206 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3207 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3208 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3209 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3210 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3211 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3212 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3213 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3214 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3215 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3216 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3217 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3218 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3219 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3220 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3221 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3222 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3223 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3224 { 0x003a, "NVidia MCP04" },
3225 { 0x746d, "AMD AMD8111" },
3226 { 0x7445, "AMD AMD768" },
3227 { 0x5455, "ALi M5455" },
3228 { 0, NULL },
3229};
3230
3231static struct snd_pci_quirk spdif_aclink_defaults[] = {
3232 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3233 { } /* end */
3234};
3235
3236/* look up white/black list for SPDIF over ac-link */
3237static int check_default_spdif_aclink(struct pci_dev *pci)
3238{
3239 const struct snd_pci_quirk *w;
3240
3241 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3242 if (w) {
3243 if (w->value)
3244 dev_dbg(&pci->dev,
3245 "Using SPDIF over AC-Link for %s\n",
3246 snd_pci_quirk_name(w));
3247 else
3248 dev_dbg(&pci->dev,
3249 "Using integrated SPDIF DMA for %s\n",
3250 snd_pci_quirk_name(w));
3251 return w->value;
3252 }
3253 return 0;
3254}
3255
3256static int snd_intel8x0_probe(struct pci_dev *pci,
3257 const struct pci_device_id *pci_id)
3258{
3259 struct snd_card *card;
3260 struct intel8x0 *chip;
3261 int err;
3262 struct shortname_table *name;
3263
3264 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3265 if (err < 0)
3266 return err;
3267
3268 if (spdif_aclink < 0)
3269 spdif_aclink = check_default_spdif_aclink(pci);
3270
3271 strcpy(card->driver, "ICH");
3272 if (!spdif_aclink) {
3273 switch (pci_id->driver_data) {
3274 case DEVICE_NFORCE:
3275 strcpy(card->driver, "NFORCE");
3276 break;
3277 case DEVICE_INTEL_ICH4:
3278 strcpy(card->driver, "ICH4");
3279 }
3280 }
3281
3282 strcpy(card->shortname, "Intel ICH");
3283 for (name = shortnames; name->id; name++) {
3284 if (pci->device == name->id) {
3285 strcpy(card->shortname, name->s);
3286 break;
3287 }
3288 }
3289
3290 if (buggy_irq < 0) {
3291 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3292 * Needs to return IRQ_HANDLED for unknown irqs.
3293 */
3294 if (pci_id->driver_data == DEVICE_NFORCE)
3295 buggy_irq = 1;
3296 else
3297 buggy_irq = 0;
3298 }
3299
3300 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3301 &chip)) < 0) {
3302 snd_card_free(card);
3303 return err;
3304 }
3305 card->private_data = chip;
3306
3307 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3308 snd_card_free(card);
3309 return err;
3310 }
3311 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3312 snd_card_free(card);
3313 return err;
3314 }
3315
3316 snd_intel8x0_proc_init(chip);
3317
3318 snprintf(card->longname, sizeof(card->longname),
3319 "%s with %s at irq %i", card->shortname,
3320 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3321
3322 if (ac97_clock == 0 || ac97_clock == 1) {
3323 if (ac97_clock == 0) {
3324 if (intel8x0_in_clock_list(chip) == 0)
3325 intel8x0_measure_ac97_clock(chip);
3326 } else {
3327 intel8x0_measure_ac97_clock(chip);
3328 }
3329 }
3330
3331 if ((err = snd_card_register(card)) < 0) {
3332 snd_card_free(card);
3333 return err;
3334 }
3335 pci_set_drvdata(pci, card);
3336 return 0;
3337}
3338
3339static void snd_intel8x0_remove(struct pci_dev *pci)
3340{
3341 snd_card_free(pci_get_drvdata(pci));
3342}
3343
3344static struct pci_driver intel8x0_driver = {
3345 .name = KBUILD_MODNAME,
3346 .id_table = snd_intel8x0_ids,
3347 .probe = snd_intel8x0_probe,
3348 .remove = snd_intel8x0_remove,
3349 .driver = {
3350 .pm = INTEL8X0_PM_OPS,
3351 },
3352};
3353
3354module_pci_driver(intel8x0_driver);
1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <asm/io.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/slab.h>
35#include <linux/moduleparam.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/initval.h>
41/* for 440MX workaround */
42#include <asm/pgtable.h>
43#include <asm/cacheflush.h>
44
45MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
46MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
47MODULE_LICENSE("GPL");
48MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
49 "{Intel,82901AB-ICH0},"
50 "{Intel,82801BA-ICH2},"
51 "{Intel,82801CA-ICH3},"
52 "{Intel,82801DB-ICH4},"
53 "{Intel,ICH5},"
54 "{Intel,ICH6},"
55 "{Intel,ICH7},"
56 "{Intel,6300ESB},"
57 "{Intel,ESB2},"
58 "{Intel,MX440},"
59 "{SiS,SI7012},"
60 "{NVidia,nForce Audio},"
61 "{NVidia,nForce2 Audio},"
62 "{NVidia,nForce3 Audio},"
63 "{NVidia,MCP04},"
64 "{NVidia,MCP501},"
65 "{NVidia,CK804},"
66 "{NVidia,CK8},"
67 "{NVidia,CK8S},"
68 "{AMD,AMD768},"
69 "{AMD,AMD8111},"
70 "{ALI,M5455}}");
71
72static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
73static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
74static int ac97_clock;
75static char *ac97_quirk;
76static int buggy_semaphore;
77static int buggy_irq = -1; /* auto-check */
78static int xbox;
79static int spdif_aclink = -1;
80
81module_param(index, int, 0444);
82MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
83module_param(id, charp, 0444);
84MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
85module_param(ac97_clock, int, 0444);
86MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
87module_param(ac97_quirk, charp, 0444);
88MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
89module_param(buggy_semaphore, bool, 0444);
90MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
91module_param(buggy_irq, bool, 0444);
92MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
93module_param(xbox, bool, 0444);
94MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
95module_param(spdif_aclink, int, 0444);
96MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
97
98/* just for backward compatibility */
99static int enable;
100module_param(enable, bool, 0444);
101static int joystick;
102module_param(joystick, int, 0444);
103
104/*
105 * Direct registers
106 */
107enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
108
109#define ICHREG(x) ICH_REG_##x
110
111#define DEFINE_REGSET(name,base) \
112enum { \
113 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
114 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
115 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
116 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
117 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
118 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
119 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
120};
121
122/* busmaster blocks */
123DEFINE_REGSET(OFF, 0); /* offset */
124DEFINE_REGSET(PI, 0x00); /* PCM in */
125DEFINE_REGSET(PO, 0x10); /* PCM out */
126DEFINE_REGSET(MC, 0x20); /* Mic in */
127
128/* ICH4 busmaster blocks */
129DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
130DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
131DEFINE_REGSET(SP, 0x60); /* SPDIF out */
132
133/* values for each busmaster block */
134
135/* LVI */
136#define ICH_REG_LVI_MASK 0x1f
137
138/* SR */
139#define ICH_FIFOE 0x10 /* FIFO error */
140#define ICH_BCIS 0x08 /* buffer completion interrupt status */
141#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
142#define ICH_CELV 0x02 /* current equals last valid */
143#define ICH_DCH 0x01 /* DMA controller halted */
144
145/* PIV */
146#define ICH_REG_PIV_MASK 0x1f /* mask */
147
148/* CR */
149#define ICH_IOCE 0x10 /* interrupt on completion enable */
150#define ICH_FEIE 0x08 /* fifo error interrupt enable */
151#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
152#define ICH_RESETREGS 0x02 /* reset busmaster registers */
153#define ICH_STARTBM 0x01 /* start busmaster operation */
154
155
156/* global block */
157#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
158#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
159#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
160#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
161#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
162#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
163#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
164#define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
165#define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
166#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
167#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
168#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
169#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
170#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
171#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
172#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
173#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
174#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
175#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
176#define ICH_ACLINK 0x00000008 /* AClink shut off */
177#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
178#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
179#define ICH_GIE 0x00000001 /* GPI interrupt enable */
180#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
181#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
182#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
183#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
184#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
185#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
186#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
187#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
188#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
189#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
190#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
191#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
192#define ICH_MD3 0x00020000 /* modem power down semaphore */
193#define ICH_AD3 0x00010000 /* audio power down semaphore */
194#define ICH_RCS 0x00008000 /* read completion status */
195#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
196#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
197#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
198#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
199#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
200#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
201#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
202#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
203#define ICH_POINT 0x00000040 /* playback interrupt */
204#define ICH_PIINT 0x00000020 /* capture interrupt */
205#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
206#define ICH_MOINT 0x00000004 /* modem playback interrupt */
207#define ICH_MIINT 0x00000002 /* modem capture interrupt */
208#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
209#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
210#define ICH_CAS 0x01 /* codec access semaphore */
211#define ICH_REG_SDM 0x80
212#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
213#define ICH_DI2L_SHIFT 6
214#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
215#define ICH_DI1L_SHIFT 4
216#define ICH_SE 0x00000008 /* steer enable */
217#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
218
219#define ICH_MAX_FRAGS 32 /* max hw frags */
220
221
222/*
223 * registers for Ali5455
224 */
225
226/* ALi 5455 busmaster blocks */
227DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
228DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
229DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
230DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
231DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
232DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
233DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
234DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
235DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
236DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
237DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
238
239enum {
240 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
241 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
242 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
243 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
244 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
245 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
246 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
247 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
248 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
249 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
250 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
251 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
252 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
253 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
254 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
255 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
256 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
257 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
258 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
259 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
260 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
261};
262
263#define ALI_CAS_SEM_BUSY 0x80000000
264#define ALI_CPR_ADDR_SECONDARY 0x100
265#define ALI_CPR_ADDR_READ 0x80
266#define ALI_CSPSR_CODEC_READY 0x08
267#define ALI_CSPSR_READ_OK 0x02
268#define ALI_CSPSR_WRITE_OK 0x01
269
270/* interrupts for the whole chip by interrupt status register finish */
271
272#define ALI_INT_MICIN2 (1<<26)
273#define ALI_INT_PCMIN2 (1<<25)
274#define ALI_INT_I2SIN (1<<24)
275#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
276#define ALI_INT_SPDIFIN (1<<22)
277#define ALI_INT_LFEOUT (1<<21)
278#define ALI_INT_CENTEROUT (1<<20)
279#define ALI_INT_CODECSPDIFOUT (1<<19)
280#define ALI_INT_MICIN (1<<18)
281#define ALI_INT_PCMOUT (1<<17)
282#define ALI_INT_PCMIN (1<<16)
283#define ALI_INT_CPRAIS (1<<7) /* command port available */
284#define ALI_INT_SPRAIS (1<<5) /* status port available */
285#define ALI_INT_GPIO (1<<1)
286#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
287 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
288
289#define ICH_ALI_SC_RESET (1<<31) /* master reset */
290#define ICH_ALI_SC_AC97_DBL (1<<30)
291#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
292#define ICH_ALI_SC_IN_BITS (3<<18)
293#define ICH_ALI_SC_OUT_BITS (3<<16)
294#define ICH_ALI_SC_6CH_CFG (3<<14)
295#define ICH_ALI_SC_PCM_4 (1<<8)
296#define ICH_ALI_SC_PCM_6 (2<<8)
297#define ICH_ALI_SC_PCM_246_MASK (3<<8)
298
299#define ICH_ALI_SS_SEC_ID (3<<5)
300#define ICH_ALI_SS_PRI_ID (3<<3)
301
302#define ICH_ALI_IF_AC97SP (1<<21)
303#define ICH_ALI_IF_MC (1<<20)
304#define ICH_ALI_IF_PI (1<<19)
305#define ICH_ALI_IF_MC2 (1<<18)
306#define ICH_ALI_IF_PI2 (1<<17)
307#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
308#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
309#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
310#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
311#define ICH_ALI_IF_PO_SPDF (1<<3)
312#define ICH_ALI_IF_PO (1<<1)
313
314/*
315 *
316 */
317
318enum {
319 ICHD_PCMIN,
320 ICHD_PCMOUT,
321 ICHD_MIC,
322 ICHD_MIC2,
323 ICHD_PCM2IN,
324 ICHD_SPBAR,
325 ICHD_LAST = ICHD_SPBAR
326};
327enum {
328 NVD_PCMIN,
329 NVD_PCMOUT,
330 NVD_MIC,
331 NVD_SPBAR,
332 NVD_LAST = NVD_SPBAR
333};
334enum {
335 ALID_PCMIN,
336 ALID_PCMOUT,
337 ALID_MIC,
338 ALID_AC97SPDIFOUT,
339 ALID_SPDIFIN,
340 ALID_SPDIFOUT,
341 ALID_LAST = ALID_SPDIFOUT
342};
343
344#define get_ichdev(substream) (substream->runtime->private_data)
345
346struct ichdev {
347 unsigned int ichd; /* ich device number */
348 unsigned long reg_offset; /* offset to bmaddr */
349 u32 *bdbar; /* CPU address (32bit) */
350 unsigned int bdbar_addr; /* PCI bus address (32bit) */
351 struct snd_pcm_substream *substream;
352 unsigned int physbuf; /* physical address (32bit) */
353 unsigned int size;
354 unsigned int fragsize;
355 unsigned int fragsize1;
356 unsigned int position;
357 unsigned int pos_shift;
358 unsigned int last_pos;
359 int frags;
360 int lvi;
361 int lvi_frag;
362 int civ;
363 int ack;
364 int ack_reload;
365 unsigned int ack_bit;
366 unsigned int roff_sr;
367 unsigned int roff_picb;
368 unsigned int int_sta_mask; /* interrupt status mask */
369 unsigned int ali_slot; /* ALI DMA slot */
370 struct ac97_pcm *pcm;
371 int pcm_open_flag;
372 unsigned int page_attr_changed: 1;
373 unsigned int suspended: 1;
374};
375
376struct intel8x0 {
377 unsigned int device_type;
378
379 int irq;
380
381 void __iomem *addr;
382 void __iomem *bmaddr;
383
384 struct pci_dev *pci;
385 struct snd_card *card;
386
387 int pcm_devs;
388 struct snd_pcm *pcm[6];
389 struct ichdev ichd[6];
390
391 unsigned multi4: 1,
392 multi6: 1,
393 multi8 :1,
394 dra: 1,
395 smp20bit: 1;
396 unsigned in_ac97_init: 1,
397 in_sdin_init: 1;
398 unsigned in_measurement: 1; /* during ac97 clock measurement */
399 unsigned fix_nocache: 1; /* workaround for 440MX */
400 unsigned buggy_irq: 1; /* workaround for buggy mobos */
401 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
402 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
403
404 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
405 unsigned int sdm_saved; /* SDM reg value */
406
407 struct snd_ac97_bus *ac97_bus;
408 struct snd_ac97 *ac97[3];
409 unsigned int ac97_sdin[3];
410 unsigned int max_codecs, ncodecs;
411 unsigned int *codec_bit;
412 unsigned int codec_isr_bits;
413 unsigned int codec_ready_bits;
414
415 spinlock_t reg_lock;
416
417 u32 bdbars_count;
418 struct snd_dma_buffer bdbars;
419 u32 int_sta_reg; /* interrupt status register */
420 u32 int_sta_mask; /* interrupt status mask */
421};
422
423static DEFINE_PCI_DEVICE_TABLE(snd_intel8x0_ids) = {
424 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
425 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
426 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
427 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
428 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
429 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
430 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
431 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
432 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
433 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
434 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
435 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
436 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
437 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
438 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
439 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
440 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
441 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
442 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
443 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
444 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
445 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
446 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
447 { 0, }
448};
449
450MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
451
452/*
453 * Lowlevel I/O - busmaster
454 */
455
456static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
457{
458 return ioread8(chip->bmaddr + offset);
459}
460
461static inline u16 igetword(struct intel8x0 *chip, u32 offset)
462{
463 return ioread16(chip->bmaddr + offset);
464}
465
466static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
467{
468 return ioread32(chip->bmaddr + offset);
469}
470
471static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
472{
473 iowrite8(val, chip->bmaddr + offset);
474}
475
476static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
477{
478 iowrite16(val, chip->bmaddr + offset);
479}
480
481static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
482{
483 iowrite32(val, chip->bmaddr + offset);
484}
485
486/*
487 * Lowlevel I/O - AC'97 registers
488 */
489
490static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
491{
492 return ioread16(chip->addr + offset);
493}
494
495static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
496{
497 iowrite16(val, chip->addr + offset);
498}
499
500/*
501 * Basic I/O
502 */
503
504/*
505 * access to AC97 codec via normal i/o (for ICH and SIS7012)
506 */
507
508static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
509{
510 int time;
511
512 if (codec > 2)
513 return -EIO;
514 if (chip->in_sdin_init) {
515 /* we don't know the ready bit assignment at the moment */
516 /* so we check any */
517 codec = chip->codec_isr_bits;
518 } else {
519 codec = chip->codec_bit[chip->ac97_sdin[codec]];
520 }
521
522 /* codec ready ? */
523 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
524 return -EIO;
525
526 if (chip->buggy_semaphore)
527 return 0; /* just ignore ... */
528
529 /* Anyone holding a semaphore for 1 msec should be shot... */
530 time = 100;
531 do {
532 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
533 return 0;
534 udelay(10);
535 } while (time--);
536
537 /* access to some forbidden (non existent) ac97 registers will not
538 * reset the semaphore. So even if you don't get the semaphore, still
539 * continue the access. We don't need the semaphore anyway. */
540 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
541 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
542 iagetword(chip, 0); /* clear semaphore flag */
543 /* I don't care about the semaphore */
544 return -EBUSY;
545}
546
547static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
548 unsigned short reg,
549 unsigned short val)
550{
551 struct intel8x0 *chip = ac97->private_data;
552
553 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
554 if (! chip->in_ac97_init)
555 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
556 }
557 iaputword(chip, reg + ac97->num * 0x80, val);
558}
559
560static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
561 unsigned short reg)
562{
563 struct intel8x0 *chip = ac97->private_data;
564 unsigned short res;
565 unsigned int tmp;
566
567 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
568 if (! chip->in_ac97_init)
569 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
570 res = 0xffff;
571 } else {
572 res = iagetword(chip, reg + ac97->num * 0x80);
573 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
574 /* reset RCS and preserve other R/WC bits */
575 iputdword(chip, ICHREG(GLOB_STA), tmp &
576 ~(chip->codec_ready_bits | ICH_GSCI));
577 if (! chip->in_ac97_init)
578 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
579 res = 0xffff;
580 }
581 }
582 return res;
583}
584
585static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
586 unsigned int codec)
587{
588 unsigned int tmp;
589
590 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
591 iagetword(chip, codec * 0x80);
592 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
593 /* reset RCS and preserve other R/WC bits */
594 iputdword(chip, ICHREG(GLOB_STA), tmp &
595 ~(chip->codec_ready_bits | ICH_GSCI));
596 }
597 }
598}
599
600/*
601 * access to AC97 for Ali5455
602 */
603static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
604{
605 int count = 0;
606 for (count = 0; count < 0x7f; count++) {
607 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
608 if (val & mask)
609 return 0;
610 }
611 if (! chip->in_ac97_init)
612 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
613 return -EBUSY;
614}
615
616static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
617{
618 int time = 100;
619 if (chip->buggy_semaphore)
620 return 0; /* just ignore ... */
621 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
622 udelay(1);
623 if (! time && ! chip->in_ac97_init)
624 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
625 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
626}
627
628static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
629{
630 struct intel8x0 *chip = ac97->private_data;
631 unsigned short data = 0xffff;
632
633 if (snd_intel8x0_ali_codec_semaphore(chip))
634 goto __err;
635 reg |= ALI_CPR_ADDR_READ;
636 if (ac97->num)
637 reg |= ALI_CPR_ADDR_SECONDARY;
638 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
639 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
640 goto __err;
641 data = igetword(chip, ICHREG(ALI_SPR));
642 __err:
643 return data;
644}
645
646static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
647 unsigned short val)
648{
649 struct intel8x0 *chip = ac97->private_data;
650
651 if (snd_intel8x0_ali_codec_semaphore(chip))
652 return;
653 iputword(chip, ICHREG(ALI_CPR), val);
654 if (ac97->num)
655 reg |= ALI_CPR_ADDR_SECONDARY;
656 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
657 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
658}
659
660
661/*
662 * DMA I/O
663 */
664static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
665{
666 int idx;
667 u32 *bdbar = ichdev->bdbar;
668 unsigned long port = ichdev->reg_offset;
669
670 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
671 if (ichdev->size == ichdev->fragsize) {
672 ichdev->ack_reload = ichdev->ack = 2;
673 ichdev->fragsize1 = ichdev->fragsize >> 1;
674 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
675 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
676 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
677 ichdev->fragsize1 >> ichdev->pos_shift);
678 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
679 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
680 ichdev->fragsize1 >> ichdev->pos_shift);
681 }
682 ichdev->frags = 2;
683 } else {
684 ichdev->ack_reload = ichdev->ack = 1;
685 ichdev->fragsize1 = ichdev->fragsize;
686 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
687 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
688 (((idx >> 1) * ichdev->fragsize) %
689 ichdev->size));
690 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
691 ichdev->fragsize >> ichdev->pos_shift);
692#if 0
693 printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
694 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
695#endif
696 }
697 ichdev->frags = ichdev->size / ichdev->fragsize;
698 }
699 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
700 ichdev->civ = 0;
701 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
702 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
703 ichdev->position = 0;
704#if 0
705 printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
706 "period_size1 = 0x%x\n",
707 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
708 ichdev->fragsize1);
709#endif
710 /* clear interrupts */
711 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
712}
713
714#ifdef __i386__
715/*
716 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
717 * which aborts PCI busmaster for audio transfer. A workaround is to set
718 * the pages as non-cached. For details, see the errata in
719 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
720 */
721static void fill_nocache(void *buf, int size, int nocache)
722{
723 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
724 if (nocache)
725 set_pages_uc(virt_to_page(buf), size);
726 else
727 set_pages_wb(virt_to_page(buf), size);
728}
729#else
730#define fill_nocache(buf, size, nocache) do { ; } while (0)
731#endif
732
733/*
734 * Interrupt handler
735 */
736
737static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
738{
739 unsigned long port = ichdev->reg_offset;
740 unsigned long flags;
741 int status, civ, i, step;
742 int ack = 0;
743
744 spin_lock_irqsave(&chip->reg_lock, flags);
745 status = igetbyte(chip, port + ichdev->roff_sr);
746 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
747 if (!(status & ICH_BCIS)) {
748 step = 0;
749 } else if (civ == ichdev->civ) {
750 // snd_printd("civ same %d\n", civ);
751 step = 1;
752 ichdev->civ++;
753 ichdev->civ &= ICH_REG_LVI_MASK;
754 } else {
755 step = civ - ichdev->civ;
756 if (step < 0)
757 step += ICH_REG_LVI_MASK + 1;
758 // if (step != 1)
759 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
760 ichdev->civ = civ;
761 }
762
763 ichdev->position += step * ichdev->fragsize1;
764 if (! chip->in_measurement)
765 ichdev->position %= ichdev->size;
766 ichdev->lvi += step;
767 ichdev->lvi &= ICH_REG_LVI_MASK;
768 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
769 for (i = 0; i < step; i++) {
770 ichdev->lvi_frag++;
771 ichdev->lvi_frag %= ichdev->frags;
772 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
773#if 0
774 printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
775 "all = 0x%x, 0x%x\n",
776 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
777 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
778 inl(port + 4), inb(port + ICH_REG_OFF_CR));
779#endif
780 if (--ichdev->ack == 0) {
781 ichdev->ack = ichdev->ack_reload;
782 ack = 1;
783 }
784 }
785 spin_unlock_irqrestore(&chip->reg_lock, flags);
786 if (ack && ichdev->substream) {
787 snd_pcm_period_elapsed(ichdev->substream);
788 }
789 iputbyte(chip, port + ichdev->roff_sr,
790 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
791}
792
793static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
794{
795 struct intel8x0 *chip = dev_id;
796 struct ichdev *ichdev;
797 unsigned int status;
798 unsigned int i;
799
800 status = igetdword(chip, chip->int_sta_reg);
801 if (status == 0xffffffff) /* we are not yet resumed */
802 return IRQ_NONE;
803
804 if ((status & chip->int_sta_mask) == 0) {
805 if (status) {
806 /* ack */
807 iputdword(chip, chip->int_sta_reg, status);
808 if (! chip->buggy_irq)
809 status = 0;
810 }
811 return IRQ_RETVAL(status);
812 }
813
814 for (i = 0; i < chip->bdbars_count; i++) {
815 ichdev = &chip->ichd[i];
816 if (status & ichdev->int_sta_mask)
817 snd_intel8x0_update(chip, ichdev);
818 }
819
820 /* ack them */
821 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
822
823 return IRQ_HANDLED;
824}
825
826/*
827 * PCM part
828 */
829
830static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
831{
832 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
833 struct ichdev *ichdev = get_ichdev(substream);
834 unsigned char val = 0;
835 unsigned long port = ichdev->reg_offset;
836
837 switch (cmd) {
838 case SNDRV_PCM_TRIGGER_RESUME:
839 ichdev->suspended = 0;
840 /* fallthru */
841 case SNDRV_PCM_TRIGGER_START:
842 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
843 val = ICH_IOCE | ICH_STARTBM;
844 ichdev->last_pos = ichdev->position;
845 break;
846 case SNDRV_PCM_TRIGGER_SUSPEND:
847 ichdev->suspended = 1;
848 /* fallthru */
849 case SNDRV_PCM_TRIGGER_STOP:
850 val = 0;
851 break;
852 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
853 val = ICH_IOCE;
854 break;
855 default:
856 return -EINVAL;
857 }
858 iputbyte(chip, port + ICH_REG_OFF_CR, val);
859 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
860 /* wait until DMA stopped */
861 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
862 /* reset whole DMA things */
863 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
864 }
865 return 0;
866}
867
868static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
869{
870 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
871 struct ichdev *ichdev = get_ichdev(substream);
872 unsigned long port = ichdev->reg_offset;
873 static int fiforeg[] = {
874 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
875 };
876 unsigned int val, fifo;
877
878 val = igetdword(chip, ICHREG(ALI_DMACR));
879 switch (cmd) {
880 case SNDRV_PCM_TRIGGER_RESUME:
881 ichdev->suspended = 0;
882 /* fallthru */
883 case SNDRV_PCM_TRIGGER_START:
884 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
885 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
886 /* clear FIFO for synchronization of channels */
887 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
888 fifo &= ~(0xff << (ichdev->ali_slot % 4));
889 fifo |= 0x83 << (ichdev->ali_slot % 4);
890 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
891 }
892 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
893 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
894 /* start DMA */
895 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
896 break;
897 case SNDRV_PCM_TRIGGER_SUSPEND:
898 ichdev->suspended = 1;
899 /* fallthru */
900 case SNDRV_PCM_TRIGGER_STOP:
901 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
902 /* pause */
903 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
904 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
905 while (igetbyte(chip, port + ICH_REG_OFF_CR))
906 ;
907 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
908 break;
909 /* reset whole DMA things */
910 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
911 /* clear interrupts */
912 iputbyte(chip, port + ICH_REG_OFF_SR,
913 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
914 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
915 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
916 break;
917 default:
918 return -EINVAL;
919 }
920 return 0;
921}
922
923static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
924 struct snd_pcm_hw_params *hw_params)
925{
926 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
927 struct ichdev *ichdev = get_ichdev(substream);
928 struct snd_pcm_runtime *runtime = substream->runtime;
929 int dbl = params_rate(hw_params) > 48000;
930 int err;
931
932 if (chip->fix_nocache && ichdev->page_attr_changed) {
933 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
934 ichdev->page_attr_changed = 0;
935 }
936 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
937 if (err < 0)
938 return err;
939 if (chip->fix_nocache) {
940 if (runtime->dma_area && ! ichdev->page_attr_changed) {
941 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
942 ichdev->page_attr_changed = 1;
943 }
944 }
945 if (ichdev->pcm_open_flag) {
946 snd_ac97_pcm_close(ichdev->pcm);
947 ichdev->pcm_open_flag = 0;
948 }
949 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
950 params_channels(hw_params),
951 ichdev->pcm->r[dbl].slots);
952 if (err >= 0) {
953 ichdev->pcm_open_flag = 1;
954 /* Force SPDIF setting */
955 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
956 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
957 params_rate(hw_params));
958 }
959 return err;
960}
961
962static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
963{
964 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
965 struct ichdev *ichdev = get_ichdev(substream);
966
967 if (ichdev->pcm_open_flag) {
968 snd_ac97_pcm_close(ichdev->pcm);
969 ichdev->pcm_open_flag = 0;
970 }
971 if (chip->fix_nocache && ichdev->page_attr_changed) {
972 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
973 ichdev->page_attr_changed = 0;
974 }
975 return snd_pcm_lib_free_pages(substream);
976}
977
978static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
979 struct snd_pcm_runtime *runtime)
980{
981 unsigned int cnt;
982 int dbl = runtime->rate > 48000;
983
984 spin_lock_irq(&chip->reg_lock);
985 switch (chip->device_type) {
986 case DEVICE_ALI:
987 cnt = igetdword(chip, ICHREG(ALI_SCR));
988 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
989 if (runtime->channels == 4 || dbl)
990 cnt |= ICH_ALI_SC_PCM_4;
991 else if (runtime->channels == 6)
992 cnt |= ICH_ALI_SC_PCM_6;
993 iputdword(chip, ICHREG(ALI_SCR), cnt);
994 break;
995 case DEVICE_SIS:
996 cnt = igetdword(chip, ICHREG(GLOB_CNT));
997 cnt &= ~ICH_SIS_PCM_246_MASK;
998 if (runtime->channels == 4 || dbl)
999 cnt |= ICH_SIS_PCM_4;
1000 else if (runtime->channels == 6)
1001 cnt |= ICH_SIS_PCM_6;
1002 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1003 break;
1004 default:
1005 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1006 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1007 if (runtime->channels == 4 || dbl)
1008 cnt |= ICH_PCM_4;
1009 else if (runtime->channels == 6)
1010 cnt |= ICH_PCM_6;
1011 else if (runtime->channels == 8)
1012 cnt |= ICH_PCM_8;
1013 if (chip->device_type == DEVICE_NFORCE) {
1014 /* reset to 2ch once to keep the 6 channel data in alignment,
1015 * to start from Front Left always
1016 */
1017 if (cnt & ICH_PCM_246_MASK) {
1018 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1019 spin_unlock_irq(&chip->reg_lock);
1020 msleep(50); /* grrr... */
1021 spin_lock_irq(&chip->reg_lock);
1022 }
1023 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1024 if (runtime->sample_bits > 16)
1025 cnt |= ICH_PCM_20BIT;
1026 }
1027 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1028 break;
1029 }
1030 spin_unlock_irq(&chip->reg_lock);
1031}
1032
1033static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1034{
1035 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1036 struct snd_pcm_runtime *runtime = substream->runtime;
1037 struct ichdev *ichdev = get_ichdev(substream);
1038
1039 ichdev->physbuf = runtime->dma_addr;
1040 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1041 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1042 if (ichdev->ichd == ICHD_PCMOUT) {
1043 snd_intel8x0_setup_pcm_out(chip, runtime);
1044 if (chip->device_type == DEVICE_INTEL_ICH4)
1045 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1046 }
1047 snd_intel8x0_setup_periods(chip, ichdev);
1048 return 0;
1049}
1050
1051static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1052{
1053 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1054 struct ichdev *ichdev = get_ichdev(substream);
1055 size_t ptr1, ptr;
1056 int civ, timeout = 10;
1057 unsigned int position;
1058
1059 spin_lock(&chip->reg_lock);
1060 do {
1061 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1062 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1063 position = ichdev->position;
1064 if (ptr1 == 0) {
1065 udelay(10);
1066 continue;
1067 }
1068 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1069 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1070 break;
1071 } while (timeout--);
1072 ptr = ichdev->last_pos;
1073 if (ptr1 != 0) {
1074 ptr1 <<= ichdev->pos_shift;
1075 ptr = ichdev->fragsize1 - ptr1;
1076 ptr += position;
1077 if (ptr < ichdev->last_pos) {
1078 unsigned int pos_base, last_base;
1079 pos_base = position / ichdev->fragsize1;
1080 last_base = ichdev->last_pos / ichdev->fragsize1;
1081 /* another sanity check; ptr1 can go back to full
1082 * before the base position is updated
1083 */
1084 if (pos_base == last_base)
1085 ptr = ichdev->last_pos;
1086 }
1087 }
1088 ichdev->last_pos = ptr;
1089 spin_unlock(&chip->reg_lock);
1090 if (ptr >= ichdev->size)
1091 return 0;
1092 return bytes_to_frames(substream->runtime, ptr);
1093}
1094
1095static struct snd_pcm_hardware snd_intel8x0_stream =
1096{
1097 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1098 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1099 SNDRV_PCM_INFO_MMAP_VALID |
1100 SNDRV_PCM_INFO_PAUSE |
1101 SNDRV_PCM_INFO_RESUME),
1102 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1103 .rates = SNDRV_PCM_RATE_48000,
1104 .rate_min = 48000,
1105 .rate_max = 48000,
1106 .channels_min = 2,
1107 .channels_max = 2,
1108 .buffer_bytes_max = 128 * 1024,
1109 .period_bytes_min = 32,
1110 .period_bytes_max = 128 * 1024,
1111 .periods_min = 1,
1112 .periods_max = 1024,
1113 .fifo_size = 0,
1114};
1115
1116static unsigned int channels4[] = {
1117 2, 4,
1118};
1119
1120static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1121 .count = ARRAY_SIZE(channels4),
1122 .list = channels4,
1123 .mask = 0,
1124};
1125
1126static unsigned int channels6[] = {
1127 2, 4, 6,
1128};
1129
1130static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1131 .count = ARRAY_SIZE(channels6),
1132 .list = channels6,
1133 .mask = 0,
1134};
1135
1136static unsigned int channels8[] = {
1137 2, 4, 6, 8,
1138};
1139
1140static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1141 .count = ARRAY_SIZE(channels8),
1142 .list = channels8,
1143 .mask = 0,
1144};
1145
1146static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1147{
1148 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1149 struct snd_pcm_runtime *runtime = substream->runtime;
1150 int err;
1151
1152 ichdev->substream = substream;
1153 runtime->hw = snd_intel8x0_stream;
1154 runtime->hw.rates = ichdev->pcm->rates;
1155 snd_pcm_limit_hw_rates(runtime);
1156 if (chip->device_type == DEVICE_SIS) {
1157 runtime->hw.buffer_bytes_max = 64*1024;
1158 runtime->hw.period_bytes_max = 64*1024;
1159 }
1160 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1161 return err;
1162 runtime->private_data = ichdev;
1163 return 0;
1164}
1165
1166static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1167{
1168 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1169 struct snd_pcm_runtime *runtime = substream->runtime;
1170 int err;
1171
1172 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1173 if (err < 0)
1174 return err;
1175
1176 if (chip->multi8) {
1177 runtime->hw.channels_max = 8;
1178 snd_pcm_hw_constraint_list(runtime, 0,
1179 SNDRV_PCM_HW_PARAM_CHANNELS,
1180 &hw_constraints_channels8);
1181 } else if (chip->multi6) {
1182 runtime->hw.channels_max = 6;
1183 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1184 &hw_constraints_channels6);
1185 } else if (chip->multi4) {
1186 runtime->hw.channels_max = 4;
1187 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1188 &hw_constraints_channels4);
1189 }
1190 if (chip->dra) {
1191 snd_ac97_pcm_double_rate_rules(runtime);
1192 }
1193 if (chip->smp20bit) {
1194 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1195 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1196 }
1197 return 0;
1198}
1199
1200static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1201{
1202 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1203
1204 chip->ichd[ICHD_PCMOUT].substream = NULL;
1205 return 0;
1206}
1207
1208static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1209{
1210 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1211
1212 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1213}
1214
1215static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1216{
1217 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1218
1219 chip->ichd[ICHD_PCMIN].substream = NULL;
1220 return 0;
1221}
1222
1223static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1224{
1225 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1226
1227 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1228}
1229
1230static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1231{
1232 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1233
1234 chip->ichd[ICHD_MIC].substream = NULL;
1235 return 0;
1236}
1237
1238static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1239{
1240 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1241
1242 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1243}
1244
1245static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1246{
1247 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1248
1249 chip->ichd[ICHD_MIC2].substream = NULL;
1250 return 0;
1251}
1252
1253static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1254{
1255 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1256
1257 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1258}
1259
1260static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1261{
1262 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1263
1264 chip->ichd[ICHD_PCM2IN].substream = NULL;
1265 return 0;
1266}
1267
1268static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1269{
1270 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1271 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1272
1273 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1274}
1275
1276static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1277{
1278 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1279 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1280
1281 chip->ichd[idx].substream = NULL;
1282 return 0;
1283}
1284
1285static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1286{
1287 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1288 unsigned int val;
1289
1290 spin_lock_irq(&chip->reg_lock);
1291 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1292 val |= ICH_ALI_IF_AC97SP;
1293 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1294 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1295 spin_unlock_irq(&chip->reg_lock);
1296
1297 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1298}
1299
1300static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1301{
1302 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1303 unsigned int val;
1304
1305 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1306 spin_lock_irq(&chip->reg_lock);
1307 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1308 val &= ~ICH_ALI_IF_AC97SP;
1309 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1310 spin_unlock_irq(&chip->reg_lock);
1311
1312 return 0;
1313}
1314
1315#if 0 // NYI
1316static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1317{
1318 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1319
1320 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1321}
1322
1323static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1324{
1325 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1326
1327 chip->ichd[ALID_SPDIFIN].substream = NULL;
1328 return 0;
1329}
1330
1331static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1332{
1333 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1334
1335 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1336}
1337
1338static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1339{
1340 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1341
1342 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1343 return 0;
1344}
1345#endif
1346
1347static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1348 .open = snd_intel8x0_playback_open,
1349 .close = snd_intel8x0_playback_close,
1350 .ioctl = snd_pcm_lib_ioctl,
1351 .hw_params = snd_intel8x0_hw_params,
1352 .hw_free = snd_intel8x0_hw_free,
1353 .prepare = snd_intel8x0_pcm_prepare,
1354 .trigger = snd_intel8x0_pcm_trigger,
1355 .pointer = snd_intel8x0_pcm_pointer,
1356};
1357
1358static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1359 .open = snd_intel8x0_capture_open,
1360 .close = snd_intel8x0_capture_close,
1361 .ioctl = snd_pcm_lib_ioctl,
1362 .hw_params = snd_intel8x0_hw_params,
1363 .hw_free = snd_intel8x0_hw_free,
1364 .prepare = snd_intel8x0_pcm_prepare,
1365 .trigger = snd_intel8x0_pcm_trigger,
1366 .pointer = snd_intel8x0_pcm_pointer,
1367};
1368
1369static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1370 .open = snd_intel8x0_mic_open,
1371 .close = snd_intel8x0_mic_close,
1372 .ioctl = snd_pcm_lib_ioctl,
1373 .hw_params = snd_intel8x0_hw_params,
1374 .hw_free = snd_intel8x0_hw_free,
1375 .prepare = snd_intel8x0_pcm_prepare,
1376 .trigger = snd_intel8x0_pcm_trigger,
1377 .pointer = snd_intel8x0_pcm_pointer,
1378};
1379
1380static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1381 .open = snd_intel8x0_mic2_open,
1382 .close = snd_intel8x0_mic2_close,
1383 .ioctl = snd_pcm_lib_ioctl,
1384 .hw_params = snd_intel8x0_hw_params,
1385 .hw_free = snd_intel8x0_hw_free,
1386 .prepare = snd_intel8x0_pcm_prepare,
1387 .trigger = snd_intel8x0_pcm_trigger,
1388 .pointer = snd_intel8x0_pcm_pointer,
1389};
1390
1391static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1392 .open = snd_intel8x0_capture2_open,
1393 .close = snd_intel8x0_capture2_close,
1394 .ioctl = snd_pcm_lib_ioctl,
1395 .hw_params = snd_intel8x0_hw_params,
1396 .hw_free = snd_intel8x0_hw_free,
1397 .prepare = snd_intel8x0_pcm_prepare,
1398 .trigger = snd_intel8x0_pcm_trigger,
1399 .pointer = snd_intel8x0_pcm_pointer,
1400};
1401
1402static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1403 .open = snd_intel8x0_spdif_open,
1404 .close = snd_intel8x0_spdif_close,
1405 .ioctl = snd_pcm_lib_ioctl,
1406 .hw_params = snd_intel8x0_hw_params,
1407 .hw_free = snd_intel8x0_hw_free,
1408 .prepare = snd_intel8x0_pcm_prepare,
1409 .trigger = snd_intel8x0_pcm_trigger,
1410 .pointer = snd_intel8x0_pcm_pointer,
1411};
1412
1413static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1414 .open = snd_intel8x0_playback_open,
1415 .close = snd_intel8x0_playback_close,
1416 .ioctl = snd_pcm_lib_ioctl,
1417 .hw_params = snd_intel8x0_hw_params,
1418 .hw_free = snd_intel8x0_hw_free,
1419 .prepare = snd_intel8x0_pcm_prepare,
1420 .trigger = snd_intel8x0_ali_trigger,
1421 .pointer = snd_intel8x0_pcm_pointer,
1422};
1423
1424static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1425 .open = snd_intel8x0_capture_open,
1426 .close = snd_intel8x0_capture_close,
1427 .ioctl = snd_pcm_lib_ioctl,
1428 .hw_params = snd_intel8x0_hw_params,
1429 .hw_free = snd_intel8x0_hw_free,
1430 .prepare = snd_intel8x0_pcm_prepare,
1431 .trigger = snd_intel8x0_ali_trigger,
1432 .pointer = snd_intel8x0_pcm_pointer,
1433};
1434
1435static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1436 .open = snd_intel8x0_mic_open,
1437 .close = snd_intel8x0_mic_close,
1438 .ioctl = snd_pcm_lib_ioctl,
1439 .hw_params = snd_intel8x0_hw_params,
1440 .hw_free = snd_intel8x0_hw_free,
1441 .prepare = snd_intel8x0_pcm_prepare,
1442 .trigger = snd_intel8x0_ali_trigger,
1443 .pointer = snd_intel8x0_pcm_pointer,
1444};
1445
1446static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1447 .open = snd_intel8x0_ali_ac97spdifout_open,
1448 .close = snd_intel8x0_ali_ac97spdifout_close,
1449 .ioctl = snd_pcm_lib_ioctl,
1450 .hw_params = snd_intel8x0_hw_params,
1451 .hw_free = snd_intel8x0_hw_free,
1452 .prepare = snd_intel8x0_pcm_prepare,
1453 .trigger = snd_intel8x0_ali_trigger,
1454 .pointer = snd_intel8x0_pcm_pointer,
1455};
1456
1457#if 0 // NYI
1458static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1459 .open = snd_intel8x0_ali_spdifin_open,
1460 .close = snd_intel8x0_ali_spdifin_close,
1461 .ioctl = snd_pcm_lib_ioctl,
1462 .hw_params = snd_intel8x0_hw_params,
1463 .hw_free = snd_intel8x0_hw_free,
1464 .prepare = snd_intel8x0_pcm_prepare,
1465 .trigger = snd_intel8x0_pcm_trigger,
1466 .pointer = snd_intel8x0_pcm_pointer,
1467};
1468
1469static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1470 .open = snd_intel8x0_ali_spdifout_open,
1471 .close = snd_intel8x0_ali_spdifout_close,
1472 .ioctl = snd_pcm_lib_ioctl,
1473 .hw_params = snd_intel8x0_hw_params,
1474 .hw_free = snd_intel8x0_hw_free,
1475 .prepare = snd_intel8x0_pcm_prepare,
1476 .trigger = snd_intel8x0_pcm_trigger,
1477 .pointer = snd_intel8x0_pcm_pointer,
1478};
1479#endif // NYI
1480
1481struct ich_pcm_table {
1482 char *suffix;
1483 struct snd_pcm_ops *playback_ops;
1484 struct snd_pcm_ops *capture_ops;
1485 size_t prealloc_size;
1486 size_t prealloc_max_size;
1487 int ac97_idx;
1488};
1489
1490static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1491 struct ich_pcm_table *rec)
1492{
1493 struct snd_pcm *pcm;
1494 int err;
1495 char name[32];
1496
1497 if (rec->suffix)
1498 sprintf(name, "Intel ICH - %s", rec->suffix);
1499 else
1500 strcpy(name, "Intel ICH");
1501 err = snd_pcm_new(chip->card, name, device,
1502 rec->playback_ops ? 1 : 0,
1503 rec->capture_ops ? 1 : 0, &pcm);
1504 if (err < 0)
1505 return err;
1506
1507 if (rec->playback_ops)
1508 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1509 if (rec->capture_ops)
1510 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1511
1512 pcm->private_data = chip;
1513 pcm->info_flags = 0;
1514 if (rec->suffix)
1515 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1516 else
1517 strcpy(pcm->name, chip->card->shortname);
1518 chip->pcm[device] = pcm;
1519
1520 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1521 snd_dma_pci_data(chip->pci),
1522 rec->prealloc_size, rec->prealloc_max_size);
1523
1524 return 0;
1525}
1526
1527static struct ich_pcm_table intel_pcms[] __devinitdata = {
1528 {
1529 .playback_ops = &snd_intel8x0_playback_ops,
1530 .capture_ops = &snd_intel8x0_capture_ops,
1531 .prealloc_size = 64 * 1024,
1532 .prealloc_max_size = 128 * 1024,
1533 },
1534 {
1535 .suffix = "MIC ADC",
1536 .capture_ops = &snd_intel8x0_capture_mic_ops,
1537 .prealloc_size = 0,
1538 .prealloc_max_size = 128 * 1024,
1539 .ac97_idx = ICHD_MIC,
1540 },
1541 {
1542 .suffix = "MIC2 ADC",
1543 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1544 .prealloc_size = 0,
1545 .prealloc_max_size = 128 * 1024,
1546 .ac97_idx = ICHD_MIC2,
1547 },
1548 {
1549 .suffix = "ADC2",
1550 .capture_ops = &snd_intel8x0_capture2_ops,
1551 .prealloc_size = 0,
1552 .prealloc_max_size = 128 * 1024,
1553 .ac97_idx = ICHD_PCM2IN,
1554 },
1555 {
1556 .suffix = "IEC958",
1557 .playback_ops = &snd_intel8x0_spdif_ops,
1558 .prealloc_size = 64 * 1024,
1559 .prealloc_max_size = 128 * 1024,
1560 .ac97_idx = ICHD_SPBAR,
1561 },
1562};
1563
1564static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1565 {
1566 .playback_ops = &snd_intel8x0_playback_ops,
1567 .capture_ops = &snd_intel8x0_capture_ops,
1568 .prealloc_size = 64 * 1024,
1569 .prealloc_max_size = 128 * 1024,
1570 },
1571 {
1572 .suffix = "MIC ADC",
1573 .capture_ops = &snd_intel8x0_capture_mic_ops,
1574 .prealloc_size = 0,
1575 .prealloc_max_size = 128 * 1024,
1576 .ac97_idx = NVD_MIC,
1577 },
1578 {
1579 .suffix = "IEC958",
1580 .playback_ops = &snd_intel8x0_spdif_ops,
1581 .prealloc_size = 64 * 1024,
1582 .prealloc_max_size = 128 * 1024,
1583 .ac97_idx = NVD_SPBAR,
1584 },
1585};
1586
1587static struct ich_pcm_table ali_pcms[] __devinitdata = {
1588 {
1589 .playback_ops = &snd_intel8x0_ali_playback_ops,
1590 .capture_ops = &snd_intel8x0_ali_capture_ops,
1591 .prealloc_size = 64 * 1024,
1592 .prealloc_max_size = 128 * 1024,
1593 },
1594 {
1595 .suffix = "MIC ADC",
1596 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1597 .prealloc_size = 0,
1598 .prealloc_max_size = 128 * 1024,
1599 .ac97_idx = ALID_MIC,
1600 },
1601 {
1602 .suffix = "IEC958",
1603 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1604 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1605 .prealloc_size = 64 * 1024,
1606 .prealloc_max_size = 128 * 1024,
1607 .ac97_idx = ALID_AC97SPDIFOUT,
1608 },
1609#if 0 // NYI
1610 {
1611 .suffix = "HW IEC958",
1612 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1613 .prealloc_size = 64 * 1024,
1614 .prealloc_max_size = 128 * 1024,
1615 },
1616#endif
1617};
1618
1619static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1620{
1621 int i, tblsize, device, err;
1622 struct ich_pcm_table *tbl, *rec;
1623
1624 switch (chip->device_type) {
1625 case DEVICE_INTEL_ICH4:
1626 tbl = intel_pcms;
1627 tblsize = ARRAY_SIZE(intel_pcms);
1628 if (spdif_aclink)
1629 tblsize--;
1630 break;
1631 case DEVICE_NFORCE:
1632 tbl = nforce_pcms;
1633 tblsize = ARRAY_SIZE(nforce_pcms);
1634 if (spdif_aclink)
1635 tblsize--;
1636 break;
1637 case DEVICE_ALI:
1638 tbl = ali_pcms;
1639 tblsize = ARRAY_SIZE(ali_pcms);
1640 break;
1641 default:
1642 tbl = intel_pcms;
1643 tblsize = 2;
1644 break;
1645 }
1646
1647 device = 0;
1648 for (i = 0; i < tblsize; i++) {
1649 rec = tbl + i;
1650 if (i > 0 && rec->ac97_idx) {
1651 /* activate PCM only when associated AC'97 codec */
1652 if (! chip->ichd[rec->ac97_idx].pcm)
1653 continue;
1654 }
1655 err = snd_intel8x0_pcm1(chip, device, rec);
1656 if (err < 0)
1657 return err;
1658 device++;
1659 }
1660
1661 chip->pcm_devs = device;
1662 return 0;
1663}
1664
1665
1666/*
1667 * Mixer part
1668 */
1669
1670static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1671{
1672 struct intel8x0 *chip = bus->private_data;
1673 chip->ac97_bus = NULL;
1674}
1675
1676static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1677{
1678 struct intel8x0 *chip = ac97->private_data;
1679 chip->ac97[ac97->num] = NULL;
1680}
1681
1682static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1683 /* front PCM */
1684 {
1685 .exclusive = 1,
1686 .r = { {
1687 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1688 (1 << AC97_SLOT_PCM_RIGHT) |
1689 (1 << AC97_SLOT_PCM_CENTER) |
1690 (1 << AC97_SLOT_PCM_SLEFT) |
1691 (1 << AC97_SLOT_PCM_SRIGHT) |
1692 (1 << AC97_SLOT_LFE)
1693 },
1694 {
1695 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1696 (1 << AC97_SLOT_PCM_RIGHT) |
1697 (1 << AC97_SLOT_PCM_LEFT_0) |
1698 (1 << AC97_SLOT_PCM_RIGHT_0)
1699 }
1700 }
1701 },
1702 /* PCM IN #1 */
1703 {
1704 .stream = 1,
1705 .exclusive = 1,
1706 .r = { {
1707 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1708 (1 << AC97_SLOT_PCM_RIGHT)
1709 }
1710 }
1711 },
1712 /* MIC IN #1 */
1713 {
1714 .stream = 1,
1715 .exclusive = 1,
1716 .r = { {
1717 .slots = (1 << AC97_SLOT_MIC)
1718 }
1719 }
1720 },
1721 /* S/PDIF PCM */
1722 {
1723 .exclusive = 1,
1724 .spdif = 1,
1725 .r = { {
1726 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1727 (1 << AC97_SLOT_SPDIF_RIGHT2)
1728 }
1729 }
1730 },
1731 /* PCM IN #2 */
1732 {
1733 .stream = 1,
1734 .exclusive = 1,
1735 .r = { {
1736 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1737 (1 << AC97_SLOT_PCM_RIGHT)
1738 }
1739 }
1740 },
1741 /* MIC IN #2 */
1742 {
1743 .stream = 1,
1744 .exclusive = 1,
1745 .r = { {
1746 .slots = (1 << AC97_SLOT_MIC)
1747 }
1748 }
1749 },
1750};
1751
1752static struct ac97_quirk ac97_quirks[] __devinitdata = {
1753 {
1754 .subvendor = 0x0e11,
1755 .subdevice = 0x000e,
1756 .name = "Compaq Deskpro EN", /* AD1885 */
1757 .type = AC97_TUNE_HP_ONLY
1758 },
1759 {
1760 .subvendor = 0x0e11,
1761 .subdevice = 0x008a,
1762 .name = "Compaq Evo W4000", /* AD1885 */
1763 .type = AC97_TUNE_HP_ONLY
1764 },
1765 {
1766 .subvendor = 0x0e11,
1767 .subdevice = 0x00b8,
1768 .name = "Compaq Evo D510C",
1769 .type = AC97_TUNE_HP_ONLY
1770 },
1771 {
1772 .subvendor = 0x0e11,
1773 .subdevice = 0x0860,
1774 .name = "HP/Compaq nx7010",
1775 .type = AC97_TUNE_MUTE_LED
1776 },
1777 {
1778 .subvendor = 0x1014,
1779 .subdevice = 0x0534,
1780 .name = "ThinkPad X31",
1781 .type = AC97_TUNE_INV_EAPD
1782 },
1783 {
1784 .subvendor = 0x1014,
1785 .subdevice = 0x1f00,
1786 .name = "MS-9128",
1787 .type = AC97_TUNE_ALC_JACK
1788 },
1789 {
1790 .subvendor = 0x1014,
1791 .subdevice = 0x0267,
1792 .name = "IBM NetVista A30p", /* AD1981B */
1793 .type = AC97_TUNE_HP_ONLY
1794 },
1795 {
1796 .subvendor = 0x1025,
1797 .subdevice = 0x0082,
1798 .name = "Acer Travelmate 2310",
1799 .type = AC97_TUNE_HP_ONLY
1800 },
1801 {
1802 .subvendor = 0x1025,
1803 .subdevice = 0x0083,
1804 .name = "Acer Aspire 3003LCi",
1805 .type = AC97_TUNE_HP_ONLY
1806 },
1807 {
1808 .subvendor = 0x1028,
1809 .subdevice = 0x00d8,
1810 .name = "Dell Precision 530", /* AD1885 */
1811 .type = AC97_TUNE_HP_ONLY
1812 },
1813 {
1814 .subvendor = 0x1028,
1815 .subdevice = 0x010d,
1816 .name = "Dell", /* which model? AD1885 */
1817 .type = AC97_TUNE_HP_ONLY
1818 },
1819 {
1820 .subvendor = 0x1028,
1821 .subdevice = 0x0126,
1822 .name = "Dell Optiplex GX260", /* AD1981A */
1823 .type = AC97_TUNE_HP_ONLY
1824 },
1825 {
1826 .subvendor = 0x1028,
1827 .subdevice = 0x012c,
1828 .name = "Dell Precision 650", /* AD1981A */
1829 .type = AC97_TUNE_HP_ONLY
1830 },
1831 {
1832 .subvendor = 0x1028,
1833 .subdevice = 0x012d,
1834 .name = "Dell Precision 450", /* AD1981B*/
1835 .type = AC97_TUNE_HP_ONLY
1836 },
1837 {
1838 .subvendor = 0x1028,
1839 .subdevice = 0x0147,
1840 .name = "Dell", /* which model? AD1981B*/
1841 .type = AC97_TUNE_HP_ONLY
1842 },
1843 {
1844 .subvendor = 0x1028,
1845 .subdevice = 0x0151,
1846 .name = "Dell Optiplex GX270", /* AD1981B */
1847 .type = AC97_TUNE_HP_ONLY
1848 },
1849 {
1850 .subvendor = 0x1028,
1851 .subdevice = 0x014e,
1852 .name = "Dell D800", /* STAC9750/51 */
1853 .type = AC97_TUNE_HP_ONLY
1854 },
1855 {
1856 .subvendor = 0x1028,
1857 .subdevice = 0x0163,
1858 .name = "Dell Unknown", /* STAC9750/51 */
1859 .type = AC97_TUNE_HP_ONLY
1860 },
1861 {
1862 .subvendor = 0x1028,
1863 .subdevice = 0x016a,
1864 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1865 .type = AC97_TUNE_HP_ONLY
1866 },
1867 {
1868 .subvendor = 0x1028,
1869 .subdevice = 0x0182,
1870 .name = "Dell Latitude D610", /* STAC9750/51 */
1871 .type = AC97_TUNE_HP_ONLY
1872 },
1873 {
1874 .subvendor = 0x1028,
1875 .subdevice = 0x0186,
1876 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1877 .type = AC97_TUNE_HP_MUTE_LED
1878 },
1879 {
1880 .subvendor = 0x1028,
1881 .subdevice = 0x0188,
1882 .name = "Dell Inspiron 6000",
1883 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1884 },
1885 {
1886 .subvendor = 0x1028,
1887 .subdevice = 0x0189,
1888 .name = "Dell Inspiron 9300",
1889 .type = AC97_TUNE_HP_MUTE_LED
1890 },
1891 {
1892 .subvendor = 0x1028,
1893 .subdevice = 0x0191,
1894 .name = "Dell Inspiron 8600",
1895 .type = AC97_TUNE_HP_ONLY
1896 },
1897 {
1898 .subvendor = 0x103c,
1899 .subdevice = 0x006d,
1900 .name = "HP zv5000",
1901 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1902 },
1903 { /* FIXME: which codec? */
1904 .subvendor = 0x103c,
1905 .subdevice = 0x00c3,
1906 .name = "HP xw6000",
1907 .type = AC97_TUNE_HP_ONLY
1908 },
1909 {
1910 .subvendor = 0x103c,
1911 .subdevice = 0x088c,
1912 .name = "HP nc8000",
1913 .type = AC97_TUNE_HP_MUTE_LED
1914 },
1915 {
1916 .subvendor = 0x103c,
1917 .subdevice = 0x0890,
1918 .name = "HP nc6000",
1919 .type = AC97_TUNE_MUTE_LED
1920 },
1921 {
1922 .subvendor = 0x103c,
1923 .subdevice = 0x129d,
1924 .name = "HP xw8000",
1925 .type = AC97_TUNE_HP_ONLY
1926 },
1927 {
1928 .subvendor = 0x103c,
1929 .subdevice = 0x0938,
1930 .name = "HP nc4200",
1931 .type = AC97_TUNE_HP_MUTE_LED
1932 },
1933 {
1934 .subvendor = 0x103c,
1935 .subdevice = 0x099c,
1936 .name = "HP nx6110/nc6120",
1937 .type = AC97_TUNE_HP_MUTE_LED
1938 },
1939 {
1940 .subvendor = 0x103c,
1941 .subdevice = 0x0944,
1942 .name = "HP nc6220",
1943 .type = AC97_TUNE_HP_MUTE_LED
1944 },
1945 {
1946 .subvendor = 0x103c,
1947 .subdevice = 0x0934,
1948 .name = "HP nc8220",
1949 .type = AC97_TUNE_HP_MUTE_LED
1950 },
1951 {
1952 .subvendor = 0x103c,
1953 .subdevice = 0x12f1,
1954 .name = "HP xw8200", /* AD1981B*/
1955 .type = AC97_TUNE_HP_ONLY
1956 },
1957 {
1958 .subvendor = 0x103c,
1959 .subdevice = 0x12f2,
1960 .name = "HP xw6200",
1961 .type = AC97_TUNE_HP_ONLY
1962 },
1963 {
1964 .subvendor = 0x103c,
1965 .subdevice = 0x3008,
1966 .name = "HP xw4200", /* AD1981B*/
1967 .type = AC97_TUNE_HP_ONLY
1968 },
1969 {
1970 .subvendor = 0x104d,
1971 .subdevice = 0x8144,
1972 .name = "Sony",
1973 .type = AC97_TUNE_INV_EAPD
1974 },
1975 {
1976 .subvendor = 0x104d,
1977 .subdevice = 0x8197,
1978 .name = "Sony S1XP",
1979 .type = AC97_TUNE_INV_EAPD
1980 },
1981 {
1982 .subvendor = 0x104d,
1983 .subdevice = 0x81c0,
1984 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1985 .type = AC97_TUNE_INV_EAPD
1986 },
1987 {
1988 .subvendor = 0x104d,
1989 .subdevice = 0x81c5,
1990 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1991 .type = AC97_TUNE_INV_EAPD
1992 },
1993 {
1994 .subvendor = 0x1043,
1995 .subdevice = 0x80f3,
1996 .name = "ASUS ICH5/AD1985",
1997 .type = AC97_TUNE_AD_SHARING
1998 },
1999 {
2000 .subvendor = 0x10cf,
2001 .subdevice = 0x11c3,
2002 .name = "Fujitsu-Siemens E4010",
2003 .type = AC97_TUNE_HP_ONLY
2004 },
2005 {
2006 .subvendor = 0x10cf,
2007 .subdevice = 0x1225,
2008 .name = "Fujitsu-Siemens T3010",
2009 .type = AC97_TUNE_HP_ONLY
2010 },
2011 {
2012 .subvendor = 0x10cf,
2013 .subdevice = 0x1253,
2014 .name = "Fujitsu S6210", /* STAC9750/51 */
2015 .type = AC97_TUNE_HP_ONLY
2016 },
2017 {
2018 .subvendor = 0x10cf,
2019 .subdevice = 0x127d,
2020 .name = "Fujitsu Lifebook P7010",
2021 .type = AC97_TUNE_HP_ONLY
2022 },
2023 {
2024 .subvendor = 0x10cf,
2025 .subdevice = 0x127e,
2026 .name = "Fujitsu Lifebook C1211D",
2027 .type = AC97_TUNE_HP_ONLY
2028 },
2029 {
2030 .subvendor = 0x10cf,
2031 .subdevice = 0x12ec,
2032 .name = "Fujitsu-Siemens 4010",
2033 .type = AC97_TUNE_HP_ONLY
2034 },
2035 {
2036 .subvendor = 0x10cf,
2037 .subdevice = 0x12f2,
2038 .name = "Fujitsu-Siemens Celsius H320",
2039 .type = AC97_TUNE_SWAP_HP
2040 },
2041 {
2042 .subvendor = 0x10f1,
2043 .subdevice = 0x2665,
2044 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
2045 .type = AC97_TUNE_HP_ONLY
2046 },
2047 {
2048 .subvendor = 0x10f1,
2049 .subdevice = 0x2885,
2050 .name = "AMD64 Mobo", /* ALC650 */
2051 .type = AC97_TUNE_HP_ONLY
2052 },
2053 {
2054 .subvendor = 0x10f1,
2055 .subdevice = 0x2895,
2056 .name = "Tyan Thunder K8WE",
2057 .type = AC97_TUNE_HP_ONLY
2058 },
2059 {
2060 .subvendor = 0x10f7,
2061 .subdevice = 0x834c,
2062 .name = "Panasonic CF-R4",
2063 .type = AC97_TUNE_HP_ONLY,
2064 },
2065 {
2066 .subvendor = 0x110a,
2067 .subdevice = 0x0056,
2068 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
2069 .type = AC97_TUNE_HP_ONLY
2070 },
2071 {
2072 .subvendor = 0x11d4,
2073 .subdevice = 0x5375,
2074 .name = "ADI AD1985 (discrete)",
2075 .type = AC97_TUNE_HP_ONLY
2076 },
2077 {
2078 .subvendor = 0x1462,
2079 .subdevice = 0x5470,
2080 .name = "MSI P4 ATX 645 Ultra",
2081 .type = AC97_TUNE_HP_ONLY
2082 },
2083 {
2084 .subvendor = 0x161f,
2085 .subdevice = 0x203a,
2086 .name = "Gateway 4525GZ", /* AD1981B */
2087 .type = AC97_TUNE_INV_EAPD
2088 },
2089 {
2090 .subvendor = 0x1734,
2091 .subdevice = 0x0088,
2092 .name = "Fujitsu-Siemens D1522", /* AD1981 */
2093 .type = AC97_TUNE_HP_ONLY
2094 },
2095 {
2096 .subvendor = 0x8086,
2097 .subdevice = 0x2000,
2098 .mask = 0xfff0,
2099 .name = "Intel ICH5/AD1985",
2100 .type = AC97_TUNE_AD_SHARING
2101 },
2102 {
2103 .subvendor = 0x8086,
2104 .subdevice = 0x4000,
2105 .mask = 0xfff0,
2106 .name = "Intel ICH5/AD1985",
2107 .type = AC97_TUNE_AD_SHARING
2108 },
2109 {
2110 .subvendor = 0x8086,
2111 .subdevice = 0x4856,
2112 .name = "Intel D845WN (82801BA)",
2113 .type = AC97_TUNE_SWAP_HP
2114 },
2115 {
2116 .subvendor = 0x8086,
2117 .subdevice = 0x4d44,
2118 .name = "Intel D850EMV2", /* AD1885 */
2119 .type = AC97_TUNE_HP_ONLY
2120 },
2121 {
2122 .subvendor = 0x8086,
2123 .subdevice = 0x4d56,
2124 .name = "Intel ICH/AD1885",
2125 .type = AC97_TUNE_HP_ONLY
2126 },
2127 {
2128 .subvendor = 0x8086,
2129 .subdevice = 0x6000,
2130 .mask = 0xfff0,
2131 .name = "Intel ICH5/AD1985",
2132 .type = AC97_TUNE_AD_SHARING
2133 },
2134 {
2135 .subvendor = 0x8086,
2136 .subdevice = 0xe000,
2137 .mask = 0xfff0,
2138 .name = "Intel ICH5/AD1985",
2139 .type = AC97_TUNE_AD_SHARING
2140 },
2141#if 0 /* FIXME: this seems wrong on most boards */
2142 {
2143 .subvendor = 0x8086,
2144 .subdevice = 0xa000,
2145 .mask = 0xfff0,
2146 .name = "Intel ICH5/AD1985",
2147 .type = AC97_TUNE_HP_ONLY
2148 },
2149#endif
2150 { } /* terminator */
2151};
2152
2153static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2154 const char *quirk_override)
2155{
2156 struct snd_ac97_bus *pbus;
2157 struct snd_ac97_template ac97;
2158 int err;
2159 unsigned int i, codecs;
2160 unsigned int glob_sta = 0;
2161 struct snd_ac97_bus_ops *ops;
2162 static struct snd_ac97_bus_ops standard_bus_ops = {
2163 .write = snd_intel8x0_codec_write,
2164 .read = snd_intel8x0_codec_read,
2165 };
2166 static struct snd_ac97_bus_ops ali_bus_ops = {
2167 .write = snd_intel8x0_ali_codec_write,
2168 .read = snd_intel8x0_ali_codec_read,
2169 };
2170
2171 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2172 if (!spdif_aclink) {
2173 switch (chip->device_type) {
2174 case DEVICE_NFORCE:
2175 chip->spdif_idx = NVD_SPBAR;
2176 break;
2177 case DEVICE_ALI:
2178 chip->spdif_idx = ALID_AC97SPDIFOUT;
2179 break;
2180 case DEVICE_INTEL_ICH4:
2181 chip->spdif_idx = ICHD_SPBAR;
2182 break;
2183 };
2184 }
2185
2186 chip->in_ac97_init = 1;
2187
2188 memset(&ac97, 0, sizeof(ac97));
2189 ac97.private_data = chip;
2190 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2191 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2192 if (chip->xbox)
2193 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2194 if (chip->device_type != DEVICE_ALI) {
2195 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2196 ops = &standard_bus_ops;
2197 chip->in_sdin_init = 1;
2198 codecs = 0;
2199 for (i = 0; i < chip->max_codecs; i++) {
2200 if (! (glob_sta & chip->codec_bit[i]))
2201 continue;
2202 if (chip->device_type == DEVICE_INTEL_ICH4) {
2203 snd_intel8x0_codec_read_test(chip, codecs);
2204 chip->ac97_sdin[codecs] =
2205 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2206 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2207 chip->ac97_sdin[codecs] = 0;
2208 } else
2209 chip->ac97_sdin[codecs] = i;
2210 codecs++;
2211 }
2212 chip->in_sdin_init = 0;
2213 if (! codecs)
2214 codecs = 1;
2215 } else {
2216 ops = &ali_bus_ops;
2217 codecs = 1;
2218 /* detect the secondary codec */
2219 for (i = 0; i < 100; i++) {
2220 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2221 if (reg & 0x40) {
2222 codecs = 2;
2223 break;
2224 }
2225 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2226 udelay(1);
2227 }
2228 }
2229 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2230 goto __err;
2231 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2232 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2233 pbus->clock = ac97_clock;
2234 /* FIXME: my test board doesn't work well with VRA... */
2235 if (chip->device_type == DEVICE_ALI)
2236 pbus->no_vra = 1;
2237 else
2238 pbus->dra = 1;
2239 chip->ac97_bus = pbus;
2240 chip->ncodecs = codecs;
2241
2242 ac97.pci = chip->pci;
2243 for (i = 0; i < codecs; i++) {
2244 ac97.num = i;
2245 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2246 if (err != -EACCES)
2247 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2248 if (i == 0)
2249 goto __err;
2250 }
2251 }
2252 /* tune up the primary codec */
2253 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2254 /* enable separate SDINs for ICH4 */
2255 if (chip->device_type == DEVICE_INTEL_ICH4)
2256 pbus->isdin = 1;
2257 /* find the available PCM streams */
2258 i = ARRAY_SIZE(ac97_pcm_defs);
2259 if (chip->device_type != DEVICE_INTEL_ICH4)
2260 i -= 2; /* do not allocate PCM2IN and MIC2 */
2261 if (chip->spdif_idx < 0)
2262 i--; /* do not allocate S/PDIF */
2263 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2264 if (err < 0)
2265 goto __err;
2266 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2267 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2268 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2269 if (chip->spdif_idx >= 0)
2270 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2271 if (chip->device_type == DEVICE_INTEL_ICH4) {
2272 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2273 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2274 }
2275 /* enable separate SDINs for ICH4 */
2276 if (chip->device_type == DEVICE_INTEL_ICH4) {
2277 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2278 u8 tmp = igetbyte(chip, ICHREG(SDM));
2279 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2280 if (pcm) {
2281 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2282 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2283 for (i = 1; i < 4; i++) {
2284 if (pcm->r[0].codec[i]) {
2285 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2286 break;
2287 }
2288 }
2289 } else {
2290 tmp &= ~ICH_SE; /* steer disable */
2291 }
2292 iputbyte(chip, ICHREG(SDM), tmp);
2293 }
2294 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2295 chip->multi4 = 1;
2296 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2297 chip->multi6 = 1;
2298 if (chip->ac97[0]->flags & AC97_HAS_8CH)
2299 chip->multi8 = 1;
2300 }
2301 }
2302 if (pbus->pcms[0].r[1].rslots[0]) {
2303 chip->dra = 1;
2304 }
2305 if (chip->device_type == DEVICE_INTEL_ICH4) {
2306 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2307 chip->smp20bit = 1;
2308 }
2309 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2310 /* 48kHz only */
2311 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2312 }
2313 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2314 /* use slot 10/11 for SPDIF */
2315 u32 val;
2316 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2317 val |= ICH_PCM_SPDIF_1011;
2318 iputdword(chip, ICHREG(GLOB_CNT), val);
2319 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2320 }
2321 chip->in_ac97_init = 0;
2322 return 0;
2323
2324 __err:
2325 /* clear the cold-reset bit for the next chance */
2326 if (chip->device_type != DEVICE_ALI)
2327 iputdword(chip, ICHREG(GLOB_CNT),
2328 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2329 return err;
2330}
2331
2332
2333/*
2334 *
2335 */
2336
2337static void do_ali_reset(struct intel8x0 *chip)
2338{
2339 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2340 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2341 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2342 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2343 iputdword(chip, ICHREG(ALI_INTERFACECR),
2344 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2345 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2346 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2347}
2348
2349#ifdef CONFIG_SND_AC97_POWER_SAVE
2350static struct snd_pci_quirk ich_chip_reset_mode[] = {
2351 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2352 { } /* end */
2353};
2354
2355static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2356{
2357 unsigned int cnt;
2358 /* ACLink on, 2 channels */
2359
2360 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2361 return -EIO;
2362
2363 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2364 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2365
2366 /* do cold reset - the full ac97 powerdown may leave the controller
2367 * in a warm state but actually it cannot communicate with the codec.
2368 */
2369 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2370 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2371 udelay(10);
2372 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2373 msleep(1);
2374 return 0;
2375}
2376#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2377 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2378#else
2379#define snd_intel8x0_ich_chip_cold_reset(chip) 0
2380#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2381#endif
2382
2383static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2384{
2385 unsigned long end_time;
2386 unsigned int cnt;
2387 /* ACLink on, 2 channels */
2388 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2389 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2390 /* finish cold or do warm reset */
2391 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2392 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2393 end_time = (jiffies + (HZ / 4)) + 1;
2394 do {
2395 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2396 return 0;
2397 schedule_timeout_uninterruptible(1);
2398 } while (time_after_eq(end_time, jiffies));
2399 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2400 igetdword(chip, ICHREG(GLOB_CNT)));
2401 return -EIO;
2402}
2403
2404static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2405{
2406 unsigned long end_time;
2407 unsigned int status, nstatus;
2408 unsigned int cnt;
2409 int err;
2410
2411 /* put logic to right state */
2412 /* first clear status bits */
2413 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2414 if (chip->device_type == DEVICE_NFORCE)
2415 status |= ICH_NVSPINT;
2416 cnt = igetdword(chip, ICHREG(GLOB_STA));
2417 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2418
2419 if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2420 err = snd_intel8x0_ich_chip_cold_reset(chip);
2421 else
2422 err = snd_intel8x0_ich_chip_reset(chip);
2423 if (err < 0)
2424 return err;
2425
2426 if (probing) {
2427 /* wait for any codec ready status.
2428 * Once it becomes ready it should remain ready
2429 * as long as we do not disable the ac97 link.
2430 */
2431 end_time = jiffies + HZ;
2432 do {
2433 status = igetdword(chip, ICHREG(GLOB_STA)) &
2434 chip->codec_isr_bits;
2435 if (status)
2436 break;
2437 schedule_timeout_uninterruptible(1);
2438 } while (time_after_eq(end_time, jiffies));
2439 if (! status) {
2440 /* no codec is found */
2441 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2442 igetdword(chip, ICHREG(GLOB_STA)));
2443 return -EIO;
2444 }
2445
2446 /* wait for other codecs ready status. */
2447 end_time = jiffies + HZ / 4;
2448 while (status != chip->codec_isr_bits &&
2449 time_after_eq(end_time, jiffies)) {
2450 schedule_timeout_uninterruptible(1);
2451 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2452 chip->codec_isr_bits;
2453 }
2454
2455 } else {
2456 /* resume phase */
2457 int i;
2458 status = 0;
2459 for (i = 0; i < chip->ncodecs; i++)
2460 if (chip->ac97[i])
2461 status |= chip->codec_bit[chip->ac97_sdin[i]];
2462 /* wait until all the probed codecs are ready */
2463 end_time = jiffies + HZ;
2464 do {
2465 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2466 chip->codec_isr_bits;
2467 if (status == nstatus)
2468 break;
2469 schedule_timeout_uninterruptible(1);
2470 } while (time_after_eq(end_time, jiffies));
2471 }
2472
2473 if (chip->device_type == DEVICE_SIS) {
2474 /* unmute the output on SIS7012 */
2475 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2476 }
2477 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2478 /* enable SPDIF interrupt */
2479 unsigned int val;
2480 pci_read_config_dword(chip->pci, 0x4c, &val);
2481 val |= 0x1000000;
2482 pci_write_config_dword(chip->pci, 0x4c, val);
2483 }
2484 return 0;
2485}
2486
2487static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2488{
2489 u32 reg;
2490 int i = 0;
2491
2492 reg = igetdword(chip, ICHREG(ALI_SCR));
2493 if ((reg & 2) == 0) /* Cold required */
2494 reg |= 2;
2495 else
2496 reg |= 1; /* Warm */
2497 reg &= ~0x80000000; /* ACLink on */
2498 iputdword(chip, ICHREG(ALI_SCR), reg);
2499
2500 for (i = 0; i < HZ / 2; i++) {
2501 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2502 goto __ok;
2503 schedule_timeout_uninterruptible(1);
2504 }
2505 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2506 if (probing)
2507 return -EIO;
2508
2509 __ok:
2510 for (i = 0; i < HZ / 2; i++) {
2511 reg = igetdword(chip, ICHREG(ALI_RTSR));
2512 if (reg & 0x80) /* primary codec */
2513 break;
2514 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2515 schedule_timeout_uninterruptible(1);
2516 }
2517
2518 do_ali_reset(chip);
2519 return 0;
2520}
2521
2522static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2523{
2524 unsigned int i, timeout;
2525 int err;
2526
2527 if (chip->device_type != DEVICE_ALI) {
2528 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2529 return err;
2530 iagetword(chip, 0); /* clear semaphore flag */
2531 } else {
2532 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2533 return err;
2534 }
2535
2536 /* disable interrupts */
2537 for (i = 0; i < chip->bdbars_count; i++)
2538 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2539 /* reset channels */
2540 for (i = 0; i < chip->bdbars_count; i++)
2541 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2542 for (i = 0; i < chip->bdbars_count; i++) {
2543 timeout = 100000;
2544 while (--timeout != 0) {
2545 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2546 break;
2547 }
2548 if (timeout == 0)
2549 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2550 }
2551 /* initialize Buffer Descriptor Lists */
2552 for (i = 0; i < chip->bdbars_count; i++)
2553 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2554 chip->ichd[i].bdbar_addr);
2555 return 0;
2556}
2557
2558static int snd_intel8x0_free(struct intel8x0 *chip)
2559{
2560 unsigned int i;
2561
2562 if (chip->irq < 0)
2563 goto __hw_end;
2564 /* disable interrupts */
2565 for (i = 0; i < chip->bdbars_count; i++)
2566 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2567 /* reset channels */
2568 for (i = 0; i < chip->bdbars_count; i++)
2569 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2570 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2571 /* stop the spdif interrupt */
2572 unsigned int val;
2573 pci_read_config_dword(chip->pci, 0x4c, &val);
2574 val &= ~0x1000000;
2575 pci_write_config_dword(chip->pci, 0x4c, val);
2576 }
2577 /* --- */
2578
2579 __hw_end:
2580 if (chip->irq >= 0)
2581 free_irq(chip->irq, chip);
2582 if (chip->bdbars.area) {
2583 if (chip->fix_nocache)
2584 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2585 snd_dma_free_pages(&chip->bdbars);
2586 }
2587 if (chip->addr)
2588 pci_iounmap(chip->pci, chip->addr);
2589 if (chip->bmaddr)
2590 pci_iounmap(chip->pci, chip->bmaddr);
2591 pci_release_regions(chip->pci);
2592 pci_disable_device(chip->pci);
2593 kfree(chip);
2594 return 0;
2595}
2596
2597#ifdef CONFIG_PM
2598/*
2599 * power management
2600 */
2601static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2602{
2603 struct snd_card *card = pci_get_drvdata(pci);
2604 struct intel8x0 *chip = card->private_data;
2605 int i;
2606
2607 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2608 for (i = 0; i < chip->pcm_devs; i++)
2609 snd_pcm_suspend_all(chip->pcm[i]);
2610 /* clear nocache */
2611 if (chip->fix_nocache) {
2612 for (i = 0; i < chip->bdbars_count; i++) {
2613 struct ichdev *ichdev = &chip->ichd[i];
2614 if (ichdev->substream && ichdev->page_attr_changed) {
2615 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2616 if (runtime->dma_area)
2617 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2618 }
2619 }
2620 }
2621 for (i = 0; i < chip->ncodecs; i++)
2622 snd_ac97_suspend(chip->ac97[i]);
2623 if (chip->device_type == DEVICE_INTEL_ICH4)
2624 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2625
2626 if (chip->irq >= 0) {
2627 free_irq(chip->irq, chip);
2628 chip->irq = -1;
2629 }
2630 pci_disable_device(pci);
2631 pci_save_state(pci);
2632 /* The call below may disable built-in speaker on some laptops
2633 * after S2RAM. So, don't touch it.
2634 */
2635 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
2636 return 0;
2637}
2638
2639static int intel8x0_resume(struct pci_dev *pci)
2640{
2641 struct snd_card *card = pci_get_drvdata(pci);
2642 struct intel8x0 *chip = card->private_data;
2643 int i;
2644
2645 pci_set_power_state(pci, PCI_D0);
2646 pci_restore_state(pci);
2647 if (pci_enable_device(pci) < 0) {
2648 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2649 "disabling device\n");
2650 snd_card_disconnect(card);
2651 return -EIO;
2652 }
2653 pci_set_master(pci);
2654 snd_intel8x0_chip_init(chip, 0);
2655 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2656 IRQF_SHARED, KBUILD_MODNAME, chip)) {
2657 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2658 "disabling device\n", pci->irq);
2659 snd_card_disconnect(card);
2660 return -EIO;
2661 }
2662 chip->irq = pci->irq;
2663 synchronize_irq(chip->irq);
2664
2665 /* re-initialize mixer stuff */
2666 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2667 /* enable separate SDINs for ICH4 */
2668 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2669 /* use slot 10/11 for SPDIF */
2670 iputdword(chip, ICHREG(GLOB_CNT),
2671 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2672 ICH_PCM_SPDIF_1011);
2673 }
2674
2675 /* refill nocache */
2676 if (chip->fix_nocache)
2677 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2678
2679 for (i = 0; i < chip->ncodecs; i++)
2680 snd_ac97_resume(chip->ac97[i]);
2681
2682 /* refill nocache */
2683 if (chip->fix_nocache) {
2684 for (i = 0; i < chip->bdbars_count; i++) {
2685 struct ichdev *ichdev = &chip->ichd[i];
2686 if (ichdev->substream && ichdev->page_attr_changed) {
2687 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2688 if (runtime->dma_area)
2689 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2690 }
2691 }
2692 }
2693
2694 /* resume status */
2695 for (i = 0; i < chip->bdbars_count; i++) {
2696 struct ichdev *ichdev = &chip->ichd[i];
2697 unsigned long port = ichdev->reg_offset;
2698 if (! ichdev->substream || ! ichdev->suspended)
2699 continue;
2700 if (ichdev->ichd == ICHD_PCMOUT)
2701 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2702 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2703 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2704 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2705 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2706 }
2707
2708 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2709 return 0;
2710}
2711#endif /* CONFIG_PM */
2712
2713#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2714
2715static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2716{
2717 struct snd_pcm_substream *subs;
2718 struct ichdev *ichdev;
2719 unsigned long port;
2720 unsigned long pos, pos1, t;
2721 int civ, timeout = 1000, attempt = 1;
2722 struct timespec start_time, stop_time;
2723
2724 if (chip->ac97_bus->clock != 48000)
2725 return; /* specified in module option */
2726
2727 __again:
2728 subs = chip->pcm[0]->streams[0].substream;
2729 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2730 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2731 return;
2732 }
2733 ichdev = &chip->ichd[ICHD_PCMOUT];
2734 ichdev->physbuf = subs->dma_buffer.addr;
2735 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2736 ichdev->substream = NULL; /* don't process interrupts */
2737
2738 /* set rate */
2739 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2740 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2741 return;
2742 }
2743 snd_intel8x0_setup_periods(chip, ichdev);
2744 port = ichdev->reg_offset;
2745 spin_lock_irq(&chip->reg_lock);
2746 chip->in_measurement = 1;
2747 /* trigger */
2748 if (chip->device_type != DEVICE_ALI)
2749 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2750 else {
2751 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2752 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2753 }
2754 do_posix_clock_monotonic_gettime(&start_time);
2755 spin_unlock_irq(&chip->reg_lock);
2756 msleep(50);
2757 spin_lock_irq(&chip->reg_lock);
2758 /* check the position */
2759 do {
2760 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2761 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2762 if (pos1 == 0) {
2763 udelay(10);
2764 continue;
2765 }
2766 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2767 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2768 break;
2769 } while (timeout--);
2770 if (pos1 == 0) { /* oops, this value is not reliable */
2771 pos = 0;
2772 } else {
2773 pos = ichdev->fragsize1;
2774 pos -= pos1 << ichdev->pos_shift;
2775 pos += ichdev->position;
2776 }
2777 chip->in_measurement = 0;
2778 do_posix_clock_monotonic_gettime(&stop_time);
2779 /* stop */
2780 if (chip->device_type == DEVICE_ALI) {
2781 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2782 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2783 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2784 ;
2785 } else {
2786 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2787 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2788 ;
2789 }
2790 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2791 spin_unlock_irq(&chip->reg_lock);
2792
2793 if (pos == 0) {
2794 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2795 __retry:
2796 if (attempt < 3) {
2797 msleep(300);
2798 attempt++;
2799 goto __again;
2800 }
2801 goto __end;
2802 }
2803
2804 pos /= 4;
2805 t = stop_time.tv_sec - start_time.tv_sec;
2806 t *= 1000000;
2807 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
2808 printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2809 if (t == 0) {
2810 snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
2811 goto __retry;
2812 }
2813 pos *= 1000;
2814 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2815 if (pos < 40000 || pos >= 60000) {
2816 /* abnormal value. hw problem? */
2817 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2818 goto __retry;
2819 } else if (pos > 40500 && pos < 41500)
2820 /* first exception - 41000Hz reference clock */
2821 chip->ac97_bus->clock = 41000;
2822 else if (pos > 43600 && pos < 44600)
2823 /* second exception - 44100HZ reference clock */
2824 chip->ac97_bus->clock = 44100;
2825 else if (pos < 47500 || pos > 48500)
2826 /* not 48000Hz, tuning the clock.. */
2827 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2828 __end:
2829 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2830 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2831}
2832
2833static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
2834 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2835 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2836 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2837 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2838 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2839 { } /* terminator */
2840};
2841
2842static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
2843{
2844 struct pci_dev *pci = chip->pci;
2845 const struct snd_pci_quirk *wl;
2846
2847 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2848 if (!wl)
2849 return 0;
2850 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
2851 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2852 chip->ac97_bus->clock = wl->value;
2853 return 1;
2854}
2855
2856#ifdef CONFIG_PROC_FS
2857static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2858 struct snd_info_buffer *buffer)
2859{
2860 struct intel8x0 *chip = entry->private_data;
2861 unsigned int tmp;
2862
2863 snd_iprintf(buffer, "Intel8x0\n\n");
2864 if (chip->device_type == DEVICE_ALI)
2865 return;
2866 tmp = igetdword(chip, ICHREG(GLOB_STA));
2867 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2868 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2869 if (chip->device_type == DEVICE_INTEL_ICH4)
2870 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2871 snd_iprintf(buffer, "AC'97 codecs ready :");
2872 if (tmp & chip->codec_isr_bits) {
2873 int i;
2874 static const char *codecs[3] = {
2875 "primary", "secondary", "tertiary"
2876 };
2877 for (i = 0; i < chip->max_codecs; i++)
2878 if (tmp & chip->codec_bit[i])
2879 snd_iprintf(buffer, " %s", codecs[i]);
2880 } else
2881 snd_iprintf(buffer, " none");
2882 snd_iprintf(buffer, "\n");
2883 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2884 chip->device_type == DEVICE_SIS)
2885 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2886 chip->ac97_sdin[0],
2887 chip->ac97_sdin[1],
2888 chip->ac97_sdin[2]);
2889}
2890
2891static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2892{
2893 struct snd_info_entry *entry;
2894
2895 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2896 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2897}
2898#else
2899#define snd_intel8x0_proc_init(x)
2900#endif
2901
2902static int snd_intel8x0_dev_free(struct snd_device *device)
2903{
2904 struct intel8x0 *chip = device->device_data;
2905 return snd_intel8x0_free(chip);
2906}
2907
2908struct ich_reg_info {
2909 unsigned int int_sta_mask;
2910 unsigned int offset;
2911};
2912
2913static unsigned int ich_codec_bits[3] = {
2914 ICH_PCR, ICH_SCR, ICH_TCR
2915};
2916static unsigned int sis_codec_bits[3] = {
2917 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2918};
2919
2920static int __devinit snd_intel8x0_create(struct snd_card *card,
2921 struct pci_dev *pci,
2922 unsigned long device_type,
2923 struct intel8x0 ** r_intel8x0)
2924{
2925 struct intel8x0 *chip;
2926 int err;
2927 unsigned int i;
2928 unsigned int int_sta_masks;
2929 struct ichdev *ichdev;
2930 static struct snd_device_ops ops = {
2931 .dev_free = snd_intel8x0_dev_free,
2932 };
2933
2934 static unsigned int bdbars[] = {
2935 3, /* DEVICE_INTEL */
2936 6, /* DEVICE_INTEL_ICH4 */
2937 3, /* DEVICE_SIS */
2938 6, /* DEVICE_ALI */
2939 4, /* DEVICE_NFORCE */
2940 };
2941 static struct ich_reg_info intel_regs[6] = {
2942 { ICH_PIINT, 0 },
2943 { ICH_POINT, 0x10 },
2944 { ICH_MCINT, 0x20 },
2945 { ICH_M2INT, 0x40 },
2946 { ICH_P2INT, 0x50 },
2947 { ICH_SPINT, 0x60 },
2948 };
2949 static struct ich_reg_info nforce_regs[4] = {
2950 { ICH_PIINT, 0 },
2951 { ICH_POINT, 0x10 },
2952 { ICH_MCINT, 0x20 },
2953 { ICH_NVSPINT, 0x70 },
2954 };
2955 static struct ich_reg_info ali_regs[6] = {
2956 { ALI_INT_PCMIN, 0x40 },
2957 { ALI_INT_PCMOUT, 0x50 },
2958 { ALI_INT_MICIN, 0x60 },
2959 { ALI_INT_CODECSPDIFOUT, 0x70 },
2960 { ALI_INT_SPDIFIN, 0xa0 },
2961 { ALI_INT_SPDIFOUT, 0xb0 },
2962 };
2963 struct ich_reg_info *tbl;
2964
2965 *r_intel8x0 = NULL;
2966
2967 if ((err = pci_enable_device(pci)) < 0)
2968 return err;
2969
2970 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2971 if (chip == NULL) {
2972 pci_disable_device(pci);
2973 return -ENOMEM;
2974 }
2975 spin_lock_init(&chip->reg_lock);
2976 chip->device_type = device_type;
2977 chip->card = card;
2978 chip->pci = pci;
2979 chip->irq = -1;
2980
2981 /* module parameters */
2982 chip->buggy_irq = buggy_irq;
2983 chip->buggy_semaphore = buggy_semaphore;
2984 if (xbox)
2985 chip->xbox = 1;
2986
2987 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2988 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2989 chip->fix_nocache = 1; /* enable workaround */
2990
2991 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2992 kfree(chip);
2993 pci_disable_device(pci);
2994 return err;
2995 }
2996
2997 if (device_type == DEVICE_ALI) {
2998 /* ALI5455 has no ac97 region */
2999 chip->bmaddr = pci_iomap(pci, 0, 0);
3000 goto port_inited;
3001 }
3002
3003 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3004 chip->addr = pci_iomap(pci, 2, 0);
3005 else
3006 chip->addr = pci_iomap(pci, 0, 0);
3007 if (!chip->addr) {
3008 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
3009 snd_intel8x0_free(chip);
3010 return -EIO;
3011 }
3012 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3013 chip->bmaddr = pci_iomap(pci, 3, 0);
3014 else
3015 chip->bmaddr = pci_iomap(pci, 1, 0);
3016 if (!chip->bmaddr) {
3017 snd_printk(KERN_ERR "Controller space ioremap problem\n");
3018 snd_intel8x0_free(chip);
3019 return -EIO;
3020 }
3021
3022 port_inited:
3023 chip->bdbars_count = bdbars[device_type];
3024
3025 /* initialize offsets */
3026 switch (device_type) {
3027 case DEVICE_NFORCE:
3028 tbl = nforce_regs;
3029 break;
3030 case DEVICE_ALI:
3031 tbl = ali_regs;
3032 break;
3033 default:
3034 tbl = intel_regs;
3035 break;
3036 }
3037 for (i = 0; i < chip->bdbars_count; i++) {
3038 ichdev = &chip->ichd[i];
3039 ichdev->ichd = i;
3040 ichdev->reg_offset = tbl[i].offset;
3041 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3042 if (device_type == DEVICE_SIS) {
3043 /* SiS 7012 swaps the registers */
3044 ichdev->roff_sr = ICH_REG_OFF_PICB;
3045 ichdev->roff_picb = ICH_REG_OFF_SR;
3046 } else {
3047 ichdev->roff_sr = ICH_REG_OFF_SR;
3048 ichdev->roff_picb = ICH_REG_OFF_PICB;
3049 }
3050 if (device_type == DEVICE_ALI)
3051 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3052 /* SIS7012 handles the pcm data in bytes, others are in samples */
3053 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3054 }
3055
3056 /* allocate buffer descriptor lists */
3057 /* the start of each lists must be aligned to 8 bytes */
3058 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
3059 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3060 &chip->bdbars) < 0) {
3061 snd_intel8x0_free(chip);
3062 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
3063 return -ENOMEM;
3064 }
3065 /* tables must be aligned to 8 bytes here, but the kernel pages
3066 are much bigger, so we don't care (on i386) */
3067 /* workaround for 440MX */
3068 if (chip->fix_nocache)
3069 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
3070 int_sta_masks = 0;
3071 for (i = 0; i < chip->bdbars_count; i++) {
3072 ichdev = &chip->ichd[i];
3073 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
3074 (i * ICH_MAX_FRAGS * 2);
3075 ichdev->bdbar_addr = chip->bdbars.addr +
3076 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3077 int_sta_masks |= ichdev->int_sta_mask;
3078 }
3079 chip->int_sta_reg = device_type == DEVICE_ALI ?
3080 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3081 chip->int_sta_mask = int_sta_masks;
3082
3083 pci_set_master(pci);
3084
3085 switch(chip->device_type) {
3086 case DEVICE_INTEL_ICH4:
3087 /* ICH4 can have three codecs */
3088 chip->max_codecs = 3;
3089 chip->codec_bit = ich_codec_bits;
3090 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3091 break;
3092 case DEVICE_SIS:
3093 /* recent SIS7012 can have three codecs */
3094 chip->max_codecs = 3;
3095 chip->codec_bit = sis_codec_bits;
3096 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3097 break;
3098 default:
3099 /* others up to two codecs */
3100 chip->max_codecs = 2;
3101 chip->codec_bit = ich_codec_bits;
3102 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3103 break;
3104 }
3105 for (i = 0; i < chip->max_codecs; i++)
3106 chip->codec_isr_bits |= chip->codec_bit[i];
3107
3108 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3109 snd_intel8x0_free(chip);
3110 return err;
3111 }
3112
3113 /* request irq after initializaing int_sta_mask, etc */
3114 if (request_irq(pci->irq, snd_intel8x0_interrupt,
3115 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3116 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3117 snd_intel8x0_free(chip);
3118 return -EBUSY;
3119 }
3120 chip->irq = pci->irq;
3121
3122 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3123 snd_intel8x0_free(chip);
3124 return err;
3125 }
3126
3127 snd_card_set_dev(card, &pci->dev);
3128
3129 *r_intel8x0 = chip;
3130 return 0;
3131}
3132
3133static struct shortname_table {
3134 unsigned int id;
3135 const char *s;
3136} shortnames[] __devinitdata = {
3137 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3138 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3139 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3140 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3141 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3142 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3143 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3144 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3145 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3146 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3147 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3148 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3149 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3150 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3151 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3152 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3153 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3154 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3155 { 0x003a, "NVidia MCP04" },
3156 { 0x746d, "AMD AMD8111" },
3157 { 0x7445, "AMD AMD768" },
3158 { 0x5455, "ALi M5455" },
3159 { 0, NULL },
3160};
3161
3162static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
3163 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3164 { } /* end */
3165};
3166
3167/* look up white/black list for SPDIF over ac-link */
3168static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
3169{
3170 const struct snd_pci_quirk *w;
3171
3172 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3173 if (w) {
3174 if (w->value)
3175 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
3176 "AC-Link for %s\n", w->name);
3177 else
3178 snd_printdd(KERN_INFO "intel8x0: Using integrated "
3179 "SPDIF DMA for %s\n", w->name);
3180 return w->value;
3181 }
3182 return 0;
3183}
3184
3185static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
3186 const struct pci_device_id *pci_id)
3187{
3188 struct snd_card *card;
3189 struct intel8x0 *chip;
3190 int err;
3191 struct shortname_table *name;
3192
3193 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
3194 if (err < 0)
3195 return err;
3196
3197 if (spdif_aclink < 0)
3198 spdif_aclink = check_default_spdif_aclink(pci);
3199
3200 strcpy(card->driver, "ICH");
3201 if (!spdif_aclink) {
3202 switch (pci_id->driver_data) {
3203 case DEVICE_NFORCE:
3204 strcpy(card->driver, "NFORCE");
3205 break;
3206 case DEVICE_INTEL_ICH4:
3207 strcpy(card->driver, "ICH4");
3208 }
3209 }
3210
3211 strcpy(card->shortname, "Intel ICH");
3212 for (name = shortnames; name->id; name++) {
3213 if (pci->device == name->id) {
3214 strcpy(card->shortname, name->s);
3215 break;
3216 }
3217 }
3218
3219 if (buggy_irq < 0) {
3220 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3221 * Needs to return IRQ_HANDLED for unknown irqs.
3222 */
3223 if (pci_id->driver_data == DEVICE_NFORCE)
3224 buggy_irq = 1;
3225 else
3226 buggy_irq = 0;
3227 }
3228
3229 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3230 &chip)) < 0) {
3231 snd_card_free(card);
3232 return err;
3233 }
3234 card->private_data = chip;
3235
3236 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3237 snd_card_free(card);
3238 return err;
3239 }
3240 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3241 snd_card_free(card);
3242 return err;
3243 }
3244
3245 snd_intel8x0_proc_init(chip);
3246
3247 snprintf(card->longname, sizeof(card->longname),
3248 "%s with %s at irq %i", card->shortname,
3249 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3250
3251 if (ac97_clock == 0 || ac97_clock == 1) {
3252 if (ac97_clock == 0) {
3253 if (intel8x0_in_clock_list(chip) == 0)
3254 intel8x0_measure_ac97_clock(chip);
3255 } else {
3256 intel8x0_measure_ac97_clock(chip);
3257 }
3258 }
3259
3260 if ((err = snd_card_register(card)) < 0) {
3261 snd_card_free(card);
3262 return err;
3263 }
3264 pci_set_drvdata(pci, card);
3265 return 0;
3266}
3267
3268static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3269{
3270 snd_card_free(pci_get_drvdata(pci));
3271 pci_set_drvdata(pci, NULL);
3272}
3273
3274static struct pci_driver driver = {
3275 .name = KBUILD_MODNAME,
3276 .id_table = snd_intel8x0_ids,
3277 .probe = snd_intel8x0_probe,
3278 .remove = __devexit_p(snd_intel8x0_remove),
3279#ifdef CONFIG_PM
3280 .suspend = intel8x0_suspend,
3281 .resume = intel8x0_resume,
3282#endif
3283};
3284
3285
3286static int __init alsa_card_intel8x0_init(void)
3287{
3288 return pci_register_driver(&driver);
3289}
3290
3291static void __exit alsa_card_intel8x0_exit(void)
3292{
3293 pci_unregister_driver(&driver);
3294}
3295
3296module_init(alsa_card_intel8x0_init)
3297module_exit(alsa_card_intel8x0_exit)