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1/*
2 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
3 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
4 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the version 2 of the GNU General Public License
8 * as published by the Free Software Foundation
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/netdevice.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/pci.h>
26#include <linux/can/dev.h>
27#include <linux/io.h>
28
29#include "sja1000.h"
30
31#define DRV_NAME "ems_pci"
32
33MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
34MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
35MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
36MODULE_LICENSE("GPL v2");
37
38#define EMS_PCI_V1_MAX_CHAN 2
39#define EMS_PCI_V2_MAX_CHAN 4
40#define EMS_PCI_MAX_CHAN EMS_PCI_V2_MAX_CHAN
41
42struct ems_pci_card {
43 int version;
44 int channels;
45
46 struct pci_dev *pci_dev;
47 struct net_device *net_dev[EMS_PCI_MAX_CHAN];
48
49 void __iomem *conf_addr;
50 void __iomem *base_addr;
51};
52
53#define EMS_PCI_CAN_CLOCK (16000000 / 2)
54
55/*
56 * Register definitions and descriptions are from LinCAN 0.3.3.
57 *
58 * PSB4610 PITA-2 bridge control registers
59 */
60#define PITA2_ICR 0x00 /* Interrupt Control Register */
61#define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
62#define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */
63
64#define PITA2_MISC 0x1c /* Miscellaneous Register */
65#define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */
66
67/*
68 * Register definitions for the PLX 9030
69 */
70#define PLX_ICSR 0x4c /* Interrupt Control/Status register */
71#define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
72#define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
73#define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
74#define PLX_ICSR_ENA_CLR (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
75 PLX_ICSR_LINTI1_CLR)
76
77/*
78 * The board configuration is probably following:
79 * RX1 is connected to ground.
80 * TX1 is not connected.
81 * CLKO is not connected.
82 * Setting the OCR register to 0xDA is a good idea.
83 * This means normal output mode, push-pull and the correct polarity.
84 */
85#define EMS_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
86
87/*
88 * In the CDR register, you should set CBP to 1.
89 * You will probably also want to set the clock divider value to 7
90 * (meaning direct oscillator output) because the second SJA1000 chip
91 * is driven by the first one CLKOUT output.
92 */
93#define EMS_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
94
95#define EMS_PCI_V1_BASE_BAR 1
96#define EMS_PCI_V1_CONF_SIZE 4096 /* size of PITA control area */
97#define EMS_PCI_V2_BASE_BAR 2
98#define EMS_PCI_V2_CONF_SIZE 128 /* size of PLX control area */
99#define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
100#define EMS_PCI_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
101
102#define EMS_PCI_BASE_SIZE 4096 /* size of controller area */
103
104static const struct pci_device_id ems_pci_tbl[] = {
105 /* CPC-PCI v1 */
106 {PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
107 /* CPC-PCI v2 */
108 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
109 /* CPC-104P v2 */
110 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
111 {0,}
112};
113MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
114
115/*
116 * Helper to read internal registers from card logic (not CAN)
117 */
118static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
119{
120 return readb(card->base_addr + (port * 4));
121}
122
123static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
124{
125 return readb(priv->reg_base + (port * 4));
126}
127
128static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
129 int port, u8 val)
130{
131 writeb(val, priv->reg_base + (port * 4));
132}
133
134static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
135{
136 struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
137
138 /* reset int flag of pita */
139 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
140 card->conf_addr + PITA2_ICR);
141}
142
143static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
144{
145 return readb(priv->reg_base + port);
146}
147
148static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
149 int port, u8 val)
150{
151 writeb(val, priv->reg_base + port);
152}
153
154static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
155{
156 struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
157
158 writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
159}
160
161/*
162 * Check if a CAN controller is present at the specified location
163 * by trying to set 'em into the PeliCAN mode
164 */
165static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
166{
167 unsigned char res;
168
169 /* Make sure SJA1000 is in reset mode */
170 priv->write_reg(priv, SJA1000_MOD, 1);
171
172 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
173
174 /* read reset-values */
175 res = priv->read_reg(priv, SJA1000_CDR);
176
177 if (res == CDR_PELICAN)
178 return 1;
179
180 return 0;
181}
182
183static void ems_pci_del_card(struct pci_dev *pdev)
184{
185 struct ems_pci_card *card = pci_get_drvdata(pdev);
186 struct net_device *dev;
187 int i = 0;
188
189 for (i = 0; i < card->channels; i++) {
190 dev = card->net_dev[i];
191
192 if (!dev)
193 continue;
194
195 dev_info(&pdev->dev, "Removing %s.\n", dev->name);
196 unregister_sja1000dev(dev);
197 free_sja1000dev(dev);
198 }
199
200 if (card->base_addr != NULL)
201 pci_iounmap(card->pci_dev, card->base_addr);
202
203 if (card->conf_addr != NULL)
204 pci_iounmap(card->pci_dev, card->conf_addr);
205
206 kfree(card);
207
208 pci_disable_device(pdev);
209}
210
211static void ems_pci_card_reset(struct ems_pci_card *card)
212{
213 /* Request board reset */
214 writeb(0, card->base_addr);
215}
216
217/*
218 * Probe PCI device for EMS CAN signature and register each available
219 * CAN channel to SJA1000 Socket-CAN subsystem.
220 */
221static int ems_pci_add_card(struct pci_dev *pdev,
222 const struct pci_device_id *ent)
223{
224 struct sja1000_priv *priv;
225 struct net_device *dev;
226 struct ems_pci_card *card;
227 int max_chan, conf_size, base_bar;
228 int err, i;
229
230 /* Enabling PCI device */
231 if (pci_enable_device(pdev) < 0) {
232 dev_err(&pdev->dev, "Enabling PCI device failed\n");
233 return -ENODEV;
234 }
235
236 /* Allocating card structures to hold addresses, ... */
237 card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
238 if (card == NULL) {
239 pci_disable_device(pdev);
240 return -ENOMEM;
241 }
242
243 pci_set_drvdata(pdev, card);
244
245 card->pci_dev = pdev;
246
247 card->channels = 0;
248
249 if (pdev->vendor == PCI_VENDOR_ID_PLX) {
250 card->version = 2; /* CPC-PCI v2 */
251 max_chan = EMS_PCI_V2_MAX_CHAN;
252 base_bar = EMS_PCI_V2_BASE_BAR;
253 conf_size = EMS_PCI_V2_CONF_SIZE;
254 } else {
255 card->version = 1; /* CPC-PCI v1 */
256 max_chan = EMS_PCI_V1_MAX_CHAN;
257 base_bar = EMS_PCI_V1_BASE_BAR;
258 conf_size = EMS_PCI_V1_CONF_SIZE;
259 }
260
261 /* Remap configuration space and controller memory area */
262 card->conf_addr = pci_iomap(pdev, 0, conf_size);
263 if (card->conf_addr == NULL) {
264 err = -ENOMEM;
265 goto failure_cleanup;
266 }
267
268 card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
269 if (card->base_addr == NULL) {
270 err = -ENOMEM;
271 goto failure_cleanup;
272 }
273
274 if (card->version == 1) {
275 /* Configure PITA-2 parallel interface (enable MUX) */
276 writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
277
278 /* Check for unique EMS CAN signature */
279 if (ems_pci_v1_readb(card, 0) != 0x55 ||
280 ems_pci_v1_readb(card, 1) != 0xAA ||
281 ems_pci_v1_readb(card, 2) != 0x01 ||
282 ems_pci_v1_readb(card, 3) != 0xCB ||
283 ems_pci_v1_readb(card, 4) != 0x11) {
284 dev_err(&pdev->dev,
285 "Not EMS Dr. Thomas Wuensche interface\n");
286 err = -ENODEV;
287 goto failure_cleanup;
288 }
289 }
290
291 ems_pci_card_reset(card);
292
293 /* Detect available channels */
294 for (i = 0; i < max_chan; i++) {
295 dev = alloc_sja1000dev(0);
296 if (dev == NULL) {
297 err = -ENOMEM;
298 goto failure_cleanup;
299 }
300
301 card->net_dev[i] = dev;
302 priv = netdev_priv(dev);
303 priv->priv = card;
304 priv->irq_flags = IRQF_SHARED;
305
306 dev->irq = pdev->irq;
307 priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
308 + (i * EMS_PCI_CAN_CTRL_SIZE);
309 if (card->version == 1) {
310 priv->read_reg = ems_pci_v1_read_reg;
311 priv->write_reg = ems_pci_v1_write_reg;
312 priv->post_irq = ems_pci_v1_post_irq;
313 } else {
314 priv->read_reg = ems_pci_v2_read_reg;
315 priv->write_reg = ems_pci_v2_write_reg;
316 priv->post_irq = ems_pci_v2_post_irq;
317 }
318
319 /* Check if channel is present */
320 if (ems_pci_check_chan(priv)) {
321 priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
322 priv->ocr = EMS_PCI_OCR;
323 priv->cdr = EMS_PCI_CDR;
324
325 SET_NETDEV_DEV(dev, &pdev->dev);
326 dev->dev_id = i;
327
328 if (card->version == 1)
329 /* reset int flag of pita */
330 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
331 card->conf_addr + PITA2_ICR);
332 else
333 /* enable IRQ in PLX 9030 */
334 writel(PLX_ICSR_ENA_CLR,
335 card->conf_addr + PLX_ICSR);
336
337 /* Register SJA1000 device */
338 err = register_sja1000dev(dev);
339 if (err) {
340 dev_err(&pdev->dev, "Registering device failed "
341 "(err=%d)\n", err);
342 free_sja1000dev(dev);
343 goto failure_cleanup;
344 }
345
346 card->channels++;
347
348 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
349 i + 1, priv->reg_base, dev->irq);
350 } else {
351 free_sja1000dev(dev);
352 }
353 }
354
355 return 0;
356
357failure_cleanup:
358 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
359
360 ems_pci_del_card(pdev);
361
362 return err;
363}
364
365static struct pci_driver ems_pci_driver = {
366 .name = DRV_NAME,
367 .id_table = ems_pci_tbl,
368 .probe = ems_pci_add_card,
369 .remove = ems_pci_del_card,
370};
371
372module_pci_driver(ems_pci_driver);
1/*
2 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
3 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
4 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the version 2 of the GNU General Public License
8 * as published by the Free Software Foundation
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/interrupt.h>
23#include <linux/netdevice.h>
24#include <linux/delay.h>
25#include <linux/slab.h>
26#include <linux/pci.h>
27#include <linux/can/dev.h>
28#include <linux/io.h>
29
30#include "sja1000.h"
31
32#define DRV_NAME "ems_pci"
33
34MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
35MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
36MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
37MODULE_LICENSE("GPL v2");
38
39#define EMS_PCI_V1_MAX_CHAN 2
40#define EMS_PCI_V2_MAX_CHAN 4
41#define EMS_PCI_MAX_CHAN EMS_PCI_V2_MAX_CHAN
42
43struct ems_pci_card {
44 int version;
45 int channels;
46
47 struct pci_dev *pci_dev;
48 struct net_device *net_dev[EMS_PCI_MAX_CHAN];
49
50 void __iomem *conf_addr;
51 void __iomem *base_addr;
52};
53
54#define EMS_PCI_CAN_CLOCK (16000000 / 2)
55
56/*
57 * Register definitions and descriptions are from LinCAN 0.3.3.
58 *
59 * PSB4610 PITA-2 bridge control registers
60 */
61#define PITA2_ICR 0x00 /* Interrupt Control Register */
62#define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
63#define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */
64
65#define PITA2_MISC 0x1c /* Miscellaneous Register */
66#define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */
67
68/*
69 * Register definitions for the PLX 9030
70 */
71#define PLX_ICSR 0x4c /* Interrupt Control/Status register */
72#define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
73#define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
74#define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
75#define PLX_ICSR_ENA_CLR (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
76 PLX_ICSR_LINTI1_CLR)
77
78/*
79 * The board configuration is probably following:
80 * RX1 is connected to ground.
81 * TX1 is not connected.
82 * CLKO is not connected.
83 * Setting the OCR register to 0xDA is a good idea.
84 * This means normal output mode, push-pull and the correct polarity.
85 */
86#define EMS_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
87
88/*
89 * In the CDR register, you should set CBP to 1.
90 * You will probably also want to set the clock divider value to 7
91 * (meaning direct oscillator output) because the second SJA1000 chip
92 * is driven by the first one CLKOUT output.
93 */
94#define EMS_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
95
96#define EMS_PCI_V1_BASE_BAR 1
97#define EMS_PCI_V1_CONF_SIZE 4096 /* size of PITA control area */
98#define EMS_PCI_V2_BASE_BAR 2
99#define EMS_PCI_V2_CONF_SIZE 128 /* size of PLX control area */
100#define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
101#define EMS_PCI_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
102
103#define EMS_PCI_BASE_SIZE 4096 /* size of controller area */
104
105static DEFINE_PCI_DEVICE_TABLE(ems_pci_tbl) = {
106 /* CPC-PCI v1 */
107 {PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
108 /* CPC-PCI v2 */
109 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
110 /* CPC-104P v2 */
111 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
112 {0,}
113};
114MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
115
116/*
117 * Helper to read internal registers from card logic (not CAN)
118 */
119static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
120{
121 return readb(card->base_addr + (port * 4));
122}
123
124static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
125{
126 return readb(priv->reg_base + (port * 4));
127}
128
129static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
130 int port, u8 val)
131{
132 writeb(val, priv->reg_base + (port * 4));
133}
134
135static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
136{
137 struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
138
139 /* reset int flag of pita */
140 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
141 card->conf_addr + PITA2_ICR);
142}
143
144static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
145{
146 return readb(priv->reg_base + port);
147}
148
149static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
150 int port, u8 val)
151{
152 writeb(val, priv->reg_base + port);
153}
154
155static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
156{
157 struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
158
159 writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
160}
161
162/*
163 * Check if a CAN controller is present at the specified location
164 * by trying to set 'em into the PeliCAN mode
165 */
166static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
167{
168 unsigned char res;
169
170 /* Make sure SJA1000 is in reset mode */
171 priv->write_reg(priv, REG_MOD, 1);
172
173 priv->write_reg(priv, REG_CDR, CDR_PELICAN);
174
175 /* read reset-values */
176 res = priv->read_reg(priv, REG_CDR);
177
178 if (res == CDR_PELICAN)
179 return 1;
180
181 return 0;
182}
183
184static void ems_pci_del_card(struct pci_dev *pdev)
185{
186 struct ems_pci_card *card = pci_get_drvdata(pdev);
187 struct net_device *dev;
188 int i = 0;
189
190 for (i = 0; i < card->channels; i++) {
191 dev = card->net_dev[i];
192
193 if (!dev)
194 continue;
195
196 dev_info(&pdev->dev, "Removing %s.\n", dev->name);
197 unregister_sja1000dev(dev);
198 free_sja1000dev(dev);
199 }
200
201 if (card->base_addr != NULL)
202 pci_iounmap(card->pci_dev, card->base_addr);
203
204 if (card->conf_addr != NULL)
205 pci_iounmap(card->pci_dev, card->conf_addr);
206
207 kfree(card);
208
209 pci_disable_device(pdev);
210 pci_set_drvdata(pdev, NULL);
211}
212
213static void ems_pci_card_reset(struct ems_pci_card *card)
214{
215 /* Request board reset */
216 writeb(0, card->base_addr);
217}
218
219/*
220 * Probe PCI device for EMS CAN signature and register each available
221 * CAN channel to SJA1000 Socket-CAN subsystem.
222 */
223static int __devinit ems_pci_add_card(struct pci_dev *pdev,
224 const struct pci_device_id *ent)
225{
226 struct sja1000_priv *priv;
227 struct net_device *dev;
228 struct ems_pci_card *card;
229 int max_chan, conf_size, base_bar;
230 int err, i;
231
232 /* Enabling PCI device */
233 if (pci_enable_device(pdev) < 0) {
234 dev_err(&pdev->dev, "Enabling PCI device failed\n");
235 return -ENODEV;
236 }
237
238 /* Allocating card structures to hold addresses, ... */
239 card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
240 if (card == NULL) {
241 dev_err(&pdev->dev, "Unable to allocate memory\n");
242 pci_disable_device(pdev);
243 return -ENOMEM;
244 }
245
246 pci_set_drvdata(pdev, card);
247
248 card->pci_dev = pdev;
249
250 card->channels = 0;
251
252 if (pdev->vendor == PCI_VENDOR_ID_PLX) {
253 card->version = 2; /* CPC-PCI v2 */
254 max_chan = EMS_PCI_V2_MAX_CHAN;
255 base_bar = EMS_PCI_V2_BASE_BAR;
256 conf_size = EMS_PCI_V2_CONF_SIZE;
257 } else {
258 card->version = 1; /* CPC-PCI v1 */
259 max_chan = EMS_PCI_V1_MAX_CHAN;
260 base_bar = EMS_PCI_V1_BASE_BAR;
261 conf_size = EMS_PCI_V1_CONF_SIZE;
262 }
263
264 /* Remap configuration space and controller memory area */
265 card->conf_addr = pci_iomap(pdev, 0, conf_size);
266 if (card->conf_addr == NULL) {
267 err = -ENOMEM;
268 goto failure_cleanup;
269 }
270
271 card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
272 if (card->base_addr == NULL) {
273 err = -ENOMEM;
274 goto failure_cleanup;
275 }
276
277 if (card->version == 1) {
278 /* Configure PITA-2 parallel interface (enable MUX) */
279 writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
280
281 /* Check for unique EMS CAN signature */
282 if (ems_pci_v1_readb(card, 0) != 0x55 ||
283 ems_pci_v1_readb(card, 1) != 0xAA ||
284 ems_pci_v1_readb(card, 2) != 0x01 ||
285 ems_pci_v1_readb(card, 3) != 0xCB ||
286 ems_pci_v1_readb(card, 4) != 0x11) {
287 dev_err(&pdev->dev,
288 "Not EMS Dr. Thomas Wuensche interface\n");
289 err = -ENODEV;
290 goto failure_cleanup;
291 }
292 }
293
294 ems_pci_card_reset(card);
295
296 /* Detect available channels */
297 for (i = 0; i < max_chan; i++) {
298 dev = alloc_sja1000dev(0);
299 if (dev == NULL) {
300 err = -ENOMEM;
301 goto failure_cleanup;
302 }
303
304 card->net_dev[i] = dev;
305 priv = netdev_priv(dev);
306 priv->priv = card;
307 priv->irq_flags = IRQF_SHARED;
308
309 dev->irq = pdev->irq;
310 priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
311 + (i * EMS_PCI_CAN_CTRL_SIZE);
312 if (card->version == 1) {
313 priv->read_reg = ems_pci_v1_read_reg;
314 priv->write_reg = ems_pci_v1_write_reg;
315 priv->post_irq = ems_pci_v1_post_irq;
316 } else {
317 priv->read_reg = ems_pci_v2_read_reg;
318 priv->write_reg = ems_pci_v2_write_reg;
319 priv->post_irq = ems_pci_v2_post_irq;
320 }
321
322 /* Check if channel is present */
323 if (ems_pci_check_chan(priv)) {
324 priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
325 priv->ocr = EMS_PCI_OCR;
326 priv->cdr = EMS_PCI_CDR;
327
328 SET_NETDEV_DEV(dev, &pdev->dev);
329
330 if (card->version == 1)
331 /* reset int flag of pita */
332 writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
333 card->conf_addr + PITA2_ICR);
334 else
335 /* enable IRQ in PLX 9030 */
336 writel(PLX_ICSR_ENA_CLR,
337 card->conf_addr + PLX_ICSR);
338
339 /* Register SJA1000 device */
340 err = register_sja1000dev(dev);
341 if (err) {
342 dev_err(&pdev->dev, "Registering device failed "
343 "(err=%d)\n", err);
344 free_sja1000dev(dev);
345 goto failure_cleanup;
346 }
347
348 card->channels++;
349
350 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
351 i + 1, priv->reg_base, dev->irq);
352 } else {
353 free_sja1000dev(dev);
354 }
355 }
356
357 return 0;
358
359failure_cleanup:
360 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
361
362 ems_pci_del_card(pdev);
363
364 return err;
365}
366
367static struct pci_driver ems_pci_driver = {
368 .name = DRV_NAME,
369 .id_table = ems_pci_tbl,
370 .probe = ems_pci_add_card,
371 .remove = ems_pci_del_card,
372};
373
374static int __init ems_pci_init(void)
375{
376 return pci_register_driver(&ems_pci_driver);
377}
378
379static void __exit ems_pci_exit(void)
380{
381 pci_unregister_driver(&ems_pci_driver);
382}
383
384module_init(ems_pci_init);
385module_exit(ems_pci_exit);
386