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1/* pci_sun4v.c: SUN4V specific PCI controller support.
2 *
3 * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/pci.h>
9#include <linux/init.h>
10#include <linux/slab.h>
11#include <linux/interrupt.h>
12#include <linux/percpu.h>
13#include <linux/irq.h>
14#include <linux/msi.h>
15#include <linux/export.h>
16#include <linux/log2.h>
17#include <linux/of_device.h>
18#include <linux/iommu-common.h>
19
20#include <asm/iommu.h>
21#include <asm/irq.h>
22#include <asm/hypervisor.h>
23#include <asm/prom.h>
24
25#include "pci_impl.h"
26#include "iommu_common.h"
27
28#include "pci_sun4v.h"
29
30#define DRIVER_NAME "pci_sun4v"
31#define PFX DRIVER_NAME ": "
32
33static unsigned long vpci_major;
34static unsigned long vpci_minor;
35
36struct vpci_version {
37 unsigned long major;
38 unsigned long minor;
39};
40
41/* Ordered from largest major to lowest */
42static struct vpci_version vpci_versions[] = {
43 { .major = 2, .minor = 0 },
44 { .major = 1, .minor = 1 },
45};
46
47static unsigned long vatu_major = 1;
48static unsigned long vatu_minor = 1;
49
50#define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
51
52struct iommu_batch {
53 struct device *dev; /* Device mapping is for. */
54 unsigned long prot; /* IOMMU page protections */
55 unsigned long entry; /* Index into IOTSB. */
56 u64 *pglist; /* List of physical pages */
57 unsigned long npages; /* Number of pages in list. */
58};
59
60static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
61static int iommu_batch_initialized;
62
63/* Interrupts must be disabled. */
64static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
65{
66 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
67
68 p->dev = dev;
69 p->prot = prot;
70 p->entry = entry;
71 p->npages = 0;
72}
73
74/* Interrupts must be disabled. */
75static long iommu_batch_flush(struct iommu_batch *p, u64 mask)
76{
77 struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
78 u64 *pglist = p->pglist;
79 u64 index_count;
80 unsigned long devhandle = pbm->devhandle;
81 unsigned long prot = p->prot;
82 unsigned long entry = p->entry;
83 unsigned long npages = p->npages;
84 unsigned long iotsb_num;
85 unsigned long ret;
86 long num;
87
88 /* VPCI maj=1, min=[0,1] only supports read and write */
89 if (vpci_major < 2)
90 prot &= (HV_PCI_MAP_ATTR_READ | HV_PCI_MAP_ATTR_WRITE);
91
92 while (npages != 0) {
93 if (mask <= DMA_BIT_MASK(32)) {
94 num = pci_sun4v_iommu_map(devhandle,
95 HV_PCI_TSBID(0, entry),
96 npages,
97 prot,
98 __pa(pglist));
99 if (unlikely(num < 0)) {
100 pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n",
101 __func__,
102 devhandle,
103 HV_PCI_TSBID(0, entry),
104 npages, prot, __pa(pglist),
105 num);
106 return -1;
107 }
108 } else {
109 index_count = HV_PCI_IOTSB_INDEX_COUNT(npages, entry),
110 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num;
111 ret = pci_sun4v_iotsb_map(devhandle,
112 iotsb_num,
113 index_count,
114 prot,
115 __pa(pglist),
116 &num);
117 if (unlikely(ret != HV_EOK)) {
118 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n",
119 __func__,
120 devhandle, iotsb_num,
121 index_count, prot,
122 __pa(pglist), ret);
123 return -1;
124 }
125 }
126 entry += num;
127 npages -= num;
128 pglist += num;
129 }
130
131 p->entry = entry;
132 p->npages = 0;
133
134 return 0;
135}
136
137static inline void iommu_batch_new_entry(unsigned long entry, u64 mask)
138{
139 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
140
141 if (p->entry + p->npages == entry)
142 return;
143 if (p->entry != ~0UL)
144 iommu_batch_flush(p, mask);
145 p->entry = entry;
146}
147
148/* Interrupts must be disabled. */
149static inline long iommu_batch_add(u64 phys_page, u64 mask)
150{
151 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
152
153 BUG_ON(p->npages >= PGLIST_NENTS);
154
155 p->pglist[p->npages++] = phys_page;
156 if (p->npages == PGLIST_NENTS)
157 return iommu_batch_flush(p, mask);
158
159 return 0;
160}
161
162/* Interrupts must be disabled. */
163static inline long iommu_batch_end(u64 mask)
164{
165 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
166
167 BUG_ON(p->npages >= PGLIST_NENTS);
168
169 return iommu_batch_flush(p, mask);
170}
171
172static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
173 dma_addr_t *dma_addrp, gfp_t gfp,
174 unsigned long attrs)
175{
176 u64 mask;
177 unsigned long flags, order, first_page, npages, n;
178 unsigned long prot = 0;
179 struct iommu *iommu;
180 struct atu *atu;
181 struct iommu_map_table *tbl;
182 struct page *page;
183 void *ret;
184 long entry;
185 int nid;
186
187 size = IO_PAGE_ALIGN(size);
188 order = get_order(size);
189 if (unlikely(order >= MAX_ORDER))
190 return NULL;
191
192 npages = size >> IO_PAGE_SHIFT;
193
194 if (attrs & DMA_ATTR_WEAK_ORDERING)
195 prot = HV_PCI_MAP_ATTR_RELAXED_ORDER;
196
197 nid = dev->archdata.numa_node;
198 page = alloc_pages_node(nid, gfp, order);
199 if (unlikely(!page))
200 return NULL;
201
202 first_page = (unsigned long) page_address(page);
203 memset((char *)first_page, 0, PAGE_SIZE << order);
204
205 iommu = dev->archdata.iommu;
206 atu = iommu->atu;
207
208 mask = dev->coherent_dma_mask;
209 if (mask <= DMA_BIT_MASK(32))
210 tbl = &iommu->tbl;
211 else
212 tbl = &atu->tbl;
213
214 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
215 (unsigned long)(-1), 0);
216
217 if (unlikely(entry == IOMMU_ERROR_CODE))
218 goto range_alloc_fail;
219
220 *dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
221 ret = (void *) first_page;
222 first_page = __pa(first_page);
223
224 local_irq_save(flags);
225
226 iommu_batch_start(dev,
227 (HV_PCI_MAP_ATTR_READ | prot |
228 HV_PCI_MAP_ATTR_WRITE),
229 entry);
230
231 for (n = 0; n < npages; n++) {
232 long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask);
233 if (unlikely(err < 0L))
234 goto iommu_map_fail;
235 }
236
237 if (unlikely(iommu_batch_end(mask) < 0L))
238 goto iommu_map_fail;
239
240 local_irq_restore(flags);
241
242 return ret;
243
244iommu_map_fail:
245 local_irq_restore(flags);
246 iommu_tbl_range_free(tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
247
248range_alloc_fail:
249 free_pages(first_page, order);
250 return NULL;
251}
252
253unsigned long dma_4v_iotsb_bind(unsigned long devhandle,
254 unsigned long iotsb_num,
255 struct pci_bus *bus_dev)
256{
257 struct pci_dev *pdev;
258 unsigned long err;
259 unsigned int bus;
260 unsigned int device;
261 unsigned int fun;
262
263 list_for_each_entry(pdev, &bus_dev->devices, bus_list) {
264 if (pdev->subordinate) {
265 /* No need to bind pci bridge */
266 dma_4v_iotsb_bind(devhandle, iotsb_num,
267 pdev->subordinate);
268 } else {
269 bus = bus_dev->number;
270 device = PCI_SLOT(pdev->devfn);
271 fun = PCI_FUNC(pdev->devfn);
272 err = pci_sun4v_iotsb_bind(devhandle, iotsb_num,
273 HV_PCI_DEVICE_BUILD(bus,
274 device,
275 fun));
276
277 /* If bind fails for one device it is going to fail
278 * for rest of the devices because we are sharing
279 * IOTSB. So in case of failure simply return with
280 * error.
281 */
282 if (err)
283 return err;
284 }
285 }
286
287 return 0;
288}
289
290static void dma_4v_iommu_demap(struct device *dev, unsigned long devhandle,
291 dma_addr_t dvma, unsigned long iotsb_num,
292 unsigned long entry, unsigned long npages)
293{
294 unsigned long num, flags;
295 unsigned long ret;
296
297 local_irq_save(flags);
298 do {
299 if (dvma <= DMA_BIT_MASK(32)) {
300 num = pci_sun4v_iommu_demap(devhandle,
301 HV_PCI_TSBID(0, entry),
302 npages);
303 } else {
304 ret = pci_sun4v_iotsb_demap(devhandle, iotsb_num,
305 entry, npages, &num);
306 if (unlikely(ret != HV_EOK)) {
307 pr_err_ratelimited("pci_iotsb_demap() failed with error: %ld\n",
308 ret);
309 }
310 }
311 entry += num;
312 npages -= num;
313 } while (npages != 0);
314 local_irq_restore(flags);
315}
316
317static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
318 dma_addr_t dvma, unsigned long attrs)
319{
320 struct pci_pbm_info *pbm;
321 struct iommu *iommu;
322 struct atu *atu;
323 struct iommu_map_table *tbl;
324 unsigned long order, npages, entry;
325 unsigned long iotsb_num;
326 u32 devhandle;
327
328 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
329 iommu = dev->archdata.iommu;
330 pbm = dev->archdata.host_controller;
331 atu = iommu->atu;
332 devhandle = pbm->devhandle;
333
334 if (dvma <= DMA_BIT_MASK(32)) {
335 tbl = &iommu->tbl;
336 iotsb_num = 0; /* we don't care for legacy iommu */
337 } else {
338 tbl = &atu->tbl;
339 iotsb_num = atu->iotsb->iotsb_num;
340 }
341 entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT);
342 dma_4v_iommu_demap(dev, devhandle, dvma, iotsb_num, entry, npages);
343 iommu_tbl_range_free(tbl, dvma, npages, IOMMU_ERROR_CODE);
344 order = get_order(size);
345 if (order < 10)
346 free_pages((unsigned long)cpu, order);
347}
348
349static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
350 unsigned long offset, size_t sz,
351 enum dma_data_direction direction,
352 unsigned long attrs)
353{
354 struct iommu *iommu;
355 struct atu *atu;
356 struct iommu_map_table *tbl;
357 u64 mask;
358 unsigned long flags, npages, oaddr;
359 unsigned long i, base_paddr;
360 unsigned long prot;
361 dma_addr_t bus_addr, ret;
362 long entry;
363
364 iommu = dev->archdata.iommu;
365 atu = iommu->atu;
366
367 if (unlikely(direction == DMA_NONE))
368 goto bad;
369
370 oaddr = (unsigned long)(page_address(page) + offset);
371 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
372 npages >>= IO_PAGE_SHIFT;
373
374 mask = *dev->dma_mask;
375 if (mask <= DMA_BIT_MASK(32))
376 tbl = &iommu->tbl;
377 else
378 tbl = &atu->tbl;
379
380 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
381 (unsigned long)(-1), 0);
382
383 if (unlikely(entry == IOMMU_ERROR_CODE))
384 goto bad;
385
386 bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
387 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
388 base_paddr = __pa(oaddr & IO_PAGE_MASK);
389 prot = HV_PCI_MAP_ATTR_READ;
390 if (direction != DMA_TO_DEVICE)
391 prot |= HV_PCI_MAP_ATTR_WRITE;
392
393 if (attrs & DMA_ATTR_WEAK_ORDERING)
394 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
395
396 local_irq_save(flags);
397
398 iommu_batch_start(dev, prot, entry);
399
400 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
401 long err = iommu_batch_add(base_paddr, mask);
402 if (unlikely(err < 0L))
403 goto iommu_map_fail;
404 }
405 if (unlikely(iommu_batch_end(mask) < 0L))
406 goto iommu_map_fail;
407
408 local_irq_restore(flags);
409
410 return ret;
411
412bad:
413 if (printk_ratelimit())
414 WARN_ON(1);
415 return DMA_ERROR_CODE;
416
417iommu_map_fail:
418 local_irq_restore(flags);
419 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
420 return DMA_ERROR_CODE;
421}
422
423static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
424 size_t sz, enum dma_data_direction direction,
425 unsigned long attrs)
426{
427 struct pci_pbm_info *pbm;
428 struct iommu *iommu;
429 struct atu *atu;
430 struct iommu_map_table *tbl;
431 unsigned long npages;
432 unsigned long iotsb_num;
433 long entry;
434 u32 devhandle;
435
436 if (unlikely(direction == DMA_NONE)) {
437 if (printk_ratelimit())
438 WARN_ON(1);
439 return;
440 }
441
442 iommu = dev->archdata.iommu;
443 pbm = dev->archdata.host_controller;
444 atu = iommu->atu;
445 devhandle = pbm->devhandle;
446
447 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
448 npages >>= IO_PAGE_SHIFT;
449 bus_addr &= IO_PAGE_MASK;
450
451 if (bus_addr <= DMA_BIT_MASK(32)) {
452 iotsb_num = 0; /* we don't care for legacy iommu */
453 tbl = &iommu->tbl;
454 } else {
455 iotsb_num = atu->iotsb->iotsb_num;
456 tbl = &atu->tbl;
457 }
458 entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT;
459 dma_4v_iommu_demap(dev, devhandle, bus_addr, iotsb_num, entry, npages);
460 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
461}
462
463static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
464 int nelems, enum dma_data_direction direction,
465 unsigned long attrs)
466{
467 struct scatterlist *s, *outs, *segstart;
468 unsigned long flags, handle, prot;
469 dma_addr_t dma_next = 0, dma_addr;
470 unsigned int max_seg_size;
471 unsigned long seg_boundary_size;
472 int outcount, incount, i;
473 struct iommu *iommu;
474 struct atu *atu;
475 struct iommu_map_table *tbl;
476 u64 mask;
477 unsigned long base_shift;
478 long err;
479
480 BUG_ON(direction == DMA_NONE);
481
482 iommu = dev->archdata.iommu;
483 if (nelems == 0 || !iommu)
484 return 0;
485 atu = iommu->atu;
486
487 prot = HV_PCI_MAP_ATTR_READ;
488 if (direction != DMA_TO_DEVICE)
489 prot |= HV_PCI_MAP_ATTR_WRITE;
490
491 if (attrs & DMA_ATTR_WEAK_ORDERING)
492 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
493
494 outs = s = segstart = &sglist[0];
495 outcount = 1;
496 incount = nelems;
497 handle = 0;
498
499 /* Init first segment length for backout at failure */
500 outs->dma_length = 0;
501
502 local_irq_save(flags);
503
504 iommu_batch_start(dev, prot, ~0UL);
505
506 max_seg_size = dma_get_max_seg_size(dev);
507 seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
508 IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
509
510 mask = *dev->dma_mask;
511 if (mask <= DMA_BIT_MASK(32))
512 tbl = &iommu->tbl;
513 else
514 tbl = &atu->tbl;
515
516 base_shift = tbl->table_map_base >> IO_PAGE_SHIFT;
517
518 for_each_sg(sglist, s, nelems, i) {
519 unsigned long paddr, npages, entry, out_entry = 0, slen;
520
521 slen = s->length;
522 /* Sanity check */
523 if (slen == 0) {
524 dma_next = 0;
525 continue;
526 }
527 /* Allocate iommu entries for that segment */
528 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
529 npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
530 entry = iommu_tbl_range_alloc(dev, tbl, npages,
531 &handle, (unsigned long)(-1), 0);
532
533 /* Handle failure */
534 if (unlikely(entry == IOMMU_ERROR_CODE)) {
535 pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n",
536 tbl, paddr, npages);
537 goto iommu_map_failed;
538 }
539
540 iommu_batch_new_entry(entry, mask);
541
542 /* Convert entry to a dma_addr_t */
543 dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT);
544 dma_addr |= (s->offset & ~IO_PAGE_MASK);
545
546 /* Insert into HW table */
547 paddr &= IO_PAGE_MASK;
548 while (npages--) {
549 err = iommu_batch_add(paddr, mask);
550 if (unlikely(err < 0L))
551 goto iommu_map_failed;
552 paddr += IO_PAGE_SIZE;
553 }
554
555 /* If we are in an open segment, try merging */
556 if (segstart != s) {
557 /* We cannot merge if:
558 * - allocated dma_addr isn't contiguous to previous allocation
559 */
560 if ((dma_addr != dma_next) ||
561 (outs->dma_length + s->length > max_seg_size) ||
562 (is_span_boundary(out_entry, base_shift,
563 seg_boundary_size, outs, s))) {
564 /* Can't merge: create a new segment */
565 segstart = s;
566 outcount++;
567 outs = sg_next(outs);
568 } else {
569 outs->dma_length += s->length;
570 }
571 }
572
573 if (segstart == s) {
574 /* This is a new segment, fill entries */
575 outs->dma_address = dma_addr;
576 outs->dma_length = slen;
577 out_entry = entry;
578 }
579
580 /* Calculate next page pointer for contiguous check */
581 dma_next = dma_addr + slen;
582 }
583
584 err = iommu_batch_end(mask);
585
586 if (unlikely(err < 0L))
587 goto iommu_map_failed;
588
589 local_irq_restore(flags);
590
591 if (outcount < incount) {
592 outs = sg_next(outs);
593 outs->dma_address = DMA_ERROR_CODE;
594 outs->dma_length = 0;
595 }
596
597 return outcount;
598
599iommu_map_failed:
600 for_each_sg(sglist, s, nelems, i) {
601 if (s->dma_length != 0) {
602 unsigned long vaddr, npages;
603
604 vaddr = s->dma_address & IO_PAGE_MASK;
605 npages = iommu_num_pages(s->dma_address, s->dma_length,
606 IO_PAGE_SIZE);
607 iommu_tbl_range_free(tbl, vaddr, npages,
608 IOMMU_ERROR_CODE);
609 /* XXX demap? XXX */
610 s->dma_address = DMA_ERROR_CODE;
611 s->dma_length = 0;
612 }
613 if (s == outs)
614 break;
615 }
616 local_irq_restore(flags);
617
618 return 0;
619}
620
621static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
622 int nelems, enum dma_data_direction direction,
623 unsigned long attrs)
624{
625 struct pci_pbm_info *pbm;
626 struct scatterlist *sg;
627 struct iommu *iommu;
628 struct atu *atu;
629 unsigned long flags, entry;
630 unsigned long iotsb_num;
631 u32 devhandle;
632
633 BUG_ON(direction == DMA_NONE);
634
635 iommu = dev->archdata.iommu;
636 pbm = dev->archdata.host_controller;
637 atu = iommu->atu;
638 devhandle = pbm->devhandle;
639
640 local_irq_save(flags);
641
642 sg = sglist;
643 while (nelems--) {
644 dma_addr_t dma_handle = sg->dma_address;
645 unsigned int len = sg->dma_length;
646 unsigned long npages;
647 struct iommu_map_table *tbl;
648 unsigned long shift = IO_PAGE_SHIFT;
649
650 if (!len)
651 break;
652 npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
653
654 if (dma_handle <= DMA_BIT_MASK(32)) {
655 iotsb_num = 0; /* we don't care for legacy iommu */
656 tbl = &iommu->tbl;
657 } else {
658 iotsb_num = atu->iotsb->iotsb_num;
659 tbl = &atu->tbl;
660 }
661 entry = ((dma_handle - tbl->table_map_base) >> shift);
662 dma_4v_iommu_demap(dev, devhandle, dma_handle, iotsb_num,
663 entry, npages);
664 iommu_tbl_range_free(tbl, dma_handle, npages,
665 IOMMU_ERROR_CODE);
666 sg = sg_next(sg);
667 }
668
669 local_irq_restore(flags);
670}
671
672static struct dma_map_ops sun4v_dma_ops = {
673 .alloc = dma_4v_alloc_coherent,
674 .free = dma_4v_free_coherent,
675 .map_page = dma_4v_map_page,
676 .unmap_page = dma_4v_unmap_page,
677 .map_sg = dma_4v_map_sg,
678 .unmap_sg = dma_4v_unmap_sg,
679};
680
681static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
682{
683 struct property *prop;
684 struct device_node *dp;
685
686 dp = pbm->op->dev.of_node;
687 prop = of_find_property(dp, "66mhz-capable", NULL);
688 pbm->is_66mhz_capable = (prop != NULL);
689 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
690
691 /* XXX register error interrupt handlers XXX */
692}
693
694static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
695 struct iommu_map_table *iommu)
696{
697 struct iommu_pool *pool;
698 unsigned long i, pool_nr, cnt = 0;
699 u32 devhandle;
700
701 devhandle = pbm->devhandle;
702 for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) {
703 pool = &(iommu->pools[pool_nr]);
704 for (i = pool->start; i <= pool->end; i++) {
705 unsigned long ret, io_attrs, ra;
706
707 ret = pci_sun4v_iommu_getmap(devhandle,
708 HV_PCI_TSBID(0, i),
709 &io_attrs, &ra);
710 if (ret == HV_EOK) {
711 if (page_in_phys_avail(ra)) {
712 pci_sun4v_iommu_demap(devhandle,
713 HV_PCI_TSBID(0,
714 i), 1);
715 } else {
716 cnt++;
717 __set_bit(i, iommu->map);
718 }
719 }
720 }
721 }
722 return cnt;
723}
724
725static int pci_sun4v_atu_alloc_iotsb(struct pci_pbm_info *pbm)
726{
727 struct atu *atu = pbm->iommu->atu;
728 struct atu_iotsb *iotsb;
729 void *table;
730 u64 table_size;
731 u64 iotsb_num;
732 unsigned long order;
733 unsigned long err;
734
735 iotsb = kzalloc(sizeof(*iotsb), GFP_KERNEL);
736 if (!iotsb) {
737 err = -ENOMEM;
738 goto out_err;
739 }
740 atu->iotsb = iotsb;
741
742 /* calculate size of IOTSB */
743 table_size = (atu->size / IO_PAGE_SIZE) * 8;
744 order = get_order(table_size);
745 table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
746 if (!table) {
747 err = -ENOMEM;
748 goto table_failed;
749 }
750 iotsb->table = table;
751 iotsb->ra = __pa(table);
752 iotsb->dvma_size = atu->size;
753 iotsb->dvma_base = atu->base;
754 iotsb->table_size = table_size;
755 iotsb->page_size = IO_PAGE_SIZE;
756
757 /* configure and register IOTSB with HV */
758 err = pci_sun4v_iotsb_conf(pbm->devhandle,
759 iotsb->ra,
760 iotsb->table_size,
761 iotsb->page_size,
762 iotsb->dvma_base,
763 &iotsb_num);
764 if (err) {
765 pr_err(PFX "pci_iotsb_conf failed error: %ld\n", err);
766 goto iotsb_conf_failed;
767 }
768 iotsb->iotsb_num = iotsb_num;
769
770 err = dma_4v_iotsb_bind(pbm->devhandle, iotsb_num, pbm->pci_bus);
771 if (err) {
772 pr_err(PFX "pci_iotsb_bind failed error: %ld\n", err);
773 goto iotsb_conf_failed;
774 }
775
776 return 0;
777
778iotsb_conf_failed:
779 free_pages((unsigned long)table, order);
780table_failed:
781 kfree(iotsb);
782out_err:
783 return err;
784}
785
786static int pci_sun4v_atu_init(struct pci_pbm_info *pbm)
787{
788 struct atu *atu = pbm->iommu->atu;
789 unsigned long err;
790 const u64 *ranges;
791 u64 map_size, num_iotte;
792 u64 dma_mask;
793 const u32 *page_size;
794 int len;
795
796 ranges = of_get_property(pbm->op->dev.of_node, "iommu-address-ranges",
797 &len);
798 if (!ranges) {
799 pr_err(PFX "No iommu-address-ranges\n");
800 return -EINVAL;
801 }
802
803 page_size = of_get_property(pbm->op->dev.of_node, "iommu-pagesizes",
804 NULL);
805 if (!page_size) {
806 pr_err(PFX "No iommu-pagesizes\n");
807 return -EINVAL;
808 }
809
810 /* There are 4 iommu-address-ranges supported. Each range is pair of
811 * {base, size}. The ranges[0] and ranges[1] are 32bit address space
812 * while ranges[2] and ranges[3] are 64bit space. We want to use 64bit
813 * address ranges to support 64bit addressing. Because 'size' for
814 * address ranges[2] and ranges[3] are same we can select either of
815 * ranges[2] or ranges[3] for mapping. However due to 'size' is too
816 * large for OS to allocate IOTSB we are using fix size 32G
817 * (ATU_64_SPACE_SIZE) which is more than enough for all PCIe devices
818 * to share.
819 */
820 atu->ranges = (struct atu_ranges *)ranges;
821 atu->base = atu->ranges[3].base;
822 atu->size = ATU_64_SPACE_SIZE;
823
824 /* Create IOTSB */
825 err = pci_sun4v_atu_alloc_iotsb(pbm);
826 if (err) {
827 pr_err(PFX "Error creating ATU IOTSB\n");
828 return err;
829 }
830
831 /* Create ATU iommu map.
832 * One bit represents one iotte in IOTSB table.
833 */
834 dma_mask = (roundup_pow_of_two(atu->size) - 1UL);
835 num_iotte = atu->size / IO_PAGE_SIZE;
836 map_size = num_iotte / 8;
837 atu->tbl.table_map_base = atu->base;
838 atu->dma_addr_mask = dma_mask;
839 atu->tbl.map = kzalloc(map_size, GFP_KERNEL);
840 if (!atu->tbl.map)
841 return -ENOMEM;
842
843 iommu_tbl_pool_init(&atu->tbl, num_iotte, IO_PAGE_SHIFT,
844 NULL, false /* no large_pool */,
845 0 /* default npools */,
846 false /* want span boundary checking */);
847
848 return 0;
849}
850
851static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
852{
853 static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
854 struct iommu *iommu = pbm->iommu;
855 unsigned long num_tsb_entries, sz;
856 u32 dma_mask, dma_offset;
857 const u32 *vdma;
858
859 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
860 if (!vdma)
861 vdma = vdma_default;
862
863 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
864 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
865 vdma[0], vdma[1]);
866 return -EINVAL;
867 }
868
869 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
870 num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
871
872 dma_offset = vdma[0];
873
874 /* Setup initial software IOMMU state. */
875 spin_lock_init(&iommu->lock);
876 iommu->ctx_lowest_free = 1;
877 iommu->tbl.table_map_base = dma_offset;
878 iommu->dma_addr_mask = dma_mask;
879
880 /* Allocate and initialize the free area map. */
881 sz = (num_tsb_entries + 7) / 8;
882 sz = (sz + 7UL) & ~7UL;
883 iommu->tbl.map = kzalloc(sz, GFP_KERNEL);
884 if (!iommu->tbl.map) {
885 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
886 return -ENOMEM;
887 }
888 iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
889 NULL, false /* no large_pool */,
890 0 /* default npools */,
891 false /* want span boundary checking */);
892 sz = probe_existing_entries(pbm, &iommu->tbl);
893 if (sz)
894 printk("%s: Imported %lu TSB entries from OBP\n",
895 pbm->name, sz);
896
897 return 0;
898}
899
900#ifdef CONFIG_PCI_MSI
901struct pci_sun4v_msiq_entry {
902 u64 version_type;
903#define MSIQ_VERSION_MASK 0xffffffff00000000UL
904#define MSIQ_VERSION_SHIFT 32
905#define MSIQ_TYPE_MASK 0x00000000000000ffUL
906#define MSIQ_TYPE_SHIFT 0
907#define MSIQ_TYPE_NONE 0x00
908#define MSIQ_TYPE_MSG 0x01
909#define MSIQ_TYPE_MSI32 0x02
910#define MSIQ_TYPE_MSI64 0x03
911#define MSIQ_TYPE_INTX 0x08
912#define MSIQ_TYPE_NONE2 0xff
913
914 u64 intx_sysino;
915 u64 reserved1;
916 u64 stick;
917 u64 req_id; /* bus/device/func */
918#define MSIQ_REQID_BUS_MASK 0xff00UL
919#define MSIQ_REQID_BUS_SHIFT 8
920#define MSIQ_REQID_DEVICE_MASK 0x00f8UL
921#define MSIQ_REQID_DEVICE_SHIFT 3
922#define MSIQ_REQID_FUNC_MASK 0x0007UL
923#define MSIQ_REQID_FUNC_SHIFT 0
924
925 u64 msi_address;
926
927 /* The format of this value is message type dependent.
928 * For MSI bits 15:0 are the data from the MSI packet.
929 * For MSI-X bits 31:0 are the data from the MSI packet.
930 * For MSG, the message code and message routing code where:
931 * bits 39:32 is the bus/device/fn of the msg target-id
932 * bits 18:16 is the message routing code
933 * bits 7:0 is the message code
934 * For INTx the low order 2-bits are:
935 * 00 - INTA
936 * 01 - INTB
937 * 10 - INTC
938 * 11 - INTD
939 */
940 u64 msi_data;
941
942 u64 reserved2;
943};
944
945static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
946 unsigned long *head)
947{
948 unsigned long err, limit;
949
950 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
951 if (unlikely(err))
952 return -ENXIO;
953
954 limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
955 if (unlikely(*head >= limit))
956 return -EFBIG;
957
958 return 0;
959}
960
961static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
962 unsigned long msiqid, unsigned long *head,
963 unsigned long *msi)
964{
965 struct pci_sun4v_msiq_entry *ep;
966 unsigned long err, type;
967
968 /* Note: void pointer arithmetic, 'head' is a byte offset */
969 ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
970 (pbm->msiq_ent_count *
971 sizeof(struct pci_sun4v_msiq_entry))) +
972 *head);
973
974 if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
975 return 0;
976
977 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
978 if (unlikely(type != MSIQ_TYPE_MSI32 &&
979 type != MSIQ_TYPE_MSI64))
980 return -EINVAL;
981
982 *msi = ep->msi_data;
983
984 err = pci_sun4v_msi_setstate(pbm->devhandle,
985 ep->msi_data /* msi_num */,
986 HV_MSISTATE_IDLE);
987 if (unlikely(err))
988 return -ENXIO;
989
990 /* Clear the entry. */
991 ep->version_type &= ~MSIQ_TYPE_MASK;
992
993 (*head) += sizeof(struct pci_sun4v_msiq_entry);
994 if (*head >=
995 (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
996 *head = 0;
997
998 return 1;
999}
1000
1001static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
1002 unsigned long head)
1003{
1004 unsigned long err;
1005
1006 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
1007 if (unlikely(err))
1008 return -EINVAL;
1009
1010 return 0;
1011}
1012
1013static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
1014 unsigned long msi, int is_msi64)
1015{
1016 if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
1017 (is_msi64 ?
1018 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
1019 return -ENXIO;
1020 if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
1021 return -ENXIO;
1022 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
1023 return -ENXIO;
1024 return 0;
1025}
1026
1027static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
1028{
1029 unsigned long err, msiqid;
1030
1031 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
1032 if (err)
1033 return -ENXIO;
1034
1035 pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
1036
1037 return 0;
1038}
1039
1040static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
1041{
1042 unsigned long q_size, alloc_size, pages, order;
1043 int i;
1044
1045 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1046 alloc_size = (pbm->msiq_num * q_size);
1047 order = get_order(alloc_size);
1048 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
1049 if (pages == 0UL) {
1050 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
1051 order);
1052 return -ENOMEM;
1053 }
1054 memset((char *)pages, 0, PAGE_SIZE << order);
1055 pbm->msi_queues = (void *) pages;
1056
1057 for (i = 0; i < pbm->msiq_num; i++) {
1058 unsigned long err, base = __pa(pages + (i * q_size));
1059 unsigned long ret1, ret2;
1060
1061 err = pci_sun4v_msiq_conf(pbm->devhandle,
1062 pbm->msiq_first + i,
1063 base, pbm->msiq_ent_count);
1064 if (err) {
1065 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
1066 err);
1067 goto h_error;
1068 }
1069
1070 err = pci_sun4v_msiq_info(pbm->devhandle,
1071 pbm->msiq_first + i,
1072 &ret1, &ret2);
1073 if (err) {
1074 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
1075 err);
1076 goto h_error;
1077 }
1078 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
1079 printk(KERN_ERR "MSI: Bogus qconf "
1080 "expected[%lx:%x] got[%lx:%lx]\n",
1081 base, pbm->msiq_ent_count,
1082 ret1, ret2);
1083 goto h_error;
1084 }
1085 }
1086
1087 return 0;
1088
1089h_error:
1090 free_pages(pages, order);
1091 return -EINVAL;
1092}
1093
1094static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
1095{
1096 unsigned long q_size, alloc_size, pages, order;
1097 int i;
1098
1099 for (i = 0; i < pbm->msiq_num; i++) {
1100 unsigned long msiqid = pbm->msiq_first + i;
1101
1102 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
1103 }
1104
1105 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1106 alloc_size = (pbm->msiq_num * q_size);
1107 order = get_order(alloc_size);
1108
1109 pages = (unsigned long) pbm->msi_queues;
1110
1111 free_pages(pages, order);
1112
1113 pbm->msi_queues = NULL;
1114}
1115
1116static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
1117 unsigned long msiqid,
1118 unsigned long devino)
1119{
1120 unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
1121
1122 if (!irq)
1123 return -ENOMEM;
1124
1125 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
1126 return -EINVAL;
1127 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
1128 return -EINVAL;
1129
1130 return irq;
1131}
1132
1133static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
1134 .get_head = pci_sun4v_get_head,
1135 .dequeue_msi = pci_sun4v_dequeue_msi,
1136 .set_head = pci_sun4v_set_head,
1137 .msi_setup = pci_sun4v_msi_setup,
1138 .msi_teardown = pci_sun4v_msi_teardown,
1139 .msiq_alloc = pci_sun4v_msiq_alloc,
1140 .msiq_free = pci_sun4v_msiq_free,
1141 .msiq_build_irq = pci_sun4v_msiq_build_irq,
1142};
1143
1144static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1145{
1146 sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
1147}
1148#else /* CONFIG_PCI_MSI */
1149static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1150{
1151}
1152#endif /* !(CONFIG_PCI_MSI) */
1153
1154static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
1155 struct platform_device *op, u32 devhandle)
1156{
1157 struct device_node *dp = op->dev.of_node;
1158 int err;
1159
1160 pbm->numa_node = of_node_to_nid(dp);
1161
1162 pbm->pci_ops = &sun4v_pci_ops;
1163 pbm->config_space_reg_bits = 12;
1164
1165 pbm->index = pci_num_pbms++;
1166
1167 pbm->op = op;
1168
1169 pbm->devhandle = devhandle;
1170
1171 pbm->name = dp->full_name;
1172
1173 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1174 printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
1175
1176 pci_determine_mem_io_space(pbm);
1177
1178 pci_get_pbm_props(pbm);
1179
1180 err = pci_sun4v_iommu_init(pbm);
1181 if (err)
1182 return err;
1183
1184 pci_sun4v_msi_init(pbm);
1185
1186 pci_sun4v_scan_bus(pbm, &op->dev);
1187
1188 /* if atu_init fails its not complete failure.
1189 * we can still continue using legacy iommu.
1190 */
1191 if (pbm->iommu->atu) {
1192 err = pci_sun4v_atu_init(pbm);
1193 if (err) {
1194 kfree(pbm->iommu->atu);
1195 pbm->iommu->atu = NULL;
1196 pr_err(PFX "ATU init failed, err=%d\n", err);
1197 }
1198 }
1199
1200 pbm->next = pci_pbm_root;
1201 pci_pbm_root = pbm;
1202
1203 return 0;
1204}
1205
1206static int pci_sun4v_probe(struct platform_device *op)
1207{
1208 const struct linux_prom64_registers *regs;
1209 static int hvapi_negotiated = 0;
1210 struct pci_pbm_info *pbm;
1211 struct device_node *dp;
1212 struct iommu *iommu;
1213 struct atu *atu;
1214 u32 devhandle;
1215 int i, err = -ENODEV;
1216 static bool hv_atu = true;
1217
1218 dp = op->dev.of_node;
1219
1220 if (!hvapi_negotiated++) {
1221 for (i = 0; i < ARRAY_SIZE(vpci_versions); i++) {
1222 vpci_major = vpci_versions[i].major;
1223 vpci_minor = vpci_versions[i].minor;
1224
1225 err = sun4v_hvapi_register(HV_GRP_PCI, vpci_major,
1226 &vpci_minor);
1227 if (!err)
1228 break;
1229 }
1230
1231 if (err) {
1232 pr_err(PFX "Could not register hvapi, err=%d\n", err);
1233 return err;
1234 }
1235 pr_info(PFX "Registered hvapi major[%lu] minor[%lu]\n",
1236 vpci_major, vpci_minor);
1237
1238 err = sun4v_hvapi_register(HV_GRP_ATU, vatu_major, &vatu_minor);
1239 if (err) {
1240 /* don't return an error if we fail to register the
1241 * ATU group, but ATU hcalls won't be available.
1242 */
1243 hv_atu = false;
1244 pr_err(PFX "Could not register hvapi ATU err=%d\n",
1245 err);
1246 } else {
1247 pr_info(PFX "Registered hvapi ATU major[%lu] minor[%lu]\n",
1248 vatu_major, vatu_minor);
1249 }
1250
1251 dma_ops = &sun4v_dma_ops;
1252 }
1253
1254 regs = of_get_property(dp, "reg", NULL);
1255 err = -ENODEV;
1256 if (!regs) {
1257 printk(KERN_ERR PFX "Could not find config registers\n");
1258 goto out_err;
1259 }
1260 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1261
1262 err = -ENOMEM;
1263 if (!iommu_batch_initialized) {
1264 for_each_possible_cpu(i) {
1265 unsigned long page = get_zeroed_page(GFP_KERNEL);
1266
1267 if (!page)
1268 goto out_err;
1269
1270 per_cpu(iommu_batch, i).pglist = (u64 *) page;
1271 }
1272 iommu_batch_initialized = 1;
1273 }
1274
1275 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1276 if (!pbm) {
1277 printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
1278 goto out_err;
1279 }
1280
1281 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1282 if (!iommu) {
1283 printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
1284 goto out_free_controller;
1285 }
1286
1287 pbm->iommu = iommu;
1288 iommu->atu = NULL;
1289 if (hv_atu) {
1290 atu = kzalloc(sizeof(*atu), GFP_KERNEL);
1291 if (!atu)
1292 pr_err(PFX "Could not allocate atu\n");
1293 else
1294 iommu->atu = atu;
1295 }
1296
1297 err = pci_sun4v_pbm_init(pbm, op, devhandle);
1298 if (err)
1299 goto out_free_iommu;
1300
1301 dev_set_drvdata(&op->dev, pbm);
1302
1303 return 0;
1304
1305out_free_iommu:
1306 kfree(iommu->atu);
1307 kfree(pbm->iommu);
1308
1309out_free_controller:
1310 kfree(pbm);
1311
1312out_err:
1313 return err;
1314}
1315
1316static const struct of_device_id pci_sun4v_match[] = {
1317 {
1318 .name = "pci",
1319 .compatible = "SUNW,sun4v-pci",
1320 },
1321 {},
1322};
1323
1324static struct platform_driver pci_sun4v_driver = {
1325 .driver = {
1326 .name = DRIVER_NAME,
1327 .of_match_table = pci_sun4v_match,
1328 },
1329 .probe = pci_sun4v_probe,
1330};
1331
1332static int __init pci_sun4v_init(void)
1333{
1334 return platform_driver_register(&pci_sun4v_driver);
1335}
1336
1337subsys_initcall(pci_sun4v_init);
1/* pci_sun4v.c: SUN4V specific PCI controller support.
2 *
3 * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/pci.h>
9#include <linux/init.h>
10#include <linux/slab.h>
11#include <linux/interrupt.h>
12#include <linux/percpu.h>
13#include <linux/irq.h>
14#include <linux/msi.h>
15#include <linux/log2.h>
16#include <linux/of_device.h>
17
18#include <asm/iommu.h>
19#include <asm/irq.h>
20#include <asm/hypervisor.h>
21#include <asm/prom.h>
22
23#include "pci_impl.h"
24#include "iommu_common.h"
25
26#include "pci_sun4v.h"
27
28#define DRIVER_NAME "pci_sun4v"
29#define PFX DRIVER_NAME ": "
30
31static unsigned long vpci_major = 1;
32static unsigned long vpci_minor = 1;
33
34#define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
35
36struct iommu_batch {
37 struct device *dev; /* Device mapping is for. */
38 unsigned long prot; /* IOMMU page protections */
39 unsigned long entry; /* Index into IOTSB. */
40 u64 *pglist; /* List of physical pages */
41 unsigned long npages; /* Number of pages in list. */
42};
43
44static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
45static int iommu_batch_initialized;
46
47/* Interrupts must be disabled. */
48static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
49{
50 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
51
52 p->dev = dev;
53 p->prot = prot;
54 p->entry = entry;
55 p->npages = 0;
56}
57
58/* Interrupts must be disabled. */
59static long iommu_batch_flush(struct iommu_batch *p)
60{
61 struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
62 unsigned long devhandle = pbm->devhandle;
63 unsigned long prot = p->prot;
64 unsigned long entry = p->entry;
65 u64 *pglist = p->pglist;
66 unsigned long npages = p->npages;
67
68 while (npages != 0) {
69 long num;
70
71 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
72 npages, prot, __pa(pglist));
73 if (unlikely(num < 0)) {
74 if (printk_ratelimit())
75 printk("iommu_batch_flush: IOMMU map of "
76 "[%08lx:%08llx:%lx:%lx:%lx] failed with "
77 "status %ld\n",
78 devhandle, HV_PCI_TSBID(0, entry),
79 npages, prot, __pa(pglist), num);
80 return -1;
81 }
82
83 entry += num;
84 npages -= num;
85 pglist += num;
86 }
87
88 p->entry = entry;
89 p->npages = 0;
90
91 return 0;
92}
93
94static inline void iommu_batch_new_entry(unsigned long entry)
95{
96 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
97
98 if (p->entry + p->npages == entry)
99 return;
100 if (p->entry != ~0UL)
101 iommu_batch_flush(p);
102 p->entry = entry;
103}
104
105/* Interrupts must be disabled. */
106static inline long iommu_batch_add(u64 phys_page)
107{
108 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
109
110 BUG_ON(p->npages >= PGLIST_NENTS);
111
112 p->pglist[p->npages++] = phys_page;
113 if (p->npages == PGLIST_NENTS)
114 return iommu_batch_flush(p);
115
116 return 0;
117}
118
119/* Interrupts must be disabled. */
120static inline long iommu_batch_end(void)
121{
122 struct iommu_batch *p = &__get_cpu_var(iommu_batch);
123
124 BUG_ON(p->npages >= PGLIST_NENTS);
125
126 return iommu_batch_flush(p);
127}
128
129static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
130 dma_addr_t *dma_addrp, gfp_t gfp)
131{
132 unsigned long flags, order, first_page, npages, n;
133 struct iommu *iommu;
134 struct page *page;
135 void *ret;
136 long entry;
137 int nid;
138
139 size = IO_PAGE_ALIGN(size);
140 order = get_order(size);
141 if (unlikely(order >= MAX_ORDER))
142 return NULL;
143
144 npages = size >> IO_PAGE_SHIFT;
145
146 nid = dev->archdata.numa_node;
147 page = alloc_pages_node(nid, gfp, order);
148 if (unlikely(!page))
149 return NULL;
150
151 first_page = (unsigned long) page_address(page);
152 memset((char *)first_page, 0, PAGE_SIZE << order);
153
154 iommu = dev->archdata.iommu;
155
156 spin_lock_irqsave(&iommu->lock, flags);
157 entry = iommu_range_alloc(dev, iommu, npages, NULL);
158 spin_unlock_irqrestore(&iommu->lock, flags);
159
160 if (unlikely(entry == DMA_ERROR_CODE))
161 goto range_alloc_fail;
162
163 *dma_addrp = (iommu->page_table_map_base +
164 (entry << IO_PAGE_SHIFT));
165 ret = (void *) first_page;
166 first_page = __pa(first_page);
167
168 local_irq_save(flags);
169
170 iommu_batch_start(dev,
171 (HV_PCI_MAP_ATTR_READ |
172 HV_PCI_MAP_ATTR_WRITE),
173 entry);
174
175 for (n = 0; n < npages; n++) {
176 long err = iommu_batch_add(first_page + (n * PAGE_SIZE));
177 if (unlikely(err < 0L))
178 goto iommu_map_fail;
179 }
180
181 if (unlikely(iommu_batch_end() < 0L))
182 goto iommu_map_fail;
183
184 local_irq_restore(flags);
185
186 return ret;
187
188iommu_map_fail:
189 /* Interrupts are disabled. */
190 spin_lock(&iommu->lock);
191 iommu_range_free(iommu, *dma_addrp, npages);
192 spin_unlock_irqrestore(&iommu->lock, flags);
193
194range_alloc_fail:
195 free_pages(first_page, order);
196 return NULL;
197}
198
199static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
200 dma_addr_t dvma)
201{
202 struct pci_pbm_info *pbm;
203 struct iommu *iommu;
204 unsigned long flags, order, npages, entry;
205 u32 devhandle;
206
207 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
208 iommu = dev->archdata.iommu;
209 pbm = dev->archdata.host_controller;
210 devhandle = pbm->devhandle;
211 entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
212
213 spin_lock_irqsave(&iommu->lock, flags);
214
215 iommu_range_free(iommu, dvma, npages);
216
217 do {
218 unsigned long num;
219
220 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
221 npages);
222 entry += num;
223 npages -= num;
224 } while (npages != 0);
225
226 spin_unlock_irqrestore(&iommu->lock, flags);
227
228 order = get_order(size);
229 if (order < 10)
230 free_pages((unsigned long)cpu, order);
231}
232
233static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
234 unsigned long offset, size_t sz,
235 enum dma_data_direction direction,
236 struct dma_attrs *attrs)
237{
238 struct iommu *iommu;
239 unsigned long flags, npages, oaddr;
240 unsigned long i, base_paddr;
241 u32 bus_addr, ret;
242 unsigned long prot;
243 long entry;
244
245 iommu = dev->archdata.iommu;
246
247 if (unlikely(direction == DMA_NONE))
248 goto bad;
249
250 oaddr = (unsigned long)(page_address(page) + offset);
251 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
252 npages >>= IO_PAGE_SHIFT;
253
254 spin_lock_irqsave(&iommu->lock, flags);
255 entry = iommu_range_alloc(dev, iommu, npages, NULL);
256 spin_unlock_irqrestore(&iommu->lock, flags);
257
258 if (unlikely(entry == DMA_ERROR_CODE))
259 goto bad;
260
261 bus_addr = (iommu->page_table_map_base +
262 (entry << IO_PAGE_SHIFT));
263 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
264 base_paddr = __pa(oaddr & IO_PAGE_MASK);
265 prot = HV_PCI_MAP_ATTR_READ;
266 if (direction != DMA_TO_DEVICE)
267 prot |= HV_PCI_MAP_ATTR_WRITE;
268
269 local_irq_save(flags);
270
271 iommu_batch_start(dev, prot, entry);
272
273 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
274 long err = iommu_batch_add(base_paddr);
275 if (unlikely(err < 0L))
276 goto iommu_map_fail;
277 }
278 if (unlikely(iommu_batch_end() < 0L))
279 goto iommu_map_fail;
280
281 local_irq_restore(flags);
282
283 return ret;
284
285bad:
286 if (printk_ratelimit())
287 WARN_ON(1);
288 return DMA_ERROR_CODE;
289
290iommu_map_fail:
291 /* Interrupts are disabled. */
292 spin_lock(&iommu->lock);
293 iommu_range_free(iommu, bus_addr, npages);
294 spin_unlock_irqrestore(&iommu->lock, flags);
295
296 return DMA_ERROR_CODE;
297}
298
299static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
300 size_t sz, enum dma_data_direction direction,
301 struct dma_attrs *attrs)
302{
303 struct pci_pbm_info *pbm;
304 struct iommu *iommu;
305 unsigned long flags, npages;
306 long entry;
307 u32 devhandle;
308
309 if (unlikely(direction == DMA_NONE)) {
310 if (printk_ratelimit())
311 WARN_ON(1);
312 return;
313 }
314
315 iommu = dev->archdata.iommu;
316 pbm = dev->archdata.host_controller;
317 devhandle = pbm->devhandle;
318
319 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
320 npages >>= IO_PAGE_SHIFT;
321 bus_addr &= IO_PAGE_MASK;
322
323 spin_lock_irqsave(&iommu->lock, flags);
324
325 iommu_range_free(iommu, bus_addr, npages);
326
327 entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
328 do {
329 unsigned long num;
330
331 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
332 npages);
333 entry += num;
334 npages -= num;
335 } while (npages != 0);
336
337 spin_unlock_irqrestore(&iommu->lock, flags);
338}
339
340static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
341 int nelems, enum dma_data_direction direction,
342 struct dma_attrs *attrs)
343{
344 struct scatterlist *s, *outs, *segstart;
345 unsigned long flags, handle, prot;
346 dma_addr_t dma_next = 0, dma_addr;
347 unsigned int max_seg_size;
348 unsigned long seg_boundary_size;
349 int outcount, incount, i;
350 struct iommu *iommu;
351 unsigned long base_shift;
352 long err;
353
354 BUG_ON(direction == DMA_NONE);
355
356 iommu = dev->archdata.iommu;
357 if (nelems == 0 || !iommu)
358 return 0;
359
360 prot = HV_PCI_MAP_ATTR_READ;
361 if (direction != DMA_TO_DEVICE)
362 prot |= HV_PCI_MAP_ATTR_WRITE;
363
364 outs = s = segstart = &sglist[0];
365 outcount = 1;
366 incount = nelems;
367 handle = 0;
368
369 /* Init first segment length for backout at failure */
370 outs->dma_length = 0;
371
372 spin_lock_irqsave(&iommu->lock, flags);
373
374 iommu_batch_start(dev, prot, ~0UL);
375
376 max_seg_size = dma_get_max_seg_size(dev);
377 seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
378 IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
379 base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
380 for_each_sg(sglist, s, nelems, i) {
381 unsigned long paddr, npages, entry, out_entry = 0, slen;
382
383 slen = s->length;
384 /* Sanity check */
385 if (slen == 0) {
386 dma_next = 0;
387 continue;
388 }
389 /* Allocate iommu entries for that segment */
390 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
391 npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
392 entry = iommu_range_alloc(dev, iommu, npages, &handle);
393
394 /* Handle failure */
395 if (unlikely(entry == DMA_ERROR_CODE)) {
396 if (printk_ratelimit())
397 printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
398 " npages %lx\n", iommu, paddr, npages);
399 goto iommu_map_failed;
400 }
401
402 iommu_batch_new_entry(entry);
403
404 /* Convert entry to a dma_addr_t */
405 dma_addr = iommu->page_table_map_base +
406 (entry << IO_PAGE_SHIFT);
407 dma_addr |= (s->offset & ~IO_PAGE_MASK);
408
409 /* Insert into HW table */
410 paddr &= IO_PAGE_MASK;
411 while (npages--) {
412 err = iommu_batch_add(paddr);
413 if (unlikely(err < 0L))
414 goto iommu_map_failed;
415 paddr += IO_PAGE_SIZE;
416 }
417
418 /* If we are in an open segment, try merging */
419 if (segstart != s) {
420 /* We cannot merge if:
421 * - allocated dma_addr isn't contiguous to previous allocation
422 */
423 if ((dma_addr != dma_next) ||
424 (outs->dma_length + s->length > max_seg_size) ||
425 (is_span_boundary(out_entry, base_shift,
426 seg_boundary_size, outs, s))) {
427 /* Can't merge: create a new segment */
428 segstart = s;
429 outcount++;
430 outs = sg_next(outs);
431 } else {
432 outs->dma_length += s->length;
433 }
434 }
435
436 if (segstart == s) {
437 /* This is a new segment, fill entries */
438 outs->dma_address = dma_addr;
439 outs->dma_length = slen;
440 out_entry = entry;
441 }
442
443 /* Calculate next page pointer for contiguous check */
444 dma_next = dma_addr + slen;
445 }
446
447 err = iommu_batch_end();
448
449 if (unlikely(err < 0L))
450 goto iommu_map_failed;
451
452 spin_unlock_irqrestore(&iommu->lock, flags);
453
454 if (outcount < incount) {
455 outs = sg_next(outs);
456 outs->dma_address = DMA_ERROR_CODE;
457 outs->dma_length = 0;
458 }
459
460 return outcount;
461
462iommu_map_failed:
463 for_each_sg(sglist, s, nelems, i) {
464 if (s->dma_length != 0) {
465 unsigned long vaddr, npages;
466
467 vaddr = s->dma_address & IO_PAGE_MASK;
468 npages = iommu_num_pages(s->dma_address, s->dma_length,
469 IO_PAGE_SIZE);
470 iommu_range_free(iommu, vaddr, npages);
471 /* XXX demap? XXX */
472 s->dma_address = DMA_ERROR_CODE;
473 s->dma_length = 0;
474 }
475 if (s == outs)
476 break;
477 }
478 spin_unlock_irqrestore(&iommu->lock, flags);
479
480 return 0;
481}
482
483static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
484 int nelems, enum dma_data_direction direction,
485 struct dma_attrs *attrs)
486{
487 struct pci_pbm_info *pbm;
488 struct scatterlist *sg;
489 struct iommu *iommu;
490 unsigned long flags;
491 u32 devhandle;
492
493 BUG_ON(direction == DMA_NONE);
494
495 iommu = dev->archdata.iommu;
496 pbm = dev->archdata.host_controller;
497 devhandle = pbm->devhandle;
498
499 spin_lock_irqsave(&iommu->lock, flags);
500
501 sg = sglist;
502 while (nelems--) {
503 dma_addr_t dma_handle = sg->dma_address;
504 unsigned int len = sg->dma_length;
505 unsigned long npages, entry;
506
507 if (!len)
508 break;
509 npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
510 iommu_range_free(iommu, dma_handle, npages);
511
512 entry = ((dma_handle - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
513 while (npages) {
514 unsigned long num;
515
516 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
517 npages);
518 entry += num;
519 npages -= num;
520 }
521
522 sg = sg_next(sg);
523 }
524
525 spin_unlock_irqrestore(&iommu->lock, flags);
526}
527
528static struct dma_map_ops sun4v_dma_ops = {
529 .alloc_coherent = dma_4v_alloc_coherent,
530 .free_coherent = dma_4v_free_coherent,
531 .map_page = dma_4v_map_page,
532 .unmap_page = dma_4v_unmap_page,
533 .map_sg = dma_4v_map_sg,
534 .unmap_sg = dma_4v_unmap_sg,
535};
536
537static void __devinit pci_sun4v_scan_bus(struct pci_pbm_info *pbm,
538 struct device *parent)
539{
540 struct property *prop;
541 struct device_node *dp;
542
543 dp = pbm->op->dev.of_node;
544 prop = of_find_property(dp, "66mhz-capable", NULL);
545 pbm->is_66mhz_capable = (prop != NULL);
546 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
547
548 /* XXX register error interrupt handlers XXX */
549}
550
551static unsigned long __devinit probe_existing_entries(struct pci_pbm_info *pbm,
552 struct iommu *iommu)
553{
554 struct iommu_arena *arena = &iommu->arena;
555 unsigned long i, cnt = 0;
556 u32 devhandle;
557
558 devhandle = pbm->devhandle;
559 for (i = 0; i < arena->limit; i++) {
560 unsigned long ret, io_attrs, ra;
561
562 ret = pci_sun4v_iommu_getmap(devhandle,
563 HV_PCI_TSBID(0, i),
564 &io_attrs, &ra);
565 if (ret == HV_EOK) {
566 if (page_in_phys_avail(ra)) {
567 pci_sun4v_iommu_demap(devhandle,
568 HV_PCI_TSBID(0, i), 1);
569 } else {
570 cnt++;
571 __set_bit(i, arena->map);
572 }
573 }
574 }
575
576 return cnt;
577}
578
579static int __devinit pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
580{
581 static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
582 struct iommu *iommu = pbm->iommu;
583 unsigned long num_tsb_entries, sz;
584 u32 dma_mask, dma_offset;
585 const u32 *vdma;
586
587 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
588 if (!vdma)
589 vdma = vdma_default;
590
591 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
592 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
593 vdma[0], vdma[1]);
594 return -EINVAL;
595 };
596
597 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
598 num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
599
600 dma_offset = vdma[0];
601
602 /* Setup initial software IOMMU state. */
603 spin_lock_init(&iommu->lock);
604 iommu->ctx_lowest_free = 1;
605 iommu->page_table_map_base = dma_offset;
606 iommu->dma_addr_mask = dma_mask;
607
608 /* Allocate and initialize the free area map. */
609 sz = (num_tsb_entries + 7) / 8;
610 sz = (sz + 7UL) & ~7UL;
611 iommu->arena.map = kzalloc(sz, GFP_KERNEL);
612 if (!iommu->arena.map) {
613 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
614 return -ENOMEM;
615 }
616 iommu->arena.limit = num_tsb_entries;
617
618 sz = probe_existing_entries(pbm, iommu);
619 if (sz)
620 printk("%s: Imported %lu TSB entries from OBP\n",
621 pbm->name, sz);
622
623 return 0;
624}
625
626#ifdef CONFIG_PCI_MSI
627struct pci_sun4v_msiq_entry {
628 u64 version_type;
629#define MSIQ_VERSION_MASK 0xffffffff00000000UL
630#define MSIQ_VERSION_SHIFT 32
631#define MSIQ_TYPE_MASK 0x00000000000000ffUL
632#define MSIQ_TYPE_SHIFT 0
633#define MSIQ_TYPE_NONE 0x00
634#define MSIQ_TYPE_MSG 0x01
635#define MSIQ_TYPE_MSI32 0x02
636#define MSIQ_TYPE_MSI64 0x03
637#define MSIQ_TYPE_INTX 0x08
638#define MSIQ_TYPE_NONE2 0xff
639
640 u64 intx_sysino;
641 u64 reserved1;
642 u64 stick;
643 u64 req_id; /* bus/device/func */
644#define MSIQ_REQID_BUS_MASK 0xff00UL
645#define MSIQ_REQID_BUS_SHIFT 8
646#define MSIQ_REQID_DEVICE_MASK 0x00f8UL
647#define MSIQ_REQID_DEVICE_SHIFT 3
648#define MSIQ_REQID_FUNC_MASK 0x0007UL
649#define MSIQ_REQID_FUNC_SHIFT 0
650
651 u64 msi_address;
652
653 /* The format of this value is message type dependent.
654 * For MSI bits 15:0 are the data from the MSI packet.
655 * For MSI-X bits 31:0 are the data from the MSI packet.
656 * For MSG, the message code and message routing code where:
657 * bits 39:32 is the bus/device/fn of the msg target-id
658 * bits 18:16 is the message routing code
659 * bits 7:0 is the message code
660 * For INTx the low order 2-bits are:
661 * 00 - INTA
662 * 01 - INTB
663 * 10 - INTC
664 * 11 - INTD
665 */
666 u64 msi_data;
667
668 u64 reserved2;
669};
670
671static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
672 unsigned long *head)
673{
674 unsigned long err, limit;
675
676 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
677 if (unlikely(err))
678 return -ENXIO;
679
680 limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
681 if (unlikely(*head >= limit))
682 return -EFBIG;
683
684 return 0;
685}
686
687static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
688 unsigned long msiqid, unsigned long *head,
689 unsigned long *msi)
690{
691 struct pci_sun4v_msiq_entry *ep;
692 unsigned long err, type;
693
694 /* Note: void pointer arithmetic, 'head' is a byte offset */
695 ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
696 (pbm->msiq_ent_count *
697 sizeof(struct pci_sun4v_msiq_entry))) +
698 *head);
699
700 if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
701 return 0;
702
703 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
704 if (unlikely(type != MSIQ_TYPE_MSI32 &&
705 type != MSIQ_TYPE_MSI64))
706 return -EINVAL;
707
708 *msi = ep->msi_data;
709
710 err = pci_sun4v_msi_setstate(pbm->devhandle,
711 ep->msi_data /* msi_num */,
712 HV_MSISTATE_IDLE);
713 if (unlikely(err))
714 return -ENXIO;
715
716 /* Clear the entry. */
717 ep->version_type &= ~MSIQ_TYPE_MASK;
718
719 (*head) += sizeof(struct pci_sun4v_msiq_entry);
720 if (*head >=
721 (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
722 *head = 0;
723
724 return 1;
725}
726
727static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
728 unsigned long head)
729{
730 unsigned long err;
731
732 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
733 if (unlikely(err))
734 return -EINVAL;
735
736 return 0;
737}
738
739static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
740 unsigned long msi, int is_msi64)
741{
742 if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
743 (is_msi64 ?
744 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
745 return -ENXIO;
746 if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
747 return -ENXIO;
748 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
749 return -ENXIO;
750 return 0;
751}
752
753static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
754{
755 unsigned long err, msiqid;
756
757 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
758 if (err)
759 return -ENXIO;
760
761 pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
762
763 return 0;
764}
765
766static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
767{
768 unsigned long q_size, alloc_size, pages, order;
769 int i;
770
771 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
772 alloc_size = (pbm->msiq_num * q_size);
773 order = get_order(alloc_size);
774 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
775 if (pages == 0UL) {
776 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
777 order);
778 return -ENOMEM;
779 }
780 memset((char *)pages, 0, PAGE_SIZE << order);
781 pbm->msi_queues = (void *) pages;
782
783 for (i = 0; i < pbm->msiq_num; i++) {
784 unsigned long err, base = __pa(pages + (i * q_size));
785 unsigned long ret1, ret2;
786
787 err = pci_sun4v_msiq_conf(pbm->devhandle,
788 pbm->msiq_first + i,
789 base, pbm->msiq_ent_count);
790 if (err) {
791 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
792 err);
793 goto h_error;
794 }
795
796 err = pci_sun4v_msiq_info(pbm->devhandle,
797 pbm->msiq_first + i,
798 &ret1, &ret2);
799 if (err) {
800 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
801 err);
802 goto h_error;
803 }
804 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
805 printk(KERN_ERR "MSI: Bogus qconf "
806 "expected[%lx:%x] got[%lx:%lx]\n",
807 base, pbm->msiq_ent_count,
808 ret1, ret2);
809 goto h_error;
810 }
811 }
812
813 return 0;
814
815h_error:
816 free_pages(pages, order);
817 return -EINVAL;
818}
819
820static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
821{
822 unsigned long q_size, alloc_size, pages, order;
823 int i;
824
825 for (i = 0; i < pbm->msiq_num; i++) {
826 unsigned long msiqid = pbm->msiq_first + i;
827
828 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
829 }
830
831 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
832 alloc_size = (pbm->msiq_num * q_size);
833 order = get_order(alloc_size);
834
835 pages = (unsigned long) pbm->msi_queues;
836
837 free_pages(pages, order);
838
839 pbm->msi_queues = NULL;
840}
841
842static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
843 unsigned long msiqid,
844 unsigned long devino)
845{
846 unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
847
848 if (!irq)
849 return -ENOMEM;
850
851 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
852 return -EINVAL;
853 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
854 return -EINVAL;
855
856 return irq;
857}
858
859static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
860 .get_head = pci_sun4v_get_head,
861 .dequeue_msi = pci_sun4v_dequeue_msi,
862 .set_head = pci_sun4v_set_head,
863 .msi_setup = pci_sun4v_msi_setup,
864 .msi_teardown = pci_sun4v_msi_teardown,
865 .msiq_alloc = pci_sun4v_msiq_alloc,
866 .msiq_free = pci_sun4v_msiq_free,
867 .msiq_build_irq = pci_sun4v_msiq_build_irq,
868};
869
870static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
871{
872 sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
873}
874#else /* CONFIG_PCI_MSI */
875static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
876{
877}
878#endif /* !(CONFIG_PCI_MSI) */
879
880static int __devinit pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
881 struct platform_device *op, u32 devhandle)
882{
883 struct device_node *dp = op->dev.of_node;
884 int err;
885
886 pbm->numa_node = of_node_to_nid(dp);
887
888 pbm->pci_ops = &sun4v_pci_ops;
889 pbm->config_space_reg_bits = 12;
890
891 pbm->index = pci_num_pbms++;
892
893 pbm->op = op;
894
895 pbm->devhandle = devhandle;
896
897 pbm->name = dp->full_name;
898
899 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
900 printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
901
902 pci_determine_mem_io_space(pbm);
903
904 pci_get_pbm_props(pbm);
905
906 err = pci_sun4v_iommu_init(pbm);
907 if (err)
908 return err;
909
910 pci_sun4v_msi_init(pbm);
911
912 pci_sun4v_scan_bus(pbm, &op->dev);
913
914 pbm->next = pci_pbm_root;
915 pci_pbm_root = pbm;
916
917 return 0;
918}
919
920static int __devinit pci_sun4v_probe(struct platform_device *op)
921{
922 const struct linux_prom64_registers *regs;
923 static int hvapi_negotiated = 0;
924 struct pci_pbm_info *pbm;
925 struct device_node *dp;
926 struct iommu *iommu;
927 u32 devhandle;
928 int i, err;
929
930 dp = op->dev.of_node;
931
932 if (!hvapi_negotiated++) {
933 err = sun4v_hvapi_register(HV_GRP_PCI,
934 vpci_major,
935 &vpci_minor);
936
937 if (err) {
938 printk(KERN_ERR PFX "Could not register hvapi, "
939 "err=%d\n", err);
940 return err;
941 }
942 printk(KERN_INFO PFX "Registered hvapi major[%lu] minor[%lu]\n",
943 vpci_major, vpci_minor);
944
945 dma_ops = &sun4v_dma_ops;
946 }
947
948 regs = of_get_property(dp, "reg", NULL);
949 err = -ENODEV;
950 if (!regs) {
951 printk(KERN_ERR PFX "Could not find config registers\n");
952 goto out_err;
953 }
954 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
955
956 err = -ENOMEM;
957 if (!iommu_batch_initialized) {
958 for_each_possible_cpu(i) {
959 unsigned long page = get_zeroed_page(GFP_KERNEL);
960
961 if (!page)
962 goto out_err;
963
964 per_cpu(iommu_batch, i).pglist = (u64 *) page;
965 }
966 iommu_batch_initialized = 1;
967 }
968
969 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
970 if (!pbm) {
971 printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
972 goto out_err;
973 }
974
975 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
976 if (!iommu) {
977 printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
978 goto out_free_controller;
979 }
980
981 pbm->iommu = iommu;
982
983 err = pci_sun4v_pbm_init(pbm, op, devhandle);
984 if (err)
985 goto out_free_iommu;
986
987 dev_set_drvdata(&op->dev, pbm);
988
989 return 0;
990
991out_free_iommu:
992 kfree(pbm->iommu);
993
994out_free_controller:
995 kfree(pbm);
996
997out_err:
998 return err;
999}
1000
1001static const struct of_device_id pci_sun4v_match[] = {
1002 {
1003 .name = "pci",
1004 .compatible = "SUNW,sun4v-pci",
1005 },
1006 {},
1007};
1008
1009static struct platform_driver pci_sun4v_driver = {
1010 .driver = {
1011 .name = DRIVER_NAME,
1012 .owner = THIS_MODULE,
1013 .of_match_table = pci_sun4v_match,
1014 },
1015 .probe = pci_sun4v_probe,
1016};
1017
1018static int __init pci_sun4v_init(void)
1019{
1020 return platform_driver_register(&pci_sun4v_driver);
1021}
1022
1023subsys_initcall(pci_sun4v_init);