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1/* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $
2 * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver.
3 *
4 * Copyright (C) 2004 Sun Microsystems Inc.
5 * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * vendor id: 0x108E (Sun Microsystems, Inc.)
21 * device id: 0xabba (Cassini)
22 * revision ids: 0x01 = Cassini
23 * 0x02 = Cassini rev 2
24 * 0x10 = Cassini+
25 * 0x11 = Cassini+ 0.2u
26 *
27 * vendor id: 0x100b (National Semiconductor)
28 * device id: 0x0035 (DP83065/Saturn)
29 * revision ids: 0x30 = Saturn B2
30 *
31 * rings are all offset from 0.
32 *
33 * there are two clock domains:
34 * PCI: 33/66MHz clock
35 * chip: 125MHz clock
36 */
37
38#ifndef _CASSINI_H
39#define _CASSINI_H
40
41/* cassini register map: 2M memory mapped in 32-bit memory space accessible as
42 * 32-bit words. there is no i/o port access. REG_ addresses are
43 * shared between cassini and cassini+. REG_PLUS_ addresses only
44 * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
45 */
46#define CAS_ID_REV2 0x02
47#define CAS_ID_REVPLUS 0x10
48#define CAS_ID_REVPLUS02u 0x11
49#define CAS_ID_REVSATURNB2 0x30
50
51/** global resources **/
52
53/* this register sets the weights for the weighted round robin arbiter. e.g.,
54 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
55 * for its next turn to access the pci bus.
56 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
57 * DEFAULT: 0x0, SIZE: 5 bits
58 */
59#define REG_CAWR 0x0004 /* core arbitration weight */
60#define CAWR_RX_DMA_WEIGHT_SHIFT 0
61#define CAWR_RX_DMA_WEIGHT_MASK 0x03 /* [0:1] */
62#define CAWR_TX_DMA_WEIGHT_SHIFT 2
63#define CAWR_TX_DMA_WEIGHT_MASK 0x0C /* [3:2] */
64#define CAWR_RR_DIS 0x10 /* [4] */
65
66/* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
67 * sizes determined by length of packet or descriptor transfer and the
68 * max length allowed by the target.
69 * DEFAULT: 0x0, SIZE: 1 bit
70 */
71#define REG_INF_BURST 0x0008 /* infinite burst enable reg */
72#define INF_BURST_EN 0x1 /* enable */
73
74/* top level interrupts [0-9] are auto-cleared to 0 when the status
75 * register is read. second level interrupts [13 - 18] are cleared at
76 * the source. tx completion register 3 is replicated in [19 - 31]
77 * DEFAULT: 0x00000000, SIZE: 29 bits
78 */
79#define REG_INTR_STATUS 0x000C /* interrupt status register */
80#define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set
81 xferred from host queue to
82 TX FIFO */
83#define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into
84 TX FIFO. i.e.,
85 TX Kick == TX complete. if
86 PACED_MODE set, then TX FIFO
87 also empty */
88#define INTR_TX_DONE 0x00000004 /* any frame xferred into tx
89 FIFO */
90#define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing
91 corrupted. FATAL ERROR */
92#define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred
93 from RX FIFO to host mem.
94 RX completion reg updated.
95 may be delayed by recv
96 intr blanking. */
97#define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers.
98 RX Kick == RX complete */
99#define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing
100 corrupted. FATAL ERROR */
101#define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion
102 ring to post descriptors.
103 RX complete head incr to
104 almost reach RX complete
105 tail */
106#define INTR_RX_BUF_AE 0x00000100 /* less than the
107 programmable threshold #
108 of free descr avail for
109 hw use */
110#define INTR_RX_COMP_AF 0x00000200 /* less than the
111 programmable threshold #
112 of descr spaces for hw
113 use in completion descr
114 ring */
115#define INTR_RX_LEN_MISMATCH 0x00000400 /* len field from MAC !=
116 len of non-reassembly pkt
117 from fifo during DMA or
118 header parser provides TCP
119 header and payload size >
120 MAC packet size.
121 FATAL ERROR */
122#define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this
123 bit will be set if an interrupt
124 generated on the pci bus. useful
125 when driver is polling for
126 interrupts */
127#define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */
128#define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at
129 least 1 unmasked interrupt set */
130#define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at
131 least 1 unmasked interrupt set */
132#define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has
133 at least 1 unmasked interrupt
134 set */
135#define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least
136 1 unmasked interrupt set */
137#define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the
138 BIF has at least 1 unmasked
139 interrupt set */
140#define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion
141 3 reg data */
142#define INTR_TX_COMP_3_SHIFT 19
143#define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
144 INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
145 INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
146 INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
147 INTR_MAC_CTRL_STATUS)
148
149/* determines which status events will cause an interrupt. layout same
150 * as REG_INTR_STATUS.
151 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
152 */
153#define REG_INTR_MASK 0x0010 /* Interrupt mask */
154
155/* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS.
156 * useful when driver is polling for interrupts. layout same as REG_INTR_MASK.
157 * DEFAULT: 0x00000000, SIZE: 12 bits
158 */
159#define REG_ALIAS_CLEAR 0x0014 /* alias clear mask
160 (used w/ status alias) */
161/* same as REG_INTR_STATUS except that only bits cleared are those selected by
162 * REG_ALIAS_CLEAR
163 * DEFAULT: 0x00000000, SIZE: 29 bits
164 */
165#define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias
166 (selective clear) */
167
168/* DEFAULT: 0x0, SIZE: 3 bits */
169#define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */
170#define PCI_ERR_BADACK 0x01 /* reserved in Cassini+.
171 set if no ACK64# during ABS64 cycle
172 in Cassini. */
173#define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if
174 no read retry after 2^15 clocks */
175#define PCI_ERR_OTHER 0x04 /* other PCI errors */
176#define PCI_ERR_BIM_DMA_WRITE 0x08 /* BIM received 0 count DMA write req.
177 unused in Cassini. */
178#define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req.
179 unused in Cassini. */
180#define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during
181 DMA. unused in cassini. */
182
183/* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
184 * causes an interrupt to be generated.
185 * DEFAULT: 0x7, SIZE: 3 bits
186 */
187#define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */
188
189/* used to configure PCI related parameters that are not in PCI config space.
190 * DEFAULT: 0bxx000, SIZE: 5 bits
191 */
192#define REG_BIM_CFG 0x1008 /* BIM Configuration */
193#define BIM_CFG_RESERVED0 0x001 /* reserved */
194#define BIM_CFG_RESERVED1 0x002 /* reserved */
195#define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
196#define BIM_CFG_66MHZ 0x008 /* (ro) 1 = 66MHz, 0 = < 66MHz */
197#define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
198#define BIM_CFG_DPAR_INTR_ENABLE 0x020 /* detected parity err enable */
199#define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */
200#define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */
201#define BIM_CFG_RESERVED2 0x100 /* reserved */
202#define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global
203 reset. reserved in Cassini. */
204#define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended.
205 reserved in Cassini. */
206#define BIM_CFG_PERROR_BLOCK 0x800 /* block PERR# to pci bus. def: 0.
207 reserved in Cassini. */
208
209/* DEFAULT: 0x00000000, SIZE: 32 bits */
210#define REG_BIM_DIAG 0x100C /* BIM Diagnostic */
211#define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state
212 machine bits [21:0] */
213#define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state
214 machine bits [6:0] */
215
216/* writing to SW_RESET_TX and SW_RESET_RX will issue a global
217 * reset. poll until TX and RX read back as 0's for completion.
218 */
219#define REG_SW_RESET 0x1010 /* Software reset */
220#define SW_RESET_TX 0x00000001 /* reset TX DMA engine. poll until
221 cleared to 0. */
222#define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until
223 cleared to 0. */
224#define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low).
225 resets PHY and anything else
226 connected to RSTOUT#. RSTOUT#
227 is also activated by local PCI
228 reset when hot-swap is being
229 done. */
230#define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with
231 this bit set, PCS and SLINK
232 modules won't be reset.
233 i.e., link won't drop. */
234#define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */
235#define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits:
236 0b000: ARB_IDLE1
237 0b001: ARB_IDLE2
238 0b010: ARB_WB_ACK
239 0b011: ARB_WB_WAT
240 0b100: ARB_RB_ACK
241 0b101: ARB_RB_WAT
242 0b110: ARB_RB_END
243 0b111: ARB_WB_END */
244#define SW_RESET_RDPCI_SM_MASK 0x00300000 /* read pci state bits:
245 0b00: RD_PCI_WAT
246 0b01: RD_PCI_RDY
247 0b11: RD_PCI_ACK */
248#define SW_RESET_RDARB_SM_MASK 0x00C00000 /* read arbitration state bits:
249 0b00: AD_IDL_RX
250 0b01: AD_ACK_RX
251 0b10: AD_ACK_TX
252 0b11: AD_IDL_TX */
253#define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits
254 0b00: WR_PCI_WAT
255 0b01: WR_PCI_RDY
256 0b11: WR_PCI_ACK */
257#define SW_RESET_WRARB_SM_MASK 0x38000000 /* write arbitration state bits:
258 0b000: ARB_IDLE1
259 0b001: ARB_IDLE2
260 0b010: ARB_TX_ACK
261 0b011: ARB_TX_WAT
262 0b100: ARB_RX_ACK
263 0b110: ARB_RX_WAT */
264
265/* Cassini only. 64-bit register used to check PCI datapath. when read,
266 * value written has both lower and upper 32-bit halves rotated to the right
267 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
268 */
269#define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test
270 Cassini+: reserved */
271
272/* output enables are provided for each device's chip select and for the rest
273 * of the outputs from cassini to its local bus devices. two sw programmable
274 * bits are connected to general purpus control/status bits.
275 * DEFAULT: 0x7
276 */
277#define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device
278 output EN. default: 0x7 */
279#define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and
280 OE signal output enable on the
281 local bus interface. these
282 are shared between both local
283 bus devices. tristate when 0. */
284#define BIM_LOCAL_DEV_PROM 0x02 /* PROM chip select */
285#define BIM_LOCAL_DEV_EXT 0x04 /* secondary local bus device chip
286 select output enable */
287#define BIM_LOCAL_DEV_SOFT_0 0x08 /* sw programmable ctrl bit 0 */
288#define BIM_LOCAL_DEV_SOFT_1 0x10 /* sw programmable ctrl bit 1 */
289#define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */
290
291/* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
292 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
293 * _DATA_HI should be the last access of the sequence.
294 * DEFAULT: undefined
295 */
296#define REG_BIM_BUFFER_ADDR 0x1024 /* BIM buffer address. for
297 purposes. */
298#define BIM_BUFFER_ADDR_MASK 0x3F /* index (0 - 23) of buffer */
299#define BIM_BUFFER_WR_SELECT 0x40 /* write buffer access = 1
300 read buffer access = 0 */
301/* DEFAULT: undefined */
302#define REG_BIM_BUFFER_DATA_LOW 0x1028 /* BIM buffer data low */
303#define REG_BIM_BUFFER_DATA_HI 0x102C /* BIM buffer data high */
304
305/* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
306 * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
307 */
308#define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST
309 control/status */
310#define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */
311#define BIM_RAM_BIST_WR_START 0x02 /* start BIST for BIM write buffer.
312 Cassini only. reserved in
313 Cassini+. */
314#define BIM_RAM_BIST_RD_PASS 0x04 /* summary BIST pass status for read
315 buffer. */
316#define BIM_RAM_BIST_WR_PASS 0x08 /* summary BIST pass status for write
317 buffer. Cassini only. reserved
318 in Cassini+. */
319#define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */
320#define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */
321#define BIM_RAM_BIST_WR_LOW_PASS 0x40 /* write low bank passes BIST.
322 Cassini only. reserved in
323 Cassini+. */
324#define BIM_RAM_BIST_WR_HI_PASS 0x80 /* write high bank passes BIST.
325 Cassini only. reserved in
326 Cassini+. */
327
328/* ASUN: i'm not sure what this does as it's not in the spec.
329 * DEFAULT: 0xFC
330 */
331#define REG_BIM_DIAG_MUX 0x1030 /* BIM diagnostic probe mux
332 select register */
333
334/* enable probe monitoring mode and select data appearing on the P_A* bus. bit
335 * values for _SEL_HI_MASK and _SEL_LOW_MASK:
336 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
337 * wtc empty r, post pci)
338 * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp,
339 * pci rpkt comp, txdma wr req, txdma wr ack,
340 * txdma wr rdy, txdma wr xfr done)
341 * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd,
342 * rd arb state, rd pci state)
343 * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state,
344 * wrpci state)
345 * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8]
346 * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24]
347 * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40]
348 * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56]
349 * the following are not available in Cassini:
350 * 0xc: rx probe[7:0] 0xd: tx probe[7:0]
351 * 0xe: hp probe[7:0] 0xf: mac probe[7:0]
352 */
353#define REG_PLUS_PROBE_MUX_SELECT 0x1034 /* Cassini+: PROBE MUX SELECT */
354#define PROBE_MUX_EN 0x80000000 /* allow probe signals to be
355 driven on local bus P_A[15:0]
356 for debugging */
357#define PROBE_MUX_SUB_MUX_MASK 0x0000FF00 /* select sub module probe signals:
358 0x03 = mac[1:0]
359 0x0C = rx[1:0]
360 0x30 = tx[1:0]
361 0xC0 = hp[1:0] */
362#define PROBE_MUX_SEL_HI_MASK 0x000000F0 /* select which module to appear
363 on P_A[15:8]. see above for
364 values. */
365#define PROBE_MUX_SEL_LOW_MASK 0x0000000F /* select which module to appear
366 on P_A[7:0]. see above for
367 values. */
368
369/* values mean the same thing as REG_INTR_MASK excep that it's for INTB.
370 DEFAULT: 0x1F */
371#define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask
372 register 2 for INTB */
373#define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
374/* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to
375 * all of the alternate (2-4) INTR registers while _1 corresponds to only
376 * _MASK_1 and _STATUS_1 registers.
377 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
378 */
379#define INTR_RX_DONE_ALT 0x01
380#define INTR_RX_COMP_FULL_ALT 0x02
381#define INTR_RX_COMP_AF_ALT 0x04
382#define INTR_RX_BUF_UNAVAIL_1 0x08
383#define INTR_RX_BUF_AE_1 0x10 /* almost empty */
384#define INTRN_MASK_RX_EN 0x80
385#define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
386 INTR_RX_COMP_FULL_ALT | \
387 INTR_RX_COMP_AF_ALT | \
388 INTR_RX_BUF_UNAVAIL_1 | \
389 INTR_RX_BUF_AE_1)
390#define REG_PLUS_INTR_STATUS_1 0x103C /* Cassini+: interrupt status
391 register 2 for INTB. default: 0x1F */
392#define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
393#define INTR_STATUS_ALT_INTX_EN 0x80 /* generate INTX when one of the
394 flags are set. enables desc ring. */
395
396#define REG_PLUS_ALIAS_CLEAR_1 0x1040 /* Cassini+: alias clear mask
397 register 2 for INTB */
398#define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
399
400#define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status
401 register alias 2 for INTB */
402#define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
403
404#define REG_SATURN_PCFG 0x106c /* pin configuration register for
405 integrated macphy */
406
407#define SATURN_PCFG_TLA 0x00000001 /* 1 = phy actled */
408#define SATURN_PCFG_FLA 0x00000002 /* 1 = phy link10led */
409#define SATURN_PCFG_CLA 0x00000004 /* 1 = phy link100led */
410#define SATURN_PCFG_LLA 0x00000008 /* 1 = phy link1000led */
411#define SATURN_PCFG_RLA 0x00000010 /* 1 = phy duplexled */
412#define SATURN_PCFG_PDS 0x00000020 /* phy debug mode.
413 0 = normal */
414#define SATURN_PCFG_MTP 0x00000080 /* test point select */
415#define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 =
416 GMII on SERDES pins for
417 monitoring. */
418#define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all
419 pins configed as outputs.
420 for power saving when using
421 internal phy. */
422#define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl
423 polarity from strapping
424 value.
425 1 = mac core led ctrl
426 polarity active low. */
427
428
429/** transmit dma registers **/
430#define MAX_TX_RINGS_SHIFT 2
431#define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
432#define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
433
434/* TX configuration.
435 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
436 * DEFAULT: 0x3F000001
437 */
438#define REG_TX_CFG 0x2004 /* TX config */
439#define TX_CFG_DMA_EN 0x00000001 /* enable TX DMA. if cleared, DMA
440 will stop after xfer of current
441 buffer has been completed. */
442#define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be
443 accessed w/ FIFO addr
444 and data registers.
445 TX DMA should be
446 disabled. */
447#define TX_CFG_DESC_RING0_MASK 0x0000003C /* # desc entries in
448 ring 1. */
449#define TX_CFG_DESC_RING0_SHIFT 2
450#define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
451#define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
452#define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after
453 TX FIFO becomes empty.
454 if 0, TX_ALL set
455 if descr queue empty. */
456#define TX_CFG_DMA_RDPIPE_DIS 0x01000000 /* always set to 1 */
457#define TX_CFG_COMPWB_Q1 0x02000000 /* completion writeback happens at
458 the end of every packet kicked
459 through Q1. */
460#define TX_CFG_COMPWB_Q2 0x04000000 /* completion writeback happens at
461 the end of every packet kicked
462 through Q2. */
463#define TX_CFG_COMPWB_Q3 0x08000000 /* completion writeback happens at
464 the end of every packet kicked
465 through Q3 */
466#define TX_CFG_COMPWB_Q4 0x10000000 /* completion writeback happens at
467 the end of every packet kicked
468 through Q4 */
469#define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion
470 writeback */
471#define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port
472 connection
473 0b00: tx mac req,
474 tx mac retry req,
475 tx ack and tx tag.
476 0b01: txdma rd req,
477 txdma rd ack,
478 txdma rd rdy,
479 txdma rd type0
480 0b11: txdma wr req,
481 txdma wr ack,
482 txdma wr rdy,
483 txdma wr xfr done. */
484#define TX_CFG_CTX_SEL_SHIFT 30
485
486/* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
487 * used for diagnostics only.
488 */
489#define REG_TX_FIFO_WRITE_PTR 0x2014 /* TX FIFO write pointer */
490#define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write
491 pointer. temp hold reg.
492 diagnostics only. */
493#define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */
494#define REG_TX_FIFO_SHADOW_READ_PTR 0x2020 /* TX FIFO shadow read
495 pointer */
496
497/* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
498#define REG_TX_FIFO_PKT_CNT 0x2024 /* TX FIFO packet counter */
499
500/* current state of all state machines in TX */
501#define REG_TX_SM_1 0x2028 /* TX state machine reg #1 */
502#define TX_SM_1_CHAIN_MASK 0x000003FF /* chaining state machine */
503#define TX_SM_1_CSUM_MASK 0x00000C00 /* checksum state machine */
504#define TX_SM_1_FIFO_LOAD_MASK 0x0003F000 /* FIFO load state machine.
505 = 0x01 when TX disabled. */
506#define TX_SM_1_FIFO_UNLOAD_MASK 0x003C0000 /* FIFO unload state machine */
507#define TX_SM_1_CACHE_MASK 0x03C00000 /* desc. prefetch cache controller
508 state machine */
509#define TX_SM_1_CBQ_ARB_MASK 0xF8000000 /* CBQ arbiter state machine */
510
511#define REG_TX_SM_2 0x202C /* TX state machine reg #2 */
512#define TX_SM_2_COMP_WB_MASK 0x07 /* completion writeback sm */
513#define TX_SM_2_SUB_LOAD_MASK 0x38 /* sub load state machine */
514#define TX_SM_2_KICK_MASK 0xC0 /* kick state machine */
515
516/* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
517 * while the upper 23 bits are taken from the TX descriptor
518 */
519#define REG_TX_DATA_PTR_LOW 0x2030 /* TX data pointer low */
520#define REG_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */
521
522/* 13 bit registers written by driver w/ descriptor value that follows
523 * last valid xmit descriptor. kick # and complete # values are used by
524 * the xmit dma engine to control tx descr fetching. if > 1 valid
525 * tx descr is available within the cache line being read, cassini will
526 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
527 */
528#define REG_TX_KICK0 0x2038 /* TX kick reg #1 */
529#define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4)
530#define REG_TX_COMP0 0x2048 /* TX completion reg #1 */
531#define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
532
533/* values of TX_COMPLETE_1-4 are written. each completion register
534 * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment.
535 * NOTE: completion reg values are only written back prior to TX_INTME and
536 * TX_ALL interrupts. at all other times, the most up-to-date index values
537 * should be obtained from the REG_TX_COMPLETE_# registers.
538 * here's the layout:
539 * offset from base addr completion # byte
540 * 0 TX_COMPLETE_1_MSB
541 * 1 TX_COMPLETE_1_LSB
542 * 2 TX_COMPLETE_2_MSB
543 * 3 TX_COMPLETE_2_LSB
544 * 4 TX_COMPLETE_3_MSB
545 * 5 TX_COMPLETE_3_LSB
546 * 6 TX_COMPLETE_4_MSB
547 * 7 TX_COMPLETE_4_LSB
548 */
549#define TX_COMPWB_SIZE 8
550#define REG_TX_COMPWB_DB_LOW 0x2058 /* TX completion write back
551 base low */
552#define REG_TX_COMPWB_DB_HI 0x205C /* TX completion write back
553 base high */
554#define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
555#define TX_COMPWB_MSB_SHIFT 0
556#define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
557#define TX_COMPWB_LSB_SHIFT 8
558#define TX_COMPWB_NEXT(x) ((x) >> 16)
559
560/* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
561 * be 2KB-aligned. */
562#define REG_TX_DB0_LOW 0x2060 /* TX descriptor base low #1 */
563#define REG_TX_DB0_HI 0x2064 /* TX descriptor base hi #1 */
564#define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8)
565#define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8)
566
567/* 16-bit registers hold weights for the weighted round-robin of the
568 * four CBQ TX descr rings. weights correspond to # bytes xferred from
569 * host to TXFIFO in a round of WRR arbitration. can be set
570 * dynamically with new weights set upon completion of the current
571 * packet transfer from host memory to TXFIFO. a dummy write to any of
572 * these registers causes a queue1 pre-emption with all historical bw
573 * deficit data reset to 0 (useful when congestion requires a
574 * pre-emption/re-allocation of network bandwidth
575 */
576#define REG_TX_MAXBURST_0 0x2080 /* TX MaxBurst #1 */
577#define REG_TX_MAXBURST_1 0x2084 /* TX MaxBurst #2 */
578#define REG_TX_MAXBURST_2 0x2088 /* TX MaxBurst #3 */
579#define REG_TX_MAXBURST_3 0x208C /* TX MaxBurst #4 */
580
581/* diagnostics access to any TX FIFO location. every access is 65
582 * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit.
583 * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag
584 * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if
585 * TX FIFO data integrity is desired, TX DMA should be
586 * disabled. _DATA_HI_Tx should be the last access of the sequence.
587 */
588#define REG_TX_FIFO_ADDR 0x2104 /* TX FIFO address */
589#define REG_TX_FIFO_TAG 0x2108 /* TX FIFO tag */
590#define REG_TX_FIFO_DATA_LOW 0x210C /* TX FIFO data low */
591#define REG_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data high t1 */
592#define REG_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data high t0 */
593#define REG_TX_FIFO_SIZE 0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */
594
595/* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
596 * passed for the specified memory
597 */
598#define REG_TX_RAMBIST 0x211C /* TX RAMBIST control/status */
599#define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST
600 controller state machine */
601#define TX_RAMBIST_RAM33A_PASS 0x0020 /* RAM33A passed */
602#define TX_RAMBIST_RAM32A_PASS 0x0010 /* RAM32A passed */
603#define TX_RAMBIST_RAM33B_PASS 0x0008 /* RAM33B passed */
604#define TX_RAMBIST_RAM32B_PASS 0x0004 /* RAM32B passed */
605#define TX_RAMBIST_SUMMARY 0x0002 /* all RAM passed */
606#define TX_RAMBIST_START 0x0001 /* write 1 to start BIST. self
607 clears on completion. */
608
609/** receive dma registers **/
610#define MAX_RX_DESC_RINGS 2
611#define MAX_RX_COMP_RINGS 4
612
613/* receive DMA channel configuration. default: 0x80910
614 * free ring size = (1 << n)*32 -> [32 - 8k]
615 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
616 * DEFAULT: 0x80910
617 */
618#define REG_RX_CFG 0x4000 /* RX config */
619#define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops
620 channel as soon as current
621 frame xfer has completed.
622 driver should disable MAC
623 for 200ms before disabling
624 RX */
625#define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX
626 free desc ring.
627 def: 0x8 = 8k */
628#define RX_CFG_DESC_RING_SHIFT 1
629#define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete
630 ring. def: 0x8 = 32k */
631#define RX_CFG_COMP_RING_SHIFT 5
632#define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc
633 batching. def: 0x0 =
634 enabled */
635#define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st
636 data byte of the packet
637 w/in 8 byte boundares.
638 this swivels the data
639 DMA'ed to header
640 buffers, jumbo buffers
641 when header split is not
642 requested and MTU sized
643 buffers. def: 0x2 */
644#define RX_CFG_SWIVEL_SHIFT 10
645
646/* cassini+ only */
647#define RX_CFG_DESC_RING1_MASK 0x000F0000 /* # of desc entries in
648 RX free desc ring 2.
649 def: 0x8 = 8k */
650#define RX_CFG_DESC_RING1_SHIFT 16
651
652
653/* the page size register allows cassini chips to do the following with
654 * received data:
655 * [--------------------------------------------------------------] page
656 * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad]
657 * |--------------| = PAGE_SIZE_BUFFER_STRIDE
658 * page = PAGE_SIZE
659 * offset = PAGE_SIZE_MTU_OFF
660 * for the above example, MTU_BUFFER_COUNT = 4.
661 * NOTE: as is apparent, you need to ensure that the following holds:
662 * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE
663 * DEFAULT: 0x48002002 (8k pages)
664 */
665#define REG_RX_PAGE_SIZE 0x4004 /* RX page size */
666#define RX_PAGE_SIZE_MASK 0x00000003 /* size of pages pointed to
667 by receive descriptors.
668 if jumbo buffers are
669 supported the page size
670 should not be < 8k.
671 0b00 = 2k, 0b01 = 4k
672 0b10 = 8k, 0b11 = 16k
673 DEFAULT: 8k */
674#define RX_PAGE_SIZE_SHIFT 0
675#define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800 /* # of MTU buffers the hw
676 packs into a page.
677 DEFAULT: 4 */
678#define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
679#define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate
680 each MTU buffer +
681 offset from each
682 other.
683 0b00 = 1k, 0b01 = 2k
684 0b10 = 4k, 0b11 = 8k
685 DEFAULT: 0x1 */
686#define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
687#define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000 /* offset in each page that
688 hw writes the MTU buffer
689 into.
690 0b00 = 0,
691 0b01 = 64 bytes
692 0b10 = 96, 0b11 = 128
693 DEFAULT: 0x1 */
694#define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
695
696/* 11-bit counter points to next location in RX FIFO to be loaded/read.
697 * shadow write pointers enable retries in case of early receive aborts.
698 * DEFAULT: 0x0. generated on 64-bit boundaries.
699 */
700#define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */
701#define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */
702#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write
703 pointer */
704#define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read
705 pointer */
706#define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read
707 pointer. (8-bit counter) */
708
709/* current state of RX DMA state engines + other info
710 * DEFAULT: 0x0
711 */
712#define REG_RX_DEBUG 0x401C /* RX debug */
713#define RX_DEBUG_LOAD_STATE_MASK 0x0000000F /* load state machine w/ MAC:
714 0x0 = idle, 0x1 = load_bop
715 0x2 = load 1, 0x3 = load 2
716 0x4 = load 3, 0x5 = load 4
717 0x6 = last detect
718 0x7 = wait req
719 0x8 = wait req statuss 1st
720 0x9 = load st
721 0xa = bubble mac
722 0xb = error */
723#define RX_DEBUG_LM_STATE_MASK 0x00000070 /* load state machine w/ HP and
724 RX FIFO:
725 0x0 = idle, 0x1 = hp xfr
726 0x2 = wait hp ready
727 0x3 = wait flow code
728 0x4 = fifo xfer
729 0x5 = make status
730 0x6 = csum ready
731 0x7 = error */
732#define RX_DEBUG_FC_STATE_MASK 0x000000180 /* flow control state machine
733 w/ MAC:
734 0x0 = idle
735 0x1 = wait xoff ack
736 0x2 = wait xon
737 0x3 = wait xon ack */
738#define RX_DEBUG_DATA_STATE_MASK 0x000001E00 /* unload data state machine
739 states:
740 0x0 = idle data
741 0x1 = header begin
742 0x2 = xfer header
743 0x3 = xfer header ld
744 0x4 = mtu begin
745 0x5 = xfer mtu
746 0x6 = xfer mtu ld
747 0x7 = jumbo begin
748 0x8 = xfer jumbo
749 0x9 = xfer jumbo ld
750 0xa = reas begin
751 0xb = xfer reas
752 0xc = flush tag
753 0xd = xfer reas ld
754 0xe = error
755 0xf = bubble idle */
756#define RX_DEBUG_DESC_STATE_MASK 0x0001E000 /* unload desc state machine
757 states:
758 0x0 = idle desc
759 0x1 = wait ack
760 0x9 = wait ack 2
761 0x2 = fetch desc 1
762 0xa = fetch desc 2
763 0x3 = load ptrs
764 0x4 = wait dma
765 0x5 = wait ack batch
766 0x6 = post batch
767 0x7 = xfr done */
768#define RX_DEBUG_INTR_READ_PTR_MASK 0x30000000 /* interrupt read ptr of the
769 interrupt queue */
770#define RX_DEBUG_INTR_WRITE_PTR_MASK 0xC0000000 /* interrupt write pointer
771 of the interrupt queue */
772
773/* flow control frames are emitted using two PAUSE thresholds:
774 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
775 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
776 * PAUSE thresholds defined in terms of FIFO occupancy and may be translated
777 * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames
778 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
779 * value is is 0x6F.
780 * DEFAULT: 0x00078
781 */
782#define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */
783#define RX_PAUSE_THRESH_QUANTUM 64
784#define RX_PAUSE_THRESH_OFF_MASK 0x000001FF /* XOFF PAUSE emitted when
785 RX FIFO occupancy >
786 value*64B */
787#define RX_PAUSE_THRESH_OFF_SHIFT 0
788#define RX_PAUSE_THRESH_ON_MASK 0x001FF000 /* XON PAUSE emitted after
789 emitting XOFF PAUSE when RX
790 FIFO occupancy falls below
791 this value*64B. must be
792 < XOFF threshold. if =
793 RX_FIFO_SIZE< XON frames are
794 never emitted. */
795#define RX_PAUSE_THRESH_ON_SHIFT 12
796
797/* 13-bit register used to control RX desc fetching and intr generation. if 4+
798 * valid RX descriptors are available, Cassini will read 4 at a time.
799 * writing N means that all desc up to *but* excluding N are available. N must
800 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
801 * DEFAULT: 0 on reset
802 */
803#define REG_RX_KICK 0x4024 /* RX kick reg */
804
805/* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
806 * lower 13 bits of the low register are hard-wired to 0.
807 */
808#define REG_RX_DB_LOW 0x4028 /* RX descriptor ring
809 base low */
810#define REG_RX_DB_HI 0x402C /* RX descriptor ring
811 base hi */
812#define REG_RX_CB_LOW 0x4030 /* RX completion ring
813 base low */
814#define REG_RX_CB_HI 0x4034 /* RX completion ring
815 base hi */
816/* 13-bit register indicate desc used by cassini for receive frames. used
817 * for diagnostic purposes.
818 * DEFAULT: 0 on reset
819 */
820#define REG_RX_COMP 0x4038 /* (ro) RX completion */
821
822/* HEAD and TAIL are used to control RX desc posting and interrupt
823 * generation. hw moves the head register to pass ownership to sw. sw
824 * moves the tail register to pass ownership back to hw. to give all
825 * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no
826 * more entries are available, DMA will pause and an interrupt will be
827 * generated to indicate no more entries are available. sw can use
828 * this interrupt to reduce the # of times it must update the
829 * completion tail register.
830 * DEFAULT: 0 on reset
831 */
832#define REG_RX_COMP_HEAD 0x403C /* RX completion head */
833#define REG_RX_COMP_TAIL 0x4040 /* RX completion tail */
834
835/* values used for receive interrupt blanking. loaded each time the ISR is read
836 * DEFAULT: 0x00000000
837 */
838#define REG_RX_BLANK 0x4044 /* RX blanking register
839 for ISR read */
840#define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if
841 this many sets of completion
842 writebacks (up to 2 packets)
843 occur since the last time
844 the ISR was read. 0 = no
845 packet blanking */
846#define RX_BLANK_INTR_PKT_SHIFT 0
847#define RX_BLANK_INTR_TIME_MASK 0x3FFFF000 /* RX_DONE interrupt asserted
848 if that many clocks were
849 counted since last time the
850 ISR was read.
851 each count is 512 core
852 clocks (125MHz). 0 = no
853 time blanking */
854#define RX_BLANK_INTR_TIME_SHIFT 12
855
856/* values used for interrupt generation based on threshold values of how
857 * many free desc and completion entries are available for hw use.
858 * DEFAULT: 0x00000000
859 */
860#define REG_RX_AE_THRESH 0x4048 /* RX almost empty
861 thresholds */
862#define RX_AE_THRESH_FREE_MASK 0x00001FFF /* RX_BUF_AE will be
863 generated if # desc
864 avail for hw use <=
865 # */
866#define RX_AE_THRESH_FREE_SHIFT 0
867#define RX_AE_THRESH_COMP_MASK 0x0FFFE000 /* RX_COMP_AE will be
868 generated if # of
869 completion entries
870 avail for hw use <=
871 # */
872#define RX_AE_THRESH_COMP_SHIFT 13
873
874/* probabilities for random early drop (RED) thresholds on a FIFO threshold
875 * basis. probability should increase when the FIFO level increases. control
876 * packets are never dropped and not counted in stats. probability programmed
877 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped.
878 * DEFAULT: 0x00000000
879 */
880#define REG_RX_RED 0x404C /* RX random early detect enable */
881#define RX_RED_4K_6K_FIFO_MASK 0x000000FF /* 4KB < FIFO thresh < 6KB */
882#define RX_RED_6K_8K_FIFO_MASK 0x0000FF00 /* 6KB < FIFO thresh < 8KB */
883#define RX_RED_8K_10K_FIFO_MASK 0x00FF0000 /* 8KB < FIFO thresh < 10KB */
884#define RX_RED_10K_12K_FIFO_MASK 0xFF000000 /* 10KB < FIFO thresh < 12KB */
885
886/* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO.
887 * RX control FIFO = # of packets in RX FIFO.
888 * DEFAULT: 0x0
889 */
890#define REG_RX_FIFO_FULLNESS 0x4050 /* (ro) RX FIFO fullness */
891#define RX_FIFO_FULLNESS_RX_FIFO_MASK 0x3FF80000 /* level w/ 8B granularity */
892#define RX_FIFO_FULLNESS_IPP_FIFO_MASK 0x0007FF00 /* level w/ 8B granularity */
893#define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF /* # packets in RX FIFO */
894#define REG_RX_IPP_PACKET_COUNT 0x4054 /* RX IPP packet counter */
895#define REG_RX_WORK_DMA_PTR_LOW 0x4058 /* RX working DMA ptr low */
896#define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr
897 high */
898
899/* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST
900 * START/COMPLETE is writeable. START will clear when the BIST has completed
901 * checking all 17 RAMS.
902 * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0
903 */
904#define REG_RX_BIST 0x4060 /* (ro) RX BIST */
905#define RX_BIST_32A_PASS 0x80000000 /* RX FIFO 32A passed */
906#define RX_BIST_33A_PASS 0x40000000 /* RX FIFO 33A passed */
907#define RX_BIST_32B_PASS 0x20000000 /* RX FIFO 32B passed */
908#define RX_BIST_33B_PASS 0x10000000 /* RX FIFO 33B passed */
909#define RX_BIST_32C_PASS 0x08000000 /* RX FIFO 32C passed */
910#define RX_BIST_33C_PASS 0x04000000 /* RX FIFO 33C passed */
911#define RX_BIST_IPP_32A_PASS 0x02000000 /* RX IPP FIFO 33B passed */
912#define RX_BIST_IPP_33A_PASS 0x01000000 /* RX IPP FIFO 33A passed */
913#define RX_BIST_IPP_32B_PASS 0x00800000 /* RX IPP FIFO 32B passed */
914#define RX_BIST_IPP_33B_PASS 0x00400000 /* RX IPP FIFO 33B passed */
915#define RX_BIST_IPP_32C_PASS 0x00200000 /* RX IPP FIFO 32C passed */
916#define RX_BIST_IPP_33C_PASS 0x00100000 /* RX IPP FIFO 33C passed */
917#define RX_BIST_CTRL_32_PASS 0x00800000 /* RX CTRL FIFO 32 passed */
918#define RX_BIST_CTRL_33_PASS 0x00400000 /* RX CTRL FIFO 33 passed */
919#define RX_BIST_REAS_26A_PASS 0x00200000 /* RX Reas 26A passed */
920#define RX_BIST_REAS_26B_PASS 0x00100000 /* RX Reas 26B passed */
921#define RX_BIST_REAS_27_PASS 0x00080000 /* RX Reas 27 passed */
922#define RX_BIST_STATE_MASK 0x00078000 /* BIST state machine */
923#define RX_BIST_SUMMARY 0x00000002 /* when BIST complete,
924 summary pass bit
925 contains AND of BIST
926 results of all 16
927 RAMS */
928#define RX_BIST_START 0x00000001 /* write 1 to start
929 BIST. self clears
930 on completion. */
931
932/* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
933 * from to retrieve packet control info.
934 * DEFAULT: 0
935 */
936#define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO
937 write ptr */
938#define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read
939 ptr */
940
941/* receive interrupt blanking. loaded each time interrupt alias register is
942 * read.
943 * DEFAULT: 0x0
944 */
945#define REG_RX_BLANK_ALIAS_READ 0x406C /* RX blanking register for
946 alias read */
947#define RX_BAR_INTR_PACKET_MASK 0x000001FF /* assert RX_DONE if #
948 completion writebacks
949 > # since last ISR
950 read. 0 = no
951 blanking. up to 2
952 packets per
953 completion wb. */
954#define RX_BAR_INTR_TIME_MASK 0x3FFFF000 /* assert RX_DONE if #
955 clocks > # since last
956 ISR read. each count
957 is 512 core clocks
958 (125MHz). 0 = no
959 blanking. */
960
961/* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed
962 * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0
963 * will unset the tag bit while writing HI_T1 will set the tag bit. to reset
964 * to normal operation after diagnostics, write to address location 0x0.
965 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
966 * be the last write access of a write sequence.
967 * DEFAULT: undefined
968 */
969#define REG_RX_FIFO_ADDR 0x4080 /* RX FIFO address */
970#define REG_RX_FIFO_TAG 0x4084 /* RX FIFO tag */
971#define REG_RX_FIFO_DATA_LOW 0x4088 /* RX FIFO data low */
972#define REG_RX_FIFO_DATA_HI_T0 0x408C /* RX FIFO data high T0 */
973#define REG_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data high T1 */
974
975/* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of
976 * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit
977 * accesses. HI is 7-bits with 6-bit flow id and 1 bit control
978 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
979 * should be last write access of the write sequence.
980 * DEFAULT: undefined
981 */
982#define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and
983 Batching FIFO addr */
984#define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data
985 low */
986#define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data
987 mid */
988#define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data
989 hi and flow id */
990#define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001 /* upper bit of ctrl word */
991#define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E /* flow id */
992
993/* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO.
994 * DEFAULT: undefined
995 */
996#define REG_RX_IPP_FIFO_ADDR 0x4104 /* RX IPP FIFO address */
997#define REG_RX_IPP_FIFO_TAG 0x4108 /* RX IPP FIFO tag */
998#define REG_RX_IPP_FIFO_DATA_LOW 0x410C /* RX IPP FIFO data low */
999#define REG_RX_IPP_FIFO_DATA_HI_T0 0x4110 /* RX IPP FIFO data high
1000 T0 */
1001#define REG_RX_IPP_FIFO_DATA_HI_T1 0x4114 /* RX IPP FIFO data high
1002 T1 */
1003
1004/* 64-bit pointer to receive data buffer in host memory used for headers and
1005 * small packets. MSB in high register. loaded by DMA state machine and
1006 * increments as DMA writes receive data. only 50 LSB are incremented. top
1007 * 13 bits taken from RX descriptor.
1008 * DEFAULT: undefined
1009 */
1010#define REG_RX_HEADER_PAGE_PTR_LOW 0x4118 /* (ro) RX header page ptr
1011 low */
1012#define REG_RX_HEADER_PAGE_PTR_HI 0x411C /* (ro) RX header page ptr
1013 high */
1014#define REG_RX_MTU_PAGE_PTR_LOW 0x4120 /* (ro) RX MTU page pointer
1015 low */
1016#define REG_RX_MTU_PAGE_PTR_HI 0x4124 /* (ro) RX MTU page pointer
1017 high */
1018
1019/* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
1020 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
1021 * one of the 64 byte locations in the Batching table. LOW holds 32 LSB.
1022 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set
1023 * to 0 for PIO access. DATA_HIGH should be last write of write sequence.
1024 * layout:
1025 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0]
1026 * DEFAULT: undefined
1027 */
1028#define REG_RX_TABLE_ADDR 0x4128 /* RX reassembly DMA table
1029 address */
1030#define RX_TABLE_ADDR_MASK 0x0000003F /* address mask */
1031
1032#define REG_RX_TABLE_DATA_LOW 0x412C /* RX reassembly DMA table
1033 data low */
1034#define REG_RX_TABLE_DATA_MID 0x4130 /* RX reassembly DMA table
1035 data mid */
1036#define REG_RX_TABLE_DATA_HI 0x4134 /* RX reassembly DMA table
1037 data high */
1038
1039/* cassini+ only */
1040/* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to
1041 * 0. same semantics as primary desc/complete rings.
1042 */
1043#define REG_PLUS_RX_DB1_LOW 0x4200 /* RX descriptor ring
1044 2 base low */
1045#define REG_PLUS_RX_DB1_HI 0x4204 /* RX descriptor ring
1046 2 base high */
1047#define REG_PLUS_RX_CB1_LOW 0x4208 /* RX completion ring
1048 2 base low. 4 total */
1049#define REG_PLUS_RX_CB1_HI 0x420C /* RX completion ring
1050 2 base high. 4 total */
1051#define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1052#define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1053#define REG_PLUS_RX_KICK1 0x4220 /* RX Kick 2 register */
1054#define REG_PLUS_RX_COMP1 0x4224 /* (ro) RX completion 2
1055 reg */
1056#define REG_PLUS_RX_COMP1_HEAD 0x4228 /* (ro) RX completion 2
1057 head reg. 4 total. */
1058#define REG_PLUS_RX_COMP1_TAIL 0x422C /* RX completion 2
1059 tail reg. 4 total. */
1060#define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1061#define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1062#define REG_PLUS_RX_AE1_THRESH 0x4240 /* RX almost empty 2
1063 thresholds */
1064#define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK
1065#define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT
1066
1067/** header parser registers **/
1068
1069/* RX parser configuration register.
1070 * DEFAULT: 0x1651004
1071 */
1072#define REG_HP_CFG 0x4140 /* header parser
1073 configuration reg */
1074#define HP_CFG_PARSE_EN 0x00000001 /* enab header parsing */
1075#define HP_CFG_NUM_CPU_MASK 0x000000FC /* # processors
1076 0 = 64. 0x3f = 63 */
1077#define HP_CFG_NUM_CPU_SHIFT 2
1078#define HP_CFG_SYN_INC_MASK 0x00000100 /* SYN bit won't increment
1079 TCP seq # by one when
1080 stored in FDBM */
1081#define HP_CFG_TCP_THRESH_MASK 0x000FFE00 /* # bytes of TCP data
1082 needed to be considered
1083 for reassembly */
1084#define HP_CFG_TCP_THRESH_SHIFT 9
1085
1086/* access to RX Instruction RAM. 5-bit register/counter holds addr
1087 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI.
1088 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1089 * of sequence.
1090 * DEFAULT: undefined
1091 */
1092#define REG_HP_INSTR_RAM_ADDR 0x4144 /* HP instruction RAM
1093 address */
1094#define HP_INSTR_RAM_ADDR_MASK 0x01F /* 5-bit mask */
1095#define REG_HP_INSTR_RAM_DATA_LOW 0x4148 /* HP instruction RAM
1096 data low */
1097#define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF
1098#define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0
1099#define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000
1100#define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16
1101#define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000
1102#define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20
1103#define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
1104#define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22
1105#define REG_HP_INSTR_RAM_DATA_MID 0x414C /* HP instruction RAM
1106 data mid */
1107#define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
1108#define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
1109#define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C
1110#define HP_INSTR_RAM_MID_OUTOP_SHIFT 2
1111#define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0
1112#define HP_INSTR_RAM_MID_FNEXT_SHIFT 6
1113#define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800
1114#define HP_INSTR_RAM_MID_FOFF_SHIFT 11
1115#define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000
1116#define HP_INSTR_RAM_MID_SNEXT_SHIFT 18
1117#define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000
1118#define HP_INSTR_RAM_MID_SOFF_SHIFT 23
1119#define HP_INSTR_RAM_MID_OP_MASK 0xC0000000
1120#define HP_INSTR_RAM_MID_OP_SHIFT 30
1121#define REG_HP_INSTR_RAM_DATA_HI 0x4150 /* HP instruction RAM
1122 data high */
1123#define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF
1124#define HP_INSTR_RAM_HI_VAL_SHIFT 0
1125#define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000
1126#define HP_INSTR_RAM_HI_MASK_SHIFT 16
1127
1128/* PIO access into RX Header parser data RAM and flow database.
1129 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
1130 * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM.
1131 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1132 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
1133 * flow database.
1134 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1135 * should be the last write access of the write sequence.
1136 * DEFAULT: undefined
1137 */
1138#define REG_HP_DATA_RAM_FDB_ADDR 0x4154 /* HP data and FDB
1139 RAM address */
1140#define HP_DATA_RAM_FDB_DATA_MASK 0x001F /* select 1 of 86 byte
1141 locations in header
1142 parser data ram to
1143 read/write */
1144#define HP_DATA_RAM_FDB_FDB_MASK 0x3F00 /* 1 of 64 353-bit locations
1145 in the flow database */
1146#define REG_HP_DATA_RAM_DATA 0x4158 /* HP data RAM data */
1147
1148/* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1149 * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64]
1150 * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0]
1151 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64]
1152 * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0]
1153 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]}
1154 * FLOW_DB(10) = bit 0 has value for flow valid
1155 * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0]
1156 */
1157#define REG_HP_FLOW_DB0 0x415C /* HP flow database 1 reg */
1158#define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4)
1159
1160/* diagnostics for RX Header Parser block.
1161 * ASUN: the header parser state machine register is used for diagnostics
1162 * purposes. however, the spec doesn't have any details on it.
1163 */
1164#define REG_HP_STATE_MACHINE 0x418C /* (ro) HP state machine */
1165#define REG_HP_STATUS0 0x4190 /* (ro) HP status 1 */
1166#define HP_STATUS0_SAP_MASK 0xFFFF0000 /* SAP */
1167#define HP_STATUS0_L3_OFF_MASK 0x0000FE00 /* L3 offset */
1168#define HP_STATUS0_LB_CPUNUM_MASK 0x000001F8 /* load balancing CPU
1169 number */
1170#define HP_STATUS0_HRP_OPCODE_MASK 0x00000007 /* HRP opcode */
1171
1172#define REG_HP_STATUS1 0x4194 /* (ro) HP status 2 */
1173#define HP_STATUS1_ACCUR2_MASK 0xE0000000 /* accu R2[6:4] */
1174#define HP_STATUS1_FLOWID_MASK 0x1F800000 /* flow id */
1175#define HP_STATUS1_TCP_OFF_MASK 0x007F0000 /* tcp payload offset */
1176#define HP_STATUS1_TCP_SIZE_MASK 0x0000FFFF /* tcp payload size */
1177
1178#define REG_HP_STATUS2 0x4198 /* (ro) HP status 3 */
1179#define HP_STATUS2_ACCUR2_MASK 0xF0000000 /* accu R2[3:0] */
1180#define HP_STATUS2_CSUM_OFF_MASK 0x07F00000 /* checksum start
1181 start offset */
1182#define HP_STATUS2_ACCUR1_MASK 0x000FE000 /* accu R1 */
1183#define HP_STATUS2_FORCE_DROP 0x00001000 /* force drop */
1184#define HP_STATUS2_BWO_REASSM 0x00000800 /* batching w/o
1185 reassembly */
1186#define HP_STATUS2_JH_SPLIT_EN 0x00000400 /* jumbo header split
1187 enable */
1188#define HP_STATUS2_FORCE_TCP_NOCHECK 0x00000200 /* force tcp no payload
1189 check */
1190#define HP_STATUS2_DATA_MASK_ZERO 0x00000100 /* mask of data length
1191 equal to zero */
1192#define HP_STATUS2_FORCE_TCP_CHECK 0x00000080 /* force tcp payload
1193 chk */
1194#define HP_STATUS2_MASK_TCP_THRESH 0x00000040 /* mask of payload
1195 threshold */
1196#define HP_STATUS2_NO_ASSIST 0x00000020 /* no assist */
1197#define HP_STATUS2_CTRL_PACKET_FLAG 0x00000010 /* control packet flag */
1198#define HP_STATUS2_TCP_FLAG_CHECK 0x00000008 /* tcp flag check */
1199#define HP_STATUS2_SYN_FLAG 0x00000004 /* syn flag */
1200#define HP_STATUS2_TCP_CHECK 0x00000002 /* tcp payload chk */
1201#define HP_STATUS2_TCP_NOCHECK 0x00000001 /* tcp no payload chk */
1202
1203/* BIST for header parser(HP) and flow database memories (FDBM). set _START
1204 * to start BIST. controller clears _START on completion. _START can also
1205 * be cleared to force termination of BIST. a bit set indicates that that
1206 * memory passed its BIST.
1207 */
1208#define REG_HP_RAM_BIST 0x419C /* HP RAM BIST reg */
1209#define HP_RAM_BIST_HP_DATA_PASS 0x80000000 /* HP data ram */
1210#define HP_RAM_BIST_HP_INSTR0_PASS 0x40000000 /* HP instr ram 0 */
1211#define HP_RAM_BIST_HP_INSTR1_PASS 0x20000000 /* HP instr ram 1 */
1212#define HP_RAM_BIST_HP_INSTR2_PASS 0x10000000 /* HP instr ram 2 */
1213#define HP_RAM_BIST_FDBM_AGE0_PASS 0x08000000 /* FDBM aging RAM0 */
1214#define HP_RAM_BIST_FDBM_AGE1_PASS 0x04000000 /* FDBM aging RAM1 */
1215#define HP_RAM_BIST_FDBM_FLOWID00_PASS 0x02000000 /* FDBM flowid RAM0
1216 bank 0 */
1217#define HP_RAM_BIST_FDBM_FLOWID10_PASS 0x01000000 /* FDBM flowid RAM1
1218 bank 0 */
1219#define HP_RAM_BIST_FDBM_FLOWID20_PASS 0x00800000 /* FDBM flowid RAM2
1220 bank 0 */
1221#define HP_RAM_BIST_FDBM_FLOWID30_PASS 0x00400000 /* FDBM flowid RAM3
1222 bank 0 */
1223#define HP_RAM_BIST_FDBM_FLOWID01_PASS 0x00200000 /* FDBM flowid RAM0
1224 bank 1 */
1225#define HP_RAM_BIST_FDBM_FLOWID11_PASS 0x00100000 /* FDBM flowid RAM1
1226 bank 2 */
1227#define HP_RAM_BIST_FDBM_FLOWID21_PASS 0x00080000 /* FDBM flowid RAM2
1228 bank 1 */
1229#define HP_RAM_BIST_FDBM_FLOWID31_PASS 0x00040000 /* FDBM flowid RAM3
1230 bank 1 */
1231#define HP_RAM_BIST_FDBM_TCPSEQ_PASS 0x00020000 /* FDBM tcp sequence
1232 RAM */
1233#define HP_RAM_BIST_SUMMARY 0x00000002 /* all BIST tests */
1234#define HP_RAM_BIST_START 0x00000001 /* start/stop BIST */
1235
1236
1237/** MAC registers. **/
1238/* reset bits are set using a PIO write and self-cleared after the command
1239 * execution has completed.
1240 */
1241#define REG_MAC_TX_RESET 0x6000 /* TX MAC software reset
1242 command (default: 0x0) */
1243#define REG_MAC_RX_RESET 0x6004 /* RX MAC software reset
1244 command (default: 0x0) */
1245/* execute a pause flow control frame transmission
1246 DEFAULT: 0x0XXXX */
1247#define REG_MAC_SEND_PAUSE 0x6008 /* send pause command reg */
1248#define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time
1249 to be sent on network
1250 in units of slot
1251 times */
1252#define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl
1253 frame on network */
1254
1255/* bit set indicates that event occurred. auto-cleared when status register
1256 * is read and have corresponding mask bits in mask register. events will
1257 * trigger an interrupt if the corresponding mask bit is 0.
1258 * status register default: 0x00000000
1259 * mask register default = 0xFFFFFFFF on reset
1260 */
1261#define REG_MAC_TX_STATUS 0x6010 /* TX MAC status reg */
1262#define MAC_TX_FRAME_XMIT 0x0001 /* successful frame
1263 transmision */
1264#define MAC_TX_UNDERRUN 0x0002 /* terminated frame
1265 transmission due to
1266 data starvation in the
1267 xmit data path */
1268#define MAC_TX_MAX_PACKET_ERR 0x0004 /* frame exceeds max allowed
1269 length passed to TX MAC
1270 by the DMA engine */
1271#define MAC_TX_COLL_NORMAL 0x0008 /* rollover of the normal
1272 collision counter */
1273#define MAC_TX_COLL_EXCESS 0x0010 /* rollover of the excessive
1274 collision counter */
1275#define MAC_TX_COLL_LATE 0x0020 /* rollover of the late
1276 collision counter */
1277#define MAC_TX_COLL_FIRST 0x0040 /* rollover of the first
1278 collision counter */
1279#define MAC_TX_DEFER_TIMER 0x0080 /* rollover of the defer
1280 timer */
1281#define MAC_TX_PEAK_ATTEMPTS 0x0100 /* rollover of the peak
1282 attempts counter */
1283
1284#define REG_MAC_RX_STATUS 0x6014 /* RX MAC status reg */
1285#define MAC_RX_FRAME_RECV 0x0001 /* successful receipt of
1286 a frame */
1287#define MAC_RX_OVERFLOW 0x0002 /* dropped frame due to
1288 RX FIFO overflow */
1289#define MAC_RX_FRAME_COUNT 0x0004 /* rollover of receive frame
1290 counter */
1291#define MAC_RX_ALIGN_ERR 0x0008 /* rollover of alignment
1292 error counter */
1293#define MAC_RX_CRC_ERR 0x0010 /* rollover of crc error
1294 counter */
1295#define MAC_RX_LEN_ERR 0x0020 /* rollover of length
1296 error counter */
1297#define MAC_RX_VIOL_ERR 0x0040 /* rollover of code
1298 violation error */
1299
1300/* DEFAULT: 0xXXXX0000 on reset */
1301#define REG_MAC_CTRL_STATUS 0x6018 /* MAC control status reg */
1302#define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful
1303 reception of a
1304 pause control
1305 frame */
1306#define MAC_CTRL_PAUSE_STATE 0x00000002 /* MAC has made a
1307 transition from
1308 "not paused" to
1309 "paused" */
1310#define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* MAC has made a
1311 transition from
1312 "paused" to "not
1313 paused" */
1314#define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time
1315 operand that was
1316 received in the last
1317 pause flow control
1318 frame */
1319
1320/* layout identical to TX MAC[8:0] */
1321#define REG_MAC_TX_MASK 0x6020 /* TX MAC mask reg */
1322/* layout identical to RX MAC[6:0] */
1323#define REG_MAC_RX_MASK 0x6024 /* RX MAC mask reg */
1324/* layout identical to CTRL MAC[2:0] */
1325#define REG_MAC_CTRL_MASK 0x6028 /* MAC control mask reg */
1326
1327/* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
1328 * imposed before writes to other bits in the TX_MAC_CFG register or any of
1329 * the MAC parameters is performed. delay dependent upon time required to
1330 * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g.,
1331 * the delay for a 1518-byte frame on a 100Mbps network is 125us.
1332 * alternatively, just poll TX_CFG_EN until it reads back as 0.
1333 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
1334 * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should
1335 * be 0x200 (slot time of 512 bytes)
1336 */
1337#define REG_MAC_TX_CFG 0x6030 /* TX MAC config reg */
1338#define MAC_TX_CFG_EN 0x0001 /* enable TX MAC. 0 will
1339 force TXMAC state
1340 machine to remain in
1341 idle state or to
1342 transition to idle state
1343 on completion of an
1344 ongoing packet. */
1345#define MAC_TX_CFG_IGNORE_CARRIER 0x0002 /* disable CSMA/CD deferral
1346 process. set to 1 when
1347 full duplex and 0 when
1348 half duplex */
1349#define MAC_TX_CFG_IGNORE_COLL 0x0004 /* disable CSMA/CD backoff
1350 algorithm. set to 1 when
1351 full duplex and 0 when
1352 half duplex */
1353#define MAC_TX_CFG_IPG_EN 0x0008 /* enable extension of the
1354 Rx-to-TX IPG. after
1355 receiving a frame, TX
1356 MAC will reset its
1357 deferral process to
1358 carrier sense for the
1359 amount of time = IPG0 +
1360 IPG1 and commit to
1361 transmission for time
1362 specified in IPG2. when
1363 0 or when xmitting frames
1364 back-to-pack (Tx-to-Tx
1365 IPG), TX MAC ignores
1366 IPG0 and will only use
1367 IPG1 for deferral time.
1368 IPG2 still used. */
1369#define MAC_TX_CFG_NEVER_GIVE_UP_EN 0x0010 /* TX MAC will not easily
1370 give up on frame
1371 xmission. if backoff
1372 algorithm reaches the
1373 ATTEMPT_LIMIT, it will
1374 clear attempts counter
1375 and continue trying to
1376 send the frame as
1377 specified by
1378 GIVE_UP_LIM. when 0,
1379 TX MAC will execute
1380 standard CSMA/CD prot. */
1381#define MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020 /* when set, TX MAC will
1382 continue to try to xmit
1383 until successful. when
1384 0, TX MAC will continue
1385 to try xmitting until
1386 successful or backoff
1387 algorithm reaches
1388 ATTEMPT_LIMIT*16 */
1389#define MAC_TX_CFG_NO_BACKOFF 0x0040 /* modify CSMA/CD to disable
1390 backoff algorithm. TX
1391 MAC will not back off
1392 after a xmission attempt
1393 that resulted in a
1394 collision. */
1395#define MAC_TX_CFG_SLOW_DOWN 0x0080 /* modify CSMA/CD so that
1396 deferral process is reset
1397 in response to carrier
1398 sense during the entire
1399 duration of IPG. TX MAC
1400 will only commit to frame
1401 xmission after frame
1402 xmission has actually
1403 begun. */
1404#define MAC_TX_CFG_NO_FCS 0x0100 /* TX MAC will not generate
1405 CRC for all xmitted
1406 packets. when clear, CRC
1407 generation is dependent
1408 upon NO_CRC bit in the
1409 xmit control word from
1410 TX DMA */
1411#define MAC_TX_CFG_CARRIER_EXTEND 0x0200 /* enables xmit part of the
1412 carrier extension
1413 feature. this allows for
1414 longer collision domains
1415 by extending the carrier
1416 and collision window
1417 from the end of FCS until
1418 the end of the slot time
1419 if necessary. Required
1420 for half-duplex at 1Gbps,
1421 clear otherwise. */
1422
1423/* when CRC is not stripped, reassembly packets will not contain the CRC.
1424 * these will be stripped by HRP because it reassembles layer 4 data, and the
1425 * CRC is layer 2. however, non-reassembly packets will still contain the CRC
1426 * when passed to the host. to ensure proper operation, need to wait 3.2ms
1427 * after clearing RX_CFG_EN before writing to any other RX MAC registers
1428 * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears
1429 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
1430 * restrictions as CFG_EN.
1431 */
1432#define REG_MAC_RX_CFG 0x6034 /* RX MAC config reg */
1433#define MAC_RX_CFG_EN 0x0001 /* enable RX MAC */
1434#define MAC_RX_CFG_STRIP_PAD 0x0002 /* always program to 0.
1435 feature not supported */
1436#define MAC_RX_CFG_STRIP_FCS 0x0004 /* RX MAC will strip the
1437 last 4 bytes of a
1438 received frame. */
1439#define MAC_RX_CFG_PROMISC_EN 0x0008 /* promiscuous mode */
1440#define MAC_RX_CFG_PROMISC_GROUP_EN 0x0010 /* accept all valid
1441 multicast frames (group
1442 bit in DA field set) */
1443#define MAC_RX_CFG_HASH_FILTER_EN 0x0020 /* use hash table to filter
1444 multicast addresses */
1445#define MAC_RX_CFG_ADDR_FILTER_EN 0x0040 /* cause RX MAC to use
1446 address filtering regs
1447 to filter both unicast
1448 and multicast
1449 addresses */
1450#define MAC_RX_CFG_DISABLE_DISCARD 0x0080 /* pass errored frames to
1451 RX DMA by setting BAD
1452 bit but not Abort bit
1453 in the status. CRC,
1454 framing, and length errs
1455 will not increment
1456 error counters. frames
1457 which don't match dest
1458 addr will be passed up
1459 w/ BAD bit set. */
1460#define MAC_RX_CFG_CARRIER_EXTEND 0x0100 /* enable reception of
1461 packet bursts generated
1462 by carrier extension
1463 with packet bursting
1464 senders. only applies
1465 to half-duplex 1Gbps */
1466
1467/* DEFAULT: 0x0 */
1468#define REG_MAC_CTRL_CFG 0x6038 /* MAC control config reg */
1469#define MAC_CTRL_CFG_SEND_PAUSE_EN 0x0001 /* respond to requests for
1470 sending pause flow ctrl
1471 frames */
1472#define MAC_CTRL_CFG_RECV_PAUSE_EN 0x0002 /* respond to received
1473 pause flow ctrl frames */
1474#define MAC_CTRL_CFG_PASS_CTRL 0x0004 /* pass valid MAC ctrl
1475 packets to RX DMA */
1476
1477/* to ensure proper operation, a global initialization sequence should be
1478 * performed when a loopback config is entered or exited. if programmed after
1479 * a hw or global sw reset, RX/TX MAC software reset and initialization
1480 * should be done to ensure stable clocking.
1481 * DEFAULT: 0x0
1482 */
1483#define REG_MAC_XIF_CFG 0x603C /* XIF config reg */
1484#define MAC_XIF_TX_MII_OUTPUT_EN 0x0001 /* enable output drivers
1485 on MII xmit bus */
1486#define MAC_XIF_MII_INT_LOOPBACK 0x0002 /* loopback GMII xmit data
1487 path to GMII recv data
1488 path. phy mode register
1489 clock selection must be
1490 set to GMII mode and
1491 GMII_MODE should be set
1492 to 1. in loopback mode,
1493 REFCLK will drive the
1494 entire mac core. 0 for
1495 normal operation. */
1496#define MAC_XIF_DISABLE_ECHO 0x0004 /* disables receive data
1497 path during packet
1498 xmission. clear to 0
1499 in any full duplex mode,
1500 in any loopback mode,
1501 or in half-duplex SERDES
1502 or SLINK modes. set when
1503 in half-duplex when
1504 using external phy. */
1505#define MAC_XIF_GMII_MODE 0x0008 /* MAC operates with GMII
1506 clocks and datapath */
1507#define MAC_XIF_MII_BUFFER_OUTPUT_EN 0x0010 /* MII_BUF_EN pin. enable
1508 external tristate buffer
1509 on the MII receive
1510 bus. */
1511#define MAC_XIF_LINK_LED 0x0020 /* LINKLED# active (low) */
1512#define MAC_XIF_FDPLX_LED 0x0040 /* FDPLXLED# active (low) */
1513
1514#define REG_MAC_IPG0 0x6040 /* inter-packet gap0 reg.
1515 recommended: 0x00 */
1516#define REG_MAC_IPG1 0x6044 /* inter-packet gap1 reg
1517 recommended: 0x08 */
1518#define REG_MAC_IPG2 0x6048 /* inter-packet gap2 reg
1519 recommended: 0x04 */
1520#define REG_MAC_SLOT_TIME 0x604C /* slot time reg
1521 recommended: 0x40 */
1522#define REG_MAC_FRAMESIZE_MIN 0x6050 /* min frame size reg
1523 recommended: 0x40 */
1524
1525/* FRAMESIZE_MAX holds both the max frame size as well as the max burst size.
1526 * recommended value: 0x2000.05EE
1527 */
1528#define REG_MAC_FRAMESIZE_MAX 0x6054 /* max frame size reg */
1529#define MAC_FRAMESIZE_MAX_BURST_MASK 0x3FFF0000 /* max burst size */
1530#define MAC_FRAMESIZE_MAX_BURST_SHIFT 16
1531#define MAC_FRAMESIZE_MAX_FRAME_MASK 0x00007FFF /* max frame size */
1532#define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0
1533#define REG_MAC_PA_SIZE 0x6058 /* PA size reg. number of
1534 preamble bytes that the
1535 TX MAC will xmit at the
1536 beginning of each frame
1537 value should be 2 or
1538 greater. recommended
1539 value: 0x07 */
1540#define REG_MAC_JAM_SIZE 0x605C /* jam size reg. duration
1541 of jam in units of media
1542 byte time. recommended
1543 value: 0x04 */
1544#define REG_MAC_ATTEMPT_LIMIT 0x6060 /* attempt limit reg. #
1545 of attempts TX MAC will
1546 make to xmit a frame
1547 before it resets its
1548 attempts counter. after
1549 the limit has been
1550 reached, TX MAC may or
1551 may not drop the frame
1552 dependent upon value
1553 in TX_MAC_CFG.
1554 recommended
1555 value: 0x10 */
1556#define REG_MAC_CTRL_TYPE 0x6064 /* MAC control type reg.
1557 type field of a MAC
1558 ctrl frame. recommended
1559 value: 0x8808 */
1560
1561/* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1562 * register contains comparison
1563 * 0 16 MSB of primary MAC addr [47:32] of DA field
1564 * 1 16 middle bits "" [31:16] of DA field
1565 * 2 16 LSB "" [15:0] of DA field
1566 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field
1567 * 4*x 16 middle bits "" [31:16]
1568 * 5*x 16 LSB "" [15:0]
1569 * 42 16 MSB of MAC CTRL addr [47:32] of DA.
1570 * 43 16 middle bits "" [31:16]
1571 * 44 16 LSB "" [15:0]
1572 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
1573 * if there is a match, MAC will set the bit for alternative address
1574 * filter pass [15]
1575
1576 * here is the map of registers given MAC address notation: a:b:c:d:e:f
1577 * ab cd ef
1578 * primary addr reg 2 reg 1 reg 0
1579 * alt addr 1 reg 5 reg 4 reg 3
1580 * alt addr x reg 5*x reg 4*x reg 3*x
1581 * ctrl addr reg 44 reg 43 reg 42
1582 */
1583#define REG_MAC_ADDR0 0x6080 /* MAC address 0 reg */
1584#define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4)
1585#define REG_MAC_ADDR_FILTER0 0x614C /* address filter 0 reg
1586 [47:32] */
1587#define REG_MAC_ADDR_FILTER1 0x6150 /* address filter 1 reg
1588 [31:16] */
1589#define REG_MAC_ADDR_FILTER2 0x6154 /* address filter 2 reg
1590 [15:0] */
1591#define REG_MAC_ADDR_FILTER2_1_MASK 0x6158 /* address filter 2 and 1
1592 mask reg. 8-bit reg
1593 contains nibble mask for
1594 reg 2 and 1. */
1595#define REG_MAC_ADDR_FILTER0_MASK 0x615C /* address filter 0 mask
1596 reg */
1597
1598/* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1599 * 16-bit registers contain bits of the hash table.
1600 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)].
1601 * e.g., 15 -> [15:0], 0 -> [255:240]
1602 */
1603#define REG_MAC_HASH_TABLE0 0x6160 /* hash table 0 reg */
1604#define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4)
1605
1606/* statistics registers. these registers generate an interrupt on
1607 * overflow. recommended initialization: 0x0000. most are 16-bits except
1608 * for PEAK_ATTEMPTS register which is 8 bits.
1609 */
1610#define REG_MAC_COLL_NORMAL 0x61A0 /* normal collision
1611 counter. */
1612#define REG_MAC_COLL_FIRST 0x61A4 /* first attempt
1613 successful collision
1614 counter */
1615#define REG_MAC_COLL_EXCESS 0x61A8 /* excessive collision
1616 counter */
1617#define REG_MAC_COLL_LATE 0x61AC /* late collision counter */
1618#define REG_MAC_TIMER_DEFER 0x61B0 /* defer timer. time base
1619 is the media byte
1620 clock/256 */
1621#define REG_MAC_ATTEMPTS_PEAK 0x61B4 /* peak attempts reg */
1622#define REG_MAC_RECV_FRAME 0x61B8 /* receive frame counter */
1623#define REG_MAC_LEN_ERR 0x61BC /* length error counter */
1624#define REG_MAC_ALIGN_ERR 0x61C0 /* alignment error counter */
1625#define REG_MAC_FCS_ERR 0x61C4 /* FCS error counter */
1626#define REG_MAC_RX_CODE_ERR 0x61C8 /* RX code violation
1627 error counter */
1628
1629/* misc registers */
1630#define REG_MAC_RANDOM_SEED 0x61CC /* random number seed reg.
1631 10-bit register used as a
1632 seed for the random number
1633 generator for the CSMA/CD
1634 backoff algorithm. only
1635 programmed after power-on
1636 reset and should be a
1637 random value which has a
1638 high likelihood of being
1639 unique for each MAC
1640 attached to a network
1641 segment (e.g., 10 LSB of
1642 MAC address) */
1643
1644/* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address
1645 * map
1646 */
1647
1648/* 27-bit register has the current state for key state machines in the MAC */
1649#define REG_MAC_STATE_MACHINE 0x61D0 /* (ro) state machine reg */
1650#define MAC_SM_RLM_MASK 0x07800000
1651#define MAC_SM_RLM_SHIFT 23
1652#define MAC_SM_RX_FC_MASK 0x00700000
1653#define MAC_SM_RX_FC_SHIFT 20
1654#define MAC_SM_TLM_MASK 0x000F0000
1655#define MAC_SM_TLM_SHIFT 16
1656#define MAC_SM_ENCAP_SM_MASK 0x0000F000
1657#define MAC_SM_ENCAP_SM_SHIFT 12
1658#define MAC_SM_TX_REQ_MASK 0x00000C00
1659#define MAC_SM_TX_REQ_SHIFT 10
1660#define MAC_SM_TX_FC_MASK 0x000003C0
1661#define MAC_SM_TX_FC_SHIFT 6
1662#define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
1663#define MAC_SM_FIFO_WRITE_SEL_SHIFT 3
1664#define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
1665#define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
1666
1667/** MIF registers. the MIF can be programmed in either bit-bang or
1668 * frame mode.
1669 **/
1670#define REG_MIF_BIT_BANG_CLOCK 0x6200 /* MIF bit-bang clock.
1671 1 -> 0 will generate a
1672 rising edge. 0 -> 1 will
1673 generate a falling edge. */
1674#define REG_MIF_BIT_BANG_DATA 0x6204 /* MIF bit-bang data. 1-bit
1675 register generates data */
1676#define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208 /* MIF bit-bang output
1677 enable. enable when
1678 xmitting data from MIF to
1679 transceiver. */
1680
1681/* 32-bit register serves as an instruction register when the MIF is
1682 * programmed in frame mode. load this register w/ a valid instruction
1683 * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1684 * execution completion. during a read operation, this register will also
1685 * contain the 16-bit data returned by the tranceiver. unless specified
1686 * otherwise, fields are considered "don't care" when polling for
1687 * completion.
1688 */
1689#define REG_MIF_FRAME 0x620C /* MIF frame/output reg */
1690#define MIF_FRAME_START_MASK 0xC0000000 /* start of frame.
1691 load w/ 01 when
1692 issuing an instr */
1693#define MIF_FRAME_ST 0x40000000 /* STart of frame */
1694#define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode. 01 for a
1695 write. 10 for a
1696 read */
1697#define MIF_FRAME_OP_READ 0x20000000 /* read OPcode */
1698#define MIF_FRAME_OP_WRITE 0x10000000 /* write OPcode */
1699#define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address. when
1700 issuing an instr,
1701 this field should be
1702 loaded w/ the XCVR
1703 addr */
1704#define MIF_FRAME_PHY_ADDR_SHIFT 23
1705#define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* register address.
1706 when issuing an instr,
1707 addr of register
1708 to be read/written */
1709#define MIF_FRAME_REG_ADDR_SHIFT 18
1710#define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB.
1711 when issuing an instr,
1712 set this bit to 1 */
1713#define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB.
1714 when issuing an instr,
1715 set this bit to 0.
1716 when polling for
1717 completion, 1 means
1718 that instr execution
1719 has been completed */
1720#define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload
1721 load with 16-bit data
1722 to be written in
1723 transceiver reg for a
1724 write. doesn't matter
1725 in a read. when
1726 polling for
1727 completion, field is
1728 "don't care" for write
1729 and 16-bit data
1730 returned by the
1731 transceiver for a
1732 read (if valid bit
1733 is set) */
1734#define REG_MIF_CFG 0x6210 /* MIF config reg */
1735#define MIF_CFG_PHY_SELECT 0x0001 /* 1 -> select MDIO_1
1736 0 -> select MDIO_0 */
1737#define MIF_CFG_POLL_EN 0x0002 /* enable polling
1738 mechanism. if set,
1739 BB_MODE should be 0 */
1740#define MIF_CFG_BB_MODE 0x0004 /* 1 -> bit-bang mode
1741 0 -> frame mode */
1742#define MIF_CFG_POLL_REG_MASK 0x00F8 /* register address to be
1743 used by polling mode.
1744 only meaningful if POLL_EN
1745 is set to 1 */
1746#define MIF_CFG_POLL_REG_SHIFT 3
1747#define MIF_CFG_MDIO_0 0x0100 /* (ro) dual purpose.
1748 when MDIO_0 is idle,
1749 1 -> tranceiver is
1750 connected to MDIO_0.
1751 when MIF is communicating
1752 w/ MDIO_0 in bit-bang
1753 mode, this bit indicates
1754 the incoming bit stream
1755 during a read op */
1756#define MIF_CFG_MDIO_1 0x0200 /* (ro) dual purpose.
1757 when MDIO_1 is idle,
1758 1 -> transceiver is
1759 connected to MDIO_1.
1760 when MIF is communicating
1761 w/ MDIO_1 in bit-bang
1762 mode, this bit indicates
1763 the incoming bit stream
1764 during a read op */
1765#define MIF_CFG_POLL_PHY_MASK 0x7C00 /* tranceiver address to
1766 be polled */
1767#define MIF_CFG_POLL_PHY_SHIFT 10
1768
1769/* 16-bit register used to determine which bits in the POLL_STATUS portion of
1770 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
1771 * corresponding bit of the POLL_STATUS will generate a MIF interrupt when
1772 * set. DEFAULT: 0xFFFF
1773 */
1774#define REG_MIF_MASK 0x6214 /* MIF mask reg */
1775
1776/* 32-bit register used when in poll mode. auto-cleared after being read */
1777#define REG_MIF_STATUS 0x6218 /* MIF status reg */
1778#define MIF_STATUS_POLL_DATA_MASK 0xFFFF0000 /* poll data contains
1779 the "latest image"
1780 update of the XCVR
1781 reg being read */
1782#define MIF_STATUS_POLL_DATA_SHIFT 16
1783#define MIF_STATUS_POLL_STATUS_MASK 0x0000FFFF /* poll status indicates
1784 which bits in the
1785 POLL_DATA field have
1786 changed since the
1787 MIF_STATUS reg was
1788 last read */
1789#define MIF_STATUS_POLL_STATUS_SHIFT 0
1790
1791/* 7-bit register has current state for all state machines in the MIF */
1792#define REG_MIF_STATE_MACHINE 0x621C /* MIF state machine reg */
1793#define MIF_SM_CONTROL_MASK 0x07 /* control state machine
1794 state */
1795#define MIF_SM_EXECUTION_MASK 0x60 /* execution state machine
1796 state */
1797
1798/** PCS/Serialink. the following registers are equivalent to the standard
1799 * MII management registers except that they're directly mapped in
1800 * Cassini's register space.
1801 **/
1802
1803/* the auto-negotiation enable bit should be programmed the same at
1804 * the link partner as in the local device to enable auto-negotiation to
1805 * complete. when that bit is reprogrammed, auto-neg/manual config is
1806 * restarted automatically.
1807 * DEFAULT: 0x1040
1808 */
1809#define REG_PCS_MII_CTRL 0x9000 /* PCS MII control reg */
1810#define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on
1811 writes */
1812#define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal at the PCS
1813 to MAC interface is
1814 activated regardless
1815 of activity */
1816#define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. PCS
1817 behaviour same for
1818 half and full dplx */
1819#define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing.
1820 restart auto-
1821 negotiation */
1822#define PCS_MII_ISOLATE 0x0400 /* read as 0. ignored
1823 on writes */
1824#define PCS_MII_POWER_DOWN 0x0800 /* read as 0. ignored
1825 on writes */
1826#define PCS_MII_AUTONEG_EN 0x1000 /* default 1. PCS goes
1827 through automatic
1828 link config before it
1829 can be used. when 0,
1830 link can be used
1831 w/out any link config
1832 phase */
1833#define PCS_MII_10_100_SEL 0x2000 /* read as 0. ignored on
1834 writes */
1835#define PCS_MII_RESET 0x8000 /* reset PCS. self-clears
1836 when done */
1837
1838/* DEFAULT: 0x0108 */
1839#define REG_PCS_MII_STATUS 0x9004 /* PCS MII status reg */
1840#define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */
1841#define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */
1842#define PCS_MII_STATUS_LINK_STATUS 0x0004 /* 1 -> link up.
1843 0 -> link down. 0 is
1844 latched so that 0 is
1845 kept until read. read
1846 2x to determine if the
1847 link has gone up again */
1848#define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 (able to perform
1849 auto-neg) */
1850#define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* 1 -> remote fault detected
1851 from received link code
1852 word. only valid after
1853 auto-neg completed */
1854#define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* 1 -> auto-negotiation
1855 completed
1856 0 -> auto-negotiation not
1857 completed */
1858#define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* reads as 1. used as an
1859 indication that this is
1860 a 1000 Base-X PHY. writes
1861 to it are ignored */
1862
1863/* used during auto-negotiation.
1864 * DEFAULT: 0x00E0
1865 */
1866#define REG_PCS_MII_ADVERT 0x9008 /* PCS MII advertisement
1867 reg */
1868#define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex
1869 1000 Base-X */
1870#define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex
1871 1000 Base-X */
1872#define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE
1873 symmetric capability */
1874#define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE
1875 asymmetric capability */
1876#define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault. write bit13
1877 to optionally indicate to
1878 link partner that chip is
1879 going off-line. bit12 will
1880 get set when signal
1881 detect == FAIL and will
1882 remain set until
1883 successful negotiation */
1884#define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */
1885#define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */
1886
1887/* contents updated as a result of autonegotiation. layout and definitions
1888 * identical to PCS_MII_ADVERT
1889 */
1890#define REG_PCS_MII_LPA 0x900C /* PCS MII link partner
1891 ability reg */
1892#define PCS_MII_LPA_FD PCS_MII_ADVERT_FD
1893#define PCS_MII_LPA_HD PCS_MII_ADVERT_HD
1894#define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE
1895#define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE
1896#define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK
1897#define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK
1898#define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE
1899
1900/* DEFAULT: 0x0 */
1901#define REG_PCS_CFG 0x9010 /* PCS config reg */
1902#define PCS_CFG_EN 0x01 /* enable PCS. must be
1903 0 when modifying
1904 PCS_MII_ADVERT */
1905#define PCS_CFG_SD_OVERRIDE 0x02 /* sets signal detect to
1906 OK. bit is
1907 non-resettable */
1908#define PCS_CFG_SD_ACTIVE_LOW 0x04 /* changes interpretation
1909 of optical signal to make
1910 signal detect okay when
1911 signal is low */
1912#define PCS_CFG_JITTER_STUDY_MASK 0x18 /* used to make jitter
1913 measurements. a single
1914 code group is xmitted
1915 regularly.
1916 0x0 = normal operation
1917 0x1 = high freq test
1918 pattern, D21.5
1919 0x2 = low freq test
1920 pattern, K28.7
1921 0x3 = reserved */
1922#define PCS_CFG_10MS_TIMER_OVERRIDE 0x20 /* shortens 10-20ms auto-
1923 negotiation timer to
1924 a few cycles for test
1925 purposes */
1926
1927/* used for diagnostic purposes. bits 20-22 autoclear on read */
1928#define REG_PCS_STATE_MACHINE 0x9014 /* (ro) PCS state machine
1929 and diagnostic reg */
1930#define PCS_SM_TX_STATE_MASK 0x0000000F /* 0 and 1 indicate
1931 xmission of idle.
1932 otherwise, xmission of
1933 a packet */
1934#define PCS_SM_RX_STATE_MASK 0x000000F0 /* 0 indicates reception
1935 of idle. otherwise,
1936 reception of packet */
1937#define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* 0 indicates loss of
1938 sync */
1939#define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* cycling through 0-3
1940 indicates reception of
1941 Config codes. cycling
1942 through 0-1 indicates
1943 reception of idles */
1944#define PCS_SM_LINK_STATE_MASK 0x0001E000
1945#define SM_LINK_STATE_UP 0x00016000 /* link state is up */
1946
1947#define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link due to
1948 recept of Config
1949 codes */
1950#define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of link due to
1951 loss of sync */
1952#define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect goes
1953 from OK to FAIL. bit29
1954 will also be set if
1955 this is set */
1956#define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* link not up due to
1957 receipt of breaklink
1958 C codes from partner.
1959 C codes w/ 0 content
1960 received triggering
1961 start/restart of
1962 autonegotiation.
1963 should be sent for
1964 no longer than 20ms */
1965#define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes being
1966 initialized. see serdes
1967 state reg */
1968#define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable or
1969 not received */
1970#define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not
1971 achieved */
1972#define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes
1973 w/ ack bit set */
1974#define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* link partner continues
1975 to send C codes
1976 instead of idle
1977 symbols or pkt data */
1978
1979/* this register indicates interrupt changes in specific PCS MII status bits.
1980 * PCS_INT may be masked at the ISR level. only a single bit is implemented
1981 * for link status change.
1982 */
1983#define REG_PCS_INTR_STATUS 0x9018 /* PCS interrupt status */
1984#define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed
1985 since last read */
1986
1987/* control which network interface is used. no more than one bit should
1988 * be set.
1989 * DEFAULT: none
1990 */
1991#define REG_PCS_DATAPATH_MODE 0x9050 /* datapath mode reg */
1992#define PCS_DATAPATH_MODE_MII 0x00 /* PCS is not used and
1993 MII/GMII is selected.
1994 selection between MII and
1995 GMII is controlled by
1996 XIF_CFG */
1997#define PCS_DATAPATH_MODE_SERDES 0x02 /* PCS is used via the
1998 10-bit interface */
1999
2000/* input to serdes chip or serialink block */
2001#define REG_PCS_SERDES_CTRL 0x9054 /* serdes control reg */
2002#define PCS_SERDES_CTRL_LOOPBACK 0x01 /* enable loopback on
2003 serdes interface */
2004#define PCS_SERDES_CTRL_SYNCD_EN 0x02 /* enable sync carrier
2005 detection. should be
2006 0x0 for normal
2007 operation */
2008#define PCS_SERDES_CTRL_LOCKREF 0x04 /* frequency-lock RBC[0:1]
2009 to REFCLK when set.
2010 when clear, receiver
2011 clock locks to incoming
2012 serial data */
2013
2014/* multiplex test outputs into the PROM address (PA_3 through PA_0) pins.
2015 * should be 0x0 for normal operations.
2016 * 0b000 normal operation, PROM address[3:0] selected
2017 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read
2018 * 0b010 rxmac req, rx ack, rx tag, rx clk shared
2019 * 0b011 txmac req, tx ack, tx tag, tx retry req
2020 * 0b100 tx tp3, tx tp2, tx tp1, tx tp0
2021 * 0b101 R period RX, R period TX, R period HP, R period BIM
2022 * DEFAULT: 0x0
2023 */
2024#define REG_PCS_SHARED_OUTPUT_SEL 0x9058 /* shared output select */
2025#define PCS_SOS_PROM_ADDR_MASK 0x0007
2026
2027/* used for diagnostics. this register indicates progress of the SERDES
2028 * boot up.
2029 * 0b00 undergoing reset
2030 * 0b01 waiting 500us while lockrefn is asserted
2031 * 0b10 waiting for comma detect
2032 * 0b11 receive data is synchronized
2033 * DEFAULT: 0x0
2034 */
2035#define REG_PCS_SERDES_STATE 0x905C /* (ro) serdes state */
2036#define PCS_SERDES_STATE_MASK 0x03
2037
2038/* used for diagnostics. indicates number of packets transmitted or received.
2039 * counters rollover w/out generating an interrupt.
2040 * DEFAULT: 0x0
2041 */
2042#define REG_PCS_PACKET_COUNT 0x9060 /* (ro) PCS packet counter */
2043#define PCS_PACKET_COUNT_TX 0x000007FF /* pkts xmitted by PCS */
2044#define PCS_PACKET_COUNT_RX 0x07FF0000 /* pkts recvd by PCS
2045 whether they
2046 encountered an error
2047 or not */
2048
2049/** LocalBus Devices. the following provides run-time access to the
2050 * Cassini's PROM
2051 ***/
2052#define REG_EXPANSION_ROM_RUN_START 0x100000 /* expansion rom run time
2053 access */
2054#define REG_EXPANSION_ROM_RUN_END 0x17FFFF
2055
2056#define REG_SECOND_LOCALBUS_START 0x180000 /* secondary local bus
2057 device */
2058#define REG_SECOND_LOCALBUS_END 0x1FFFFF
2059
2060/* entropy device */
2061#define REG_ENTROPY_START REG_SECOND_LOCALBUS_START
2062#define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00)
2063#define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04)
2064#define ENTROPY_STATUS_DRDY 0x01
2065#define ENTROPY_STATUS_BUSY 0x02
2066#define ENTROPY_STATUS_CIPHER 0x04
2067#define ENTROPY_STATUS_BYPASS_MASK 0x18
2068#define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05)
2069#define ENTROPY_MODE_KEY_MASK 0x07
2070#define ENTROPY_MODE_ENCRYPT 0x40
2071#define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06)
2072#define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07)
2073#define ENTROPY_RESET_DES_IO 0x01
2074#define ENTROPY_RESET_STC_MODE 0x02
2075#define ENTROPY_RESET_KEY_CACHE 0x04
2076#define ENTROPY_RESET_IV 0x08
2077#define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08)
2078#define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10)
2079#define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x))
2080
2081/* phys of interest w/ their special mii registers */
2082#define PHY_LUCENT_B0 0x00437421
2083#define LUCENT_MII_REG 0x1F
2084
2085#define PHY_NS_DP83065 0x20005c78
2086#define DP83065_MII_MEM 0x16
2087#define DP83065_MII_REGD 0x1D
2088#define DP83065_MII_REGE 0x1E
2089
2090#define PHY_BROADCOM_5411 0x00206071
2091#define PHY_BROADCOM_B0 0x00206050
2092#define BROADCOM_MII_REG4 0x14
2093#define BROADCOM_MII_REG5 0x15
2094#define BROADCOM_MII_REG7 0x17
2095#define BROADCOM_MII_REG8 0x18
2096
2097#define CAS_MII_ANNPTR 0x07
2098#define CAS_MII_ANNPRR 0x08
2099#define CAS_MII_1000_CTRL 0x09
2100#define CAS_MII_1000_STATUS 0x0A
2101#define CAS_MII_1000_EXTEND 0x0F
2102
2103#define CAS_BMSR_1000_EXTEND 0x0100 /* supports 1000Base-T extended status */
2104/*
2105 * if autoneg is disabled, here's the table:
2106 * BMCR_SPEED100 = 100Mbps
2107 * BMCR_SPEED1000 = 1000Mbps
2108 * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps
2109 */
2110#define CAS_BMCR_SPEED1000 0x0040 /* Select 1000Mbps */
2111
2112#define CAS_ADVERTISE_1000HALF 0x0100
2113#define CAS_ADVERTISE_1000FULL 0x0200
2114#define CAS_ADVERTISE_PAUSE 0x0400
2115#define CAS_ADVERTISE_ASYM_PAUSE 0x0800
2116
2117/* regular lpa register */
2118#define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE
2119#define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE
2120
2121/* 1000_STATUS register */
2122#define CAS_LPA_1000HALF 0x0400
2123#define CAS_LPA_1000FULL 0x0800
2124
2125#define CAS_EXTEND_1000XFULL 0x8000
2126#define CAS_EXTEND_1000XHALF 0x4000
2127#define CAS_EXTEND_1000TFULL 0x2000
2128#define CAS_EXTEND_1000THALF 0x1000
2129
2130/* cassini header parser firmware */
2131typedef struct cas_hp_inst {
2132 const char *note;
2133
2134 u16 mask, val;
2135
2136 u8 op;
2137 u8 soff, snext; /* if match succeeds, new offset and match */
2138 u8 foff, fnext; /* if match fails, new offset and match */
2139 /* output info */
2140 u8 outop; /* output opcode */
2141
2142 u16 outarg; /* output argument */
2143 u8 outenab; /* output enable: 0 = not, 1 = if match
2144 2 = if !match, 3 = always */
2145 u8 outshift; /* barrel shift right, 4 bits */
2146 u16 outmask;
2147} cas_hp_inst_t;
2148
2149/* comparison */
2150#define OP_EQ 0 /* packet == value */
2151#define OP_LT 1 /* packet < value */
2152#define OP_GT 2 /* packet > value */
2153#define OP_NP 3 /* new packet */
2154
2155/* output opcodes */
2156#define CL_REG 0
2157#define LD_FID 1
2158#define LD_SEQ 2
2159#define LD_CTL 3
2160#define LD_SAP 4
2161#define LD_R1 5
2162#define LD_L3 6
2163#define LD_SUM 7
2164#define LD_HDR 8
2165#define IM_FID 9
2166#define IM_SEQ 10
2167#define IM_SAP 11
2168#define IM_R1 12
2169#define IM_CTL 13
2170#define LD_LEN 14
2171#define ST_FLG 15
2172
2173/* match setp #s for IP4TCP4 */
2174#define S1_PCKT 0
2175#define S1_VLAN 1
2176#define S1_CFI 2
2177#define S1_8023 3
2178#define S1_LLC 4
2179#define S1_LLCc 5
2180#define S1_IPV4 6
2181#define S1_IPV4c 7
2182#define S1_IPV4F 8
2183#define S1_TCP44 9
2184#define S1_IPV6 10
2185#define S1_IPV6L 11
2186#define S1_IPV6c 12
2187#define S1_TCP64 13
2188#define S1_TCPSQ 14
2189#define S1_TCPFG 15
2190#define S1_TCPHL 16
2191#define S1_TCPHc 17
2192#define S1_CLNP 18
2193#define S1_CLNP2 19
2194#define S1_DROP 20
2195#define S2_HTTP 21
2196#define S1_ESP4 22
2197#define S1_AH4 23
2198#define S1_ESP6 24
2199#define S1_AH6 25
2200
2201#define CAS_PROG_IP46TCP4_PREAMBLE \
2202{ "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, \
2203 CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
2204{ "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, \
2205 IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
2206{ "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, \
2207 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2208{ "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, \
2209 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2210{ "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, \
2211 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2212{ "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
2213 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2214{ "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, \
2215 LD_SAP, 0x100, 3, 0x0, 0xffff}, \
2216{ "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, \
2217 LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
2218{ "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, \
2219 LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
2220{ "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, \
2221 LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ \
2222{ "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, \
2223 LD_SUM, 0x015, 1, 0x0, 0x0000}, \
2224{ "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, \
2225 IM_R1, 0x128, 1, 0x0, 0xffff}, \
2226{ "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, \
2227 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ \
2228{ "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, \
2229 LD_LEN, 0x03f, 1, 0x0, 0xffff}
2230
2231#ifdef USE_HP_IP46TCP4
2232static cas_hp_inst_t cas_prog_ip46tcp4tab[] = {
2233 CAS_PROG_IP46TCP4_PREAMBLE,
2234 { "TCP seq", /* DADDR should point to dest port */
2235 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2236 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2237 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2238 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
2239 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2240 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2241 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2242 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2243 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2244 IM_CTL, 0x001, 3, 0x0, 0x0001},
2245 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2246 IM_CTL, 0x000, 0, 0x0, 0x0000},
2247 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2248 IM_CTL, 0x080, 3, 0x0, 0xffff},
2249 { NULL },
2250};
2251#ifdef HP_IP46TCP4_DEFAULT
2252#define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab
2253#endif
2254#endif
2255
2256/*
2257 * Alternate table load which excludes HTTP server traffic from reassembly.
2258 * It is substantially similar to the basic table, with one extra state
2259 * and a few extra compares. */
2260#ifdef USE_HP_IP46TCP4NOHTTP
2261static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = {
2262 CAS_PROG_IP46TCP4_PREAMBLE,
2263 { "TCP seq", /* DADDR should point to dest port */
2264 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2265 0x081, 3, 0x0, 0xffff} , /* Load TCP seq # */
2266 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2267 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, }, /* Load TCP flags */
2268 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2269 LD_R1, 0x205, 3, 0xB, 0xf000},
2270 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2271 LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2272 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2273 IM_CTL, 0x001, 3, 0x0, 0x0001},
2274 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2275 CL_REG, 0x002, 3, 0x0, 0x0000},
2276 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2277 IM_CTL, 0x080, 3, 0x0, 0xffff},
2278 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2279 IM_CTL, 0x044, 3, 0x0, 0xffff},
2280 { NULL },
2281};
2282#ifdef HP_IP46TCP4NOHTTP_DEFAULT
2283#define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab
2284#endif
2285#endif
2286
2287/* match step #s for IP4FRAG */
2288#define S3_IPV6c 11
2289#define S3_TCP64 12
2290#define S3_TCPSQ 13
2291#define S3_TCPFG 14
2292#define S3_TCPHL 15
2293#define S3_TCPHc 16
2294#define S3_FRAG 17
2295#define S3_FOFF 18
2296#define S3_CLNP 19
2297
2298#ifdef USE_HP_IP4FRAG
2299static cas_hp_inst_t cas_prog_ip4fragtab[] = {
2300 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT,
2301 CL_REG, 0x3ff, 1, 0x0, 0x0000},
2302 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2303 IM_CTL, 0x00a, 3, 0x0, 0xffff},
2304 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S3_CLNP, 1, S1_8023,
2305 CL_REG, 0x000, 0, 0x0, 0x0000},
2306 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2307 CL_REG, 0x000, 0, 0x0, 0x0000},
2308 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S3_CLNP,
2309 CL_REG, 0x000, 0, 0x0, 0x0000},
2310 { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP,
2311 CL_REG, 0x000, 0, 0x0, 0x0000},
2312 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2313 LD_SAP, 0x100, 3, 0x0, 0xffff},
2314 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S3_CLNP,
2315 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2316 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S3_FRAG,
2317 LD_LEN, 0x03e, 3, 0x0, 0xffff},
2318 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S3_TCPSQ, 0, S3_CLNP,
2319 LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2320 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S3_IPV6c, 0, S3_CLNP,
2321 LD_SUM, 0x015, 1, 0x0, 0x0000},
2322 { "IPV6 cont?", 0xf000, 0x6000, OP_EQ, 3, S3_TCP64, 0, S3_CLNP,
2323 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2324 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S3_TCPSQ, 0, S3_CLNP,
2325 LD_LEN, 0x03f, 1, 0x0, 0xffff},
2326 { "TCP seq", /* DADDR should point to dest port */
2327 0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ,
2328 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2329 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0,
2330 S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
2331 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc,
2332 LD_R1, 0x205, 3, 0xB, 0xf000},
2333 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2334 LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2335 { "IP4 Fragment", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2336 LD_FID, 0x103, 3, 0x0, 0xffff}, /* FID IP4 src+dst */
2337 { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2338 LD_SEQ, 0x040, 1, 0xD, 0xfff8},
2339 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2340 IM_CTL, 0x001, 3, 0x0, 0x0001},
2341 { NULL },
2342};
2343#ifdef HP_IP4FRAG_DEFAULT
2344#define CAS_HP_FIRMWARE cas_prog_ip4fragtab
2345#endif
2346#endif
2347
2348/*
2349 * Alternate table which does batching without reassembly
2350 */
2351#ifdef USE_HP_IP46TCP4BATCH
2352static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = {
2353 CAS_PROG_IP46TCP4_PREAMBLE,
2354 { "TCP seq", /* DADDR should point to dest port */
2355 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ,
2356 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2357 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2358 S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000}, /* Load TCP flags */
2359 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2360 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2361 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2362 S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff}, /* set batch bit */
2363 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2364 IM_CTL, 0x001, 3, 0x0, 0x0001},
2365 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2366 S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff},
2367 { NULL },
2368};
2369#ifdef HP_IP46TCP4BATCH_DEFAULT
2370#define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab
2371#endif
2372#endif
2373
2374/* Workaround for Cassini rev2 descriptor corruption problem.
2375 * Does batching without reassembly, and sets the SAP to a known
2376 * data pattern for all packets.
2377 */
2378#ifdef USE_HP_WORKAROUND
2379static cas_hp_inst_t cas_prog_workaroundtab[] = {
2380 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2381 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000} ,
2382 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2383 IM_CTL, 0x04a, 3, 0x0, 0xffff},
2384 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2385 CL_REG, 0x000, 0, 0x0, 0x0000},
2386 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2387 CL_REG, 0x000, 0, 0x0, 0x0000},
2388 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2389 CL_REG, 0x000, 0, 0x0, 0x0000},
2390 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2391 CL_REG, 0x000, 0, 0x0, 0x0000},
2392 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2393 IM_SAP, 0x6AE, 3, 0x0, 0xffff},
2394 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2395 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2396 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2397 LD_LEN, 0x03e, 1, 0x0, 0xffff},
2398 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP,
2399 LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2400 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
2401 LD_SUM, 0x015, 1, 0x0, 0x0000},
2402 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2403 IM_R1, 0x128, 1, 0x0, 0xffff},
2404 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2405 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2406 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP,
2407 LD_LEN, 0x03f, 1, 0x0, 0xffff},
2408 { "TCP seq", /* DADDR should point to dest port */
2409 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2410 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2411 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2412 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */
2413 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2414 LD_R1, 0x205, 3, 0xB, 0xf000},
2415 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2416 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2417 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2418 IM_SAP, 0x6AE, 3, 0x0, 0xffff} ,
2419 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2420 IM_CTL, 0x001, 3, 0x0, 0x0001},
2421 { NULL },
2422};
2423#ifdef HP_WORKAROUND_DEFAULT
2424#define CAS_HP_FIRMWARE cas_prog_workaroundtab
2425#endif
2426#endif
2427
2428#ifdef USE_HP_ENCRYPT
2429static cas_hp_inst_t cas_prog_encryptiontab[] = {
2430 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2431 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000},
2432 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2433 IM_CTL, 0x00a, 3, 0x0, 0xffff},
2434#if 0
2435//"CFI?", /* 02 FIND CFI and If FIND go to S1_DROP */
2436//0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x00
2437 00,
2438#endif
2439 { "CFI?", /* FIND CFI and If FIND go to CleanUP1 (ignore and send to host) */
2440 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2441 CL_REG, 0x000, 0, 0x0, 0x0000},
2442 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2443 CL_REG, 0x000, 0, 0x0, 0x0000},
2444 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2445 CL_REG, 0x000, 0, 0x0, 0x0000},
2446 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2447 CL_REG, 0x000, 0, 0x0, 0x0000},
2448 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2449 LD_SAP, 0x100, 3, 0x0, 0xffff},
2450 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2451 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2452 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2453 LD_LEN, 0x03e, 1, 0x0, 0xffff},
2454 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4,
2455 LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */
2456 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
2457 LD_SUM, 0x015, 1, 0x0, 0x0000},
2458 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2459 IM_R1, 0x128, 1, 0x0, 0xffff},
2460 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2461 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */
2462 { "TCP64?",
2463#if 0
2464//@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff,
2465#endif
2466 0xff00, 0x0600, OP_EQ, 12, S1_TCPSQ, 0, S1_ESP6, LD_LEN,
2467 0x03f, 1, 0x0, 0xffff},
2468 { "TCP seq", /* 14:DADDR should point to dest port */
2469 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2470 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */
2471 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2472 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f}, /* Load TCP flags */
2473 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2474 LD_R1, 0x205, 3, 0xB, 0xf000} ,
2475 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2476 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2477 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2478 IM_CTL, 0x001, 3, 0x0, 0x0001},
2479 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2480 CL_REG, 0x002, 3, 0x0, 0x0000},
2481 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2482 IM_CTL, 0x080, 3, 0x0, 0xffff},
2483 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2484 IM_CTL, 0x044, 3, 0x0, 0xffff},
2485 { "IPV4 ESP encrypted?", /* S1_ESP4 */
2486 0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL,
2487 0x021, 1, 0x0, 0xffff},
2488 { "IPV4 AH encrypted?", /* S1_AH4 */
2489 0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2490 0x021, 1, 0x0, 0xffff},
2491 { "IPV6 ESP encrypted?", /* S1_ESP6 */
2492#if 0
2493//@@@0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1, 0x0, 0xffff,
2494#endif
2495 0xff00, 0x3200, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL,
2496 0x021, 1, 0x0, 0xffff},
2497 { "IPV6 AH encrypted?", /* S1_AH6 */
2498#if 0
2499//@@@0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff,
2500#endif
2501 0xff00, 0x3300, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2502 0x021, 1, 0x0, 0xffff},
2503 { NULL },
2504};
2505#ifdef HP_ENCRYPT_DEFAULT
2506#define CAS_HP_FIRMWARE cas_prog_encryptiontab
2507#endif
2508#endif
2509
2510static cas_hp_inst_t cas_prog_null[] = { {NULL} };
2511#ifdef HP_NULL_DEFAULT
2512#define CAS_HP_FIRMWARE cas_prog_null
2513#endif
2514
2515/* phy types */
2516#define CAS_PHY_UNKNOWN 0x00
2517#define CAS_PHY_SERDES 0x01
2518#define CAS_PHY_MII_MDIO0 0x02
2519#define CAS_PHY_MII_MDIO1 0x04
2520#define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
2521
2522/* _RING_INDEX is the index for the ring sizes to be used. _RING_SIZE
2523 * is the actual size. the default index for the various rings is
2524 * 8. NOTE: there a bunch of alignment constraints for the rings. to
2525 * deal with that, i just allocate rings to create the desired
2526 * alignment. here are the constraints:
2527 * RX DESC and COMP rings must be 8KB aligned
2528 * TX DESC must be 2KB aligned.
2529 * if you change the numbers, be cognizant of how the alignment will change
2530 * in INIT_BLOCK as well.
2531 */
2532
2533#define DESC_RING_I_TO_S(x) (32*(1 << (x)))
2534#define COMP_RING_I_TO_S(x) (128*(1 << (x)))
2535#define TX_DESC_RING_INDEX 4 /* 512 = 8k */
2536#define RX_DESC_RING_INDEX 4 /* 512 = 8k */
2537#define RX_COMP_RING_INDEX 4 /* 2048 = 64k: should be 4x rx ring size */
2538
2539#if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
2540#error TX_DESC_RING_INDEX must be between 0 and 8
2541#endif
2542
2543#if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
2544#error RX_DESC_RING_INDEX must be between 0 and 8
2545#endif
2546
2547#if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
2548#error RX_COMP_RING_INDEX must be between 0 and 8
2549#endif
2550
2551#define N_TX_RINGS MAX_TX_RINGS /* for QoS */
2552#define N_TX_RINGS_MASK MAX_TX_RINGS_MASK
2553#define N_RX_DESC_RINGS MAX_RX_DESC_RINGS /* 1 for ipsec */
2554#define N_RX_COMP_RINGS 0x1 /* for mult. PCI interrupts */
2555
2556/* number of flows that can go through re-assembly */
2557#define N_RX_FLOWS 64
2558
2559#define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
2560#define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
2561#define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
2562#define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX
2563#define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX
2564#define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX
2565#define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE
2566#define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE
2567#define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE
2568
2569/* convert values */
2570#define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK))
2571#define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT))
2572#define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \
2573 TX_CFG_DESC_RINGN_SHIFT(y)) & \
2574 TX_CFG_DESC_RINGN_MASK(y))
2575
2576/* min is 2k, but we can't do jumbo frames unless it's at least 8k */
2577#define CAS_MIN_PAGE_SHIFT 11 /* 2048 */
2578#define CAS_JUMBO_PAGE_SHIFT 13 /* 8192 */
2579#define CAS_MAX_PAGE_SHIFT 14 /* 16384 */
2580
2581#define TX_DESC_BUFLEN_MASK 0x0000000000003FFFULL /* buffer length in
2582 bytes. 0 - 9256 */
2583#define TX_DESC_BUFLEN_SHIFT 0
2584#define TX_DESC_CSUM_START_MASK 0x00000000001F8000ULL /* checksum start. #
2585 of bytes to be
2586 skipped before
2587 csum calc begins.
2588 value must be
2589 even */
2590#define TX_DESC_CSUM_START_SHIFT 15
2591#define TX_DESC_CSUM_STUFF_MASK 0x000000001FE00000ULL /* checksum stuff.
2592 byte offset w/in
2593 the pkt for the
2594 1st csum byte.
2595 must be > 8 */
2596#define TX_DESC_CSUM_STUFF_SHIFT 21
2597#define TX_DESC_CSUM_EN 0x0000000020000000ULL /* enable checksum */
2598#define TX_DESC_EOF 0x0000000040000000ULL /* end of frame */
2599#define TX_DESC_SOF 0x0000000080000000ULL /* start of frame */
2600#define TX_DESC_INTME 0x0000000100000000ULL /* interrupt me */
2601#define TX_DESC_NO_CRC 0x0000000200000000ULL /* debugging only.
2602 CRC will not be
2603 inserted into
2604 outgoing frame. */
2605struct cas_tx_desc {
2606 __le64 control;
2607 __le64 buffer;
2608};
2609
2610/* descriptor ring for free buffers contains page-sized buffers. the index
2611 * value is not used by the hw in any way. it's just stored and returned in
2612 * the completion ring.
2613 */
2614struct cas_rx_desc {
2615 __le64 index;
2616 __le64 buffer;
2617};
2618
2619/* received packets are put on the completion ring. */
2620/* word 1 */
2621#define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
2622#define RX_COMP1_DATA_SIZE_SHIFT 13
2623#define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
2624#define RX_COMP1_DATA_OFF_SHIFT 27
2625#define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL
2626#define RX_COMP1_DATA_INDEX_SHIFT 41
2627#define RX_COMP1_SKIP_MASK 0x0180000000000000ULL
2628#define RX_COMP1_SKIP_SHIFT 55
2629#define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
2630#define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
2631#define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
2632#define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
2633#define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
2634#define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
2635#define RX_COMP1_TYPE_SHIFT 62
2636
2637/* word 2 */
2638#define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL
2639#define RX_COMP2_NEXT_INDEX_SHIFT 21
2640#define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL
2641#define RX_COMP2_HDR_SIZE_SHIFT 35
2642#define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL
2643#define RX_COMP2_HDR_OFF_SHIFT 44
2644#define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL
2645#define RX_COMP2_HDR_INDEX_SHIFT 50
2646
2647/* word 3 */
2648#define RX_COMP3_SMALL_PKT 0x0000000000000001ULL
2649#define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL
2650#define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL
2651#define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL
2652#define RX_COMP3_CSUM_START_SHIFT 12
2653#define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL
2654#define RX_COMP3_FLOWID_SHIFT 19
2655#define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL
2656#define RX_COMP3_OPCODE_SHIFT 25
2657#define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL
2658#define RX_COMP3_NO_ASSIST 0x0000000020000000ULL
2659#define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL
2660#define RX_COMP3_LOAD_BAL_SHIFT 35
2661#define RX_PLUS_COMP3_ENC_PKT 0x0000020000000000ULL /* cas+ */
2662#define RX_COMP3_L3_HEAD_OFF_MASK 0x0000FE0000000000ULL /* cas */
2663#define RX_COMP3_L3_HEAD_OFF_SHIFT 41
2664#define RX_PLUS_COMP_L3_HEAD_OFF_MASK 0x0000FC0000000000ULL /* cas+ */
2665#define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42
2666#define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL
2667#define RX_COMP3_SAP_SHIFT 48
2668
2669/* word 4 */
2670#define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL
2671#define RX_COMP4_TCP_CSUM_SHIFT 0
2672#define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL
2673#define RX_COMP4_PKT_LEN_SHIFT 16
2674#define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL
2675#define RX_COMP4_PERFECT_MATCH_SHIFT 30
2676#define RX_COMP4_ZERO 0x0000080000000000ULL
2677#define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL
2678#define RX_COMP4_HASH_VAL_SHIFT 44
2679#define RX_COMP4_HASH_PASS 0x1000000000000000ULL
2680#define RX_COMP4_BAD 0x4000000000000000ULL
2681#define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL
2682
2683/* we encode the following: ring/index/release. only 14 bits
2684 * are usable.
2685 * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and
2686 * MAX_RX_DESC_RINGS. */
2687#define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
2688#define RX_INDEX_NUM_SHIFT 0
2689#define RX_INDEX_RING_MASK 0x0000000000001000ULL
2690#define RX_INDEX_RING_SHIFT 12
2691#define RX_INDEX_RELEASE 0x0000000000002000ULL
2692
2693struct cas_rx_comp {
2694 __le64 word1;
2695 __le64 word2;
2696 __le64 word3;
2697 __le64 word4;
2698};
2699
2700enum link_state {
2701 link_down = 0, /* No link, will retry */
2702 link_aneg, /* Autoneg in progress */
2703 link_force_try, /* Try Forced link speed */
2704 link_force_ret, /* Forced mode worked, retrying autoneg */
2705 link_force_ok, /* Stay in forced mode */
2706 link_up /* Link is up */
2707};
2708
2709typedef struct cas_page {
2710 struct list_head list;
2711 struct page *buffer;
2712 dma_addr_t dma_addr;
2713 int used;
2714} cas_page_t;
2715
2716
2717/* some alignment constraints:
2718 * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
2719 * TX COMPWB must be 8-byte aligned.
2720 * to accomplish this, here's what we do:
2721 *
2722 * INIT_BLOCK_RX_COMP = 64k (already aligned)
2723 * INIT_BLOCK_RX_DESC = 8k
2724 * INIT_BLOCK_TX = 8k
2725 * INIT_BLOCK_RX1_DESC = 8k
2726 * TX COMPWB
2727 */
2728#define INIT_BLOCK_TX (TX_DESC_RING_SIZE)
2729#define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE)
2730#define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE)
2731
2732struct cas_init_block {
2733 struct cas_rx_comp rxcs[N_RX_COMP_RINGS][INIT_BLOCK_RX_COMP];
2734 struct cas_rx_desc rxds[N_RX_DESC_RINGS][INIT_BLOCK_RX_DESC];
2735 struct cas_tx_desc txds[N_TX_RINGS][INIT_BLOCK_TX];
2736 __le64 tx_compwb;
2737};
2738
2739/* tiny buffers to deal with target abort issue. we allocate a bit
2740 * over so that we don't have target abort issues with these buffers
2741 * as well.
2742 */
2743#define TX_TINY_BUF_LEN 0x100
2744#define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
2745
2746struct cas_tiny_count {
2747 int nbufs;
2748 int used;
2749};
2750
2751struct cas {
2752 spinlock_t lock; /* for most bits */
2753 spinlock_t tx_lock[N_TX_RINGS]; /* tx bits */
2754 spinlock_t stat_lock[N_TX_RINGS + 1]; /* for stat gathering */
2755 spinlock_t rx_inuse_lock; /* rx inuse list */
2756 spinlock_t rx_spare_lock; /* rx spare list */
2757
2758 void __iomem *regs;
2759 int tx_new[N_TX_RINGS], tx_old[N_TX_RINGS];
2760 int rx_old[N_RX_DESC_RINGS];
2761 int rx_cur[N_RX_COMP_RINGS], rx_new[N_RX_COMP_RINGS];
2762 int rx_last[N_RX_DESC_RINGS];
2763
2764 struct napi_struct napi;
2765
2766 /* Set when chip is actually in operational state
2767 * (ie. not power managed) */
2768 int hw_running;
2769 int opened;
2770 struct mutex pm_mutex; /* open/close/suspend/resume */
2771
2772 struct cas_init_block *init_block;
2773 struct cas_tx_desc *init_txds[MAX_TX_RINGS];
2774 struct cas_rx_desc *init_rxds[MAX_RX_DESC_RINGS];
2775 struct cas_rx_comp *init_rxcs[MAX_RX_COMP_RINGS];
2776
2777 /* we use sk_buffs for tx and pages for rx. the rx skbuffs
2778 * are there for flow re-assembly. */
2779 struct sk_buff *tx_skbs[N_TX_RINGS][TX_DESC_RING_SIZE];
2780 struct sk_buff_head rx_flows[N_RX_FLOWS];
2781 cas_page_t *rx_pages[N_RX_DESC_RINGS][RX_DESC_RING_SIZE];
2782 struct list_head rx_spare_list, rx_inuse_list;
2783 int rx_spares_needed;
2784
2785 /* for small packets when copying would be quicker than
2786 mapping */
2787 struct cas_tiny_count tx_tiny_use[N_TX_RINGS][TX_DESC_RING_SIZE];
2788 u8 *tx_tiny_bufs[N_TX_RINGS];
2789
2790 u32 msg_enable;
2791
2792 /* N_TX_RINGS must be >= N_RX_DESC_RINGS */
2793 struct net_device_stats net_stats[N_TX_RINGS + 1];
2794
2795 u32 pci_cfg[64 >> 2];
2796 u8 pci_revision;
2797
2798 int phy_type;
2799 int phy_addr;
2800 u32 phy_id;
2801#define CAS_FLAG_1000MB_CAP 0x00000001
2802#define CAS_FLAG_REG_PLUS 0x00000002
2803#define CAS_FLAG_TARGET_ABORT 0x00000004
2804#define CAS_FLAG_SATURN 0x00000008
2805#define CAS_FLAG_RXD_POST_MASK 0x000000F0
2806#define CAS_FLAG_RXD_POST_SHIFT 4
2807#define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
2808 CAS_FLAG_RXD_POST_MASK)
2809#define CAS_FLAG_ENTROPY_DEV 0x00000100
2810#define CAS_FLAG_NO_HW_CSUM 0x00000200
2811 u32 cas_flags;
2812 int packet_min; /* minimum packet size */
2813 int tx_fifo_size;
2814 int rx_fifo_size;
2815 int rx_pause_off;
2816 int rx_pause_on;
2817 int crc_size; /* 4 if half-duplex */
2818
2819 int pci_irq_INTC;
2820 int min_frame_size; /* for tx fifo workaround */
2821
2822 /* page size allocation */
2823 int page_size;
2824 int page_order;
2825 int mtu_stride;
2826
2827 u32 mac_rx_cfg;
2828
2829 /* Autoneg & PHY control */
2830 int link_cntl;
2831 int link_fcntl;
2832 enum link_state lstate;
2833 struct timer_list link_timer;
2834 int timer_ticks;
2835 struct work_struct reset_task;
2836#if 0
2837 atomic_t reset_task_pending;
2838#else
2839 atomic_t reset_task_pending;
2840 atomic_t reset_task_pending_mtu;
2841 atomic_t reset_task_pending_spare;
2842 atomic_t reset_task_pending_all;
2843#endif
2844
2845 /* Link-down problem workaround */
2846#define LINK_TRANSITION_UNKNOWN 0
2847#define LINK_TRANSITION_ON_FAILURE 1
2848#define LINK_TRANSITION_STILL_FAILED 2
2849#define LINK_TRANSITION_LINK_UP 3
2850#define LINK_TRANSITION_LINK_CONFIG 4
2851#define LINK_TRANSITION_LINK_DOWN 5
2852#define LINK_TRANSITION_REQUESTED_RESET 6
2853 int link_transition;
2854 int link_transition_jiffies_valid;
2855 unsigned long link_transition_jiffies;
2856
2857 /* Tuning */
2858 u8 orig_cacheline_size; /* value when loaded */
2859#define CAS_PREF_CACHELINE_SIZE 0x20 /* Minimum desired */
2860
2861 /* Diagnostic counters and state. */
2862 int casreg_len; /* reg-space size for dumping */
2863 u64 pause_entered;
2864 u16 pause_last_time_recvd;
2865
2866 dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS];
2867 struct pci_dev *pdev;
2868 struct net_device *dev;
2869#if defined(CONFIG_OF)
2870 struct device_node *of_node;
2871#endif
2872
2873 /* Firmware Info */
2874 u16 fw_load_addr;
2875 u32 fw_size;
2876 u8 *fw_data;
2877};
2878
2879#define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2880#define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2881#define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2882
2883#define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
2884 (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2885
2886#define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2887 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2888 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2889
2890#define CAS_ALIGN(addr, align) \
2891 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
2892
2893#define RX_FIFO_SIZE 16384
2894#define EXPANSION_ROM_SIZE 65536
2895
2896#define CAS_MC_EXACT_MATCH_SIZE 15
2897#define CAS_MC_HASH_SIZE 256
2898#define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \
2899 CAS_MC_HASH_SIZE)
2900
2901#define TX_TARGET_ABORT_LEN 0x20
2902#define RX_SWIVEL_OFF_VAL 0x2
2903#define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1)
2904#define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1)
2905#define RX_BLANK_INTR_PKT_VAL 0x05
2906#define RX_BLANK_INTR_TIME_VAL 0x0F
2907#define HP_TCP_THRESH_VAL 1530 /* reduce to enable reassembly */
2908
2909#define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1)
2910#define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2)
2911
2912#endif /* _CASSINI_H */