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1/*
2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3 *
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
6 * Marcus Andersson
7 * Thomas Charbonnel
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
10 *
11 * Modified 2009-04-13 for proper metering by Florian Faber
12 * <faber@faberman.de>
13 *
14 * Modified 2009-04-14 for native float support by Florian Faber
15 * <faber@faberman.de>
16 *
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18 * <faber@faberman.de>
19 *
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
21 *
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23 *
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25 *
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
30 *
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
35 *
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 *
40 */
41#include <linux/init.h>
42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/module.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
47#include <linux/math64.h>
48#include <asm/io.h>
49
50#include <sound/core.h>
51#include <sound/control.h>
52#include <sound/pcm.h>
53#include <sound/pcm_params.h>
54#include <sound/info.h>
55#include <sound/asoundef.h>
56#include <sound/rawmidi.h>
57#include <sound/hwdep.h>
58#include <sound/initval.h>
59
60#include <sound/hdspm.h>
61
62static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
63static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
64static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
65
66module_param_array(index, int, NULL, 0444);
67MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
68
69module_param_array(id, charp, NULL, 0444);
70MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
71
72module_param_array(enable, bool, NULL, 0444);
73MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
74
75
76MODULE_AUTHOR
77(
78 "Winfried Ritsch <ritsch_AT_iem.at>, "
79 "Paul Davis <paul@linuxaudiosystems.com>, "
80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81 "Remy Bruno <remy.bruno@trinnov.com>, "
82 "Florian Faber <faberman@linuxproaudio.org>, "
83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
84);
85MODULE_DESCRIPTION("RME HDSPM");
86MODULE_LICENSE("GPL");
87MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
88
89/* --- Write registers. ---
90 These are defined as byte-offsets from the iobase value. */
91
92#define HDSPM_WR_SETTINGS 0
93#define HDSPM_outputBufferAddress 32
94#define HDSPM_inputBufferAddress 36
95#define HDSPM_controlRegister 64
96#define HDSPM_interruptConfirmation 96
97#define HDSPM_control2Reg 256 /* not in specs ???????? */
98#define HDSPM_freqReg 256 /* for AES32 */
99#define HDSPM_midiDataOut0 352 /* just believe in old code */
100#define HDSPM_midiDataOut1 356
101#define HDSPM_eeprom_wr 384 /* for AES32 */
102
103/* DMA enable for 64 channels, only Bit 0 is relevant */
104#define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
105#define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
106
107/* 16 page addresses for each of the 64 channels DMA buffer in and out
108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109#define HDSPM_pageAddressBufferOut 8192
110#define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
111
112#define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
113
114#define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
115
116/* --- Read registers. ---
117 These are defined as byte-offsets from the iobase value */
118#define HDSPM_statusRegister 0
119/*#define HDSPM_statusRegister2 96 */
120/* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121 * offset 192, for AES32 *and* MADI
122 * => need to check that offset 192 is working on MADI */
123#define HDSPM_statusRegister2 192
124#define HDSPM_timecodeRegister 128
125
126/* AIO, RayDAT */
127#define HDSPM_RD_STATUS_0 0
128#define HDSPM_RD_STATUS_1 64
129#define HDSPM_RD_STATUS_2 128
130#define HDSPM_RD_STATUS_3 192
131
132#define HDSPM_RD_TCO 256
133#define HDSPM_RD_PLL_FREQ 512
134#define HDSPM_WR_TCO 128
135
136#define HDSPM_TCO1_TCO_lock 0x00000001
137#define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
138#define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
139#define HDSPM_TCO1_LTC_Input_valid 0x00000008
140#define HDSPM_TCO1_WCK_Input_valid 0x00000010
141#define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
142#define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
143
144#define HDSPM_TCO1_set_TC 0x00000100
145#define HDSPM_TCO1_set_drop_frame_flag 0x00000200
146#define HDSPM_TCO1_LTC_Format_LSB 0x00000400
147#define HDSPM_TCO1_LTC_Format_MSB 0x00000800
148
149#define HDSPM_TCO2_TC_run 0x00010000
150#define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
151#define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
152#define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
153#define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
154#define HDSPM_TCO2_set_jam_sync 0x00200000
155#define HDSPM_TCO2_set_flywheel 0x00400000
156
157#define HDSPM_TCO2_set_01_4 0x01000000
158#define HDSPM_TCO2_set_pull_down 0x02000000
159#define HDSPM_TCO2_set_pull_up 0x04000000
160#define HDSPM_TCO2_set_freq 0x08000000
161#define HDSPM_TCO2_set_term_75R 0x10000000
162#define HDSPM_TCO2_set_input_LSB 0x20000000
163#define HDSPM_TCO2_set_input_MSB 0x40000000
164#define HDSPM_TCO2_set_freq_from_app 0x80000000
165
166
167#define HDSPM_midiDataOut0 352
168#define HDSPM_midiDataOut1 356
169#define HDSPM_midiDataOut2 368
170
171#define HDSPM_midiDataIn0 360
172#define HDSPM_midiDataIn1 364
173#define HDSPM_midiDataIn2 372
174#define HDSPM_midiDataIn3 376
175
176/* status is data bytes in MIDI-FIFO (0-128) */
177#define HDSPM_midiStatusOut0 384
178#define HDSPM_midiStatusOut1 388
179#define HDSPM_midiStatusOut2 400
180
181#define HDSPM_midiStatusIn0 392
182#define HDSPM_midiStatusIn1 396
183#define HDSPM_midiStatusIn2 404
184#define HDSPM_midiStatusIn3 408
185
186
187/* the meters are regular i/o-mapped registers, but offset
188 considerably from the rest. the peak registers are reset
189 when read; the least-significant 4 bits are full-scale counters;
190 the actual peak value is in the most-significant 24 bits.
191*/
192
193#define HDSPM_MADI_INPUT_PEAK 4096
194#define HDSPM_MADI_PLAYBACK_PEAK 4352
195#define HDSPM_MADI_OUTPUT_PEAK 4608
196
197#define HDSPM_MADI_INPUT_RMS_L 6144
198#define HDSPM_MADI_PLAYBACK_RMS_L 6400
199#define HDSPM_MADI_OUTPUT_RMS_L 6656
200
201#define HDSPM_MADI_INPUT_RMS_H 7168
202#define HDSPM_MADI_PLAYBACK_RMS_H 7424
203#define HDSPM_MADI_OUTPUT_RMS_H 7680
204
205/* --- Control Register bits --------- */
206#define HDSPM_Start (1<<0) /* start engine */
207
208#define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
209#define HDSPM_Latency1 (1<<2) /* where n is defined */
210#define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
211
212#define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
213#define HDSPM_c0Master 0x1 /* Master clock bit in settings
214 register [RayDAT, AIO] */
215
216#define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
217
218#define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219#define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
220#define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
221#define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
222
223#define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224#define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
225 56channelMODE=0 */ /* MADI ONLY*/
226#define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
227
228#define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
229 0=off, 1=on */ /* MADI ONLY */
230#define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
231
232#define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
233 * -- MADI ONLY
234 */
235#define HDSPM_InputSelect1 (1<<15) /* should be 0 */
236
237#define HDSPM_SyncRef2 (1<<13)
238#define HDSPM_SyncRef3 (1<<25)
239
240#define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
241#define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
242 AES additional bits in
243 lower 5 Audiodatabits ??? */
244#define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
245#define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
246
247#define HDSPM_Midi0InterruptEnable 0x0400000
248#define HDSPM_Midi1InterruptEnable 0x0800000
249#define HDSPM_Midi2InterruptEnable 0x0200000
250#define HDSPM_Midi3InterruptEnable 0x4000000
251
252#define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253#define HDSPe_FLOAT_FORMAT 0x2000000
254
255#define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256#define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257#define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
258
259#define HDSPM_wclk_sel (1<<30)
260
261/* --- bit helper defines */
262#define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263#define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265#define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
266#define HDSPM_InputOptical 0
267#define HDSPM_InputCoaxial (HDSPM_InputSelect0)
268#define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269 HDSPM_SyncRef2|HDSPM_SyncRef3)
270
271#define HDSPM_c0_SyncRef0 0x2
272#define HDSPM_c0_SyncRef1 0x4
273#define HDSPM_c0_SyncRef2 0x8
274#define HDSPM_c0_SyncRef3 0x10
275#define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
277
278#define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
279#define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
280#define HDSPM_SYNC_FROM_TCO 2
281#define HDSPM_SYNC_FROM_SYNC_IN 3
282
283#define HDSPM_Frequency32KHz HDSPM_Frequency0
284#define HDSPM_Frequency44_1KHz HDSPM_Frequency1
285#define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
286#define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287#define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288#define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
289 HDSPM_Frequency0)
290#define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
291#define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
292#define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
293 HDSPM_Frequency0)
294
295
296/* Synccheck Status */
297#define HDSPM_SYNC_CHECK_NO_LOCK 0
298#define HDSPM_SYNC_CHECK_LOCK 1
299#define HDSPM_SYNC_CHECK_SYNC 2
300
301/* AutoSync References - used by "autosync_ref" control switch */
302#define HDSPM_AUTOSYNC_FROM_WORD 0
303#define HDSPM_AUTOSYNC_FROM_MADI 1
304#define HDSPM_AUTOSYNC_FROM_TCO 2
305#define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
306#define HDSPM_AUTOSYNC_FROM_NONE 4
307
308/* Possible sources of MADI input */
309#define HDSPM_OPTICAL 0 /* optical */
310#define HDSPM_COAXIAL 1 /* BNC */
311
312#define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
313#define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
314
315#define hdspm_encode_in(x) (((x)&0x3)<<14)
316#define hdspm_decode_in(x) (((x)>>14)&0x3)
317
318/* --- control2 register bits --- */
319#define HDSPM_TMS (1<<0)
320#define HDSPM_TCK (1<<1)
321#define HDSPM_TDI (1<<2)
322#define HDSPM_JTAG (1<<3)
323#define HDSPM_PWDN (1<<4)
324#define HDSPM_PROGRAM (1<<5)
325#define HDSPM_CONFIG_MODE_0 (1<<6)
326#define HDSPM_CONFIG_MODE_1 (1<<7)
327/*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
328#define HDSPM_BIGENDIAN_MODE (1<<9)
329#define HDSPM_RD_MULTIPLE (1<<10)
330
331/* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332 that do not conflict with specific bits for AES32 seem to be valid also
333 for the AES32
334 */
335#define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
336#define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337#define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
338 * (like inp0)
339 */
340
341#define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
342#define HDSPM_madiSync (1<<18) /* MADI is in sync */
343
344#define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345#define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
346
347#define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348#define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
349
350#define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351 /* since 64byte accurate, last 6 bits are not used */
352
353
354
355#define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
356
357#define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
358#define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
359#define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
360#define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
361
362#define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
363 * Interrupt
364 */
365#define HDSPM_tco_detect 0x08000000
366#define HDSPM_tco_lock 0x20000000
367
368#define HDSPM_s2_tco_detect 0x00000040
369#define HDSPM_s2_AEBO_D 0x00000080
370#define HDSPM_s2_AEBI_D 0x00000100
371
372
373#define HDSPM_midi0IRQPending 0x40000000
374#define HDSPM_midi1IRQPending 0x80000000
375#define HDSPM_midi2IRQPending 0x20000000
376#define HDSPM_midi2IRQPendingAES 0x00000020
377#define HDSPM_midi3IRQPending 0x00200000
378
379/* --- status bit helpers */
380#define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381 HDSPM_madiFreq2|HDSPM_madiFreq3)
382#define HDSPM_madiFreq32 (HDSPM_madiFreq0)
383#define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
384#define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
385#define HDSPM_madiFreq64 (HDSPM_madiFreq2)
386#define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
387#define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
388#define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389#define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390#define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
391
392/* Status2 Register bits */ /* MADI ONLY */
393
394#define HDSPM_version0 (1<<0) /* not really defined but I guess */
395#define HDSPM_version1 (1<<1) /* in former cards it was ??? */
396#define HDSPM_version2 (1<<2)
397
398#define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
399#define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
400
401#define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
402#define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
403#define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
404/* missing Bit for 111=128, 1000=176.4, 1001=192 */
405
406#define HDSPM_SyncRef0 0x10000 /* Sync Reference */
407#define HDSPM_SyncRef1 0x20000
408
409#define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
410#define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
411#define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
412
413#define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
414
415#define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416#define HDSPM_wcFreq32 (HDSPM_wc_freq0)
417#define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
418#define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
419#define HDSPM_wcFreq64 (HDSPM_wc_freq2)
420#define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
421#define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
422
423#define HDSPM_status1_F_0 0x0400000
424#define HDSPM_status1_F_1 0x0800000
425#define HDSPM_status1_F_2 0x1000000
426#define HDSPM_status1_F_3 0x2000000
427#define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
428
429
430#define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
431 HDSPM_SelSyncRef2)
432#define HDSPM_SelSyncRef_WORD 0
433#define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
434#define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
435#define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436#define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
437 HDSPM_SelSyncRef2)
438
439/*
440 For AES32, bits for status, status2 and timecode are different
441*/
442/* status */
443#define HDSPM_AES32_wcLock 0x0200000
444#define HDSPM_AES32_wcFreq_bit 22
445/* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
446 HDSPM_bit2freq */
447#define HDSPM_AES32_syncref_bit 16
448/* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
449
450#define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451#define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452#define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453#define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454#define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455#define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456#define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457#define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458#define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459#define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
460
461/* status2 */
462/* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463#define HDSPM_LockAES 0x80
464#define HDSPM_LockAES1 0x80
465#define HDSPM_LockAES2 0x40
466#define HDSPM_LockAES3 0x20
467#define HDSPM_LockAES4 0x10
468#define HDSPM_LockAES5 0x8
469#define HDSPM_LockAES6 0x4
470#define HDSPM_LockAES7 0x2
471#define HDSPM_LockAES8 0x1
472/*
473 Timecode
474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
475 AES i+1
476 bits 3210
477 0001 32kHz
478 0010 44.1kHz
479 0011 48kHz
480 0100 64kHz
481 0101 88.2kHz
482 0110 96kHz
483 0111 128kHz
484 1000 176.4kHz
485 1001 192kHz
486 NB: Timecode register doesn't seem to work on AES32 card revision 230
487*/
488
489/* Mixer Values */
490#define UNITY_GAIN 32768 /* = 65536/2 */
491#define MINUS_INFINITY_GAIN 0
492
493/* Number of channels for different Speed Modes */
494#define MADI_SS_CHANNELS 64
495#define MADI_DS_CHANNELS 32
496#define MADI_QS_CHANNELS 16
497
498#define RAYDAT_SS_CHANNELS 36
499#define RAYDAT_DS_CHANNELS 20
500#define RAYDAT_QS_CHANNELS 12
501
502#define AIO_IN_SS_CHANNELS 14
503#define AIO_IN_DS_CHANNELS 10
504#define AIO_IN_QS_CHANNELS 8
505#define AIO_OUT_SS_CHANNELS 16
506#define AIO_OUT_DS_CHANNELS 12
507#define AIO_OUT_QS_CHANNELS 10
508
509#define AES32_CHANNELS 16
510
511/* the size of a substream (1 mono data stream) */
512#define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
513#define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
514
515/* the size of the area we need to allocate for DMA transfers. the
516 size is the same regardless of the number of channels, and
517 also the latency to use.
518 for one direction !!!
519*/
520#define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521#define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
522
523#define HDSPM_RAYDAT_REV 211
524#define HDSPM_AIO_REV 212
525#define HDSPM_MADIFACE_REV 213
526
527/* speed factor modes */
528#define HDSPM_SPEED_SINGLE 0
529#define HDSPM_SPEED_DOUBLE 1
530#define HDSPM_SPEED_QUAD 2
531
532/* names for speed modes */
533static char *hdspm_speed_names[] = { "single", "double", "quad" };
534
535static char *texts_autosync_aes_tco[] = { "Word Clock",
536 "AES1", "AES2", "AES3", "AES4",
537 "AES5", "AES6", "AES7", "AES8",
538 "TCO" };
539static char *texts_autosync_aes[] = { "Word Clock",
540 "AES1", "AES2", "AES3", "AES4",
541 "AES5", "AES6", "AES7", "AES8" };
542static char *texts_autosync_madi_tco[] = { "Word Clock",
543 "MADI", "TCO", "Sync In" };
544static char *texts_autosync_madi[] = { "Word Clock",
545 "MADI", "Sync In" };
546
547static char *texts_autosync_raydat_tco[] = {
548 "Word Clock",
549 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
550 "AES", "SPDIF", "TCO", "Sync In"
551};
552static char *texts_autosync_raydat[] = {
553 "Word Clock",
554 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
555 "AES", "SPDIF", "Sync In"
556};
557static char *texts_autosync_aio_tco[] = {
558 "Word Clock",
559 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
560};
561static char *texts_autosync_aio[] = { "Word Clock",
562 "ADAT", "AES", "SPDIF", "Sync In" };
563
564static char *texts_freq[] = {
565 "No Lock",
566 "32 kHz",
567 "44.1 kHz",
568 "48 kHz",
569 "64 kHz",
570 "88.2 kHz",
571 "96 kHz",
572 "128 kHz",
573 "176.4 kHz",
574 "192 kHz"
575};
576
577static char *texts_ports_madi[] = {
578 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
579 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
580 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
581 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
582 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
583 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
584 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
585 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
586 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
587 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
588 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
589};
590
591
592static char *texts_ports_raydat_ss[] = {
593 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
594 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
595 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
596 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
597 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
598 "ADAT4.7", "ADAT4.8",
599 "AES.L", "AES.R",
600 "SPDIF.L", "SPDIF.R"
601};
602
603static char *texts_ports_raydat_ds[] = {
604 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
605 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
606 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
607 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
608 "AES.L", "AES.R",
609 "SPDIF.L", "SPDIF.R"
610};
611
612static char *texts_ports_raydat_qs[] = {
613 "ADAT1.1", "ADAT1.2",
614 "ADAT2.1", "ADAT2.2",
615 "ADAT3.1", "ADAT3.2",
616 "ADAT4.1", "ADAT4.2",
617 "AES.L", "AES.R",
618 "SPDIF.L", "SPDIF.R"
619};
620
621
622static char *texts_ports_aio_in_ss[] = {
623 "Analogue.L", "Analogue.R",
624 "AES.L", "AES.R",
625 "SPDIF.L", "SPDIF.R",
626 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
627 "ADAT.7", "ADAT.8"
628};
629
630static char *texts_ports_aio_out_ss[] = {
631 "Analogue.L", "Analogue.R",
632 "AES.L", "AES.R",
633 "SPDIF.L", "SPDIF.R",
634 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
635 "ADAT.7", "ADAT.8",
636 "Phone.L", "Phone.R"
637};
638
639static char *texts_ports_aio_in_ds[] = {
640 "Analogue.L", "Analogue.R",
641 "AES.L", "AES.R",
642 "SPDIF.L", "SPDIF.R",
643 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
644};
645
646static char *texts_ports_aio_out_ds[] = {
647 "Analogue.L", "Analogue.R",
648 "AES.L", "AES.R",
649 "SPDIF.L", "SPDIF.R",
650 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
651 "Phone.L", "Phone.R"
652};
653
654static char *texts_ports_aio_in_qs[] = {
655 "Analogue.L", "Analogue.R",
656 "AES.L", "AES.R",
657 "SPDIF.L", "SPDIF.R",
658 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
659};
660
661static char *texts_ports_aio_out_qs[] = {
662 "Analogue.L", "Analogue.R",
663 "AES.L", "AES.R",
664 "SPDIF.L", "SPDIF.R",
665 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
666 "Phone.L", "Phone.R"
667};
668
669static char *texts_ports_aes32[] = {
670 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
671 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
672 "AES.15", "AES.16"
673};
674
675/* These tables map the ALSA channels 1..N to the channels that we
676 need to use in order to find the relevant channel buffer. RME
677 refers to this kind of mapping as between "the ADAT channel and
678 the DMA channel." We index it using the logical audio channel,
679 and the value is the DMA channel (i.e. channel buffer number)
680 where the data for that channel can be read/written from/to.
681*/
682
683static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
684 0, 1, 2, 3, 4, 5, 6, 7,
685 8, 9, 10, 11, 12, 13, 14, 15,
686 16, 17, 18, 19, 20, 21, 22, 23,
687 24, 25, 26, 27, 28, 29, 30, 31,
688 32, 33, 34, 35, 36, 37, 38, 39,
689 40, 41, 42, 43, 44, 45, 46, 47,
690 48, 49, 50, 51, 52, 53, 54, 55,
691 56, 57, 58, 59, 60, 61, 62, 63
692};
693
694static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
695 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
696 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
697 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
698 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
699 0, 1, /* AES */
700 2, 3, /* SPDIF */
701 -1, -1, -1, -1,
702 -1, -1, -1, -1, -1, -1, -1, -1,
703 -1, -1, -1, -1, -1, -1, -1, -1,
704 -1, -1, -1, -1, -1, -1, -1, -1,
705};
706
707static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
708 4, 5, 6, 7, /* ADAT 1 */
709 8, 9, 10, 11, /* ADAT 2 */
710 12, 13, 14, 15, /* ADAT 3 */
711 16, 17, 18, 19, /* ADAT 4 */
712 0, 1, /* AES */
713 2, 3, /* SPDIF */
714 -1, -1, -1, -1,
715 -1, -1, -1, -1, -1, -1, -1, -1,
716 -1, -1, -1, -1, -1, -1, -1, -1,
717 -1, -1, -1, -1, -1, -1, -1, -1,
718 -1, -1, -1, -1, -1, -1, -1, -1,
719 -1, -1, -1, -1, -1, -1, -1, -1,
720};
721
722static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
723 4, 5, /* ADAT 1 */
724 6, 7, /* ADAT 2 */
725 8, 9, /* ADAT 3 */
726 10, 11, /* ADAT 4 */
727 0, 1, /* AES */
728 2, 3, /* SPDIF */
729 -1, -1, -1, -1,
730 -1, -1, -1, -1, -1, -1, -1, -1,
731 -1, -1, -1, -1, -1, -1, -1, -1,
732 -1, -1, -1, -1, -1, -1, -1, -1,
733 -1, -1, -1, -1, -1, -1, -1, -1,
734 -1, -1, -1, -1, -1, -1, -1, -1,
735 -1, -1, -1, -1, -1, -1, -1, -1,
736};
737
738static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
739 0, 1, /* line in */
740 8, 9, /* aes in, */
741 10, 11, /* spdif in */
742 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
743 -1, -1,
744 -1, -1, -1, -1, -1, -1, -1, -1,
745 -1, -1, -1, -1, -1, -1, -1, -1,
746 -1, -1, -1, -1, -1, -1, -1, -1,
747 -1, -1, -1, -1, -1, -1, -1, -1,
748 -1, -1, -1, -1, -1, -1, -1, -1,
749 -1, -1, -1, -1, -1, -1, -1, -1,
750};
751
752static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
753 0, 1, /* line out */
754 8, 9, /* aes out */
755 10, 11, /* spdif out */
756 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
757 6, 7, /* phone out */
758 -1, -1, -1, -1, -1, -1, -1, -1,
759 -1, -1, -1, -1, -1, -1, -1, -1,
760 -1, -1, -1, -1, -1, -1, -1, -1,
761 -1, -1, -1, -1, -1, -1, -1, -1,
762 -1, -1, -1, -1, -1, -1, -1, -1,
763 -1, -1, -1, -1, -1, -1, -1, -1,
764};
765
766static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
767 0, 1, /* line in */
768 8, 9, /* aes in */
769 10, 11, /* spdif in */
770 12, 14, 16, 18, /* adat in */
771 -1, -1, -1, -1, -1, -1,
772 -1, -1, -1, -1, -1, -1, -1, -1,
773 -1, -1, -1, -1, -1, -1, -1, -1,
774 -1, -1, -1, -1, -1, -1, -1, -1,
775 -1, -1, -1, -1, -1, -1, -1, -1,
776 -1, -1, -1, -1, -1, -1, -1, -1,
777 -1, -1, -1, -1, -1, -1, -1, -1
778};
779
780static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
781 0, 1, /* line out */
782 8, 9, /* aes out */
783 10, 11, /* spdif out */
784 12, 14, 16, 18, /* adat out */
785 6, 7, /* phone out */
786 -1, -1, -1, -1,
787 -1, -1, -1, -1, -1, -1, -1, -1,
788 -1, -1, -1, -1, -1, -1, -1, -1,
789 -1, -1, -1, -1, -1, -1, -1, -1,
790 -1, -1, -1, -1, -1, -1, -1, -1,
791 -1, -1, -1, -1, -1, -1, -1, -1,
792 -1, -1, -1, -1, -1, -1, -1, -1
793};
794
795static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
796 0, 1, /* line in */
797 8, 9, /* aes in */
798 10, 11, /* spdif in */
799 12, 16, /* adat in */
800 -1, -1, -1, -1, -1, -1, -1, -1,
801 -1, -1, -1, -1, -1, -1, -1, -1,
802 -1, -1, -1, -1, -1, -1, -1, -1,
803 -1, -1, -1, -1, -1, -1, -1, -1,
804 -1, -1, -1, -1, -1, -1, -1, -1,
805 -1, -1, -1, -1, -1, -1, -1, -1,
806 -1, -1, -1, -1, -1, -1, -1, -1
807};
808
809static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
810 0, 1, /* line out */
811 8, 9, /* aes out */
812 10, 11, /* spdif out */
813 12, 16, /* adat out */
814 6, 7, /* phone out */
815 -1, -1, -1, -1, -1, -1,
816 -1, -1, -1, -1, -1, -1, -1, -1,
817 -1, -1, -1, -1, -1, -1, -1, -1,
818 -1, -1, -1, -1, -1, -1, -1, -1,
819 -1, -1, -1, -1, -1, -1, -1, -1,
820 -1, -1, -1, -1, -1, -1, -1, -1,
821 -1, -1, -1, -1, -1, -1, -1, -1
822};
823
824static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
825 0, 1, 2, 3, 4, 5, 6, 7,
826 8, 9, 10, 11, 12, 13, 14, 15,
827 -1, -1, -1, -1, -1, -1, -1, -1,
828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
831 -1, -1, -1, -1, -1, -1, -1, -1,
832 -1, -1, -1, -1, -1, -1, -1, -1
833};
834
835struct hdspm_midi {
836 struct hdspm *hdspm;
837 int id;
838 struct snd_rawmidi *rmidi;
839 struct snd_rawmidi_substream *input;
840 struct snd_rawmidi_substream *output;
841 char istimer; /* timer in use */
842 struct timer_list timer;
843 spinlock_t lock;
844 int pending;
845 int dataIn;
846 int statusIn;
847 int dataOut;
848 int statusOut;
849 int ie;
850 int irq;
851};
852
853struct hdspm_tco {
854 int input;
855 int framerate;
856 int wordclock;
857 int samplerate;
858 int pull;
859 int term; /* 0 = off, 1 = on */
860};
861
862struct hdspm {
863 spinlock_t lock;
864 /* only one playback and/or capture stream */
865 struct snd_pcm_substream *capture_substream;
866 struct snd_pcm_substream *playback_substream;
867
868 char *card_name; /* for procinfo */
869 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
870
871 uint8_t io_type;
872
873 int monitor_outs; /* set up monitoring outs init flag */
874
875 u32 control_register; /* cached value */
876 u32 control2_register; /* cached value */
877 u32 settings_register;
878
879 struct hdspm_midi midi[4];
880 struct tasklet_struct midi_tasklet;
881
882 size_t period_bytes;
883 unsigned char ss_in_channels;
884 unsigned char ds_in_channels;
885 unsigned char qs_in_channels;
886 unsigned char ss_out_channels;
887 unsigned char ds_out_channels;
888 unsigned char qs_out_channels;
889
890 unsigned char max_channels_in;
891 unsigned char max_channels_out;
892
893 signed char *channel_map_in;
894 signed char *channel_map_out;
895
896 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
897 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
898
899 char **port_names_in;
900 char **port_names_out;
901
902 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
903 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
904
905 unsigned char *playback_buffer; /* suitably aligned address */
906 unsigned char *capture_buffer; /* suitably aligned address */
907
908 pid_t capture_pid; /* process id which uses capture */
909 pid_t playback_pid; /* process id which uses capture */
910 int running; /* running status */
911
912 int last_external_sample_rate; /* samplerate mystic ... */
913 int last_internal_sample_rate;
914 int system_sample_rate;
915
916 int dev; /* Hardware vars... */
917 int irq;
918 unsigned long port;
919 void __iomem *iobase;
920
921 int irq_count; /* for debug */
922 int midiPorts;
923
924 struct snd_card *card; /* one card */
925 struct snd_pcm *pcm; /* has one pcm */
926 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
927 struct pci_dev *pci; /* and an pci info */
928
929 /* Mixer vars */
930 /* fast alsa mixer */
931 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
932 /* but input to much, so not used */
933 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
934 /* full mixer accessible over mixer ioctl or hwdep-device */
935 struct hdspm_mixer *mixer;
936
937 struct hdspm_tco *tco; /* NULL if no TCO detected */
938
939 char **texts_autosync;
940 int texts_autosync_items;
941
942 cycles_t last_interrupt;
943
944 unsigned int serial;
945
946 struct hdspm_peak_rms peak_rms;
947};
948
949
950static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
951 {
952 .vendor = PCI_VENDOR_ID_XILINX,
953 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
954 .subvendor = PCI_ANY_ID,
955 .subdevice = PCI_ANY_ID,
956 .class = 0,
957 .class_mask = 0,
958 .driver_data = 0},
959 {0,}
960};
961
962MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
963
964/* prototypes */
965static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
966 struct hdspm * hdspm);
967static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
968 struct hdspm * hdspm);
969
970static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
971static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
972static int hdspm_autosync_ref(struct hdspm *hdspm);
973static int snd_hdspm_set_defaults(struct hdspm *hdspm);
974static void hdspm_set_sgbuf(struct hdspm *hdspm,
975 struct snd_pcm_substream *substream,
976 unsigned int reg, int channels);
977
978static inline int HDSPM_bit2freq(int n)
979{
980 static const int bit2freq_tab[] = {
981 0, 32000, 44100, 48000, 64000, 88200,
982 96000, 128000, 176400, 192000 };
983 if (n < 1 || n > 9)
984 return 0;
985 return bit2freq_tab[n];
986}
987
988/* Write/read to/from HDSPM with Adresses in Bytes
989 not words but only 32Bit writes are allowed */
990
991static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
992 unsigned int val)
993{
994 writel(val, hdspm->iobase + reg);
995}
996
997static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
998{
999 return readl(hdspm->iobase + reg);
1000}
1001
1002/* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1003 mixer is write only on hardware so we have to cache him for read
1004 each fader is a u32, but uses only the first 16 bit */
1005
1006static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1007 unsigned int in)
1008{
1009 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1010 return 0;
1011
1012 return hdspm->mixer->ch[chan].in[in];
1013}
1014
1015static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1016 unsigned int pb)
1017{
1018 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1019 return 0;
1020 return hdspm->mixer->ch[chan].pb[pb];
1021}
1022
1023static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1024 unsigned int in, unsigned short data)
1025{
1026 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1027 return -1;
1028
1029 hdspm_write(hdspm,
1030 HDSPM_MADI_mixerBase +
1031 ((in + 128 * chan) * sizeof(u32)),
1032 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1033 return 0;
1034}
1035
1036static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1037 unsigned int pb, unsigned short data)
1038{
1039 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1040 return -1;
1041
1042 hdspm_write(hdspm,
1043 HDSPM_MADI_mixerBase +
1044 ((64 + pb + 128 * chan) * sizeof(u32)),
1045 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1046 return 0;
1047}
1048
1049
1050/* enable DMA for specific channels, now available for DSP-MADI */
1051static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1052{
1053 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1054}
1055
1056static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1057{
1058 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1059}
1060
1061/* check if same process is writing and reading */
1062static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1063{
1064 unsigned long flags;
1065 int ret = 1;
1066
1067 spin_lock_irqsave(&hdspm->lock, flags);
1068 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1069 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1070 ret = 0;
1071 }
1072 spin_unlock_irqrestore(&hdspm->lock, flags);
1073 return ret;
1074}
1075
1076/* check for external sample rate */
1077static int hdspm_external_sample_rate(struct hdspm *hdspm)
1078{
1079 unsigned int status, status2, timecode;
1080 int syncref, rate = 0, rate_bits;
1081
1082 switch (hdspm->io_type) {
1083 case AES32:
1084 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1085 status = hdspm_read(hdspm, HDSPM_statusRegister);
1086 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1087
1088 syncref = hdspm_autosync_ref(hdspm);
1089
1090 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1091 status & HDSPM_AES32_wcLock)
1092 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1093
1094 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1095 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1096 status2 & (HDSPM_LockAES >>
1097 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1098 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1099 return 0;
1100 break;
1101
1102 case MADIface:
1103 status = hdspm_read(hdspm, HDSPM_statusRegister);
1104
1105 if (!(status & HDSPM_madiLock)) {
1106 rate = 0; /* no lock */
1107 } else {
1108 switch (status & (HDSPM_status1_freqMask)) {
1109 case HDSPM_status1_F_0*1:
1110 rate = 32000; break;
1111 case HDSPM_status1_F_0*2:
1112 rate = 44100; break;
1113 case HDSPM_status1_F_0*3:
1114 rate = 48000; break;
1115 case HDSPM_status1_F_0*4:
1116 rate = 64000; break;
1117 case HDSPM_status1_F_0*5:
1118 rate = 88200; break;
1119 case HDSPM_status1_F_0*6:
1120 rate = 96000; break;
1121 case HDSPM_status1_F_0*7:
1122 rate = 128000; break;
1123 case HDSPM_status1_F_0*8:
1124 rate = 176400; break;
1125 case HDSPM_status1_F_0*9:
1126 rate = 192000; break;
1127 default:
1128 rate = 0; break;
1129 }
1130 }
1131
1132 break;
1133
1134 case MADI:
1135 case AIO:
1136 case RayDAT:
1137 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1138 status = hdspm_read(hdspm, HDSPM_statusRegister);
1139 rate = 0;
1140
1141 /* if wordclock has synced freq and wordclock is valid */
1142 if ((status2 & HDSPM_wcLock) != 0 &&
1143 (status2 & HDSPM_SelSyncRef0) == 0) {
1144
1145 rate_bits = status2 & HDSPM_wcFreqMask;
1146
1147
1148 switch (rate_bits) {
1149 case HDSPM_wcFreq32:
1150 rate = 32000;
1151 break;
1152 case HDSPM_wcFreq44_1:
1153 rate = 44100;
1154 break;
1155 case HDSPM_wcFreq48:
1156 rate = 48000;
1157 break;
1158 case HDSPM_wcFreq64:
1159 rate = 64000;
1160 break;
1161 case HDSPM_wcFreq88_2:
1162 rate = 88200;
1163 break;
1164 case HDSPM_wcFreq96:
1165 rate = 96000;
1166 break;
1167 default:
1168 rate = 0;
1169 break;
1170 }
1171 }
1172
1173 /* if rate detected and Syncref is Word than have it,
1174 * word has priority to MADI
1175 */
1176 if (rate != 0 &&
1177 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1178 return rate;
1179
1180 /* maybe a madi input (which is taken if sel sync is madi) */
1181 if (status & HDSPM_madiLock) {
1182 rate_bits = status & HDSPM_madiFreqMask;
1183
1184 switch (rate_bits) {
1185 case HDSPM_madiFreq32:
1186 rate = 32000;
1187 break;
1188 case HDSPM_madiFreq44_1:
1189 rate = 44100;
1190 break;
1191 case HDSPM_madiFreq48:
1192 rate = 48000;
1193 break;
1194 case HDSPM_madiFreq64:
1195 rate = 64000;
1196 break;
1197 case HDSPM_madiFreq88_2:
1198 rate = 88200;
1199 break;
1200 case HDSPM_madiFreq96:
1201 rate = 96000;
1202 break;
1203 case HDSPM_madiFreq128:
1204 rate = 128000;
1205 break;
1206 case HDSPM_madiFreq176_4:
1207 rate = 176400;
1208 break;
1209 case HDSPM_madiFreq192:
1210 rate = 192000;
1211 break;
1212 default:
1213 rate = 0;
1214 break;
1215 }
1216
1217 /* QS and DS rates normally can not be detected
1218 * automatically by the card. Only exception is MADI
1219 * in 96k frame mode.
1220 *
1221 * So if we read SS values (32 .. 48k), check for
1222 * user-provided DS/QS bits in the control register
1223 * and multiply the base frequency accordingly.
1224 */
1225 if (rate <= 48000) {
1226 if (hdspm->control_register & HDSPM_QuadSpeed)
1227 rate *= 4;
1228 else if (hdspm->control_register &
1229 HDSPM_DoubleSpeed)
1230 rate *= 2;
1231 }
1232 }
1233 break;
1234 }
1235
1236 return rate;
1237}
1238
1239/* return latency in samples per period */
1240static int hdspm_get_latency(struct hdspm *hdspm)
1241{
1242 int n;
1243
1244 n = hdspm_decode_latency(hdspm->control_register);
1245
1246 /* Special case for new RME cards with 32 samples period size.
1247 * The three latency bits in the control register
1248 * (HDSP_LatencyMask) encode latency values of 64 samples as
1249 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1250 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1251 * it corresponds to 32 samples.
1252 */
1253 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1254 n = -1;
1255
1256 return 1 << (n + 6);
1257}
1258
1259/* Latency function */
1260static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1261{
1262 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1263}
1264
1265
1266static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1267{
1268 int position;
1269
1270 position = hdspm_read(hdspm, HDSPM_statusRegister);
1271
1272 switch (hdspm->io_type) {
1273 case RayDAT:
1274 case AIO:
1275 position &= HDSPM_BufferPositionMask;
1276 position /= 4; /* Bytes per sample */
1277 break;
1278 default:
1279 position = (position & HDSPM_BufferID) ?
1280 (hdspm->period_bytes / 4) : 0;
1281 }
1282
1283 return position;
1284}
1285
1286
1287static inline void hdspm_start_audio(struct hdspm * s)
1288{
1289 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1290 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1291}
1292
1293static inline void hdspm_stop_audio(struct hdspm * s)
1294{
1295 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1296 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1297}
1298
1299/* should I silence all or only opened ones ? doit all for first even is 4MB*/
1300static void hdspm_silence_playback(struct hdspm *hdspm)
1301{
1302 int i;
1303 int n = hdspm->period_bytes;
1304 void *buf = hdspm->playback_buffer;
1305
1306 if (buf == NULL)
1307 return;
1308
1309 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1310 memset(buf, 0, n);
1311 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1312 }
1313}
1314
1315static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1316{
1317 int n;
1318
1319 spin_lock_irq(&s->lock);
1320
1321 if (32 == frames) {
1322 /* Special case for new RME cards like RayDAT/AIO which
1323 * support period sizes of 32 samples. Since latency is
1324 * encoded in the three bits of HDSP_LatencyMask, we can only
1325 * have values from 0 .. 7. While 0 still means 64 samples and
1326 * 6 represents 4096 samples on all cards, 7 represents 8192
1327 * on older cards and 32 samples on new cards.
1328 *
1329 * In other words, period size in samples is calculated by
1330 * 2^(n+6) with n ranging from 0 .. 7.
1331 */
1332 n = 7;
1333 } else {
1334 frames >>= 7;
1335 n = 0;
1336 while (frames) {
1337 n++;
1338 frames >>= 1;
1339 }
1340 }
1341
1342 s->control_register &= ~HDSPM_LatencyMask;
1343 s->control_register |= hdspm_encode_latency(n);
1344
1345 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1346
1347 hdspm_compute_period_size(s);
1348
1349 spin_unlock_irq(&s->lock);
1350
1351 return 0;
1352}
1353
1354static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1355{
1356 u64 freq_const;
1357
1358 if (period == 0)
1359 return 0;
1360
1361 switch (hdspm->io_type) {
1362 case MADI:
1363 case AES32:
1364 freq_const = 110069313433624ULL;
1365 break;
1366 case RayDAT:
1367 case AIO:
1368 freq_const = 104857600000000ULL;
1369 break;
1370 case MADIface:
1371 freq_const = 131072000000000ULL;
1372 break;
1373 default:
1374 snd_BUG();
1375 return 0;
1376 }
1377
1378 return div_u64(freq_const, period);
1379}
1380
1381
1382static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1383{
1384 u64 n;
1385
1386 if (rate >= 112000)
1387 rate /= 4;
1388 else if (rate >= 56000)
1389 rate /= 2;
1390
1391 switch (hdspm->io_type) {
1392 case MADIface:
1393 n = 131072000000000ULL; /* 125 MHz */
1394 break;
1395 case MADI:
1396 case AES32:
1397 n = 110069313433624ULL; /* 105 MHz */
1398 break;
1399 case RayDAT:
1400 case AIO:
1401 n = 104857600000000ULL; /* 100 MHz */
1402 break;
1403 default:
1404 snd_BUG();
1405 return;
1406 }
1407
1408 n = div_u64(n, rate);
1409 /* n should be less than 2^32 for being written to FREQ register */
1410 snd_BUG_ON(n >> 32);
1411 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1412}
1413
1414/* dummy set rate lets see what happens */
1415static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1416{
1417 int current_rate;
1418 int rate_bits;
1419 int not_set = 0;
1420 int current_speed, target_speed;
1421
1422 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1423 it (e.g. during module initialization).
1424 */
1425
1426 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1427
1428 /* SLAVE --- */
1429 if (called_internally) {
1430
1431 /* request from ctl or card initialization
1432 just make a warning an remember setting
1433 for future master mode switching */
1434
1435 snd_printk(KERN_WARNING "HDSPM: "
1436 "Warning: device is not running "
1437 "as a clock master.\n");
1438 not_set = 1;
1439 } else {
1440
1441 /* hw_param request while in AutoSync mode */
1442 int external_freq =
1443 hdspm_external_sample_rate(hdspm);
1444
1445 if (hdspm_autosync_ref(hdspm) ==
1446 HDSPM_AUTOSYNC_FROM_NONE) {
1447
1448 snd_printk(KERN_WARNING "HDSPM: "
1449 "Detected no Externel Sync \n");
1450 not_set = 1;
1451
1452 } else if (rate != external_freq) {
1453
1454 snd_printk(KERN_WARNING "HDSPM: "
1455 "Warning: No AutoSync source for "
1456 "requested rate\n");
1457 not_set = 1;
1458 }
1459 }
1460 }
1461
1462 current_rate = hdspm->system_sample_rate;
1463
1464 /* Changing between Singe, Double and Quad speed is not
1465 allowed if any substreams are open. This is because such a change
1466 causes a shift in the location of the DMA buffers and a reduction
1467 in the number of available buffers.
1468
1469 Note that a similar but essentially insoluble problem exists for
1470 externally-driven rate changes. All we can do is to flag rate
1471 changes in the read/write routines.
1472 */
1473
1474 if (current_rate <= 48000)
1475 current_speed = HDSPM_SPEED_SINGLE;
1476 else if (current_rate <= 96000)
1477 current_speed = HDSPM_SPEED_DOUBLE;
1478 else
1479 current_speed = HDSPM_SPEED_QUAD;
1480
1481 if (rate <= 48000)
1482 target_speed = HDSPM_SPEED_SINGLE;
1483 else if (rate <= 96000)
1484 target_speed = HDSPM_SPEED_DOUBLE;
1485 else
1486 target_speed = HDSPM_SPEED_QUAD;
1487
1488 switch (rate) {
1489 case 32000:
1490 rate_bits = HDSPM_Frequency32KHz;
1491 break;
1492 case 44100:
1493 rate_bits = HDSPM_Frequency44_1KHz;
1494 break;
1495 case 48000:
1496 rate_bits = HDSPM_Frequency48KHz;
1497 break;
1498 case 64000:
1499 rate_bits = HDSPM_Frequency64KHz;
1500 break;
1501 case 88200:
1502 rate_bits = HDSPM_Frequency88_2KHz;
1503 break;
1504 case 96000:
1505 rate_bits = HDSPM_Frequency96KHz;
1506 break;
1507 case 128000:
1508 rate_bits = HDSPM_Frequency128KHz;
1509 break;
1510 case 176400:
1511 rate_bits = HDSPM_Frequency176_4KHz;
1512 break;
1513 case 192000:
1514 rate_bits = HDSPM_Frequency192KHz;
1515 break;
1516 default:
1517 return -EINVAL;
1518 }
1519
1520 if (current_speed != target_speed
1521 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1522 snd_printk
1523 (KERN_ERR "HDSPM: "
1524 "cannot change from %s speed to %s speed mode "
1525 "(capture PID = %d, playback PID = %d)\n",
1526 hdspm_speed_names[current_speed],
1527 hdspm_speed_names[target_speed],
1528 hdspm->capture_pid, hdspm->playback_pid);
1529 return -EBUSY;
1530 }
1531
1532 hdspm->control_register &= ~HDSPM_FrequencyMask;
1533 hdspm->control_register |= rate_bits;
1534 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1535
1536 /* For AES32, need to set DDS value in FREQ register
1537 For MADI, also apparently */
1538 hdspm_set_dds_value(hdspm, rate);
1539
1540 if (AES32 == hdspm->io_type && rate != current_rate)
1541 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1542
1543 hdspm->system_sample_rate = rate;
1544
1545 if (rate <= 48000) {
1546 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1547 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1548 hdspm->max_channels_in = hdspm->ss_in_channels;
1549 hdspm->max_channels_out = hdspm->ss_out_channels;
1550 hdspm->port_names_in = hdspm->port_names_in_ss;
1551 hdspm->port_names_out = hdspm->port_names_out_ss;
1552 } else if (rate <= 96000) {
1553 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1554 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1555 hdspm->max_channels_in = hdspm->ds_in_channels;
1556 hdspm->max_channels_out = hdspm->ds_out_channels;
1557 hdspm->port_names_in = hdspm->port_names_in_ds;
1558 hdspm->port_names_out = hdspm->port_names_out_ds;
1559 } else {
1560 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1561 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1562 hdspm->max_channels_in = hdspm->qs_in_channels;
1563 hdspm->max_channels_out = hdspm->qs_out_channels;
1564 hdspm->port_names_in = hdspm->port_names_in_qs;
1565 hdspm->port_names_out = hdspm->port_names_out_qs;
1566 }
1567
1568 if (not_set != 0)
1569 return -1;
1570
1571 return 0;
1572}
1573
1574/* mainly for init to 0 on load */
1575static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1576{
1577 int i, j;
1578 unsigned int gain;
1579
1580 if (sgain > UNITY_GAIN)
1581 gain = UNITY_GAIN;
1582 else if (sgain < 0)
1583 gain = 0;
1584 else
1585 gain = sgain;
1586
1587 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1588 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1589 hdspm_write_in_gain(hdspm, i, j, gain);
1590 hdspm_write_pb_gain(hdspm, i, j, gain);
1591 }
1592}
1593
1594/*----------------------------------------------------------------------------
1595 MIDI
1596 ----------------------------------------------------------------------------*/
1597
1598static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1599 int id)
1600{
1601 /* the hardware already does the relevant bit-mask with 0xff */
1602 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1603}
1604
1605static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1606 int val)
1607{
1608 /* the hardware already does the relevant bit-mask with 0xff */
1609 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1610}
1611
1612static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1613{
1614 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1615}
1616
1617static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1618{
1619 int fifo_bytes_used;
1620
1621 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1622
1623 if (fifo_bytes_used < 128)
1624 return 128 - fifo_bytes_used;
1625 else
1626 return 0;
1627}
1628
1629static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1630{
1631 while (snd_hdspm_midi_input_available (hdspm, id))
1632 snd_hdspm_midi_read_byte (hdspm, id);
1633}
1634
1635static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1636{
1637 unsigned long flags;
1638 int n_pending;
1639 int to_write;
1640 int i;
1641 unsigned char buf[128];
1642
1643 /* Output is not interrupt driven */
1644
1645 spin_lock_irqsave (&hmidi->lock, flags);
1646 if (hmidi->output &&
1647 !snd_rawmidi_transmit_empty (hmidi->output)) {
1648 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1649 hmidi->id);
1650 if (n_pending > 0) {
1651 if (n_pending > (int)sizeof (buf))
1652 n_pending = sizeof (buf);
1653
1654 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1655 n_pending);
1656 if (to_write > 0) {
1657 for (i = 0; i < to_write; ++i)
1658 snd_hdspm_midi_write_byte (hmidi->hdspm,
1659 hmidi->id,
1660 buf[i]);
1661 }
1662 }
1663 }
1664 spin_unlock_irqrestore (&hmidi->lock, flags);
1665 return 0;
1666}
1667
1668static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1669{
1670 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1671 * input FIFO size
1672 */
1673 unsigned long flags;
1674 int n_pending;
1675 int i;
1676
1677 spin_lock_irqsave (&hmidi->lock, flags);
1678 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1679 if (n_pending > 0) {
1680 if (hmidi->input) {
1681 if (n_pending > (int)sizeof (buf))
1682 n_pending = sizeof (buf);
1683 for (i = 0; i < n_pending; ++i)
1684 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1685 hmidi->id);
1686 if (n_pending)
1687 snd_rawmidi_receive (hmidi->input, buf,
1688 n_pending);
1689 } else {
1690 /* flush the MIDI input FIFO */
1691 while (n_pending--)
1692 snd_hdspm_midi_read_byte (hmidi->hdspm,
1693 hmidi->id);
1694 }
1695 }
1696 hmidi->pending = 0;
1697 spin_unlock_irqrestore(&hmidi->lock, flags);
1698
1699 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1700 hmidi->hdspm->control_register |= hmidi->ie;
1701 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1702 hmidi->hdspm->control_register);
1703 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1704
1705 return snd_hdspm_midi_output_write (hmidi);
1706}
1707
1708static void
1709snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1710{
1711 struct hdspm *hdspm;
1712 struct hdspm_midi *hmidi;
1713 unsigned long flags;
1714
1715 hmidi = substream->rmidi->private_data;
1716 hdspm = hmidi->hdspm;
1717
1718 spin_lock_irqsave (&hdspm->lock, flags);
1719 if (up) {
1720 if (!(hdspm->control_register & hmidi->ie)) {
1721 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1722 hdspm->control_register |= hmidi->ie;
1723 }
1724 } else {
1725 hdspm->control_register &= ~hmidi->ie;
1726 }
1727
1728 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1729 spin_unlock_irqrestore (&hdspm->lock, flags);
1730}
1731
1732static void snd_hdspm_midi_output_timer(unsigned long data)
1733{
1734 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1735 unsigned long flags;
1736
1737 snd_hdspm_midi_output_write(hmidi);
1738 spin_lock_irqsave (&hmidi->lock, flags);
1739
1740 /* this does not bump hmidi->istimer, because the
1741 kernel automatically removed the timer when it
1742 expired, and we are now adding it back, thus
1743 leaving istimer wherever it was set before.
1744 */
1745
1746 if (hmidi->istimer) {
1747 hmidi->timer.expires = 1 + jiffies;
1748 add_timer(&hmidi->timer);
1749 }
1750
1751 spin_unlock_irqrestore (&hmidi->lock, flags);
1752}
1753
1754static void
1755snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1756{
1757 struct hdspm_midi *hmidi;
1758 unsigned long flags;
1759
1760 hmidi = substream->rmidi->private_data;
1761 spin_lock_irqsave (&hmidi->lock, flags);
1762 if (up) {
1763 if (!hmidi->istimer) {
1764 init_timer(&hmidi->timer);
1765 hmidi->timer.function = snd_hdspm_midi_output_timer;
1766 hmidi->timer.data = (unsigned long) hmidi;
1767 hmidi->timer.expires = 1 + jiffies;
1768 add_timer(&hmidi->timer);
1769 hmidi->istimer++;
1770 }
1771 } else {
1772 if (hmidi->istimer && --hmidi->istimer <= 0)
1773 del_timer (&hmidi->timer);
1774 }
1775 spin_unlock_irqrestore (&hmidi->lock, flags);
1776 if (up)
1777 snd_hdspm_midi_output_write(hmidi);
1778}
1779
1780static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1781{
1782 struct hdspm_midi *hmidi;
1783
1784 hmidi = substream->rmidi->private_data;
1785 spin_lock_irq (&hmidi->lock);
1786 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1787 hmidi->input = substream;
1788 spin_unlock_irq (&hmidi->lock);
1789
1790 return 0;
1791}
1792
1793static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1794{
1795 struct hdspm_midi *hmidi;
1796
1797 hmidi = substream->rmidi->private_data;
1798 spin_lock_irq (&hmidi->lock);
1799 hmidi->output = substream;
1800 spin_unlock_irq (&hmidi->lock);
1801
1802 return 0;
1803}
1804
1805static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1806{
1807 struct hdspm_midi *hmidi;
1808
1809 snd_hdspm_midi_input_trigger (substream, 0);
1810
1811 hmidi = substream->rmidi->private_data;
1812 spin_lock_irq (&hmidi->lock);
1813 hmidi->input = NULL;
1814 spin_unlock_irq (&hmidi->lock);
1815
1816 return 0;
1817}
1818
1819static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1820{
1821 struct hdspm_midi *hmidi;
1822
1823 snd_hdspm_midi_output_trigger (substream, 0);
1824
1825 hmidi = substream->rmidi->private_data;
1826 spin_lock_irq (&hmidi->lock);
1827 hmidi->output = NULL;
1828 spin_unlock_irq (&hmidi->lock);
1829
1830 return 0;
1831}
1832
1833static struct snd_rawmidi_ops snd_hdspm_midi_output =
1834{
1835 .open = snd_hdspm_midi_output_open,
1836 .close = snd_hdspm_midi_output_close,
1837 .trigger = snd_hdspm_midi_output_trigger,
1838};
1839
1840static struct snd_rawmidi_ops snd_hdspm_midi_input =
1841{
1842 .open = snd_hdspm_midi_input_open,
1843 .close = snd_hdspm_midi_input_close,
1844 .trigger = snd_hdspm_midi_input_trigger,
1845};
1846
1847static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1848 struct hdspm *hdspm, int id)
1849{
1850 int err;
1851 char buf[32];
1852
1853 hdspm->midi[id].id = id;
1854 hdspm->midi[id].hdspm = hdspm;
1855 spin_lock_init (&hdspm->midi[id].lock);
1856
1857 if (0 == id) {
1858 if (MADIface == hdspm->io_type) {
1859 /* MIDI-over-MADI on HDSPe MADIface */
1860 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1861 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1862 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1863 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1864 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1865 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1866 } else {
1867 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1868 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1869 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1870 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1871 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1872 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1873 }
1874 } else if (1 == id) {
1875 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1876 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1877 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1878 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1879 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1880 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1881 } else if ((2 == id) && (MADI == hdspm->io_type)) {
1882 /* MIDI-over-MADI on HDSPe MADI */
1883 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1884 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1885 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1886 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1887 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1888 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1889 } else if (2 == id) {
1890 /* TCO MTC, read only */
1891 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1892 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1893 hdspm->midi[2].dataOut = -1;
1894 hdspm->midi[2].statusOut = -1;
1895 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1896 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1897 } else if (3 == id) {
1898 /* TCO MTC on HDSPe MADI */
1899 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1900 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1901 hdspm->midi[3].dataOut = -1;
1902 hdspm->midi[3].statusOut = -1;
1903 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1904 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1905 }
1906
1907 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1908 (MADIface == hdspm->io_type)))) {
1909 if ((id == 0) && (MADIface == hdspm->io_type)) {
1910 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1911 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1912 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1913 } else {
1914 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1915 }
1916 err = snd_rawmidi_new(card, buf, id, 1, 1,
1917 &hdspm->midi[id].rmidi);
1918 if (err < 0)
1919 return err;
1920
1921 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1922 card->id, id+1);
1923 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1924
1925 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1926 SNDRV_RAWMIDI_STREAM_OUTPUT,
1927 &snd_hdspm_midi_output);
1928 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1929 SNDRV_RAWMIDI_STREAM_INPUT,
1930 &snd_hdspm_midi_input);
1931
1932 hdspm->midi[id].rmidi->info_flags |=
1933 SNDRV_RAWMIDI_INFO_OUTPUT |
1934 SNDRV_RAWMIDI_INFO_INPUT |
1935 SNDRV_RAWMIDI_INFO_DUPLEX;
1936 } else {
1937 /* TCO MTC, read only */
1938 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1939 err = snd_rawmidi_new(card, buf, id, 1, 1,
1940 &hdspm->midi[id].rmidi);
1941 if (err < 0)
1942 return err;
1943
1944 sprintf(hdspm->midi[id].rmidi->name,
1945 "%s MTC %d", card->id, id+1);
1946 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1947
1948 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1949 SNDRV_RAWMIDI_STREAM_INPUT,
1950 &snd_hdspm_midi_input);
1951
1952 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1953 }
1954
1955 return 0;
1956}
1957
1958
1959static void hdspm_midi_tasklet(unsigned long arg)
1960{
1961 struct hdspm *hdspm = (struct hdspm *)arg;
1962 int i = 0;
1963
1964 while (i < hdspm->midiPorts) {
1965 if (hdspm->midi[i].pending)
1966 snd_hdspm_midi_input_read(&hdspm->midi[i]);
1967
1968 i++;
1969 }
1970}
1971
1972
1973/*-----------------------------------------------------------------------------
1974 Status Interface
1975 ----------------------------------------------------------------------------*/
1976
1977/* get the system sample rate which is set */
1978
1979
1980/**
1981 * Calculate the real sample rate from the
1982 * current DDS value.
1983 **/
1984static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1985{
1986 unsigned int period, rate;
1987
1988 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1989 rate = hdspm_calc_dds_value(hdspm, period);
1990
1991 if (rate > 207000) {
1992 /* Unreasonable high sample rate as seen on PCI MADI cards.
1993 * Use the cached value instead.
1994 */
1995 rate = hdspm->system_sample_rate;
1996 }
1997
1998 return rate;
1999}
2000
2001
2002#define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2003{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2004 .name = xname, \
2005 .index = xindex, \
2006 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2007 .info = snd_hdspm_info_system_sample_rate, \
2008 .get = snd_hdspm_get_system_sample_rate \
2009}
2010
2011static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2012 struct snd_ctl_elem_info *uinfo)
2013{
2014 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2015 uinfo->count = 1;
2016 uinfo->value.integer.min = 27000;
2017 uinfo->value.integer.max = 207000;
2018 uinfo->value.integer.step = 1;
2019 return 0;
2020}
2021
2022
2023static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2024 struct snd_ctl_elem_value *
2025 ucontrol)
2026{
2027 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2028
2029 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2030 return 0;
2031}
2032
2033
2034/**
2035 * Returns the WordClock sample rate class for the given card.
2036 **/
2037static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2038{
2039 int status;
2040
2041 switch (hdspm->io_type) {
2042 case RayDAT:
2043 case AIO:
2044 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2045 return (status >> 16) & 0xF;
2046 break;
2047 default:
2048 break;
2049 }
2050
2051
2052 return 0;
2053}
2054
2055
2056/**
2057 * Returns the TCO sample rate class for the given card.
2058 **/
2059static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2060{
2061 int status;
2062
2063 if (hdspm->tco) {
2064 switch (hdspm->io_type) {
2065 case RayDAT:
2066 case AIO:
2067 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2068 return (status >> 20) & 0xF;
2069 break;
2070 default:
2071 break;
2072 }
2073 }
2074
2075 return 0;
2076}
2077
2078
2079/**
2080 * Returns the SYNC_IN sample rate class for the given card.
2081 **/
2082static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2083{
2084 int status;
2085
2086 if (hdspm->tco) {
2087 switch (hdspm->io_type) {
2088 case RayDAT:
2089 case AIO:
2090 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2091 return (status >> 12) & 0xF;
2092 break;
2093 default:
2094 break;
2095 }
2096 }
2097
2098 return 0;
2099}
2100
2101
2102/**
2103 * Returns the sample rate class for input source <idx> for
2104 * 'new style' cards like the AIO and RayDAT.
2105 **/
2106static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2107{
2108 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2109
2110 return (status >> (idx*4)) & 0xF;
2111}
2112
2113
2114
2115#define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2116{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2117 .name = xname, \
2118 .private_value = xindex, \
2119 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2120 .info = snd_hdspm_info_autosync_sample_rate, \
2121 .get = snd_hdspm_get_autosync_sample_rate \
2122}
2123
2124
2125static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2126 struct snd_ctl_elem_info *uinfo)
2127{
2128 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2129 uinfo->count = 1;
2130 uinfo->value.enumerated.items = 10;
2131
2132 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2133 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2134 strcpy(uinfo->value.enumerated.name,
2135 texts_freq[uinfo->value.enumerated.item]);
2136 return 0;
2137}
2138
2139
2140static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2141 struct snd_ctl_elem_value *
2142 ucontrol)
2143{
2144 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2145
2146 switch (hdspm->io_type) {
2147 case RayDAT:
2148 switch (kcontrol->private_value) {
2149 case 0:
2150 ucontrol->value.enumerated.item[0] =
2151 hdspm_get_wc_sample_rate(hdspm);
2152 break;
2153 case 7:
2154 ucontrol->value.enumerated.item[0] =
2155 hdspm_get_tco_sample_rate(hdspm);
2156 break;
2157 case 8:
2158 ucontrol->value.enumerated.item[0] =
2159 hdspm_get_sync_in_sample_rate(hdspm);
2160 break;
2161 default:
2162 ucontrol->value.enumerated.item[0] =
2163 hdspm_get_s1_sample_rate(hdspm,
2164 kcontrol->private_value-1);
2165 }
2166
2167 case AIO:
2168 switch (kcontrol->private_value) {
2169 case 0: /* WC */
2170 ucontrol->value.enumerated.item[0] =
2171 hdspm_get_wc_sample_rate(hdspm);
2172 break;
2173 case 4: /* TCO */
2174 ucontrol->value.enumerated.item[0] =
2175 hdspm_get_tco_sample_rate(hdspm);
2176 break;
2177 case 5: /* SYNC_IN */
2178 ucontrol->value.enumerated.item[0] =
2179 hdspm_get_sync_in_sample_rate(hdspm);
2180 break;
2181 default:
2182 ucontrol->value.enumerated.item[0] =
2183 hdspm_get_s1_sample_rate(hdspm,
2184 ucontrol->id.index-1);
2185 }
2186
2187 case AES32:
2188
2189 switch (kcontrol->private_value) {
2190 case 0: /* WC */
2191 ucontrol->value.enumerated.item[0] =
2192 hdspm_get_wc_sample_rate(hdspm);
2193 break;
2194 case 9: /* TCO */
2195 ucontrol->value.enumerated.item[0] =
2196 hdspm_get_tco_sample_rate(hdspm);
2197 break;
2198 case 10: /* SYNC_IN */
2199 ucontrol->value.enumerated.item[0] =
2200 hdspm_get_sync_in_sample_rate(hdspm);
2201 break;
2202 default: /* AES1 to AES8 */
2203 ucontrol->value.enumerated.item[0] =
2204 hdspm_get_s1_sample_rate(hdspm,
2205 kcontrol->private_value-1);
2206 break;
2207
2208 }
2209 default:
2210 break;
2211 }
2212
2213 return 0;
2214}
2215
2216
2217#define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2218{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2219 .name = xname, \
2220 .index = xindex, \
2221 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2222 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2223 .info = snd_hdspm_info_system_clock_mode, \
2224 .get = snd_hdspm_get_system_clock_mode, \
2225 .put = snd_hdspm_put_system_clock_mode, \
2226}
2227
2228
2229/**
2230 * Returns the system clock mode for the given card.
2231 * @returns 0 - master, 1 - slave
2232 **/
2233static int hdspm_system_clock_mode(struct hdspm *hdspm)
2234{
2235 switch (hdspm->io_type) {
2236 case AIO:
2237 case RayDAT:
2238 if (hdspm->settings_register & HDSPM_c0Master)
2239 return 0;
2240 break;
2241
2242 default:
2243 if (hdspm->control_register & HDSPM_ClockModeMaster)
2244 return 0;
2245 }
2246
2247 return 1;
2248}
2249
2250
2251/**
2252 * Sets the system clock mode.
2253 * @param mode 0 - master, 1 - slave
2254 **/
2255static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2256{
2257 switch (hdspm->io_type) {
2258 case AIO:
2259 case RayDAT:
2260 if (0 == mode)
2261 hdspm->settings_register |= HDSPM_c0Master;
2262 else
2263 hdspm->settings_register &= ~HDSPM_c0Master;
2264
2265 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2266 break;
2267
2268 default:
2269 if (0 == mode)
2270 hdspm->control_register |= HDSPM_ClockModeMaster;
2271 else
2272 hdspm->control_register &= ~HDSPM_ClockModeMaster;
2273
2274 hdspm_write(hdspm, HDSPM_controlRegister,
2275 hdspm->control_register);
2276 }
2277}
2278
2279
2280static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2281 struct snd_ctl_elem_info *uinfo)
2282{
2283 static char *texts[] = { "Master", "AutoSync" };
2284
2285 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2286 uinfo->count = 1;
2287 uinfo->value.enumerated.items = 2;
2288 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2289 uinfo->value.enumerated.item =
2290 uinfo->value.enumerated.items - 1;
2291 strcpy(uinfo->value.enumerated.name,
2292 texts[uinfo->value.enumerated.item]);
2293 return 0;
2294}
2295
2296static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2297 struct snd_ctl_elem_value *ucontrol)
2298{
2299 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2300
2301 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2302 return 0;
2303}
2304
2305static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2306 struct snd_ctl_elem_value *ucontrol)
2307{
2308 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2309 int val;
2310
2311 if (!snd_hdspm_use_is_exclusive(hdspm))
2312 return -EBUSY;
2313
2314 val = ucontrol->value.enumerated.item[0];
2315 if (val < 0)
2316 val = 0;
2317 else if (val > 1)
2318 val = 1;
2319
2320 hdspm_set_system_clock_mode(hdspm, val);
2321
2322 return 0;
2323}
2324
2325
2326#define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2327{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2328 .name = xname, \
2329 .index = xindex, \
2330 .info = snd_hdspm_info_clock_source, \
2331 .get = snd_hdspm_get_clock_source, \
2332 .put = snd_hdspm_put_clock_source \
2333}
2334
2335
2336static int hdspm_clock_source(struct hdspm * hdspm)
2337{
2338 switch (hdspm->system_sample_rate) {
2339 case 32000: return 0;
2340 case 44100: return 1;
2341 case 48000: return 2;
2342 case 64000: return 3;
2343 case 88200: return 4;
2344 case 96000: return 5;
2345 case 128000: return 6;
2346 case 176400: return 7;
2347 case 192000: return 8;
2348 }
2349
2350 return -1;
2351}
2352
2353static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2354{
2355 int rate;
2356 switch (mode) {
2357 case 0:
2358 rate = 32000; break;
2359 case 1:
2360 rate = 44100; break;
2361 case 2:
2362 rate = 48000; break;
2363 case 3:
2364 rate = 64000; break;
2365 case 4:
2366 rate = 88200; break;
2367 case 5:
2368 rate = 96000; break;
2369 case 6:
2370 rate = 128000; break;
2371 case 7:
2372 rate = 176400; break;
2373 case 8:
2374 rate = 192000; break;
2375 default:
2376 rate = 48000;
2377 }
2378 hdspm_set_rate(hdspm, rate, 1);
2379 return 0;
2380}
2381
2382static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2383 struct snd_ctl_elem_info *uinfo)
2384{
2385 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2386 uinfo->count = 1;
2387 uinfo->value.enumerated.items = 9;
2388
2389 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2390 uinfo->value.enumerated.item =
2391 uinfo->value.enumerated.items - 1;
2392
2393 strcpy(uinfo->value.enumerated.name,
2394 texts_freq[uinfo->value.enumerated.item+1]);
2395
2396 return 0;
2397}
2398
2399static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2400 struct snd_ctl_elem_value *ucontrol)
2401{
2402 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2403
2404 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2405 return 0;
2406}
2407
2408static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2409 struct snd_ctl_elem_value *ucontrol)
2410{
2411 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2412 int change;
2413 int val;
2414
2415 if (!snd_hdspm_use_is_exclusive(hdspm))
2416 return -EBUSY;
2417 val = ucontrol->value.enumerated.item[0];
2418 if (val < 0)
2419 val = 0;
2420 if (val > 9)
2421 val = 9;
2422 spin_lock_irq(&hdspm->lock);
2423 if (val != hdspm_clock_source(hdspm))
2424 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2425 else
2426 change = 0;
2427 spin_unlock_irq(&hdspm->lock);
2428 return change;
2429}
2430
2431
2432#define HDSPM_PREF_SYNC_REF(xname, xindex) \
2433{.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2434 .name = xname, \
2435 .index = xindex, \
2436 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2437 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2438 .info = snd_hdspm_info_pref_sync_ref, \
2439 .get = snd_hdspm_get_pref_sync_ref, \
2440 .put = snd_hdspm_put_pref_sync_ref \
2441}
2442
2443
2444/**
2445 * Returns the current preferred sync reference setting.
2446 * The semantics of the return value are depending on the
2447 * card, please see the comments for clarification.
2448 **/
2449static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2450{
2451 switch (hdspm->io_type) {
2452 case AES32:
2453 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2454 case 0: return 0; /* WC */
2455 case HDSPM_SyncRef0: return 1; /* AES 1 */
2456 case HDSPM_SyncRef1: return 2; /* AES 2 */
2457 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2458 case HDSPM_SyncRef2: return 4; /* AES 4 */
2459 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2460 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2461 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2462 return 7; /* AES 7 */
2463 case HDSPM_SyncRef3: return 8; /* AES 8 */
2464 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2465 }
2466 break;
2467
2468 case MADI:
2469 case MADIface:
2470 if (hdspm->tco) {
2471 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2472 case 0: return 0; /* WC */
2473 case HDSPM_SyncRef0: return 1; /* MADI */
2474 case HDSPM_SyncRef1: return 2; /* TCO */
2475 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2476 return 3; /* SYNC_IN */
2477 }
2478 } else {
2479 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2480 case 0: return 0; /* WC */
2481 case HDSPM_SyncRef0: return 1; /* MADI */
2482 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2483 return 2; /* SYNC_IN */
2484 }
2485 }
2486 break;
2487
2488 case RayDAT:
2489 if (hdspm->tco) {
2490 switch ((hdspm->settings_register &
2491 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2492 case 0: return 0; /* WC */
2493 case 3: return 1; /* ADAT 1 */
2494 case 4: return 2; /* ADAT 2 */
2495 case 5: return 3; /* ADAT 3 */
2496 case 6: return 4; /* ADAT 4 */
2497 case 1: return 5; /* AES */
2498 case 2: return 6; /* SPDIF */
2499 case 9: return 7; /* TCO */
2500 case 10: return 8; /* SYNC_IN */
2501 }
2502 } else {
2503 switch ((hdspm->settings_register &
2504 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2505 case 0: return 0; /* WC */
2506 case 3: return 1; /* ADAT 1 */
2507 case 4: return 2; /* ADAT 2 */
2508 case 5: return 3; /* ADAT 3 */
2509 case 6: return 4; /* ADAT 4 */
2510 case 1: return 5; /* AES */
2511 case 2: return 6; /* SPDIF */
2512 case 10: return 7; /* SYNC_IN */
2513 }
2514 }
2515
2516 break;
2517
2518 case AIO:
2519 if (hdspm->tco) {
2520 switch ((hdspm->settings_register &
2521 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2522 case 0: return 0; /* WC */
2523 case 3: return 1; /* ADAT */
2524 case 1: return 2; /* AES */
2525 case 2: return 3; /* SPDIF */
2526 case 9: return 4; /* TCO */
2527 case 10: return 5; /* SYNC_IN */
2528 }
2529 } else {
2530 switch ((hdspm->settings_register &
2531 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2532 case 0: return 0; /* WC */
2533 case 3: return 1; /* ADAT */
2534 case 1: return 2; /* AES */
2535 case 2: return 3; /* SPDIF */
2536 case 10: return 4; /* SYNC_IN */
2537 }
2538 }
2539
2540 break;
2541 }
2542
2543 return -1;
2544}
2545
2546
2547/**
2548 * Set the preferred sync reference to <pref>. The semantics
2549 * of <pref> are depending on the card type, see the comments
2550 * for clarification.
2551 **/
2552static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2553{
2554 int p = 0;
2555
2556 switch (hdspm->io_type) {
2557 case AES32:
2558 hdspm->control_register &= ~HDSPM_SyncRefMask;
2559 switch (pref) {
2560 case 0: /* WC */
2561 break;
2562 case 1: /* AES 1 */
2563 hdspm->control_register |= HDSPM_SyncRef0;
2564 break;
2565 case 2: /* AES 2 */
2566 hdspm->control_register |= HDSPM_SyncRef1;
2567 break;
2568 case 3: /* AES 3 */
2569 hdspm->control_register |=
2570 HDSPM_SyncRef1+HDSPM_SyncRef0;
2571 break;
2572 case 4: /* AES 4 */
2573 hdspm->control_register |= HDSPM_SyncRef2;
2574 break;
2575 case 5: /* AES 5 */
2576 hdspm->control_register |=
2577 HDSPM_SyncRef2+HDSPM_SyncRef0;
2578 break;
2579 case 6: /* AES 6 */
2580 hdspm->control_register |=
2581 HDSPM_SyncRef2+HDSPM_SyncRef1;
2582 break;
2583 case 7: /* AES 7 */
2584 hdspm->control_register |=
2585 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2586 break;
2587 case 8: /* AES 8 */
2588 hdspm->control_register |= HDSPM_SyncRef3;
2589 break;
2590 case 9: /* TCO */
2591 hdspm->control_register |=
2592 HDSPM_SyncRef3+HDSPM_SyncRef0;
2593 break;
2594 default:
2595 return -1;
2596 }
2597
2598 break;
2599
2600 case MADI:
2601 case MADIface:
2602 hdspm->control_register &= ~HDSPM_SyncRefMask;
2603 if (hdspm->tco) {
2604 switch (pref) {
2605 case 0: /* WC */
2606 break;
2607 case 1: /* MADI */
2608 hdspm->control_register |= HDSPM_SyncRef0;
2609 break;
2610 case 2: /* TCO */
2611 hdspm->control_register |= HDSPM_SyncRef1;
2612 break;
2613 case 3: /* SYNC_IN */
2614 hdspm->control_register |=
2615 HDSPM_SyncRef0+HDSPM_SyncRef1;
2616 break;
2617 default:
2618 return -1;
2619 }
2620 } else {
2621 switch (pref) {
2622 case 0: /* WC */
2623 break;
2624 case 1: /* MADI */
2625 hdspm->control_register |= HDSPM_SyncRef0;
2626 break;
2627 case 2: /* SYNC_IN */
2628 hdspm->control_register |=
2629 HDSPM_SyncRef0+HDSPM_SyncRef1;
2630 break;
2631 default:
2632 return -1;
2633 }
2634 }
2635
2636 break;
2637
2638 case RayDAT:
2639 if (hdspm->tco) {
2640 switch (pref) {
2641 case 0: p = 0; break; /* WC */
2642 case 1: p = 3; break; /* ADAT 1 */
2643 case 2: p = 4; break; /* ADAT 2 */
2644 case 3: p = 5; break; /* ADAT 3 */
2645 case 4: p = 6; break; /* ADAT 4 */
2646 case 5: p = 1; break; /* AES */
2647 case 6: p = 2; break; /* SPDIF */
2648 case 7: p = 9; break; /* TCO */
2649 case 8: p = 10; break; /* SYNC_IN */
2650 default: return -1;
2651 }
2652 } else {
2653 switch (pref) {
2654 case 0: p = 0; break; /* WC */
2655 case 1: p = 3; break; /* ADAT 1 */
2656 case 2: p = 4; break; /* ADAT 2 */
2657 case 3: p = 5; break; /* ADAT 3 */
2658 case 4: p = 6; break; /* ADAT 4 */
2659 case 5: p = 1; break; /* AES */
2660 case 6: p = 2; break; /* SPDIF */
2661 case 7: p = 10; break; /* SYNC_IN */
2662 default: return -1;
2663 }
2664 }
2665 break;
2666
2667 case AIO:
2668 if (hdspm->tco) {
2669 switch (pref) {
2670 case 0: p = 0; break; /* WC */
2671 case 1: p = 3; break; /* ADAT */
2672 case 2: p = 1; break; /* AES */
2673 case 3: p = 2; break; /* SPDIF */
2674 case 4: p = 9; break; /* TCO */
2675 case 5: p = 10; break; /* SYNC_IN */
2676 default: return -1;
2677 }
2678 } else {
2679 switch (pref) {
2680 case 0: p = 0; break; /* WC */
2681 case 1: p = 3; break; /* ADAT */
2682 case 2: p = 1; break; /* AES */
2683 case 3: p = 2; break; /* SPDIF */
2684 case 4: p = 10; break; /* SYNC_IN */
2685 default: return -1;
2686 }
2687 }
2688 break;
2689 }
2690
2691 switch (hdspm->io_type) {
2692 case RayDAT:
2693 case AIO:
2694 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2695 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2696 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2697 break;
2698
2699 case MADI:
2700 case MADIface:
2701 case AES32:
2702 hdspm_write(hdspm, HDSPM_controlRegister,
2703 hdspm->control_register);
2704 }
2705
2706 return 0;
2707}
2708
2709
2710static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2711 struct snd_ctl_elem_info *uinfo)
2712{
2713 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2714
2715 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2716 uinfo->count = 1;
2717 uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2718
2719 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2720 uinfo->value.enumerated.item =
2721 uinfo->value.enumerated.items - 1;
2722
2723 strcpy(uinfo->value.enumerated.name,
2724 hdspm->texts_autosync[uinfo->value.enumerated.item]);
2725
2726 return 0;
2727}
2728
2729static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2730 struct snd_ctl_elem_value *ucontrol)
2731{
2732 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2733 int psf = hdspm_pref_sync_ref(hdspm);
2734
2735 if (psf >= 0) {
2736 ucontrol->value.enumerated.item[0] = psf;
2737 return 0;
2738 }
2739
2740 return -1;
2741}
2742
2743static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2744 struct snd_ctl_elem_value *ucontrol)
2745{
2746 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2747 int val, change = 0;
2748
2749 if (!snd_hdspm_use_is_exclusive(hdspm))
2750 return -EBUSY;
2751
2752 val = ucontrol->value.enumerated.item[0];
2753
2754 if (val < 0)
2755 val = 0;
2756 else if (val >= hdspm->texts_autosync_items)
2757 val = hdspm->texts_autosync_items-1;
2758
2759 spin_lock_irq(&hdspm->lock);
2760 if (val != hdspm_pref_sync_ref(hdspm))
2761 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2762
2763 spin_unlock_irq(&hdspm->lock);
2764 return change;
2765}
2766
2767
2768#define HDSPM_AUTOSYNC_REF(xname, xindex) \
2769{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2770 .name = xname, \
2771 .index = xindex, \
2772 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2773 .info = snd_hdspm_info_autosync_ref, \
2774 .get = snd_hdspm_get_autosync_ref, \
2775}
2776
2777static int hdspm_autosync_ref(struct hdspm *hdspm)
2778{
2779 if (AES32 == hdspm->io_type) {
2780 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2781 unsigned int syncref =
2782 (status >> HDSPM_AES32_syncref_bit) & 0xF;
2783 if (syncref == 0)
2784 return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2785 if (syncref <= 8)
2786 return syncref;
2787 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2788 } else if (MADI == hdspm->io_type) {
2789 /* This looks at the autosync selected sync reference */
2790 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2791
2792 switch (status2 & HDSPM_SelSyncRefMask) {
2793 case HDSPM_SelSyncRef_WORD:
2794 return HDSPM_AUTOSYNC_FROM_WORD;
2795 case HDSPM_SelSyncRef_MADI:
2796 return HDSPM_AUTOSYNC_FROM_MADI;
2797 case HDSPM_SelSyncRef_TCO:
2798 return HDSPM_AUTOSYNC_FROM_TCO;
2799 case HDSPM_SelSyncRef_SyncIn:
2800 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2801 case HDSPM_SelSyncRef_NVALID:
2802 return HDSPM_AUTOSYNC_FROM_NONE;
2803 default:
2804 return 0;
2805 }
2806
2807 }
2808 return 0;
2809}
2810
2811
2812static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2813 struct snd_ctl_elem_info *uinfo)
2814{
2815 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2816
2817 if (AES32 == hdspm->io_type) {
2818 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2819 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2820
2821 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2822 uinfo->count = 1;
2823 uinfo->value.enumerated.items = 10;
2824 if (uinfo->value.enumerated.item >=
2825 uinfo->value.enumerated.items)
2826 uinfo->value.enumerated.item =
2827 uinfo->value.enumerated.items - 1;
2828 strcpy(uinfo->value.enumerated.name,
2829 texts[uinfo->value.enumerated.item]);
2830 } else if (MADI == hdspm->io_type) {
2831 static char *texts[] = {"Word Clock", "MADI", "TCO",
2832 "Sync In", "None" };
2833
2834 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2835 uinfo->count = 1;
2836 uinfo->value.enumerated.items = 5;
2837 if (uinfo->value.enumerated.item >=
2838 uinfo->value.enumerated.items)
2839 uinfo->value.enumerated.item =
2840 uinfo->value.enumerated.items - 1;
2841 strcpy(uinfo->value.enumerated.name,
2842 texts[uinfo->value.enumerated.item]);
2843 }
2844 return 0;
2845}
2846
2847static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2848 struct snd_ctl_elem_value *ucontrol)
2849{
2850 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2851
2852 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2853 return 0;
2854}
2855
2856
2857#define HDSPM_LINE_OUT(xname, xindex) \
2858{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2859 .name = xname, \
2860 .index = xindex, \
2861 .info = snd_hdspm_info_line_out, \
2862 .get = snd_hdspm_get_line_out, \
2863 .put = snd_hdspm_put_line_out \
2864}
2865
2866static int hdspm_line_out(struct hdspm * hdspm)
2867{
2868 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2869}
2870
2871
2872static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2873{
2874 if (out)
2875 hdspm->control_register |= HDSPM_LineOut;
2876 else
2877 hdspm->control_register &= ~HDSPM_LineOut;
2878 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2879
2880 return 0;
2881}
2882
2883#define snd_hdspm_info_line_out snd_ctl_boolean_mono_info
2884
2885static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2886 struct snd_ctl_elem_value *ucontrol)
2887{
2888 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2889
2890 spin_lock_irq(&hdspm->lock);
2891 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2892 spin_unlock_irq(&hdspm->lock);
2893 return 0;
2894}
2895
2896static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2897 struct snd_ctl_elem_value *ucontrol)
2898{
2899 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2900 int change;
2901 unsigned int val;
2902
2903 if (!snd_hdspm_use_is_exclusive(hdspm))
2904 return -EBUSY;
2905 val = ucontrol->value.integer.value[0] & 1;
2906 spin_lock_irq(&hdspm->lock);
2907 change = (int) val != hdspm_line_out(hdspm);
2908 hdspm_set_line_output(hdspm, val);
2909 spin_unlock_irq(&hdspm->lock);
2910 return change;
2911}
2912
2913
2914#define HDSPM_TX_64(xname, xindex) \
2915{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2916 .name = xname, \
2917 .index = xindex, \
2918 .info = snd_hdspm_info_tx_64, \
2919 .get = snd_hdspm_get_tx_64, \
2920 .put = snd_hdspm_put_tx_64 \
2921}
2922
2923static int hdspm_tx_64(struct hdspm * hdspm)
2924{
2925 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2926}
2927
2928static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2929{
2930 if (out)
2931 hdspm->control_register |= HDSPM_TX_64ch;
2932 else
2933 hdspm->control_register &= ~HDSPM_TX_64ch;
2934 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2935
2936 return 0;
2937}
2938
2939#define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info
2940
2941static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2942 struct snd_ctl_elem_value *ucontrol)
2943{
2944 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2945
2946 spin_lock_irq(&hdspm->lock);
2947 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2948 spin_unlock_irq(&hdspm->lock);
2949 return 0;
2950}
2951
2952static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2953 struct snd_ctl_elem_value *ucontrol)
2954{
2955 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2956 int change;
2957 unsigned int val;
2958
2959 if (!snd_hdspm_use_is_exclusive(hdspm))
2960 return -EBUSY;
2961 val = ucontrol->value.integer.value[0] & 1;
2962 spin_lock_irq(&hdspm->lock);
2963 change = (int) val != hdspm_tx_64(hdspm);
2964 hdspm_set_tx_64(hdspm, val);
2965 spin_unlock_irq(&hdspm->lock);
2966 return change;
2967}
2968
2969
2970#define HDSPM_C_TMS(xname, xindex) \
2971{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2972 .name = xname, \
2973 .index = xindex, \
2974 .info = snd_hdspm_info_c_tms, \
2975 .get = snd_hdspm_get_c_tms, \
2976 .put = snd_hdspm_put_c_tms \
2977}
2978
2979static int hdspm_c_tms(struct hdspm * hdspm)
2980{
2981 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2982}
2983
2984static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
2985{
2986 if (out)
2987 hdspm->control_register |= HDSPM_clr_tms;
2988 else
2989 hdspm->control_register &= ~HDSPM_clr_tms;
2990 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2991
2992 return 0;
2993}
2994
2995#define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info
2996
2997static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2998 struct snd_ctl_elem_value *ucontrol)
2999{
3000 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3001
3002 spin_lock_irq(&hdspm->lock);
3003 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
3004 spin_unlock_irq(&hdspm->lock);
3005 return 0;
3006}
3007
3008static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
3009 struct snd_ctl_elem_value *ucontrol)
3010{
3011 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3012 int change;
3013 unsigned int val;
3014
3015 if (!snd_hdspm_use_is_exclusive(hdspm))
3016 return -EBUSY;
3017 val = ucontrol->value.integer.value[0] & 1;
3018 spin_lock_irq(&hdspm->lock);
3019 change = (int) val != hdspm_c_tms(hdspm);
3020 hdspm_set_c_tms(hdspm, val);
3021 spin_unlock_irq(&hdspm->lock);
3022 return change;
3023}
3024
3025
3026#define HDSPM_SAFE_MODE(xname, xindex) \
3027{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3028 .name = xname, \
3029 .index = xindex, \
3030 .info = snd_hdspm_info_safe_mode, \
3031 .get = snd_hdspm_get_safe_mode, \
3032 .put = snd_hdspm_put_safe_mode \
3033}
3034
3035static int hdspm_safe_mode(struct hdspm * hdspm)
3036{
3037 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
3038}
3039
3040static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
3041{
3042 if (out)
3043 hdspm->control_register |= HDSPM_AutoInp;
3044 else
3045 hdspm->control_register &= ~HDSPM_AutoInp;
3046 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3047
3048 return 0;
3049}
3050
3051#define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info
3052
3053static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
3054 struct snd_ctl_elem_value *ucontrol)
3055{
3056 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3057
3058 spin_lock_irq(&hdspm->lock);
3059 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
3060 spin_unlock_irq(&hdspm->lock);
3061 return 0;
3062}
3063
3064static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3065 struct snd_ctl_elem_value *ucontrol)
3066{
3067 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3068 int change;
3069 unsigned int val;
3070
3071 if (!snd_hdspm_use_is_exclusive(hdspm))
3072 return -EBUSY;
3073 val = ucontrol->value.integer.value[0] & 1;
3074 spin_lock_irq(&hdspm->lock);
3075 change = (int) val != hdspm_safe_mode(hdspm);
3076 hdspm_set_safe_mode(hdspm, val);
3077 spin_unlock_irq(&hdspm->lock);
3078 return change;
3079}
3080
3081
3082#define HDSPM_EMPHASIS(xname, xindex) \
3083{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3084 .name = xname, \
3085 .index = xindex, \
3086 .info = snd_hdspm_info_emphasis, \
3087 .get = snd_hdspm_get_emphasis, \
3088 .put = snd_hdspm_put_emphasis \
3089}
3090
3091static int hdspm_emphasis(struct hdspm * hdspm)
3092{
3093 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3094}
3095
3096static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3097{
3098 if (emp)
3099 hdspm->control_register |= HDSPM_Emphasis;
3100 else
3101 hdspm->control_register &= ~HDSPM_Emphasis;
3102 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3103
3104 return 0;
3105}
3106
3107#define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info
3108
3109static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3110 struct snd_ctl_elem_value *ucontrol)
3111{
3112 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3113
3114 spin_lock_irq(&hdspm->lock);
3115 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3116 spin_unlock_irq(&hdspm->lock);
3117 return 0;
3118}
3119
3120static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3121 struct snd_ctl_elem_value *ucontrol)
3122{
3123 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3124 int change;
3125 unsigned int val;
3126
3127 if (!snd_hdspm_use_is_exclusive(hdspm))
3128 return -EBUSY;
3129 val = ucontrol->value.integer.value[0] & 1;
3130 spin_lock_irq(&hdspm->lock);
3131 change = (int) val != hdspm_emphasis(hdspm);
3132 hdspm_set_emphasis(hdspm, val);
3133 spin_unlock_irq(&hdspm->lock);
3134 return change;
3135}
3136
3137
3138#define HDSPM_DOLBY(xname, xindex) \
3139{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3140 .name = xname, \
3141 .index = xindex, \
3142 .info = snd_hdspm_info_dolby, \
3143 .get = snd_hdspm_get_dolby, \
3144 .put = snd_hdspm_put_dolby \
3145}
3146
3147static int hdspm_dolby(struct hdspm * hdspm)
3148{
3149 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3150}
3151
3152static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3153{
3154 if (dol)
3155 hdspm->control_register |= HDSPM_Dolby;
3156 else
3157 hdspm->control_register &= ~HDSPM_Dolby;
3158 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3159
3160 return 0;
3161}
3162
3163#define snd_hdspm_info_dolby snd_ctl_boolean_mono_info
3164
3165static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3166 struct snd_ctl_elem_value *ucontrol)
3167{
3168 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3169
3170 spin_lock_irq(&hdspm->lock);
3171 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3172 spin_unlock_irq(&hdspm->lock);
3173 return 0;
3174}
3175
3176static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3177 struct snd_ctl_elem_value *ucontrol)
3178{
3179 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3180 int change;
3181 unsigned int val;
3182
3183 if (!snd_hdspm_use_is_exclusive(hdspm))
3184 return -EBUSY;
3185 val = ucontrol->value.integer.value[0] & 1;
3186 spin_lock_irq(&hdspm->lock);
3187 change = (int) val != hdspm_dolby(hdspm);
3188 hdspm_set_dolby(hdspm, val);
3189 spin_unlock_irq(&hdspm->lock);
3190 return change;
3191}
3192
3193
3194#define HDSPM_PROFESSIONAL(xname, xindex) \
3195{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3196 .name = xname, \
3197 .index = xindex, \
3198 .info = snd_hdspm_info_professional, \
3199 .get = snd_hdspm_get_professional, \
3200 .put = snd_hdspm_put_professional \
3201}
3202
3203static int hdspm_professional(struct hdspm * hdspm)
3204{
3205 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3206}
3207
3208static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3209{
3210 if (dol)
3211 hdspm->control_register |= HDSPM_Professional;
3212 else
3213 hdspm->control_register &= ~HDSPM_Professional;
3214 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3215
3216 return 0;
3217}
3218
3219#define snd_hdspm_info_professional snd_ctl_boolean_mono_info
3220
3221static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3222 struct snd_ctl_elem_value *ucontrol)
3223{
3224 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3225
3226 spin_lock_irq(&hdspm->lock);
3227 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3228 spin_unlock_irq(&hdspm->lock);
3229 return 0;
3230}
3231
3232static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3233 struct snd_ctl_elem_value *ucontrol)
3234{
3235 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3236 int change;
3237 unsigned int val;
3238
3239 if (!snd_hdspm_use_is_exclusive(hdspm))
3240 return -EBUSY;
3241 val = ucontrol->value.integer.value[0] & 1;
3242 spin_lock_irq(&hdspm->lock);
3243 change = (int) val != hdspm_professional(hdspm);
3244 hdspm_set_professional(hdspm, val);
3245 spin_unlock_irq(&hdspm->lock);
3246 return change;
3247}
3248
3249#define HDSPM_INPUT_SELECT(xname, xindex) \
3250{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3251 .name = xname, \
3252 .index = xindex, \
3253 .info = snd_hdspm_info_input_select, \
3254 .get = snd_hdspm_get_input_select, \
3255 .put = snd_hdspm_put_input_select \
3256}
3257
3258static int hdspm_input_select(struct hdspm * hdspm)
3259{
3260 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3261}
3262
3263static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3264{
3265 if (out)
3266 hdspm->control_register |= HDSPM_InputSelect0;
3267 else
3268 hdspm->control_register &= ~HDSPM_InputSelect0;
3269 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3270
3271 return 0;
3272}
3273
3274static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3275 struct snd_ctl_elem_info *uinfo)
3276{
3277 static char *texts[] = { "optical", "coaxial" };
3278
3279 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3280 uinfo->count = 1;
3281 uinfo->value.enumerated.items = 2;
3282
3283 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3284 uinfo->value.enumerated.item =
3285 uinfo->value.enumerated.items - 1;
3286 strcpy(uinfo->value.enumerated.name,
3287 texts[uinfo->value.enumerated.item]);
3288
3289 return 0;
3290}
3291
3292static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3293 struct snd_ctl_elem_value *ucontrol)
3294{
3295 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3296
3297 spin_lock_irq(&hdspm->lock);
3298 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3299 spin_unlock_irq(&hdspm->lock);
3300 return 0;
3301}
3302
3303static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3304 struct snd_ctl_elem_value *ucontrol)
3305{
3306 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3307 int change;
3308 unsigned int val;
3309
3310 if (!snd_hdspm_use_is_exclusive(hdspm))
3311 return -EBUSY;
3312 val = ucontrol->value.integer.value[0] & 1;
3313 spin_lock_irq(&hdspm->lock);
3314 change = (int) val != hdspm_input_select(hdspm);
3315 hdspm_set_input_select(hdspm, val);
3316 spin_unlock_irq(&hdspm->lock);
3317 return change;
3318}
3319
3320
3321#define HDSPM_DS_WIRE(xname, xindex) \
3322{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3323 .name = xname, \
3324 .index = xindex, \
3325 .info = snd_hdspm_info_ds_wire, \
3326 .get = snd_hdspm_get_ds_wire, \
3327 .put = snd_hdspm_put_ds_wire \
3328}
3329
3330static int hdspm_ds_wire(struct hdspm * hdspm)
3331{
3332 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3333}
3334
3335static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3336{
3337 if (ds)
3338 hdspm->control_register |= HDSPM_DS_DoubleWire;
3339 else
3340 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3341 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3342
3343 return 0;
3344}
3345
3346static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3347 struct snd_ctl_elem_info *uinfo)
3348{
3349 static char *texts[] = { "Single", "Double" };
3350
3351 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3352 uinfo->count = 1;
3353 uinfo->value.enumerated.items = 2;
3354
3355 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3356 uinfo->value.enumerated.item =
3357 uinfo->value.enumerated.items - 1;
3358 strcpy(uinfo->value.enumerated.name,
3359 texts[uinfo->value.enumerated.item]);
3360
3361 return 0;
3362}
3363
3364static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3365 struct snd_ctl_elem_value *ucontrol)
3366{
3367 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3368
3369 spin_lock_irq(&hdspm->lock);
3370 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3371 spin_unlock_irq(&hdspm->lock);
3372 return 0;
3373}
3374
3375static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3376 struct snd_ctl_elem_value *ucontrol)
3377{
3378 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3379 int change;
3380 unsigned int val;
3381
3382 if (!snd_hdspm_use_is_exclusive(hdspm))
3383 return -EBUSY;
3384 val = ucontrol->value.integer.value[0] & 1;
3385 spin_lock_irq(&hdspm->lock);
3386 change = (int) val != hdspm_ds_wire(hdspm);
3387 hdspm_set_ds_wire(hdspm, val);
3388 spin_unlock_irq(&hdspm->lock);
3389 return change;
3390}
3391
3392
3393#define HDSPM_QS_WIRE(xname, xindex) \
3394{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3395 .name = xname, \
3396 .index = xindex, \
3397 .info = snd_hdspm_info_qs_wire, \
3398 .get = snd_hdspm_get_qs_wire, \
3399 .put = snd_hdspm_put_qs_wire \
3400}
3401
3402static int hdspm_qs_wire(struct hdspm * hdspm)
3403{
3404 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3405 return 1;
3406 if (hdspm->control_register & HDSPM_QS_QuadWire)
3407 return 2;
3408 return 0;
3409}
3410
3411static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3412{
3413 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3414 switch (mode) {
3415 case 0:
3416 break;
3417 case 1:
3418 hdspm->control_register |= HDSPM_QS_DoubleWire;
3419 break;
3420 case 2:
3421 hdspm->control_register |= HDSPM_QS_QuadWire;
3422 break;
3423 }
3424 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3425
3426 return 0;
3427}
3428
3429static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3430 struct snd_ctl_elem_info *uinfo)
3431{
3432 static char *texts[] = { "Single", "Double", "Quad" };
3433
3434 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3435 uinfo->count = 1;
3436 uinfo->value.enumerated.items = 3;
3437
3438 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3439 uinfo->value.enumerated.item =
3440 uinfo->value.enumerated.items - 1;
3441 strcpy(uinfo->value.enumerated.name,
3442 texts[uinfo->value.enumerated.item]);
3443
3444 return 0;
3445}
3446
3447static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3448 struct snd_ctl_elem_value *ucontrol)
3449{
3450 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3451
3452 spin_lock_irq(&hdspm->lock);
3453 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3454 spin_unlock_irq(&hdspm->lock);
3455 return 0;
3456}
3457
3458static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3459 struct snd_ctl_elem_value *ucontrol)
3460{
3461 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3462 int change;
3463 int val;
3464
3465 if (!snd_hdspm_use_is_exclusive(hdspm))
3466 return -EBUSY;
3467 val = ucontrol->value.integer.value[0];
3468 if (val < 0)
3469 val = 0;
3470 if (val > 2)
3471 val = 2;
3472 spin_lock_irq(&hdspm->lock);
3473 change = val != hdspm_qs_wire(hdspm);
3474 hdspm_set_qs_wire(hdspm, val);
3475 spin_unlock_irq(&hdspm->lock);
3476 return change;
3477}
3478
3479#define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3480{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3481 .name = xname, \
3482 .index = xindex, \
3483 .info = snd_hdspm_info_madi_speedmode, \
3484 .get = snd_hdspm_get_madi_speedmode, \
3485 .put = snd_hdspm_put_madi_speedmode \
3486}
3487
3488static int hdspm_madi_speedmode(struct hdspm *hdspm)
3489{
3490 if (hdspm->control_register & HDSPM_QuadSpeed)
3491 return 2;
3492 if (hdspm->control_register & HDSPM_DoubleSpeed)
3493 return 1;
3494 return 0;
3495}
3496
3497static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3498{
3499 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3500 switch (mode) {
3501 case 0:
3502 break;
3503 case 1:
3504 hdspm->control_register |= HDSPM_DoubleSpeed;
3505 break;
3506 case 2:
3507 hdspm->control_register |= HDSPM_QuadSpeed;
3508 break;
3509 }
3510 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3511
3512 return 0;
3513}
3514
3515static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3516 struct snd_ctl_elem_info *uinfo)
3517{
3518 static char *texts[] = { "Single", "Double", "Quad" };
3519
3520 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3521 uinfo->count = 1;
3522 uinfo->value.enumerated.items = 3;
3523
3524 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3525 uinfo->value.enumerated.item =
3526 uinfo->value.enumerated.items - 1;
3527 strcpy(uinfo->value.enumerated.name,
3528 texts[uinfo->value.enumerated.item]);
3529
3530 return 0;
3531}
3532
3533static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3534 struct snd_ctl_elem_value *ucontrol)
3535{
3536 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3537
3538 spin_lock_irq(&hdspm->lock);
3539 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3540 spin_unlock_irq(&hdspm->lock);
3541 return 0;
3542}
3543
3544static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3545 struct snd_ctl_elem_value *ucontrol)
3546{
3547 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3548 int change;
3549 int val;
3550
3551 if (!snd_hdspm_use_is_exclusive(hdspm))
3552 return -EBUSY;
3553 val = ucontrol->value.integer.value[0];
3554 if (val < 0)
3555 val = 0;
3556 if (val > 2)
3557 val = 2;
3558 spin_lock_irq(&hdspm->lock);
3559 change = val != hdspm_madi_speedmode(hdspm);
3560 hdspm_set_madi_speedmode(hdspm, val);
3561 spin_unlock_irq(&hdspm->lock);
3562 return change;
3563}
3564
3565#define HDSPM_MIXER(xname, xindex) \
3566{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3567 .name = xname, \
3568 .index = xindex, \
3569 .device = 0, \
3570 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3571 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3572 .info = snd_hdspm_info_mixer, \
3573 .get = snd_hdspm_get_mixer, \
3574 .put = snd_hdspm_put_mixer \
3575}
3576
3577static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3578 struct snd_ctl_elem_info *uinfo)
3579{
3580 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3581 uinfo->count = 3;
3582 uinfo->value.integer.min = 0;
3583 uinfo->value.integer.max = 65535;
3584 uinfo->value.integer.step = 1;
3585 return 0;
3586}
3587
3588static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3589 struct snd_ctl_elem_value *ucontrol)
3590{
3591 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3592 int source;
3593 int destination;
3594
3595 source = ucontrol->value.integer.value[0];
3596 if (source < 0)
3597 source = 0;
3598 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3599 source = 2 * HDSPM_MAX_CHANNELS - 1;
3600
3601 destination = ucontrol->value.integer.value[1];
3602 if (destination < 0)
3603 destination = 0;
3604 else if (destination >= HDSPM_MAX_CHANNELS)
3605 destination = HDSPM_MAX_CHANNELS - 1;
3606
3607 spin_lock_irq(&hdspm->lock);
3608 if (source >= HDSPM_MAX_CHANNELS)
3609 ucontrol->value.integer.value[2] =
3610 hdspm_read_pb_gain(hdspm, destination,
3611 source - HDSPM_MAX_CHANNELS);
3612 else
3613 ucontrol->value.integer.value[2] =
3614 hdspm_read_in_gain(hdspm, destination, source);
3615
3616 spin_unlock_irq(&hdspm->lock);
3617
3618 return 0;
3619}
3620
3621static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3622 struct snd_ctl_elem_value *ucontrol)
3623{
3624 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3625 int change;
3626 int source;
3627 int destination;
3628 int gain;
3629
3630 if (!snd_hdspm_use_is_exclusive(hdspm))
3631 return -EBUSY;
3632
3633 source = ucontrol->value.integer.value[0];
3634 destination = ucontrol->value.integer.value[1];
3635
3636 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3637 return -1;
3638 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3639 return -1;
3640
3641 gain = ucontrol->value.integer.value[2];
3642
3643 spin_lock_irq(&hdspm->lock);
3644
3645 if (source >= HDSPM_MAX_CHANNELS)
3646 change = gain != hdspm_read_pb_gain(hdspm, destination,
3647 source -
3648 HDSPM_MAX_CHANNELS);
3649 else
3650 change = gain != hdspm_read_in_gain(hdspm, destination,
3651 source);
3652
3653 if (change) {
3654 if (source >= HDSPM_MAX_CHANNELS)
3655 hdspm_write_pb_gain(hdspm, destination,
3656 source - HDSPM_MAX_CHANNELS,
3657 gain);
3658 else
3659 hdspm_write_in_gain(hdspm, destination, source,
3660 gain);
3661 }
3662 spin_unlock_irq(&hdspm->lock);
3663
3664 return change;
3665}
3666
3667/* The simple mixer control(s) provide gain control for the
3668 basic 1:1 mappings of playback streams to output
3669 streams.
3670*/
3671
3672#define HDSPM_PLAYBACK_MIXER \
3673{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3674 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3675 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3676 .info = snd_hdspm_info_playback_mixer, \
3677 .get = snd_hdspm_get_playback_mixer, \
3678 .put = snd_hdspm_put_playback_mixer \
3679}
3680
3681static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3682 struct snd_ctl_elem_info *uinfo)
3683{
3684 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3685 uinfo->count = 1;
3686 uinfo->value.integer.min = 0;
3687 uinfo->value.integer.max = 64;
3688 uinfo->value.integer.step = 1;
3689 return 0;
3690}
3691
3692static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3693 struct snd_ctl_elem_value *ucontrol)
3694{
3695 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3696 int channel;
3697
3698 channel = ucontrol->id.index - 1;
3699
3700 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3701 return -EINVAL;
3702
3703 spin_lock_irq(&hdspm->lock);
3704 ucontrol->value.integer.value[0] =
3705 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3706 spin_unlock_irq(&hdspm->lock);
3707
3708 return 0;
3709}
3710
3711static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3712 struct snd_ctl_elem_value *ucontrol)
3713{
3714 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3715 int change;
3716 int channel;
3717 int gain;
3718
3719 if (!snd_hdspm_use_is_exclusive(hdspm))
3720 return -EBUSY;
3721
3722 channel = ucontrol->id.index - 1;
3723
3724 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3725 return -EINVAL;
3726
3727 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3728
3729 spin_lock_irq(&hdspm->lock);
3730 change =
3731 gain != hdspm_read_pb_gain(hdspm, channel,
3732 channel);
3733 if (change)
3734 hdspm_write_pb_gain(hdspm, channel, channel,
3735 gain);
3736 spin_unlock_irq(&hdspm->lock);
3737 return change;
3738}
3739
3740#define HDSPM_SYNC_CHECK(xname, xindex) \
3741{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3742 .name = xname, \
3743 .private_value = xindex, \
3744 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3745 .info = snd_hdspm_info_sync_check, \
3746 .get = snd_hdspm_get_sync_check \
3747}
3748
3749
3750static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3751 struct snd_ctl_elem_info *uinfo)
3752{
3753 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3754 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3755 uinfo->count = 1;
3756 uinfo->value.enumerated.items = 4;
3757 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3758 uinfo->value.enumerated.item =
3759 uinfo->value.enumerated.items - 1;
3760 strcpy(uinfo->value.enumerated.name,
3761 texts[uinfo->value.enumerated.item]);
3762 return 0;
3763}
3764
3765static int hdspm_wc_sync_check(struct hdspm *hdspm)
3766{
3767 int status, status2;
3768
3769 switch (hdspm->io_type) {
3770 case AES32:
3771 status = hdspm_read(hdspm, HDSPM_statusRegister);
3772 if (status & HDSPM_wcSync)
3773 return 2;
3774 else if (status & HDSPM_wcLock)
3775 return 1;
3776 return 0;
3777 break;
3778
3779 case MADI:
3780 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3781 if (status2 & HDSPM_wcLock) {
3782 if (status2 & HDSPM_wcSync)
3783 return 2;
3784 else
3785 return 1;
3786 }
3787 return 0;
3788 break;
3789
3790 case RayDAT:
3791 case AIO:
3792 status = hdspm_read(hdspm, HDSPM_statusRegister);
3793
3794 if (status & 0x2000000)
3795 return 2;
3796 else if (status & 0x1000000)
3797 return 1;
3798 return 0;
3799
3800 break;
3801
3802 case MADIface:
3803 break;
3804 }
3805
3806
3807 return 3;
3808}
3809
3810
3811static int hdspm_madi_sync_check(struct hdspm *hdspm)
3812{
3813 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3814 if (status & HDSPM_madiLock) {
3815 if (status & HDSPM_madiSync)
3816 return 2;
3817 else
3818 return 1;
3819 }
3820 return 0;
3821}
3822
3823
3824static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3825{
3826 int status, lock, sync;
3827
3828 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3829
3830 lock = (status & (0x1<<idx)) ? 1 : 0;
3831 sync = (status & (0x100<<idx)) ? 1 : 0;
3832
3833 if (lock && sync)
3834 return 2;
3835 else if (lock)
3836 return 1;
3837 return 0;
3838}
3839
3840
3841static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3842{
3843 int status, lock = 0, sync = 0;
3844
3845 switch (hdspm->io_type) {
3846 case RayDAT:
3847 case AIO:
3848 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3849 lock = (status & 0x400) ? 1 : 0;
3850 sync = (status & 0x800) ? 1 : 0;
3851 break;
3852
3853 case MADI:
3854 case AES32:
3855 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3856 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3857 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3858 break;
3859
3860 case MADIface:
3861 break;
3862 }
3863
3864 if (lock && sync)
3865 return 2;
3866 else if (lock)
3867 return 1;
3868
3869 return 0;
3870}
3871
3872static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3873{
3874 int status2, lock, sync;
3875 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3876
3877 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3878 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3879
3880 if (sync)
3881 return 2;
3882 else if (lock)
3883 return 1;
3884 return 0;
3885}
3886
3887
3888static int hdspm_tco_sync_check(struct hdspm *hdspm)
3889{
3890 int status;
3891
3892 if (hdspm->tco) {
3893 switch (hdspm->io_type) {
3894 case MADI:
3895 case AES32:
3896 status = hdspm_read(hdspm, HDSPM_statusRegister);
3897 if (status & HDSPM_tcoLock) {
3898 if (status & HDSPM_tcoSync)
3899 return 2;
3900 else
3901 return 1;
3902 }
3903 return 0;
3904
3905 break;
3906
3907 case RayDAT:
3908 case AIO:
3909 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3910
3911 if (status & 0x8000000)
3912 return 2; /* Sync */
3913 if (status & 0x4000000)
3914 return 1; /* Lock */
3915 return 0; /* No signal */
3916 break;
3917
3918 default:
3919 break;
3920 }
3921 }
3922
3923 return 3; /* N/A */
3924}
3925
3926
3927static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3928 struct snd_ctl_elem_value *ucontrol)
3929{
3930 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3931 int val = -1;
3932
3933 switch (hdspm->io_type) {
3934 case RayDAT:
3935 switch (kcontrol->private_value) {
3936 case 0: /* WC */
3937 val = hdspm_wc_sync_check(hdspm); break;
3938 case 7: /* TCO */
3939 val = hdspm_tco_sync_check(hdspm); break;
3940 case 8: /* SYNC IN */
3941 val = hdspm_sync_in_sync_check(hdspm); break;
3942 default:
3943 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3944 }
3945
3946 case AIO:
3947 switch (kcontrol->private_value) {
3948 case 0: /* WC */
3949 val = hdspm_wc_sync_check(hdspm); break;
3950 case 4: /* TCO */
3951 val = hdspm_tco_sync_check(hdspm); break;
3952 case 5: /* SYNC IN */
3953 val = hdspm_sync_in_sync_check(hdspm); break;
3954 default:
3955 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3956 }
3957
3958 case MADI:
3959 switch (kcontrol->private_value) {
3960 case 0: /* WC */
3961 val = hdspm_wc_sync_check(hdspm); break;
3962 case 1: /* MADI */
3963 val = hdspm_madi_sync_check(hdspm); break;
3964 case 2: /* TCO */
3965 val = hdspm_tco_sync_check(hdspm); break;
3966 case 3: /* SYNC_IN */
3967 val = hdspm_sync_in_sync_check(hdspm); break;
3968 }
3969
3970 case MADIface:
3971 val = hdspm_madi_sync_check(hdspm); /* MADI */
3972 break;
3973
3974 case AES32:
3975 switch (kcontrol->private_value) {
3976 case 0: /* WC */
3977 val = hdspm_wc_sync_check(hdspm); break;
3978 case 9: /* TCO */
3979 val = hdspm_tco_sync_check(hdspm); break;
3980 case 10 /* SYNC IN */:
3981 val = hdspm_sync_in_sync_check(hdspm); break;
3982 default: /* AES1 to AES8 */
3983 val = hdspm_aes_sync_check(hdspm,
3984 kcontrol->private_value-1);
3985 }
3986
3987 }
3988
3989 if (-1 == val)
3990 val = 3;
3991
3992 ucontrol->value.enumerated.item[0] = val;
3993 return 0;
3994}
3995
3996
3997
3998/**
3999 * TCO controls
4000 **/
4001static void hdspm_tco_write(struct hdspm *hdspm)
4002{
4003 unsigned int tc[4] = { 0, 0, 0, 0};
4004
4005 switch (hdspm->tco->input) {
4006 case 0:
4007 tc[2] |= HDSPM_TCO2_set_input_MSB;
4008 break;
4009 case 1:
4010 tc[2] |= HDSPM_TCO2_set_input_LSB;
4011 break;
4012 default:
4013 break;
4014 }
4015
4016 switch (hdspm->tco->framerate) {
4017 case 1:
4018 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4019 break;
4020 case 2:
4021 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4022 break;
4023 case 3:
4024 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4025 HDSPM_TCO1_set_drop_frame_flag;
4026 break;
4027 case 4:
4028 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4029 HDSPM_TCO1_LTC_Format_MSB;
4030 break;
4031 case 5:
4032 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4033 HDSPM_TCO1_LTC_Format_MSB +
4034 HDSPM_TCO1_set_drop_frame_flag;
4035 break;
4036 default:
4037 break;
4038 }
4039
4040 switch (hdspm->tco->wordclock) {
4041 case 1:
4042 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4043 break;
4044 case 2:
4045 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4046 break;
4047 default:
4048 break;
4049 }
4050
4051 switch (hdspm->tco->samplerate) {
4052 case 1:
4053 tc[2] |= HDSPM_TCO2_set_freq;
4054 break;
4055 case 2:
4056 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4057 break;
4058 default:
4059 break;
4060 }
4061
4062 switch (hdspm->tco->pull) {
4063 case 1:
4064 tc[2] |= HDSPM_TCO2_set_pull_up;
4065 break;
4066 case 2:
4067 tc[2] |= HDSPM_TCO2_set_pull_down;
4068 break;
4069 case 3:
4070 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4071 break;
4072 case 4:
4073 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4074 break;
4075 default:
4076 break;
4077 }
4078
4079 if (1 == hdspm->tco->term) {
4080 tc[2] |= HDSPM_TCO2_set_term_75R;
4081 }
4082
4083 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4084 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4085 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4086 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4087}
4088
4089
4090#define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4091{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4092 .name = xname, \
4093 .index = xindex, \
4094 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4095 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4096 .info = snd_hdspm_info_tco_sample_rate, \
4097 .get = snd_hdspm_get_tco_sample_rate, \
4098 .put = snd_hdspm_put_tco_sample_rate \
4099}
4100
4101static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4102 struct snd_ctl_elem_info *uinfo)
4103{
4104 static char *texts[] = { "44.1 kHz", "48 kHz" };
4105 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4106 uinfo->count = 1;
4107 uinfo->value.enumerated.items = 2;
4108
4109 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4110 uinfo->value.enumerated.item =
4111 uinfo->value.enumerated.items - 1;
4112
4113 strcpy(uinfo->value.enumerated.name,
4114 texts[uinfo->value.enumerated.item]);
4115
4116 return 0;
4117}
4118
4119static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4120 struct snd_ctl_elem_value *ucontrol)
4121{
4122 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4123
4124 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4125
4126 return 0;
4127}
4128
4129static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4130 struct snd_ctl_elem_value *ucontrol)
4131{
4132 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4133
4134 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4135 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4136
4137 hdspm_tco_write(hdspm);
4138
4139 return 1;
4140 }
4141
4142 return 0;
4143}
4144
4145
4146#define HDSPM_TCO_PULL(xname, xindex) \
4147{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4148 .name = xname, \
4149 .index = xindex, \
4150 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4151 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4152 .info = snd_hdspm_info_tco_pull, \
4153 .get = snd_hdspm_get_tco_pull, \
4154 .put = snd_hdspm_put_tco_pull \
4155}
4156
4157static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4158 struct snd_ctl_elem_info *uinfo)
4159{
4160 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4161 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4162 uinfo->count = 1;
4163 uinfo->value.enumerated.items = 5;
4164
4165 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4166 uinfo->value.enumerated.item =
4167 uinfo->value.enumerated.items - 1;
4168
4169 strcpy(uinfo->value.enumerated.name,
4170 texts[uinfo->value.enumerated.item]);
4171
4172 return 0;
4173}
4174
4175static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4176 struct snd_ctl_elem_value *ucontrol)
4177{
4178 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4179
4180 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4181
4182 return 0;
4183}
4184
4185static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4186 struct snd_ctl_elem_value *ucontrol)
4187{
4188 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4189
4190 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4191 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4192
4193 hdspm_tco_write(hdspm);
4194
4195 return 1;
4196 }
4197
4198 return 0;
4199}
4200
4201#define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4202{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4203 .name = xname, \
4204 .index = xindex, \
4205 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4206 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4207 .info = snd_hdspm_info_tco_wck_conversion, \
4208 .get = snd_hdspm_get_tco_wck_conversion, \
4209 .put = snd_hdspm_put_tco_wck_conversion \
4210}
4211
4212static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4213 struct snd_ctl_elem_info *uinfo)
4214{
4215 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4216 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4217 uinfo->count = 1;
4218 uinfo->value.enumerated.items = 3;
4219
4220 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4221 uinfo->value.enumerated.item =
4222 uinfo->value.enumerated.items - 1;
4223
4224 strcpy(uinfo->value.enumerated.name,
4225 texts[uinfo->value.enumerated.item]);
4226
4227 return 0;
4228}
4229
4230static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4231 struct snd_ctl_elem_value *ucontrol)
4232{
4233 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4234
4235 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4236
4237 return 0;
4238}
4239
4240static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4241 struct snd_ctl_elem_value *ucontrol)
4242{
4243 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4244
4245 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4246 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4247
4248 hdspm_tco_write(hdspm);
4249
4250 return 1;
4251 }
4252
4253 return 0;
4254}
4255
4256
4257#define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4258{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4259 .name = xname, \
4260 .index = xindex, \
4261 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4262 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4263 .info = snd_hdspm_info_tco_frame_rate, \
4264 .get = snd_hdspm_get_tco_frame_rate, \
4265 .put = snd_hdspm_put_tco_frame_rate \
4266}
4267
4268static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4269 struct snd_ctl_elem_info *uinfo)
4270{
4271 static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4272 "29.97 dfps", "30 fps", "30 dfps" };
4273 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4274 uinfo->count = 1;
4275 uinfo->value.enumerated.items = 6;
4276
4277 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4278 uinfo->value.enumerated.item =
4279 uinfo->value.enumerated.items - 1;
4280
4281 strcpy(uinfo->value.enumerated.name,
4282 texts[uinfo->value.enumerated.item]);
4283
4284 return 0;
4285}
4286
4287static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4288 struct snd_ctl_elem_value *ucontrol)
4289{
4290 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4291
4292 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4293
4294 return 0;
4295}
4296
4297static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4298 struct snd_ctl_elem_value *ucontrol)
4299{
4300 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4301
4302 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4303 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4304
4305 hdspm_tco_write(hdspm);
4306
4307 return 1;
4308 }
4309
4310 return 0;
4311}
4312
4313
4314#define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4315{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4316 .name = xname, \
4317 .index = xindex, \
4318 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4319 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4320 .info = snd_hdspm_info_tco_sync_source, \
4321 .get = snd_hdspm_get_tco_sync_source, \
4322 .put = snd_hdspm_put_tco_sync_source \
4323}
4324
4325static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4326 struct snd_ctl_elem_info *uinfo)
4327{
4328 static char *texts[] = { "LTC", "Video", "WCK" };
4329 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4330 uinfo->count = 1;
4331 uinfo->value.enumerated.items = 3;
4332
4333 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4334 uinfo->value.enumerated.item =
4335 uinfo->value.enumerated.items - 1;
4336
4337 strcpy(uinfo->value.enumerated.name,
4338 texts[uinfo->value.enumerated.item]);
4339
4340 return 0;
4341}
4342
4343static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4344 struct snd_ctl_elem_value *ucontrol)
4345{
4346 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4347
4348 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4349
4350 return 0;
4351}
4352
4353static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4354 struct snd_ctl_elem_value *ucontrol)
4355{
4356 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4357
4358 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4359 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4360
4361 hdspm_tco_write(hdspm);
4362
4363 return 1;
4364 }
4365
4366 return 0;
4367}
4368
4369
4370#define HDSPM_TCO_WORD_TERM(xname, xindex) \
4371{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4372 .name = xname, \
4373 .index = xindex, \
4374 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4375 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4376 .info = snd_hdspm_info_tco_word_term, \
4377 .get = snd_hdspm_get_tco_word_term, \
4378 .put = snd_hdspm_put_tco_word_term \
4379}
4380
4381static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4382 struct snd_ctl_elem_info *uinfo)
4383{
4384 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4385 uinfo->count = 1;
4386 uinfo->value.integer.min = 0;
4387 uinfo->value.integer.max = 1;
4388
4389 return 0;
4390}
4391
4392
4393static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4394 struct snd_ctl_elem_value *ucontrol)
4395{
4396 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4397
4398 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4399
4400 return 0;
4401}
4402
4403
4404static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4405 struct snd_ctl_elem_value *ucontrol)
4406{
4407 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4408
4409 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4410 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4411
4412 hdspm_tco_write(hdspm);
4413
4414 return 1;
4415 }
4416
4417 return 0;
4418}
4419
4420
4421
4422
4423static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4424 HDSPM_MIXER("Mixer", 0),
4425 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4426 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4427 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4428 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4429 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4430 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4431 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4432 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4433 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4434 HDSPM_LINE_OUT("Line Out", 0),
4435 HDSPM_TX_64("TX 64 channels mode", 0),
4436 HDSPM_C_TMS("Clear Track Marker", 0),
4437 HDSPM_SAFE_MODE("Safe Mode", 0),
4438 HDSPM_INPUT_SELECT("Input Select", 0),
4439 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4440};
4441
4442
4443static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4444 HDSPM_MIXER("Mixer", 0),
4445 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4446 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4447 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4448 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4449 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4450 HDSPM_TX_64("TX 64 channels mode", 0),
4451 HDSPM_C_TMS("Clear Track Marker", 0),
4452 HDSPM_SAFE_MODE("Safe Mode", 0),
4453 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4454};
4455
4456static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4457 HDSPM_MIXER("Mixer", 0),
4458 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4459 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4460 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4461 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4462 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4463 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4464 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4465 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4466 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4467 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4468 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4469 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4470 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4471 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4472 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4473 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4474 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4475 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4476
4477 /*
4478 HDSPM_INPUT_SELECT("Input Select", 0),
4479 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4480 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4481 HDSPM_SPDIF_IN("SPDIF In", 0);
4482 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4483 HDSPM_INPUT_LEVEL("Input Level", 0);
4484 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4485 HDSPM_PHONES("Phones", 0);
4486 */
4487};
4488
4489static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4490 HDSPM_MIXER("Mixer", 0),
4491 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4492 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4493 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4494 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4495 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4496 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4497 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4498 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4499 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4500 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4501 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4502 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4503 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4504 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4505 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4506 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4507 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4508 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4509 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4510 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4511 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4512 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4513};
4514
4515static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4516 HDSPM_MIXER("Mixer", 0),
4517 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4518 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4519 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4520 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4521 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4522 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4523 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4524 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4525 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4526 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4527 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4528 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4529 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4530 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4531 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4532 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4533 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4534 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4535 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4536 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4537 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4538 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4539 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4540 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4541 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4542 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4543 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4544 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4545 HDSPM_LINE_OUT("Line Out", 0),
4546 HDSPM_EMPHASIS("Emphasis", 0),
4547 HDSPM_DOLBY("Non Audio", 0),
4548 HDSPM_PROFESSIONAL("Professional", 0),
4549 HDSPM_C_TMS("Clear Track Marker", 0),
4550 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4551 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4552};
4553
4554
4555
4556/* Control elements for the optional TCO module */
4557static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4558 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4559 HDSPM_TCO_PULL("TCO Pull", 0),
4560 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4561 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4562 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4563 HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4564};
4565
4566
4567static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4568
4569
4570static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4571{
4572 int i;
4573
4574 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4575 if (hdspm->system_sample_rate > 48000) {
4576 hdspm->playback_mixer_ctls[i]->vd[0].access =
4577 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4578 SNDRV_CTL_ELEM_ACCESS_READ |
4579 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4580 } else {
4581 hdspm->playback_mixer_ctls[i]->vd[0].access =
4582 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4583 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4584 }
4585 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4586 SNDRV_CTL_EVENT_MASK_INFO,
4587 &hdspm->playback_mixer_ctls[i]->id);
4588 }
4589
4590 return 0;
4591}
4592
4593
4594static int snd_hdspm_create_controls(struct snd_card *card,
4595 struct hdspm *hdspm)
4596{
4597 unsigned int idx, limit;
4598 int err;
4599 struct snd_kcontrol *kctl;
4600 struct snd_kcontrol_new *list = NULL;
4601
4602 switch (hdspm->io_type) {
4603 case MADI:
4604 list = snd_hdspm_controls_madi;
4605 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4606 break;
4607 case MADIface:
4608 list = snd_hdspm_controls_madiface;
4609 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4610 break;
4611 case AIO:
4612 list = snd_hdspm_controls_aio;
4613 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4614 break;
4615 case RayDAT:
4616 list = snd_hdspm_controls_raydat;
4617 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4618 break;
4619 case AES32:
4620 list = snd_hdspm_controls_aes32;
4621 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4622 break;
4623 }
4624
4625 if (NULL != list) {
4626 for (idx = 0; idx < limit; idx++) {
4627 err = snd_ctl_add(card,
4628 snd_ctl_new1(&list[idx], hdspm));
4629 if (err < 0)
4630 return err;
4631 }
4632 }
4633
4634
4635 /* create simple 1:1 playback mixer controls */
4636 snd_hdspm_playback_mixer.name = "Chn";
4637 if (hdspm->system_sample_rate >= 128000) {
4638 limit = hdspm->qs_out_channels;
4639 } else if (hdspm->system_sample_rate >= 64000) {
4640 limit = hdspm->ds_out_channels;
4641 } else {
4642 limit = hdspm->ss_out_channels;
4643 }
4644 for (idx = 0; idx < limit; ++idx) {
4645 snd_hdspm_playback_mixer.index = idx + 1;
4646 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4647 err = snd_ctl_add(card, kctl);
4648 if (err < 0)
4649 return err;
4650 hdspm->playback_mixer_ctls[idx] = kctl;
4651 }
4652
4653
4654 if (hdspm->tco) {
4655 /* add tco control elements */
4656 list = snd_hdspm_controls_tco;
4657 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4658 for (idx = 0; idx < limit; idx++) {
4659 err = snd_ctl_add(card,
4660 snd_ctl_new1(&list[idx], hdspm));
4661 if (err < 0)
4662 return err;
4663 }
4664 }
4665
4666 return 0;
4667}
4668
4669/*------------------------------------------------------------
4670 /proc interface
4671 ------------------------------------------------------------*/
4672
4673static void
4674snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4675 struct snd_info_buffer *buffer)
4676{
4677 struct hdspm *hdspm = entry->private_data;
4678 unsigned int status, status2, control, freq;
4679
4680 char *pref_sync_ref;
4681 char *autosync_ref;
4682 char *system_clock_mode;
4683 char *insel;
4684 int x, x2;
4685
4686 /* TCO stuff */
4687 int a, ltc, frames, seconds, minutes, hours;
4688 unsigned int period;
4689 u64 freq_const = 0;
4690 u32 rate;
4691
4692 status = hdspm_read(hdspm, HDSPM_statusRegister);
4693 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4694 control = hdspm->control_register;
4695 freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4696
4697 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4698 hdspm->card_name, hdspm->card->number + 1,
4699 hdspm->firmware_rev,
4700 (status2 & HDSPM_version0) |
4701 (status2 & HDSPM_version1) | (status2 &
4702 HDSPM_version2));
4703
4704 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4705 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4706 hdspm->serial);
4707
4708 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4709 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4710
4711 snd_iprintf(buffer, "--- System ---\n");
4712
4713 snd_iprintf(buffer,
4714 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4715 status & HDSPM_audioIRQPending,
4716 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4717 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4718 hdspm->irq_count);
4719 snd_iprintf(buffer,
4720 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4721 "estimated= %ld (bytes)\n",
4722 ((status & HDSPM_BufferID) ? 1 : 0),
4723 (status & HDSPM_BufferPositionMask),
4724 (status & HDSPM_BufferPositionMask) %
4725 (2 * (int)hdspm->period_bytes),
4726 ((status & HDSPM_BufferPositionMask) - 64) %
4727 (2 * (int)hdspm->period_bytes),
4728 (long) hdspm_hw_pointer(hdspm) * 4);
4729
4730 snd_iprintf(buffer,
4731 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4732 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4733 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4734 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4735 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4736 snd_iprintf(buffer,
4737 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4738 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4739 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4740 snd_iprintf(buffer,
4741 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4742 "status2=0x%x\n",
4743 hdspm->control_register, hdspm->control2_register,
4744 status, status2);
4745 if (status & HDSPM_tco_detect) {
4746 snd_iprintf(buffer, "TCO module detected.\n");
4747 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4748 if (a & HDSPM_TCO1_LTC_Input_valid) {
4749 snd_iprintf(buffer, " LTC valid, ");
4750 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4751 HDSPM_TCO1_LTC_Format_MSB)) {
4752 case 0:
4753 snd_iprintf(buffer, "24 fps, ");
4754 break;
4755 case HDSPM_TCO1_LTC_Format_LSB:
4756 snd_iprintf(buffer, "25 fps, ");
4757 break;
4758 case HDSPM_TCO1_LTC_Format_MSB:
4759 snd_iprintf(buffer, "29.97 fps, ");
4760 break;
4761 default:
4762 snd_iprintf(buffer, "30 fps, ");
4763 break;
4764 }
4765 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4766 snd_iprintf(buffer, "drop frame\n");
4767 } else {
4768 snd_iprintf(buffer, "full frame\n");
4769 }
4770 } else {
4771 snd_iprintf(buffer, " no LTC\n");
4772 }
4773 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4774 snd_iprintf(buffer, " Video: NTSC\n");
4775 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4776 snd_iprintf(buffer, " Video: PAL\n");
4777 } else {
4778 snd_iprintf(buffer, " No video\n");
4779 }
4780 if (a & HDSPM_TCO1_TCO_lock) {
4781 snd_iprintf(buffer, " Sync: lock\n");
4782 } else {
4783 snd_iprintf(buffer, " Sync: no lock\n");
4784 }
4785
4786 switch (hdspm->io_type) {
4787 case MADI:
4788 case AES32:
4789 freq_const = 110069313433624ULL;
4790 break;
4791 case RayDAT:
4792 case AIO:
4793 freq_const = 104857600000000ULL;
4794 break;
4795 case MADIface:
4796 break; /* no TCO possible */
4797 }
4798
4799 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4800 snd_iprintf(buffer, " period: %u\n", period);
4801
4802
4803 /* rate = freq_const/period; */
4804 rate = div_u64(freq_const, period);
4805
4806 if (control & HDSPM_QuadSpeed) {
4807 rate *= 4;
4808 } else if (control & HDSPM_DoubleSpeed) {
4809 rate *= 2;
4810 }
4811
4812 snd_iprintf(buffer, " Frequency: %u Hz\n",
4813 (unsigned int) rate);
4814
4815 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4816 frames = ltc & 0xF;
4817 ltc >>= 4;
4818 frames += (ltc & 0x3) * 10;
4819 ltc >>= 4;
4820 seconds = ltc & 0xF;
4821 ltc >>= 4;
4822 seconds += (ltc & 0x7) * 10;
4823 ltc >>= 4;
4824 minutes = ltc & 0xF;
4825 ltc >>= 4;
4826 minutes += (ltc & 0x7) * 10;
4827 ltc >>= 4;
4828 hours = ltc & 0xF;
4829 ltc >>= 4;
4830 hours += (ltc & 0x3) * 10;
4831 snd_iprintf(buffer,
4832 " LTC In: %02d:%02d:%02d:%02d\n",
4833 hours, minutes, seconds, frames);
4834
4835 } else {
4836 snd_iprintf(buffer, "No TCO module detected.\n");
4837 }
4838
4839 snd_iprintf(buffer, "--- Settings ---\n");
4840
4841 x = hdspm_get_latency(hdspm);
4842
4843 snd_iprintf(buffer,
4844 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4845 x, (unsigned long) hdspm->period_bytes);
4846
4847 snd_iprintf(buffer, "Line out: %s\n",
4848 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4849
4850 switch (hdspm->control_register & HDSPM_InputMask) {
4851 case HDSPM_InputOptical:
4852 insel = "Optical";
4853 break;
4854 case HDSPM_InputCoaxial:
4855 insel = "Coaxial";
4856 break;
4857 default:
4858 insel = "Unkown";
4859 }
4860
4861 snd_iprintf(buffer,
4862 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4863 "Auto Input %s\n",
4864 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4865 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4866 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4867
4868
4869 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4870 system_clock_mode = "AutoSync";
4871 else
4872 system_clock_mode = "Master";
4873 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4874
4875 switch (hdspm_pref_sync_ref(hdspm)) {
4876 case HDSPM_SYNC_FROM_WORD:
4877 pref_sync_ref = "Word Clock";
4878 break;
4879 case HDSPM_SYNC_FROM_MADI:
4880 pref_sync_ref = "MADI Sync";
4881 break;
4882 case HDSPM_SYNC_FROM_TCO:
4883 pref_sync_ref = "TCO";
4884 break;
4885 case HDSPM_SYNC_FROM_SYNC_IN:
4886 pref_sync_ref = "Sync In";
4887 break;
4888 default:
4889 pref_sync_ref = "XXXX Clock";
4890 break;
4891 }
4892 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4893 pref_sync_ref);
4894
4895 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4896 hdspm->system_sample_rate);
4897
4898
4899 snd_iprintf(buffer, "--- Status:\n");
4900
4901 x = status & HDSPM_madiSync;
4902 x2 = status2 & HDSPM_wcSync;
4903
4904 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4905 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4906 "NoLock",
4907 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4908 "NoLock");
4909
4910 switch (hdspm_autosync_ref(hdspm)) {
4911 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4912 autosync_ref = "Sync In";
4913 break;
4914 case HDSPM_AUTOSYNC_FROM_TCO:
4915 autosync_ref = "TCO";
4916 break;
4917 case HDSPM_AUTOSYNC_FROM_WORD:
4918 autosync_ref = "Word Clock";
4919 break;
4920 case HDSPM_AUTOSYNC_FROM_MADI:
4921 autosync_ref = "MADI Sync";
4922 break;
4923 case HDSPM_AUTOSYNC_FROM_NONE:
4924 autosync_ref = "Input not valid";
4925 break;
4926 default:
4927 autosync_ref = "---";
4928 break;
4929 }
4930 snd_iprintf(buffer,
4931 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4932 autosync_ref, hdspm_external_sample_rate(hdspm),
4933 (status & HDSPM_madiFreqMask) >> 22,
4934 (status2 & HDSPM_wcFreqMask) >> 5);
4935
4936 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4937 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4938 (status & HDSPM_RX_64ch) ? "64 channels" :
4939 "56 channels");
4940
4941 snd_iprintf(buffer, "\n");
4942}
4943
4944static void
4945snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4946 struct snd_info_buffer *buffer)
4947{
4948 struct hdspm *hdspm = entry->private_data;
4949 unsigned int status;
4950 unsigned int status2;
4951 unsigned int timecode;
4952 int pref_syncref;
4953 char *autosync_ref;
4954 int x;
4955
4956 status = hdspm_read(hdspm, HDSPM_statusRegister);
4957 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4958 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4959
4960 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4961 hdspm->card_name, hdspm->card->number + 1,
4962 hdspm->firmware_rev);
4963
4964 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4965 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4966
4967 snd_iprintf(buffer, "--- System ---\n");
4968
4969 snd_iprintf(buffer,
4970 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4971 status & HDSPM_audioIRQPending,
4972 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4973 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4974 hdspm->irq_count);
4975 snd_iprintf(buffer,
4976 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4977 "estimated= %ld (bytes)\n",
4978 ((status & HDSPM_BufferID) ? 1 : 0),
4979 (status & HDSPM_BufferPositionMask),
4980 (status & HDSPM_BufferPositionMask) %
4981 (2 * (int)hdspm->period_bytes),
4982 ((status & HDSPM_BufferPositionMask) - 64) %
4983 (2 * (int)hdspm->period_bytes),
4984 (long) hdspm_hw_pointer(hdspm) * 4);
4985
4986 snd_iprintf(buffer,
4987 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4988 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4989 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4990 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4991 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4992 snd_iprintf(buffer,
4993 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4994 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4995 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4996 snd_iprintf(buffer,
4997 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4998 "status2=0x%x\n",
4999 hdspm->control_register, hdspm->control2_register,
5000 status, status2);
5001
5002 snd_iprintf(buffer, "--- Settings ---\n");
5003
5004 x = hdspm_get_latency(hdspm);
5005
5006 snd_iprintf(buffer,
5007 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5008 x, (unsigned long) hdspm->period_bytes);
5009
5010 snd_iprintf(buffer, "Line out: %s\n",
5011 (hdspm->
5012 control_register & HDSPM_LineOut) ? "on " : "off");
5013
5014 snd_iprintf(buffer,
5015 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5016 (hdspm->
5017 control_register & HDSPM_clr_tms) ? "on" : "off",
5018 (hdspm->
5019 control_register & HDSPM_Emphasis) ? "on" : "off",
5020 (hdspm->
5021 control_register & HDSPM_Dolby) ? "on" : "off");
5022
5023
5024 pref_syncref = hdspm_pref_sync_ref(hdspm);
5025 if (pref_syncref == 0)
5026 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5027 else
5028 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5029 pref_syncref);
5030
5031 snd_iprintf(buffer, "System Clock Frequency: %d\n",
5032 hdspm->system_sample_rate);
5033
5034 snd_iprintf(buffer, "Double speed: %s\n",
5035 hdspm->control_register & HDSPM_DS_DoubleWire?
5036 "Double wire" : "Single wire");
5037 snd_iprintf(buffer, "Quad speed: %s\n",
5038 hdspm->control_register & HDSPM_QS_DoubleWire?
5039 "Double wire" :
5040 hdspm->control_register & HDSPM_QS_QuadWire?
5041 "Quad wire" : "Single wire");
5042
5043 snd_iprintf(buffer, "--- Status:\n");
5044
5045 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
5046 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock",
5047 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5048
5049 for (x = 0; x < 8; x++) {
5050 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
5051 x+1,
5052 (status2 & (HDSPM_LockAES >> x)) ?
5053 "Sync " : "No Lock",
5054 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5055 }
5056
5057 switch (hdspm_autosync_ref(hdspm)) {
5058 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5059 autosync_ref = "None"; break;
5060 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5061 autosync_ref = "Word Clock"; break;
5062 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5063 autosync_ref = "AES1"; break;
5064 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5065 autosync_ref = "AES2"; break;
5066 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5067 autosync_ref = "AES3"; break;
5068 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5069 autosync_ref = "AES4"; break;
5070 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5071 autosync_ref = "AES5"; break;
5072 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5073 autosync_ref = "AES6"; break;
5074 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5075 autosync_ref = "AES7"; break;
5076 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5077 autosync_ref = "AES8"; break;
5078 default:
5079 autosync_ref = "---"; break;
5080 }
5081 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5082
5083 snd_iprintf(buffer, "\n");
5084}
5085
5086static void
5087snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5088 struct snd_info_buffer *buffer)
5089{
5090 struct hdspm *hdspm = entry->private_data;
5091 unsigned int status1, status2, status3, control, i;
5092 unsigned int lock, sync;
5093
5094 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5095 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5096 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5097
5098 control = hdspm->control_register;
5099
5100 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5101 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5102 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5103
5104
5105 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5106
5107 snd_iprintf(buffer, "Clock mode : %s\n",
5108 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5109 snd_iprintf(buffer, "System frequency: %d Hz\n",
5110 hdspm_get_system_sample_rate(hdspm));
5111
5112 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5113
5114 lock = 0x1;
5115 sync = 0x100;
5116
5117 for (i = 0; i < 8; i++) {
5118 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5119 i,
5120 (status1 & lock) ? 1 : 0,
5121 (status1 & sync) ? 1 : 0,
5122 texts_freq[(status2 >> (i * 4)) & 0xF]);
5123
5124 lock = lock<<1;
5125 sync = sync<<1;
5126 }
5127
5128 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5129 (status1 & 0x1000000) ? 1 : 0,
5130 (status1 & 0x2000000) ? 1 : 0,
5131 texts_freq[(status1 >> 16) & 0xF]);
5132
5133 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5134 (status1 & 0x4000000) ? 1 : 0,
5135 (status1 & 0x8000000) ? 1 : 0,
5136 texts_freq[(status1 >> 20) & 0xF]);
5137
5138 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5139 (status3 & 0x400) ? 1 : 0,
5140 (status3 & 0x800) ? 1 : 0,
5141 texts_freq[(status2 >> 12) & 0xF]);
5142
5143}
5144
5145#ifdef CONFIG_SND_DEBUG
5146static void
5147snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5148 struct snd_info_buffer *buffer)
5149{
5150 struct hdspm *hdspm = entry->private_data;
5151
5152 int j,i;
5153
5154 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5155 snd_iprintf(buffer, "0x%08X: ", i);
5156 for (j = 0; j < 16; j += 4)
5157 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5158 snd_iprintf(buffer, "\n");
5159 }
5160}
5161#endif
5162
5163
5164static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5165 struct snd_info_buffer *buffer)
5166{
5167 struct hdspm *hdspm = entry->private_data;
5168 int i;
5169
5170 snd_iprintf(buffer, "# generated by hdspm\n");
5171
5172 for (i = 0; i < hdspm->max_channels_in; i++) {
5173 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5174 }
5175}
5176
5177static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5178 struct snd_info_buffer *buffer)
5179{
5180 struct hdspm *hdspm = entry->private_data;
5181 int i;
5182
5183 snd_iprintf(buffer, "# generated by hdspm\n");
5184
5185 for (i = 0; i < hdspm->max_channels_out; i++) {
5186 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5187 }
5188}
5189
5190
5191static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5192{
5193 struct snd_info_entry *entry;
5194
5195 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5196 switch (hdspm->io_type) {
5197 case AES32:
5198 snd_info_set_text_ops(entry, hdspm,
5199 snd_hdspm_proc_read_aes32);
5200 break;
5201 case MADI:
5202 snd_info_set_text_ops(entry, hdspm,
5203 snd_hdspm_proc_read_madi);
5204 break;
5205 case MADIface:
5206 /* snd_info_set_text_ops(entry, hdspm,
5207 snd_hdspm_proc_read_madiface); */
5208 break;
5209 case RayDAT:
5210 snd_info_set_text_ops(entry, hdspm,
5211 snd_hdspm_proc_read_raydat);
5212 break;
5213 case AIO:
5214 break;
5215 }
5216 }
5217
5218 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5219 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5220 }
5221
5222 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5223 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5224 }
5225
5226#ifdef CONFIG_SND_DEBUG
5227 /* debug file to read all hdspm registers */
5228 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5229 snd_info_set_text_ops(entry, hdspm,
5230 snd_hdspm_proc_read_debug);
5231#endif
5232}
5233
5234/*------------------------------------------------------------
5235 hdspm intitialize
5236 ------------------------------------------------------------*/
5237
5238static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5239{
5240 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5241 hold it (e.g. during module initialization).
5242 */
5243
5244 /* set defaults: */
5245
5246 hdspm->settings_register = 0;
5247
5248 switch (hdspm->io_type) {
5249 case MADI:
5250 case MADIface:
5251 hdspm->control_register =
5252 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5253 break;
5254
5255 case RayDAT:
5256 case AIO:
5257 hdspm->settings_register = 0x1 + 0x1000;
5258 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5259 * line_out */
5260 hdspm->control_register =
5261 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5262 break;
5263
5264 case AES32:
5265 hdspm->control_register =
5266 HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5267 hdspm_encode_latency(7) | /* latency max=8192samples */
5268 HDSPM_SyncRef0 | /* AES1 is syncclock */
5269 HDSPM_LineOut | /* Analog output in */
5270 HDSPM_Professional; /* Professional mode */
5271 break;
5272 }
5273
5274 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5275
5276 if (AES32 == hdspm->io_type) {
5277 /* No control2 register for AES32 */
5278#ifdef SNDRV_BIG_ENDIAN
5279 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5280#else
5281 hdspm->control2_register = 0;
5282#endif
5283
5284 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5285 }
5286 hdspm_compute_period_size(hdspm);
5287
5288 /* silence everything */
5289
5290 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5291
5292 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5293 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5294 }
5295
5296 /* set a default rate so that the channel map is set up. */
5297 hdspm_set_rate(hdspm, 48000, 1);
5298
5299 return 0;
5300}
5301
5302
5303/*------------------------------------------------------------
5304 interrupt
5305 ------------------------------------------------------------*/
5306
5307static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5308{
5309 struct hdspm *hdspm = (struct hdspm *) dev_id;
5310 unsigned int status;
5311 int i, audio, midi, schedule = 0;
5312 /* cycles_t now; */
5313
5314 status = hdspm_read(hdspm, HDSPM_statusRegister);
5315
5316 audio = status & HDSPM_audioIRQPending;
5317 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5318 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5319
5320 /* now = get_cycles(); */
5321 /**
5322 * LAT_2..LAT_0 period counter (win) counter (mac)
5323 * 6 4096 ~256053425 ~514672358
5324 * 5 2048 ~128024983 ~257373821
5325 * 4 1024 ~64023706 ~128718089
5326 * 3 512 ~32005945 ~64385999
5327 * 2 256 ~16003039 ~32260176
5328 * 1 128 ~7998738 ~16194507
5329 * 0 64 ~3998231 ~8191558
5330 **/
5331 /*
5332 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5333 now-hdspm->last_interrupt, status & 0xFFC0);
5334 hdspm->last_interrupt = now;
5335 */
5336
5337 if (!audio && !midi)
5338 return IRQ_NONE;
5339
5340 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5341 hdspm->irq_count++;
5342
5343
5344 if (audio) {
5345 if (hdspm->capture_substream)
5346 snd_pcm_period_elapsed(hdspm->capture_substream);
5347
5348 if (hdspm->playback_substream)
5349 snd_pcm_period_elapsed(hdspm->playback_substream);
5350 }
5351
5352 if (midi) {
5353 i = 0;
5354 while (i < hdspm->midiPorts) {
5355 if ((hdspm_read(hdspm,
5356 hdspm->midi[i].statusIn) & 0xff) &&
5357 (status & hdspm->midi[i].irq)) {
5358 /* we disable interrupts for this input until
5359 * processing is done
5360 */
5361 hdspm->control_register &= ~hdspm->midi[i].ie;
5362 hdspm_write(hdspm, HDSPM_controlRegister,
5363 hdspm->control_register);
5364 hdspm->midi[i].pending = 1;
5365 schedule = 1;
5366 }
5367
5368 i++;
5369 }
5370
5371 if (schedule)
5372 tasklet_hi_schedule(&hdspm->midi_tasklet);
5373 }
5374
5375 return IRQ_HANDLED;
5376}
5377
5378/*------------------------------------------------------------
5379 pcm interface
5380 ------------------------------------------------------------*/
5381
5382
5383static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5384 *substream)
5385{
5386 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5387 return hdspm_hw_pointer(hdspm);
5388}
5389
5390
5391static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5392{
5393 struct snd_pcm_runtime *runtime = substream->runtime;
5394 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5395 struct snd_pcm_substream *other;
5396
5397 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5398 other = hdspm->capture_substream;
5399 else
5400 other = hdspm->playback_substream;
5401
5402 if (hdspm->running)
5403 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5404 else
5405 runtime->status->hw_ptr = 0;
5406 if (other) {
5407 struct snd_pcm_substream *s;
5408 struct snd_pcm_runtime *oruntime = other->runtime;
5409 snd_pcm_group_for_each_entry(s, substream) {
5410 if (s == other) {
5411 oruntime->status->hw_ptr =
5412 runtime->status->hw_ptr;
5413 break;
5414 }
5415 }
5416 }
5417 return 0;
5418}
5419
5420static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5421 struct snd_pcm_hw_params *params)
5422{
5423 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5424 int err;
5425 int i;
5426 pid_t this_pid;
5427 pid_t other_pid;
5428
5429 spin_lock_irq(&hdspm->lock);
5430
5431 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5432 this_pid = hdspm->playback_pid;
5433 other_pid = hdspm->capture_pid;
5434 } else {
5435 this_pid = hdspm->capture_pid;
5436 other_pid = hdspm->playback_pid;
5437 }
5438
5439 if (other_pid > 0 && this_pid != other_pid) {
5440
5441 /* The other stream is open, and not by the same
5442 task as this one. Make sure that the parameters
5443 that matter are the same.
5444 */
5445
5446 if (params_rate(params) != hdspm->system_sample_rate) {
5447 spin_unlock_irq(&hdspm->lock);
5448 _snd_pcm_hw_param_setempty(params,
5449 SNDRV_PCM_HW_PARAM_RATE);
5450 return -EBUSY;
5451 }
5452
5453 if (params_period_size(params) != hdspm->period_bytes / 4) {
5454 spin_unlock_irq(&hdspm->lock);
5455 _snd_pcm_hw_param_setempty(params,
5456 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5457 return -EBUSY;
5458 }
5459
5460 }
5461 /* We're fine. */
5462 spin_unlock_irq(&hdspm->lock);
5463
5464 /* how to make sure that the rate matches an externally-set one ? */
5465
5466 spin_lock_irq(&hdspm->lock);
5467 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5468 if (err < 0) {
5469 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5470 spin_unlock_irq(&hdspm->lock);
5471 _snd_pcm_hw_param_setempty(params,
5472 SNDRV_PCM_HW_PARAM_RATE);
5473 return err;
5474 }
5475 spin_unlock_irq(&hdspm->lock);
5476
5477 err = hdspm_set_interrupt_interval(hdspm,
5478 params_period_size(params));
5479 if (err < 0) {
5480 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5481 _snd_pcm_hw_param_setempty(params,
5482 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5483 return err;
5484 }
5485
5486 /* Memory allocation, takashi's method, dont know if we should
5487 * spinlock
5488 */
5489 /* malloc all buffer even if not enabled to get sure */
5490 /* Update for MADI rev 204: we need to allocate for all channels,
5491 * otherwise it doesn't work at 96kHz */
5492
5493 err =
5494 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5495 if (err < 0) {
5496 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5497 return err;
5498 }
5499
5500 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5501
5502 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5503 params_channels(params));
5504
5505 for (i = 0; i < params_channels(params); ++i)
5506 snd_hdspm_enable_out(hdspm, i, 1);
5507
5508 hdspm->playback_buffer =
5509 (unsigned char *) substream->runtime->dma_area;
5510 snd_printdd("Allocated sample buffer for playback at %p\n",
5511 hdspm->playback_buffer);
5512 } else {
5513 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5514 params_channels(params));
5515
5516 for (i = 0; i < params_channels(params); ++i)
5517 snd_hdspm_enable_in(hdspm, i, 1);
5518
5519 hdspm->capture_buffer =
5520 (unsigned char *) substream->runtime->dma_area;
5521 snd_printdd("Allocated sample buffer for capture at %p\n",
5522 hdspm->capture_buffer);
5523 }
5524
5525 /*
5526 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5527 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5528 "playback" : "capture",
5529 snd_pcm_sgbuf_get_addr(substream, 0));
5530 */
5531 /*
5532 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5533 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5534 "playback" : "capture",
5535 params_rate(params), params_channels(params),
5536 params_buffer_size(params));
5537 */
5538
5539
5540 /* Switch to native float format if requested */
5541 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5542 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5543 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5544
5545 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5546 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5547 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5548 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5549
5550 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5551 }
5552 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5553
5554 return 0;
5555}
5556
5557static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5558{
5559 int i;
5560 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5561
5562 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5563
5564 /* params_channels(params) should be enough,
5565 but to get sure in case of error */
5566 for (i = 0; i < hdspm->max_channels_out; ++i)
5567 snd_hdspm_enable_out(hdspm, i, 0);
5568
5569 hdspm->playback_buffer = NULL;
5570 } else {
5571 for (i = 0; i < hdspm->max_channels_in; ++i)
5572 snd_hdspm_enable_in(hdspm, i, 0);
5573
5574 hdspm->capture_buffer = NULL;
5575
5576 }
5577
5578 snd_pcm_lib_free_pages(substream);
5579
5580 return 0;
5581}
5582
5583
5584static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5585 struct snd_pcm_channel_info *info)
5586{
5587 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5588
5589 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5590 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5591 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5592 return -EINVAL;
5593 }
5594
5595 if (hdspm->channel_map_out[info->channel] < 0) {
5596 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5597 return -EINVAL;
5598 }
5599
5600 info->offset = hdspm->channel_map_out[info->channel] *
5601 HDSPM_CHANNEL_BUFFER_BYTES;
5602 } else {
5603 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5604 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5605 return -EINVAL;
5606 }
5607
5608 if (hdspm->channel_map_in[info->channel] < 0) {
5609 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5610 return -EINVAL;
5611 }
5612
5613 info->offset = hdspm->channel_map_in[info->channel] *
5614 HDSPM_CHANNEL_BUFFER_BYTES;
5615 }
5616
5617 info->first = 0;
5618 info->step = 32;
5619 return 0;
5620}
5621
5622
5623static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5624 unsigned int cmd, void *arg)
5625{
5626 switch (cmd) {
5627 case SNDRV_PCM_IOCTL1_RESET:
5628 return snd_hdspm_reset(substream);
5629
5630 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5631 {
5632 struct snd_pcm_channel_info *info = arg;
5633 return snd_hdspm_channel_info(substream, info);
5634 }
5635 default:
5636 break;
5637 }
5638
5639 return snd_pcm_lib_ioctl(substream, cmd, arg);
5640}
5641
5642static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5643{
5644 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5645 struct snd_pcm_substream *other;
5646 int running;
5647
5648 spin_lock(&hdspm->lock);
5649 running = hdspm->running;
5650 switch (cmd) {
5651 case SNDRV_PCM_TRIGGER_START:
5652 running |= 1 << substream->stream;
5653 break;
5654 case SNDRV_PCM_TRIGGER_STOP:
5655 running &= ~(1 << substream->stream);
5656 break;
5657 default:
5658 snd_BUG();
5659 spin_unlock(&hdspm->lock);
5660 return -EINVAL;
5661 }
5662 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5663 other = hdspm->capture_substream;
5664 else
5665 other = hdspm->playback_substream;
5666
5667 if (other) {
5668 struct snd_pcm_substream *s;
5669 snd_pcm_group_for_each_entry(s, substream) {
5670 if (s == other) {
5671 snd_pcm_trigger_done(s, substream);
5672 if (cmd == SNDRV_PCM_TRIGGER_START)
5673 running |= 1 << s->stream;
5674 else
5675 running &= ~(1 << s->stream);
5676 goto _ok;
5677 }
5678 }
5679 if (cmd == SNDRV_PCM_TRIGGER_START) {
5680 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5681 && substream->stream ==
5682 SNDRV_PCM_STREAM_CAPTURE)
5683 hdspm_silence_playback(hdspm);
5684 } else {
5685 if (running &&
5686 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5687 hdspm_silence_playback(hdspm);
5688 }
5689 } else {
5690 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5691 hdspm_silence_playback(hdspm);
5692 }
5693_ok:
5694 snd_pcm_trigger_done(substream, substream);
5695 if (!hdspm->running && running)
5696 hdspm_start_audio(hdspm);
5697 else if (hdspm->running && !running)
5698 hdspm_stop_audio(hdspm);
5699 hdspm->running = running;
5700 spin_unlock(&hdspm->lock);
5701
5702 return 0;
5703}
5704
5705static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5706{
5707 return 0;
5708}
5709
5710static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5711 .info = (SNDRV_PCM_INFO_MMAP |
5712 SNDRV_PCM_INFO_MMAP_VALID |
5713 SNDRV_PCM_INFO_NONINTERLEAVED |
5714 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5715 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5716 .rates = (SNDRV_PCM_RATE_32000 |
5717 SNDRV_PCM_RATE_44100 |
5718 SNDRV_PCM_RATE_48000 |
5719 SNDRV_PCM_RATE_64000 |
5720 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5721 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5722 .rate_min = 32000,
5723 .rate_max = 192000,
5724 .channels_min = 1,
5725 .channels_max = HDSPM_MAX_CHANNELS,
5726 .buffer_bytes_max =
5727 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5728 .period_bytes_min = (32 * 4),
5729 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5730 .periods_min = 2,
5731 .periods_max = 512,
5732 .fifo_size = 0
5733};
5734
5735static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5736 .info = (SNDRV_PCM_INFO_MMAP |
5737 SNDRV_PCM_INFO_MMAP_VALID |
5738 SNDRV_PCM_INFO_NONINTERLEAVED |
5739 SNDRV_PCM_INFO_SYNC_START),
5740 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5741 .rates = (SNDRV_PCM_RATE_32000 |
5742 SNDRV_PCM_RATE_44100 |
5743 SNDRV_PCM_RATE_48000 |
5744 SNDRV_PCM_RATE_64000 |
5745 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5746 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5747 .rate_min = 32000,
5748 .rate_max = 192000,
5749 .channels_min = 1,
5750 .channels_max = HDSPM_MAX_CHANNELS,
5751 .buffer_bytes_max =
5752 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5753 .period_bytes_min = (32 * 4),
5754 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5755 .periods_min = 2,
5756 .periods_max = 512,
5757 .fifo_size = 0
5758};
5759
5760static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5761 struct snd_pcm_hw_rule *rule)
5762{
5763 struct hdspm *hdspm = rule->private;
5764 struct snd_interval *c =
5765 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5766 struct snd_interval *r =
5767 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5768
5769 if (r->min > 96000 && r->max <= 192000) {
5770 struct snd_interval t = {
5771 .min = hdspm->qs_in_channels,
5772 .max = hdspm->qs_in_channels,
5773 .integer = 1,
5774 };
5775 return snd_interval_refine(c, &t);
5776 } else if (r->min > 48000 && r->max <= 96000) {
5777 struct snd_interval t = {
5778 .min = hdspm->ds_in_channels,
5779 .max = hdspm->ds_in_channels,
5780 .integer = 1,
5781 };
5782 return snd_interval_refine(c, &t);
5783 } else if (r->max < 64000) {
5784 struct snd_interval t = {
5785 .min = hdspm->ss_in_channels,
5786 .max = hdspm->ss_in_channels,
5787 .integer = 1,
5788 };
5789 return snd_interval_refine(c, &t);
5790 }
5791
5792 return 0;
5793}
5794
5795static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5796 struct snd_pcm_hw_rule * rule)
5797{
5798 struct hdspm *hdspm = rule->private;
5799 struct snd_interval *c =
5800 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5801 struct snd_interval *r =
5802 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5803
5804 if (r->min > 96000 && r->max <= 192000) {
5805 struct snd_interval t = {
5806 .min = hdspm->qs_out_channels,
5807 .max = hdspm->qs_out_channels,
5808 .integer = 1,
5809 };
5810 return snd_interval_refine(c, &t);
5811 } else if (r->min > 48000 && r->max <= 96000) {
5812 struct snd_interval t = {
5813 .min = hdspm->ds_out_channels,
5814 .max = hdspm->ds_out_channels,
5815 .integer = 1,
5816 };
5817 return snd_interval_refine(c, &t);
5818 } else if (r->max < 64000) {
5819 struct snd_interval t = {
5820 .min = hdspm->ss_out_channels,
5821 .max = hdspm->ss_out_channels,
5822 .integer = 1,
5823 };
5824 return snd_interval_refine(c, &t);
5825 } else {
5826 }
5827 return 0;
5828}
5829
5830static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5831 struct snd_pcm_hw_rule * rule)
5832{
5833 struct hdspm *hdspm = rule->private;
5834 struct snd_interval *c =
5835 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5836 struct snd_interval *r =
5837 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5838
5839 if (c->min >= hdspm->ss_in_channels) {
5840 struct snd_interval t = {
5841 .min = 32000,
5842 .max = 48000,
5843 .integer = 1,
5844 };
5845 return snd_interval_refine(r, &t);
5846 } else if (c->max <= hdspm->qs_in_channels) {
5847 struct snd_interval t = {
5848 .min = 128000,
5849 .max = 192000,
5850 .integer = 1,
5851 };
5852 return snd_interval_refine(r, &t);
5853 } else if (c->max <= hdspm->ds_in_channels) {
5854 struct snd_interval t = {
5855 .min = 64000,
5856 .max = 96000,
5857 .integer = 1,
5858 };
5859 return snd_interval_refine(r, &t);
5860 }
5861
5862 return 0;
5863}
5864static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5865 struct snd_pcm_hw_rule *rule)
5866{
5867 struct hdspm *hdspm = rule->private;
5868 struct snd_interval *c =
5869 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5870 struct snd_interval *r =
5871 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5872
5873 if (c->min >= hdspm->ss_out_channels) {
5874 struct snd_interval t = {
5875 .min = 32000,
5876 .max = 48000,
5877 .integer = 1,
5878 };
5879 return snd_interval_refine(r, &t);
5880 } else if (c->max <= hdspm->qs_out_channels) {
5881 struct snd_interval t = {
5882 .min = 128000,
5883 .max = 192000,
5884 .integer = 1,
5885 };
5886 return snd_interval_refine(r, &t);
5887 } else if (c->max <= hdspm->ds_out_channels) {
5888 struct snd_interval t = {
5889 .min = 64000,
5890 .max = 96000,
5891 .integer = 1,
5892 };
5893 return snd_interval_refine(r, &t);
5894 }
5895
5896 return 0;
5897}
5898
5899static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5900 struct snd_pcm_hw_rule *rule)
5901{
5902 unsigned int list[3];
5903 struct hdspm *hdspm = rule->private;
5904 struct snd_interval *c = hw_param_interval(params,
5905 SNDRV_PCM_HW_PARAM_CHANNELS);
5906
5907 list[0] = hdspm->qs_in_channels;
5908 list[1] = hdspm->ds_in_channels;
5909 list[2] = hdspm->ss_in_channels;
5910 return snd_interval_list(c, 3, list, 0);
5911}
5912
5913static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5914 struct snd_pcm_hw_rule *rule)
5915{
5916 unsigned int list[3];
5917 struct hdspm *hdspm = rule->private;
5918 struct snd_interval *c = hw_param_interval(params,
5919 SNDRV_PCM_HW_PARAM_CHANNELS);
5920
5921 list[0] = hdspm->qs_out_channels;
5922 list[1] = hdspm->ds_out_channels;
5923 list[2] = hdspm->ss_out_channels;
5924 return snd_interval_list(c, 3, list, 0);
5925}
5926
5927
5928static unsigned int hdspm_aes32_sample_rates[] = {
5929 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5930};
5931
5932static struct snd_pcm_hw_constraint_list
5933hdspm_hw_constraints_aes32_sample_rates = {
5934 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5935 .list = hdspm_aes32_sample_rates,
5936 .mask = 0
5937};
5938
5939static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5940{
5941 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5942 struct snd_pcm_runtime *runtime = substream->runtime;
5943
5944 spin_lock_irq(&hdspm->lock);
5945
5946 snd_pcm_set_sync(substream);
5947
5948
5949 runtime->hw = snd_hdspm_playback_subinfo;
5950
5951 if (hdspm->capture_substream == NULL)
5952 hdspm_stop_audio(hdspm);
5953
5954 hdspm->playback_pid = current->pid;
5955 hdspm->playback_substream = substream;
5956
5957 spin_unlock_irq(&hdspm->lock);
5958
5959 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5960 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5961
5962 switch (hdspm->io_type) {
5963 case AIO:
5964 case RayDAT:
5965 snd_pcm_hw_constraint_minmax(runtime,
5966 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5967 32, 4096);
5968 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
5969 snd_pcm_hw_constraint_minmax(runtime,
5970 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5971 16384, 16384);
5972 break;
5973
5974 default:
5975 snd_pcm_hw_constraint_minmax(runtime,
5976 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5977 64, 8192);
5978 break;
5979 }
5980
5981 if (AES32 == hdspm->io_type) {
5982 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
5983 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5984 &hdspm_hw_constraints_aes32_sample_rates);
5985 } else {
5986 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5987 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5988 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5989 }
5990
5991 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5992 snd_hdspm_hw_rule_out_channels, hdspm,
5993 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5994
5995 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5996 snd_hdspm_hw_rule_out_channels_rate, hdspm,
5997 SNDRV_PCM_HW_PARAM_RATE, -1);
5998
5999 return 0;
6000}
6001
6002static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6003{
6004 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6005
6006 spin_lock_irq(&hdspm->lock);
6007
6008 hdspm->playback_pid = -1;
6009 hdspm->playback_substream = NULL;
6010
6011 spin_unlock_irq(&hdspm->lock);
6012
6013 return 0;
6014}
6015
6016
6017static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6018{
6019 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6020 struct snd_pcm_runtime *runtime = substream->runtime;
6021
6022 spin_lock_irq(&hdspm->lock);
6023 snd_pcm_set_sync(substream);
6024 runtime->hw = snd_hdspm_capture_subinfo;
6025
6026 if (hdspm->playback_substream == NULL)
6027 hdspm_stop_audio(hdspm);
6028
6029 hdspm->capture_pid = current->pid;
6030 hdspm->capture_substream = substream;
6031
6032 spin_unlock_irq(&hdspm->lock);
6033
6034 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6035 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6036
6037 switch (hdspm->io_type) {
6038 case AIO:
6039 case RayDAT:
6040 snd_pcm_hw_constraint_minmax(runtime,
6041 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6042 32, 4096);
6043 snd_pcm_hw_constraint_minmax(runtime,
6044 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6045 16384, 16384);
6046 break;
6047
6048 default:
6049 snd_pcm_hw_constraint_minmax(runtime,
6050 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6051 64, 8192);
6052 break;
6053 }
6054
6055 if (AES32 == hdspm->io_type) {
6056 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6057 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6058 &hdspm_hw_constraints_aes32_sample_rates);
6059 } else {
6060 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6061 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6062 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6063 }
6064
6065 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6066 snd_hdspm_hw_rule_in_channels, hdspm,
6067 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6068
6069 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6070 snd_hdspm_hw_rule_in_channels_rate, hdspm,
6071 SNDRV_PCM_HW_PARAM_RATE, -1);
6072
6073 return 0;
6074}
6075
6076static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6077{
6078 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6079
6080 spin_lock_irq(&hdspm->lock);
6081
6082 hdspm->capture_pid = -1;
6083 hdspm->capture_substream = NULL;
6084
6085 spin_unlock_irq(&hdspm->lock);
6086 return 0;
6087}
6088
6089static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6090{
6091 /* we have nothing to initialize but the call is required */
6092 return 0;
6093}
6094
6095static inline int copy_u32_le(void __user *dest, void __iomem *src)
6096{
6097 u32 val = readl(src);
6098 return copy_to_user(dest, &val, 4);
6099}
6100
6101static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6102 unsigned int cmd, unsigned long arg)
6103{
6104 void __user *argp = (void __user *)arg;
6105 struct hdspm *hdspm = hw->private_data;
6106 struct hdspm_mixer_ioctl mixer;
6107 struct hdspm_config info;
6108 struct hdspm_status status;
6109 struct hdspm_version hdspm_version;
6110 struct hdspm_peak_rms *levels;
6111 struct hdspm_ltc ltc;
6112 unsigned int statusregister;
6113 long unsigned int s;
6114 int i = 0;
6115
6116 switch (cmd) {
6117
6118 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6119 levels = &hdspm->peak_rms;
6120 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6121 levels->input_peaks[i] =
6122 readl(hdspm->iobase +
6123 HDSPM_MADI_INPUT_PEAK + i*4);
6124 levels->playback_peaks[i] =
6125 readl(hdspm->iobase +
6126 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6127 levels->output_peaks[i] =
6128 readl(hdspm->iobase +
6129 HDSPM_MADI_OUTPUT_PEAK + i*4);
6130
6131 levels->input_rms[i] =
6132 ((uint64_t) readl(hdspm->iobase +
6133 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6134 (uint64_t) readl(hdspm->iobase +
6135 HDSPM_MADI_INPUT_RMS_L + i*4);
6136 levels->playback_rms[i] =
6137 ((uint64_t)readl(hdspm->iobase +
6138 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6139 (uint64_t)readl(hdspm->iobase +
6140 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6141 levels->output_rms[i] =
6142 ((uint64_t)readl(hdspm->iobase +
6143 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6144 (uint64_t)readl(hdspm->iobase +
6145 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6146 }
6147
6148 if (hdspm->system_sample_rate > 96000) {
6149 levels->speed = qs;
6150 } else if (hdspm->system_sample_rate > 48000) {
6151 levels->speed = ds;
6152 } else {
6153 levels->speed = ss;
6154 }
6155 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6156
6157 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6158 if (0 != s) {
6159 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6160 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6161 */
6162 return -EFAULT;
6163 }
6164 break;
6165
6166 case SNDRV_HDSPM_IOCTL_GET_LTC:
6167 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6168 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6169 if (i & HDSPM_TCO1_LTC_Input_valid) {
6170 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6171 HDSPM_TCO1_LTC_Format_MSB)) {
6172 case 0:
6173 ltc.format = fps_24;
6174 break;
6175 case HDSPM_TCO1_LTC_Format_LSB:
6176 ltc.format = fps_25;
6177 break;
6178 case HDSPM_TCO1_LTC_Format_MSB:
6179 ltc.format = fps_2997;
6180 break;
6181 default:
6182 ltc.format = 30;
6183 break;
6184 }
6185 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6186 ltc.frame = drop_frame;
6187 } else {
6188 ltc.frame = full_frame;
6189 }
6190 } else {
6191 ltc.format = format_invalid;
6192 ltc.frame = frame_invalid;
6193 }
6194 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6195 ltc.input_format = ntsc;
6196 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6197 ltc.input_format = pal;
6198 } else {
6199 ltc.input_format = no_video;
6200 }
6201
6202 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc));
6203 if (0 != s) {
6204 /*
6205 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6206 return -EFAULT;
6207 }
6208
6209 break;
6210
6211 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6212
6213 memset(&info, 0, sizeof(info));
6214 spin_lock_irq(&hdspm->lock);
6215 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6216 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6217
6218 info.system_sample_rate = hdspm->system_sample_rate;
6219 info.autosync_sample_rate =
6220 hdspm_external_sample_rate(hdspm);
6221 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6222 info.clock_source = hdspm_clock_source(hdspm);
6223 info.autosync_ref = hdspm_autosync_ref(hdspm);
6224 info.line_out = hdspm_line_out(hdspm);
6225 info.passthru = 0;
6226 spin_unlock_irq(&hdspm->lock);
6227 if (copy_to_user(argp, &info, sizeof(info)))
6228 return -EFAULT;
6229 break;
6230
6231 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6232 memset(&status, 0, sizeof(status));
6233
6234 status.card_type = hdspm->io_type;
6235
6236 status.autosync_source = hdspm_autosync_ref(hdspm);
6237
6238 status.card_clock = 110069313433624ULL;
6239 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6240
6241 switch (hdspm->io_type) {
6242 case MADI:
6243 case MADIface:
6244 status.card_specific.madi.sync_wc =
6245 hdspm_wc_sync_check(hdspm);
6246 status.card_specific.madi.sync_madi =
6247 hdspm_madi_sync_check(hdspm);
6248 status.card_specific.madi.sync_tco =
6249 hdspm_tco_sync_check(hdspm);
6250 status.card_specific.madi.sync_in =
6251 hdspm_sync_in_sync_check(hdspm);
6252
6253 statusregister =
6254 hdspm_read(hdspm, HDSPM_statusRegister);
6255 status.card_specific.madi.madi_input =
6256 (statusregister & HDSPM_AB_int) ? 1 : 0;
6257 status.card_specific.madi.channel_format =
6258 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6259 /* TODO: Mac driver sets it when f_s>48kHz */
6260 status.card_specific.madi.frame_format = 0;
6261
6262 default:
6263 break;
6264 }
6265
6266 if (copy_to_user(argp, &status, sizeof(status)))
6267 return -EFAULT;
6268
6269
6270 break;
6271
6272 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6273 memset(&hdspm_version, 0, sizeof(hdspm_version));
6274
6275 hdspm_version.card_type = hdspm->io_type;
6276 strncpy(hdspm_version.cardname, hdspm->card_name,
6277 sizeof(hdspm_version.cardname));
6278 hdspm_version.serial = hdspm->serial;
6279 hdspm_version.firmware_rev = hdspm->firmware_rev;
6280 hdspm_version.addons = 0;
6281 if (hdspm->tco)
6282 hdspm_version.addons |= HDSPM_ADDON_TCO;
6283
6284 if (copy_to_user(argp, &hdspm_version,
6285 sizeof(hdspm_version)))
6286 return -EFAULT;
6287 break;
6288
6289 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6290 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6291 return -EFAULT;
6292 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6293 sizeof(struct hdspm_mixer)))
6294 return -EFAULT;
6295 break;
6296
6297 default:
6298 return -EINVAL;
6299 }
6300 return 0;
6301}
6302
6303static struct snd_pcm_ops snd_hdspm_playback_ops = {
6304 .open = snd_hdspm_playback_open,
6305 .close = snd_hdspm_playback_release,
6306 .ioctl = snd_hdspm_ioctl,
6307 .hw_params = snd_hdspm_hw_params,
6308 .hw_free = snd_hdspm_hw_free,
6309 .prepare = snd_hdspm_prepare,
6310 .trigger = snd_hdspm_trigger,
6311 .pointer = snd_hdspm_hw_pointer,
6312 .page = snd_pcm_sgbuf_ops_page,
6313};
6314
6315static struct snd_pcm_ops snd_hdspm_capture_ops = {
6316 .open = snd_hdspm_capture_open,
6317 .close = snd_hdspm_capture_release,
6318 .ioctl = snd_hdspm_ioctl,
6319 .hw_params = snd_hdspm_hw_params,
6320 .hw_free = snd_hdspm_hw_free,
6321 .prepare = snd_hdspm_prepare,
6322 .trigger = snd_hdspm_trigger,
6323 .pointer = snd_hdspm_hw_pointer,
6324 .page = snd_pcm_sgbuf_ops_page,
6325};
6326
6327static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6328 struct hdspm * hdspm)
6329{
6330 struct snd_hwdep *hw;
6331 int err;
6332
6333 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6334 if (err < 0)
6335 return err;
6336
6337 hdspm->hwdep = hw;
6338 hw->private_data = hdspm;
6339 strcpy(hw->name, "HDSPM hwdep interface");
6340
6341 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6342 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6343 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6344 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6345
6346 return 0;
6347}
6348
6349
6350/*------------------------------------------------------------
6351 memory interface
6352 ------------------------------------------------------------*/
6353static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6354{
6355 int err;
6356 struct snd_pcm *pcm;
6357 size_t wanted;
6358
6359 pcm = hdspm->pcm;
6360
6361 wanted = HDSPM_DMA_AREA_BYTES;
6362
6363 err =
6364 snd_pcm_lib_preallocate_pages_for_all(pcm,
6365 SNDRV_DMA_TYPE_DEV_SG,
6366 snd_dma_pci_data(hdspm->pci),
6367 wanted,
6368 wanted);
6369 if (err < 0) {
6370 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6371
6372 return err;
6373 } else
6374 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6375
6376 return 0;
6377}
6378
6379
6380static void hdspm_set_sgbuf(struct hdspm *hdspm,
6381 struct snd_pcm_substream *substream,
6382 unsigned int reg, int channels)
6383{
6384 int i;
6385
6386 /* continuous memory segment */
6387 for (i = 0; i < (channels * 16); i++)
6388 hdspm_write(hdspm, reg + 4 * i,
6389 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6390}
6391
6392
6393/* ------------- ALSA Devices ---------------------------- */
6394static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6395 struct hdspm *hdspm)
6396{
6397 struct snd_pcm *pcm;
6398 int err;
6399
6400 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6401 if (err < 0)
6402 return err;
6403
6404 hdspm->pcm = pcm;
6405 pcm->private_data = hdspm;
6406 strcpy(pcm->name, hdspm->card_name);
6407
6408 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6409 &snd_hdspm_playback_ops);
6410 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6411 &snd_hdspm_capture_ops);
6412
6413 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6414
6415 err = snd_hdspm_preallocate_memory(hdspm);
6416 if (err < 0)
6417 return err;
6418
6419 return 0;
6420}
6421
6422static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6423{
6424 int i;
6425
6426 for (i = 0; i < hdspm->midiPorts; i++)
6427 snd_hdspm_flush_midi_input(hdspm, i);
6428}
6429
6430static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6431 struct hdspm * hdspm)
6432{
6433 int err, i;
6434
6435 snd_printdd("Create card...\n");
6436 err = snd_hdspm_create_pcm(card, hdspm);
6437 if (err < 0)
6438 return err;
6439
6440 i = 0;
6441 while (i < hdspm->midiPorts) {
6442 err = snd_hdspm_create_midi(card, hdspm, i);
6443 if (err < 0) {
6444 return err;
6445 }
6446 i++;
6447 }
6448
6449 err = snd_hdspm_create_controls(card, hdspm);
6450 if (err < 0)
6451 return err;
6452
6453 err = snd_hdspm_create_hwdep(card, hdspm);
6454 if (err < 0)
6455 return err;
6456
6457 snd_printdd("proc init...\n");
6458 snd_hdspm_proc_init(hdspm);
6459
6460 hdspm->system_sample_rate = -1;
6461 hdspm->last_external_sample_rate = -1;
6462 hdspm->last_internal_sample_rate = -1;
6463 hdspm->playback_pid = -1;
6464 hdspm->capture_pid = -1;
6465 hdspm->capture_substream = NULL;
6466 hdspm->playback_substream = NULL;
6467
6468 snd_printdd("Set defaults...\n");
6469 err = snd_hdspm_set_defaults(hdspm);
6470 if (err < 0)
6471 return err;
6472
6473 snd_printdd("Update mixer controls...\n");
6474 hdspm_update_simple_mixer_controls(hdspm);
6475
6476 snd_printdd("Initializeing complete ???\n");
6477
6478 err = snd_card_register(card);
6479 if (err < 0) {
6480 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6481 return err;
6482 }
6483
6484 snd_printdd("... yes now\n");
6485
6486 return 0;
6487}
6488
6489static int __devinit snd_hdspm_create(struct snd_card *card,
6490 struct hdspm *hdspm) {
6491
6492 struct pci_dev *pci = hdspm->pci;
6493 int err;
6494 unsigned long io_extent;
6495
6496 hdspm->irq = -1;
6497 hdspm->card = card;
6498
6499 spin_lock_init(&hdspm->lock);
6500
6501 pci_read_config_word(hdspm->pci,
6502 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6503
6504 strcpy(card->mixername, "Xilinx FPGA");
6505 strcpy(card->driver, "HDSPM");
6506
6507 switch (hdspm->firmware_rev) {
6508 case HDSPM_RAYDAT_REV:
6509 hdspm->io_type = RayDAT;
6510 hdspm->card_name = "RME RayDAT";
6511 hdspm->midiPorts = 2;
6512 break;
6513 case HDSPM_AIO_REV:
6514 hdspm->io_type = AIO;
6515 hdspm->card_name = "RME AIO";
6516 hdspm->midiPorts = 1;
6517 break;
6518 case HDSPM_MADIFACE_REV:
6519 hdspm->io_type = MADIface;
6520 hdspm->card_name = "RME MADIface";
6521 hdspm->midiPorts = 1;
6522 break;
6523 default:
6524 if ((hdspm->firmware_rev == 0xf0) ||
6525 ((hdspm->firmware_rev >= 0xe6) &&
6526 (hdspm->firmware_rev <= 0xea))) {
6527 hdspm->io_type = AES32;
6528 hdspm->card_name = "RME AES32";
6529 hdspm->midiPorts = 2;
6530 } else if ((hdspm->firmware_rev == 0xd2) ||
6531 ((hdspm->firmware_rev >= 0xc8) &&
6532 (hdspm->firmware_rev <= 0xcf))) {
6533 hdspm->io_type = MADI;
6534 hdspm->card_name = "RME MADI";
6535 hdspm->midiPorts = 3;
6536 } else {
6537 snd_printk(KERN_ERR
6538 "HDSPM: unknown firmware revision %x\n",
6539 hdspm->firmware_rev);
6540 return -ENODEV;
6541 }
6542 }
6543
6544 err = pci_enable_device(pci);
6545 if (err < 0)
6546 return err;
6547
6548 pci_set_master(hdspm->pci);
6549
6550 err = pci_request_regions(pci, "hdspm");
6551 if (err < 0)
6552 return err;
6553
6554 hdspm->port = pci_resource_start(pci, 0);
6555 io_extent = pci_resource_len(pci, 0);
6556
6557 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6558 hdspm->port, hdspm->port + io_extent - 1);
6559
6560 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6561 if (!hdspm->iobase) {
6562 snd_printk(KERN_ERR "HDSPM: "
6563 "unable to remap region 0x%lx-0x%lx\n",
6564 hdspm->port, hdspm->port + io_extent - 1);
6565 return -EBUSY;
6566 }
6567 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6568 (unsigned long)hdspm->iobase, hdspm->port,
6569 hdspm->port + io_extent - 1);
6570
6571 if (request_irq(pci->irq, snd_hdspm_interrupt,
6572 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6573 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6574 return -EBUSY;
6575 }
6576
6577 snd_printdd("use IRQ %d\n", pci->irq);
6578
6579 hdspm->irq = pci->irq;
6580
6581 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6582 sizeof(struct hdspm_mixer));
6583 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6584 if (!hdspm->mixer) {
6585 snd_printk(KERN_ERR "HDSPM: "
6586 "unable to kmalloc Mixer memory of %d Bytes\n",
6587 (int)sizeof(struct hdspm_mixer));
6588 return err;
6589 }
6590
6591 hdspm->port_names_in = NULL;
6592 hdspm->port_names_out = NULL;
6593
6594 switch (hdspm->io_type) {
6595 case AES32:
6596 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6597 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6598 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6599
6600 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6601 channel_map_aes32;
6602 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6603 channel_map_aes32;
6604 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6605 channel_map_aes32;
6606 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6607 texts_ports_aes32;
6608 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6609 texts_ports_aes32;
6610 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6611 texts_ports_aes32;
6612
6613 hdspm->max_channels_out = hdspm->max_channels_in =
6614 AES32_CHANNELS;
6615 hdspm->port_names_in = hdspm->port_names_out =
6616 texts_ports_aes32;
6617 hdspm->channel_map_in = hdspm->channel_map_out =
6618 channel_map_aes32;
6619
6620 break;
6621
6622 case MADI:
6623 case MADIface:
6624 hdspm->ss_in_channels = hdspm->ss_out_channels =
6625 MADI_SS_CHANNELS;
6626 hdspm->ds_in_channels = hdspm->ds_out_channels =
6627 MADI_DS_CHANNELS;
6628 hdspm->qs_in_channels = hdspm->qs_out_channels =
6629 MADI_QS_CHANNELS;
6630
6631 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6632 channel_map_unity_ss;
6633 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6634 channel_map_unity_ss;
6635 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6636 channel_map_unity_ss;
6637
6638 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6639 texts_ports_madi;
6640 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6641 texts_ports_madi;
6642 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6643 texts_ports_madi;
6644 break;
6645
6646 case AIO:
6647 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6648 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6649 }
6650
6651 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6652 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6653 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6654 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6655 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6656 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6657
6658 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6659 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6660 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6661
6662 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6663 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6664 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6665
6666 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6667 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6668 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6669 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6670 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6671 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6672
6673 break;
6674
6675 case RayDAT:
6676 hdspm->ss_in_channels = hdspm->ss_out_channels =
6677 RAYDAT_SS_CHANNELS;
6678 hdspm->ds_in_channels = hdspm->ds_out_channels =
6679 RAYDAT_DS_CHANNELS;
6680 hdspm->qs_in_channels = hdspm->qs_out_channels =
6681 RAYDAT_QS_CHANNELS;
6682
6683 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6684 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6685
6686 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6687 channel_map_raydat_ss;
6688 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6689 channel_map_raydat_ds;
6690 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6691 channel_map_raydat_qs;
6692 hdspm->channel_map_in = hdspm->channel_map_out =
6693 channel_map_raydat_ss;
6694
6695 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6696 texts_ports_raydat_ss;
6697 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6698 texts_ports_raydat_ds;
6699 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6700 texts_ports_raydat_qs;
6701
6702
6703 break;
6704
6705 }
6706
6707 /* TCO detection */
6708 switch (hdspm->io_type) {
6709 case AIO:
6710 case RayDAT:
6711 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6712 HDSPM_s2_tco_detect) {
6713 hdspm->midiPorts++;
6714 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6715 GFP_KERNEL);
6716 if (NULL != hdspm->tco) {
6717 hdspm_tco_write(hdspm);
6718 }
6719 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6720 } else {
6721 hdspm->tco = NULL;
6722 }
6723 break;
6724
6725 case MADI:
6726 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6727 hdspm->midiPorts++;
6728 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6729 GFP_KERNEL);
6730 if (NULL != hdspm->tco) {
6731 hdspm_tco_write(hdspm);
6732 }
6733 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6734 } else {
6735 hdspm->tco = NULL;
6736 }
6737 break;
6738
6739 default:
6740 hdspm->tco = NULL;
6741 }
6742
6743 /* texts */
6744 switch (hdspm->io_type) {
6745 case AES32:
6746 if (hdspm->tco) {
6747 hdspm->texts_autosync = texts_autosync_aes_tco;
6748 hdspm->texts_autosync_items = 10;
6749 } else {
6750 hdspm->texts_autosync = texts_autosync_aes;
6751 hdspm->texts_autosync_items = 9;
6752 }
6753 break;
6754
6755 case MADI:
6756 if (hdspm->tco) {
6757 hdspm->texts_autosync = texts_autosync_madi_tco;
6758 hdspm->texts_autosync_items = 4;
6759 } else {
6760 hdspm->texts_autosync = texts_autosync_madi;
6761 hdspm->texts_autosync_items = 3;
6762 }
6763 break;
6764
6765 case MADIface:
6766
6767 break;
6768
6769 case RayDAT:
6770 if (hdspm->tco) {
6771 hdspm->texts_autosync = texts_autosync_raydat_tco;
6772 hdspm->texts_autosync_items = 9;
6773 } else {
6774 hdspm->texts_autosync = texts_autosync_raydat;
6775 hdspm->texts_autosync_items = 8;
6776 }
6777 break;
6778
6779 case AIO:
6780 if (hdspm->tco) {
6781 hdspm->texts_autosync = texts_autosync_aio_tco;
6782 hdspm->texts_autosync_items = 6;
6783 } else {
6784 hdspm->texts_autosync = texts_autosync_aio;
6785 hdspm->texts_autosync_items = 5;
6786 }
6787 break;
6788
6789 }
6790
6791 tasklet_init(&hdspm->midi_tasklet,
6792 hdspm_midi_tasklet, (unsigned long) hdspm);
6793
6794
6795 if (hdspm->io_type != MADIface) {
6796 hdspm->serial = (hdspm_read(hdspm,
6797 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6798 /* id contains either a user-provided value or the default
6799 * NULL. If it's the default, we're safe to
6800 * fill card->id with the serial number.
6801 *
6802 * If the serial number is 0xFFFFFF, then we're dealing with
6803 * an old PCI revision that comes without a sane number. In
6804 * this case, we don't set card->id to avoid collisions
6805 * when running with multiple cards.
6806 */
6807 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6808 sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6809 snd_card_set_id(card, card->id);
6810 }
6811 }
6812
6813 snd_printdd("create alsa devices.\n");
6814 err = snd_hdspm_create_alsa_devices(card, hdspm);
6815 if (err < 0)
6816 return err;
6817
6818 snd_hdspm_initialize_midi_flush(hdspm);
6819
6820 return 0;
6821}
6822
6823
6824static int snd_hdspm_free(struct hdspm * hdspm)
6825{
6826
6827 if (hdspm->port) {
6828
6829 /* stop th audio, and cancel all interrupts */
6830 hdspm->control_register &=
6831 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6832 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6833 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6834 hdspm_write(hdspm, HDSPM_controlRegister,
6835 hdspm->control_register);
6836 }
6837
6838 if (hdspm->irq >= 0)
6839 free_irq(hdspm->irq, (void *) hdspm);
6840
6841 kfree(hdspm->mixer);
6842
6843 if (hdspm->iobase)
6844 iounmap(hdspm->iobase);
6845
6846 if (hdspm->port)
6847 pci_release_regions(hdspm->pci);
6848
6849 pci_disable_device(hdspm->pci);
6850 return 0;
6851}
6852
6853
6854static void snd_hdspm_card_free(struct snd_card *card)
6855{
6856 struct hdspm *hdspm = card->private_data;
6857
6858 if (hdspm)
6859 snd_hdspm_free(hdspm);
6860}
6861
6862
6863static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6864 const struct pci_device_id *pci_id)
6865{
6866 static int dev;
6867 struct hdspm *hdspm;
6868 struct snd_card *card;
6869 int err;
6870
6871 if (dev >= SNDRV_CARDS)
6872 return -ENODEV;
6873 if (!enable[dev]) {
6874 dev++;
6875 return -ENOENT;
6876 }
6877
6878 err = snd_card_create(index[dev], id[dev],
6879 THIS_MODULE, sizeof(struct hdspm), &card);
6880 if (err < 0)
6881 return err;
6882
6883 hdspm = card->private_data;
6884 card->private_free = snd_hdspm_card_free;
6885 hdspm->dev = dev;
6886 hdspm->pci = pci;
6887
6888 snd_card_set_dev(card, &pci->dev);
6889
6890 err = snd_hdspm_create(card, hdspm);
6891 if (err < 0) {
6892 snd_card_free(card);
6893 return err;
6894 }
6895
6896 if (hdspm->io_type != MADIface) {
6897 sprintf(card->shortname, "%s_%x",
6898 hdspm->card_name,
6899 hdspm->serial);
6900 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6901 hdspm->card_name,
6902 hdspm->serial,
6903 hdspm->port, hdspm->irq);
6904 } else {
6905 sprintf(card->shortname, "%s", hdspm->card_name);
6906 sprintf(card->longname, "%s at 0x%lx, irq %d",
6907 hdspm->card_name, hdspm->port, hdspm->irq);
6908 }
6909
6910 err = snd_card_register(card);
6911 if (err < 0) {
6912 snd_card_free(card);
6913 return err;
6914 }
6915
6916 pci_set_drvdata(pci, card);
6917
6918 dev++;
6919 return 0;
6920}
6921
6922static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6923{
6924 snd_card_free(pci_get_drvdata(pci));
6925 pci_set_drvdata(pci, NULL);
6926}
6927
6928static struct pci_driver hdspm_driver = {
6929 .name = KBUILD_MODNAME,
6930 .id_table = snd_hdspm_ids,
6931 .probe = snd_hdspm_probe,
6932 .remove = __devexit_p(snd_hdspm_remove),
6933};
6934
6935module_pci_driver(hdspm_driver);