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1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2009-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21/* Macros to deal with bit fields. Each bit field must have 3 #defines
22 * associated with it (_SHIFT, _MASK, and _WORD).
23 * EG. For a bit field that is in the 7th bit of the "field4" field of a
24 * structure and is 2 bits in size the following #defines must exist:
25 * struct temp {
26 * uint32_t field1;
27 * uint32_t field2;
28 * uint32_t field3;
29 * uint32_t field4;
30 * #define example_bit_field_SHIFT 7
31 * #define example_bit_field_MASK 0x03
32 * #define example_bit_field_WORD field4
33 * uint32_t field5;
34 * };
35 * Then the macros below may be used to get or set the value of that field.
36 * EG. To get the value of the bit field from the above example:
37 * struct temp t1;
38 * value = bf_get(example_bit_field, &t1);
39 * And then to set that bit field:
40 * bf_set(example_bit_field, &t1, 2);
41 * Or clear that bit field:
42 * bf_set(example_bit_field, &t1, 0);
43 */
44#define bf_get_be32(name, ptr) \
45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
46#define bf_get_le32(name, ptr) \
47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
48#define bf_get(name, ptr) \
49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
50#define bf_set_le32(name, ptr, value) \
51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
53 ~(name##_MASK << name##_SHIFT)))))
54#define bf_set(name, ptr, value) \
55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
57
58struct dma_address {
59 uint32_t addr_lo;
60 uint32_t addr_hi;
61};
62
63struct lpfc_sli_intf {
64 uint32_t word0;
65#define lpfc_sli_intf_valid_SHIFT 29
66#define lpfc_sli_intf_valid_MASK 0x00000007
67#define lpfc_sli_intf_valid_WORD word0
68#define LPFC_SLI_INTF_VALID 6
69#define lpfc_sli_intf_sli_hint2_SHIFT 24
70#define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
71#define lpfc_sli_intf_sli_hint2_WORD word0
72#define LPFC_SLI_INTF_SLI_HINT2_NONE 0
73#define lpfc_sli_intf_sli_hint1_SHIFT 16
74#define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
75#define lpfc_sli_intf_sli_hint1_WORD word0
76#define LPFC_SLI_INTF_SLI_HINT1_NONE 0
77#define LPFC_SLI_INTF_SLI_HINT1_1 1
78#define LPFC_SLI_INTF_SLI_HINT1_2 2
79#define lpfc_sli_intf_if_type_SHIFT 12
80#define lpfc_sli_intf_if_type_MASK 0x0000000F
81#define lpfc_sli_intf_if_type_WORD word0
82#define LPFC_SLI_INTF_IF_TYPE_0 0
83#define LPFC_SLI_INTF_IF_TYPE_1 1
84#define LPFC_SLI_INTF_IF_TYPE_2 2
85#define lpfc_sli_intf_sli_family_SHIFT 8
86#define lpfc_sli_intf_sli_family_MASK 0x0000000F
87#define lpfc_sli_intf_sli_family_WORD word0
88#define LPFC_SLI_INTF_FAMILY_BE2 0x0
89#define LPFC_SLI_INTF_FAMILY_BE3 0x1
90#define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
91#define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
92#define lpfc_sli_intf_slirev_SHIFT 4
93#define lpfc_sli_intf_slirev_MASK 0x0000000F
94#define lpfc_sli_intf_slirev_WORD word0
95#define LPFC_SLI_INTF_REV_SLI3 3
96#define LPFC_SLI_INTF_REV_SLI4 4
97#define lpfc_sli_intf_func_type_SHIFT 0
98#define lpfc_sli_intf_func_type_MASK 0x00000001
99#define lpfc_sli_intf_func_type_WORD word0
100#define LPFC_SLI_INTF_IF_TYPE_PHYS 0
101#define LPFC_SLI_INTF_IF_TYPE_VIRT 1
102};
103
104#define LPFC_SLI4_MBX_EMBED true
105#define LPFC_SLI4_MBX_NEMBED false
106
107#define LPFC_SLI4_MB_WORD_COUNT 64
108#define LPFC_MAX_MQ_PAGE 8
109#define LPFC_MAX_WQ_PAGE 8
110#define LPFC_MAX_CQ_PAGE 4
111#define LPFC_MAX_EQ_PAGE 8
112
113#define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */
114#define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */
115#define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
116
117/* Define SLI4 Alignment requirements. */
118#define LPFC_ALIGN_16_BYTE 16
119#define LPFC_ALIGN_64_BYTE 64
120
121/* Define SLI4 specific definitions. */
122#define LPFC_MQ_CQE_BYTE_OFFSET 256
123#define LPFC_MBX_CMD_HDR_LENGTH 16
124#define LPFC_MBX_ERROR_RANGE 0x4000
125#define LPFC_BMBX_BIT1_ADDR_HI 0x2
126#define LPFC_BMBX_BIT1_ADDR_LO 0
127#define LPFC_RPI_HDR_COUNT 64
128#define LPFC_HDR_TEMPLATE_SIZE 4096
129#define LPFC_RPI_ALLOC_ERROR 0xFFFF
130#define LPFC_FCF_RECORD_WD_CNT 132
131#define LPFC_ENTIRE_FCF_DATABASE 0
132#define LPFC_DFLT_FCF_INDEX 0
133
134/* Virtual function numbers */
135#define LPFC_VF0 0
136#define LPFC_VF1 1
137#define LPFC_VF2 2
138#define LPFC_VF3 3
139#define LPFC_VF4 4
140#define LPFC_VF5 5
141#define LPFC_VF6 6
142#define LPFC_VF7 7
143#define LPFC_VF8 8
144#define LPFC_VF9 9
145#define LPFC_VF10 10
146#define LPFC_VF11 11
147#define LPFC_VF12 12
148#define LPFC_VF13 13
149#define LPFC_VF14 14
150#define LPFC_VF15 15
151#define LPFC_VF16 16
152#define LPFC_VF17 17
153#define LPFC_VF18 18
154#define LPFC_VF19 19
155#define LPFC_VF20 20
156#define LPFC_VF21 21
157#define LPFC_VF22 22
158#define LPFC_VF23 23
159#define LPFC_VF24 24
160#define LPFC_VF25 25
161#define LPFC_VF26 26
162#define LPFC_VF27 27
163#define LPFC_VF28 28
164#define LPFC_VF29 29
165#define LPFC_VF30 30
166#define LPFC_VF31 31
167
168/* PCI function numbers */
169#define LPFC_PCI_FUNC0 0
170#define LPFC_PCI_FUNC1 1
171#define LPFC_PCI_FUNC2 2
172#define LPFC_PCI_FUNC3 3
173#define LPFC_PCI_FUNC4 4
174
175/* SLI4 interface type-2 PDEV_CTL register */
176#define LPFC_CTL_PDEV_CTL_OFFSET 0x414
177#define LPFC_CTL_PDEV_CTL_DRST 0x00000001
178#define LPFC_CTL_PDEV_CTL_FRST 0x00000002
179#define LPFC_CTL_PDEV_CTL_DD 0x00000004
180#define LPFC_CTL_PDEV_CTL_LC 0x00000008
181#define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
182#define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
183#define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
184
185#define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
186
187/* Active interrupt test count */
188#define LPFC_ACT_INTR_CNT 4
189
190/* Delay Multiplier constant */
191#define LPFC_DMULT_CONST 651042
192#define LPFC_MIM_IMAX 636
193#define LPFC_FP_DEF_IMAX 10000
194#define LPFC_SP_DEF_IMAX 10000
195
196/* PORT_CAPABILITIES constants. */
197#define LPFC_MAX_SUPPORTED_PAGES 8
198
199struct ulp_bde64 {
200 union ULP_BDE_TUS {
201 uint32_t w;
202 struct {
203#ifdef __BIG_ENDIAN_BITFIELD
204 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
205 VALUE !! */
206 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
207#else /* __LITTLE_ENDIAN_BITFIELD */
208 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
209 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
210 VALUE !! */
211#endif
212#define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
213#define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
214#define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
215#define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
216#define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
217#define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
218#define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
219 } f;
220 } tus;
221 uint32_t addrLow;
222 uint32_t addrHigh;
223};
224
225struct lpfc_sli4_flags {
226 uint32_t word0;
227#define lpfc_idx_rsrc_rdy_SHIFT 0
228#define lpfc_idx_rsrc_rdy_MASK 0x00000001
229#define lpfc_idx_rsrc_rdy_WORD word0
230#define LPFC_IDX_RSRC_RDY 1
231#define lpfc_rpi_rsrc_rdy_SHIFT 1
232#define lpfc_rpi_rsrc_rdy_MASK 0x00000001
233#define lpfc_rpi_rsrc_rdy_WORD word0
234#define LPFC_RPI_RSRC_RDY 1
235#define lpfc_vpi_rsrc_rdy_SHIFT 2
236#define lpfc_vpi_rsrc_rdy_MASK 0x00000001
237#define lpfc_vpi_rsrc_rdy_WORD word0
238#define LPFC_VPI_RSRC_RDY 1
239#define lpfc_vfi_rsrc_rdy_SHIFT 3
240#define lpfc_vfi_rsrc_rdy_MASK 0x00000001
241#define lpfc_vfi_rsrc_rdy_WORD word0
242#define LPFC_VFI_RSRC_RDY 1
243};
244
245struct sli4_bls_rsp {
246 uint32_t word0_rsvd; /* Word0 must be reserved */
247 uint32_t word1;
248#define lpfc_abts_orig_SHIFT 0
249#define lpfc_abts_orig_MASK 0x00000001
250#define lpfc_abts_orig_WORD word1
251#define LPFC_ABTS_UNSOL_RSP 1
252#define LPFC_ABTS_UNSOL_INT 0
253 uint32_t word2;
254#define lpfc_abts_rxid_SHIFT 0
255#define lpfc_abts_rxid_MASK 0x0000FFFF
256#define lpfc_abts_rxid_WORD word2
257#define lpfc_abts_oxid_SHIFT 16
258#define lpfc_abts_oxid_MASK 0x0000FFFF
259#define lpfc_abts_oxid_WORD word2
260 uint32_t word3;
261#define lpfc_vndr_code_SHIFT 0
262#define lpfc_vndr_code_MASK 0x000000FF
263#define lpfc_vndr_code_WORD word3
264#define lpfc_rsn_expln_SHIFT 8
265#define lpfc_rsn_expln_MASK 0x000000FF
266#define lpfc_rsn_expln_WORD word3
267#define lpfc_rsn_code_SHIFT 16
268#define lpfc_rsn_code_MASK 0x000000FF
269#define lpfc_rsn_code_WORD word3
270
271 uint32_t word4;
272 uint32_t word5_rsvd; /* Word5 must be reserved */
273};
274
275/* event queue entry structure */
276struct lpfc_eqe {
277 uint32_t word0;
278#define lpfc_eqe_resource_id_SHIFT 16
279#define lpfc_eqe_resource_id_MASK 0x000000FF
280#define lpfc_eqe_resource_id_WORD word0
281#define lpfc_eqe_minor_code_SHIFT 4
282#define lpfc_eqe_minor_code_MASK 0x00000FFF
283#define lpfc_eqe_minor_code_WORD word0
284#define lpfc_eqe_major_code_SHIFT 1
285#define lpfc_eqe_major_code_MASK 0x00000007
286#define lpfc_eqe_major_code_WORD word0
287#define lpfc_eqe_valid_SHIFT 0
288#define lpfc_eqe_valid_MASK 0x00000001
289#define lpfc_eqe_valid_WORD word0
290};
291
292/* completion queue entry structure (common fields for all cqe types) */
293struct lpfc_cqe {
294 uint32_t reserved0;
295 uint32_t reserved1;
296 uint32_t reserved2;
297 uint32_t word3;
298#define lpfc_cqe_valid_SHIFT 31
299#define lpfc_cqe_valid_MASK 0x00000001
300#define lpfc_cqe_valid_WORD word3
301#define lpfc_cqe_code_SHIFT 16
302#define lpfc_cqe_code_MASK 0x000000FF
303#define lpfc_cqe_code_WORD word3
304};
305
306/* Completion Queue Entry Status Codes */
307#define CQE_STATUS_SUCCESS 0x0
308#define CQE_STATUS_FCP_RSP_FAILURE 0x1
309#define CQE_STATUS_REMOTE_STOP 0x2
310#define CQE_STATUS_LOCAL_REJECT 0x3
311#define CQE_STATUS_NPORT_RJT 0x4
312#define CQE_STATUS_FABRIC_RJT 0x5
313#define CQE_STATUS_NPORT_BSY 0x6
314#define CQE_STATUS_FABRIC_BSY 0x7
315#define CQE_STATUS_INTERMED_RSP 0x8
316#define CQE_STATUS_LS_RJT 0x9
317#define CQE_STATUS_CMD_REJECT 0xb
318#define CQE_STATUS_FCP_TGT_LENCHECK 0xc
319#define CQE_STATUS_NEED_BUFF_ENTRY 0xf
320#define CQE_STATUS_DI_ERROR 0x16
321
322/* Used when mapping CQE status to IOCB */
323#define LPFC_IOCB_STATUS_MASK 0xf
324
325/* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
326#define CQE_HW_STATUS_NO_ERR 0x0
327#define CQE_HW_STATUS_UNDERRUN 0x1
328#define CQE_HW_STATUS_OVERRUN 0x2
329
330/* Completion Queue Entry Codes */
331#define CQE_CODE_COMPL_WQE 0x1
332#define CQE_CODE_RELEASE_WQE 0x2
333#define CQE_CODE_RECEIVE 0x4
334#define CQE_CODE_XRI_ABORTED 0x5
335#define CQE_CODE_RECEIVE_V1 0x9
336
337/*
338 * Define mask value for xri_aborted and wcqe completed CQE extended status.
339 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
340 */
341#define WCQE_PARAM_MASK 0x1FF;
342
343/* completion queue entry for wqe completions */
344struct lpfc_wcqe_complete {
345 uint32_t word0;
346#define lpfc_wcqe_c_request_tag_SHIFT 16
347#define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
348#define lpfc_wcqe_c_request_tag_WORD word0
349#define lpfc_wcqe_c_status_SHIFT 8
350#define lpfc_wcqe_c_status_MASK 0x000000FF
351#define lpfc_wcqe_c_status_WORD word0
352#define lpfc_wcqe_c_hw_status_SHIFT 0
353#define lpfc_wcqe_c_hw_status_MASK 0x000000FF
354#define lpfc_wcqe_c_hw_status_WORD word0
355 uint32_t total_data_placed;
356 uint32_t parameter;
357#define lpfc_wcqe_c_bg_edir_SHIFT 5
358#define lpfc_wcqe_c_bg_edir_MASK 0x00000001
359#define lpfc_wcqe_c_bg_edir_WORD parameter
360#define lpfc_wcqe_c_bg_tdpv_SHIFT 3
361#define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
362#define lpfc_wcqe_c_bg_tdpv_WORD parameter
363#define lpfc_wcqe_c_bg_re_SHIFT 2
364#define lpfc_wcqe_c_bg_re_MASK 0x00000001
365#define lpfc_wcqe_c_bg_re_WORD parameter
366#define lpfc_wcqe_c_bg_ae_SHIFT 1
367#define lpfc_wcqe_c_bg_ae_MASK 0x00000001
368#define lpfc_wcqe_c_bg_ae_WORD parameter
369#define lpfc_wcqe_c_bg_ge_SHIFT 0
370#define lpfc_wcqe_c_bg_ge_MASK 0x00000001
371#define lpfc_wcqe_c_bg_ge_WORD parameter
372 uint32_t word3;
373#define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT
374#define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK
375#define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD
376#define lpfc_wcqe_c_xb_SHIFT 28
377#define lpfc_wcqe_c_xb_MASK 0x00000001
378#define lpfc_wcqe_c_xb_WORD word3
379#define lpfc_wcqe_c_pv_SHIFT 27
380#define lpfc_wcqe_c_pv_MASK 0x00000001
381#define lpfc_wcqe_c_pv_WORD word3
382#define lpfc_wcqe_c_priority_SHIFT 24
383#define lpfc_wcqe_c_priority_MASK 0x00000007
384#define lpfc_wcqe_c_priority_WORD word3
385#define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT
386#define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK
387#define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD
388};
389
390/* completion queue entry for wqe release */
391struct lpfc_wcqe_release {
392 uint32_t reserved0;
393 uint32_t reserved1;
394 uint32_t word2;
395#define lpfc_wcqe_r_wq_id_SHIFT 16
396#define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
397#define lpfc_wcqe_r_wq_id_WORD word2
398#define lpfc_wcqe_r_wqe_index_SHIFT 0
399#define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
400#define lpfc_wcqe_r_wqe_index_WORD word2
401 uint32_t word3;
402#define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT
403#define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK
404#define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD
405#define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT
406#define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK
407#define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD
408};
409
410struct sli4_wcqe_xri_aborted {
411 uint32_t word0;
412#define lpfc_wcqe_xa_status_SHIFT 8
413#define lpfc_wcqe_xa_status_MASK 0x000000FF
414#define lpfc_wcqe_xa_status_WORD word0
415 uint32_t parameter;
416 uint32_t word2;
417#define lpfc_wcqe_xa_remote_xid_SHIFT 16
418#define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
419#define lpfc_wcqe_xa_remote_xid_WORD word2
420#define lpfc_wcqe_xa_xri_SHIFT 0
421#define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
422#define lpfc_wcqe_xa_xri_WORD word2
423 uint32_t word3;
424#define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT
425#define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK
426#define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD
427#define lpfc_wcqe_xa_ia_SHIFT 30
428#define lpfc_wcqe_xa_ia_MASK 0x00000001
429#define lpfc_wcqe_xa_ia_WORD word3
430#define CQE_XRI_ABORTED_IA_REMOTE 0
431#define CQE_XRI_ABORTED_IA_LOCAL 1
432#define lpfc_wcqe_xa_br_SHIFT 29
433#define lpfc_wcqe_xa_br_MASK 0x00000001
434#define lpfc_wcqe_xa_br_WORD word3
435#define CQE_XRI_ABORTED_BR_BA_ACC 0
436#define CQE_XRI_ABORTED_BR_BA_RJT 1
437#define lpfc_wcqe_xa_eo_SHIFT 28
438#define lpfc_wcqe_xa_eo_MASK 0x00000001
439#define lpfc_wcqe_xa_eo_WORD word3
440#define CQE_XRI_ABORTED_EO_REMOTE 0
441#define CQE_XRI_ABORTED_EO_LOCAL 1
442#define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT
443#define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK
444#define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD
445};
446
447/* completion queue entry structure for rqe completion */
448struct lpfc_rcqe {
449 uint32_t word0;
450#define lpfc_rcqe_bindex_SHIFT 16
451#define lpfc_rcqe_bindex_MASK 0x0000FFF
452#define lpfc_rcqe_bindex_WORD word0
453#define lpfc_rcqe_status_SHIFT 8
454#define lpfc_rcqe_status_MASK 0x000000FF
455#define lpfc_rcqe_status_WORD word0
456#define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
457#define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
458#define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
459#define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
460 uint32_t word1;
461#define lpfc_rcqe_fcf_id_v1_SHIFT 0
462#define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
463#define lpfc_rcqe_fcf_id_v1_WORD word1
464 uint32_t word2;
465#define lpfc_rcqe_length_SHIFT 16
466#define lpfc_rcqe_length_MASK 0x0000FFFF
467#define lpfc_rcqe_length_WORD word2
468#define lpfc_rcqe_rq_id_SHIFT 6
469#define lpfc_rcqe_rq_id_MASK 0x000003FF
470#define lpfc_rcqe_rq_id_WORD word2
471#define lpfc_rcqe_fcf_id_SHIFT 0
472#define lpfc_rcqe_fcf_id_MASK 0x0000003F
473#define lpfc_rcqe_fcf_id_WORD word2
474#define lpfc_rcqe_rq_id_v1_SHIFT 0
475#define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
476#define lpfc_rcqe_rq_id_v1_WORD word2
477 uint32_t word3;
478#define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT
479#define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK
480#define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD
481#define lpfc_rcqe_port_SHIFT 30
482#define lpfc_rcqe_port_MASK 0x00000001
483#define lpfc_rcqe_port_WORD word3
484#define lpfc_rcqe_hdr_length_SHIFT 24
485#define lpfc_rcqe_hdr_length_MASK 0x0000001F
486#define lpfc_rcqe_hdr_length_WORD word3
487#define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT
488#define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK
489#define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD
490#define lpfc_rcqe_eof_SHIFT 8
491#define lpfc_rcqe_eof_MASK 0x000000FF
492#define lpfc_rcqe_eof_WORD word3
493#define FCOE_EOFn 0x41
494#define FCOE_EOFt 0x42
495#define FCOE_EOFni 0x49
496#define FCOE_EOFa 0x50
497#define lpfc_rcqe_sof_SHIFT 0
498#define lpfc_rcqe_sof_MASK 0x000000FF
499#define lpfc_rcqe_sof_WORD word3
500#define FCOE_SOFi2 0x2d
501#define FCOE_SOFi3 0x2e
502#define FCOE_SOFn2 0x35
503#define FCOE_SOFn3 0x36
504};
505
506struct lpfc_rqe {
507 uint32_t address_hi;
508 uint32_t address_lo;
509};
510
511/* buffer descriptors */
512struct lpfc_bde4 {
513 uint32_t addr_hi;
514 uint32_t addr_lo;
515 uint32_t word2;
516#define lpfc_bde4_last_SHIFT 31
517#define lpfc_bde4_last_MASK 0x00000001
518#define lpfc_bde4_last_WORD word2
519#define lpfc_bde4_sge_offset_SHIFT 0
520#define lpfc_bde4_sge_offset_MASK 0x000003FF
521#define lpfc_bde4_sge_offset_WORD word2
522 uint32_t word3;
523#define lpfc_bde4_length_SHIFT 0
524#define lpfc_bde4_length_MASK 0x000000FF
525#define lpfc_bde4_length_WORD word3
526};
527
528struct lpfc_register {
529 uint32_t word0;
530};
531
532/* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
533#define LPFC_UERR_STATUS_HI 0x00A4
534#define LPFC_UERR_STATUS_LO 0x00A0
535#define LPFC_UE_MASK_HI 0x00AC
536#define LPFC_UE_MASK_LO 0x00A8
537
538/* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
539#define LPFC_SLI_INTF 0x0058
540
541#define LPFC_CTL_PORT_SEM_OFFSET 0x400
542#define lpfc_port_smphr_perr_SHIFT 31
543#define lpfc_port_smphr_perr_MASK 0x1
544#define lpfc_port_smphr_perr_WORD word0
545#define lpfc_port_smphr_sfi_SHIFT 30
546#define lpfc_port_smphr_sfi_MASK 0x1
547#define lpfc_port_smphr_sfi_WORD word0
548#define lpfc_port_smphr_nip_SHIFT 29
549#define lpfc_port_smphr_nip_MASK 0x1
550#define lpfc_port_smphr_nip_WORD word0
551#define lpfc_port_smphr_ipc_SHIFT 28
552#define lpfc_port_smphr_ipc_MASK 0x1
553#define lpfc_port_smphr_ipc_WORD word0
554#define lpfc_port_smphr_scr1_SHIFT 27
555#define lpfc_port_smphr_scr1_MASK 0x1
556#define lpfc_port_smphr_scr1_WORD word0
557#define lpfc_port_smphr_scr2_SHIFT 26
558#define lpfc_port_smphr_scr2_MASK 0x1
559#define lpfc_port_smphr_scr2_WORD word0
560#define lpfc_port_smphr_host_scratch_SHIFT 16
561#define lpfc_port_smphr_host_scratch_MASK 0xFF
562#define lpfc_port_smphr_host_scratch_WORD word0
563#define lpfc_port_smphr_port_status_SHIFT 0
564#define lpfc_port_smphr_port_status_MASK 0xFFFF
565#define lpfc_port_smphr_port_status_WORD word0
566
567#define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
568#define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
569#define LPFC_POST_STAGE_HOST_RDY 0x0002
570#define LPFC_POST_STAGE_BE_RESET 0x0003
571#define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
572#define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
573#define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
574#define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
575#define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
576#define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
577#define LPFC_POST_STAGE_DDR_TEST_START 0x0400
578#define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
579#define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
580#define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
581#define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
582#define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
583#define LPFC_POST_STAGE_ARMFW_START 0x0800
584#define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
585#define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
586#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
587#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
588#define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
589#define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
590#define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
591#define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
592#define LPFC_POST_STAGE_PARSE_XML 0x0B04
593#define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
594#define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
595#define LPFC_POST_STAGE_RC_DONE 0x0B07
596#define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
597#define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
598#define LPFC_POST_STAGE_PORT_READY 0xC000
599#define LPFC_POST_STAGE_PORT_UE 0xF000
600
601#define LPFC_CTL_PORT_STA_OFFSET 0x404
602#define lpfc_sliport_status_err_SHIFT 31
603#define lpfc_sliport_status_err_MASK 0x1
604#define lpfc_sliport_status_err_WORD word0
605#define lpfc_sliport_status_end_SHIFT 30
606#define lpfc_sliport_status_end_MASK 0x1
607#define lpfc_sliport_status_end_WORD word0
608#define lpfc_sliport_status_oti_SHIFT 29
609#define lpfc_sliport_status_oti_MASK 0x1
610#define lpfc_sliport_status_oti_WORD word0
611#define lpfc_sliport_status_rn_SHIFT 24
612#define lpfc_sliport_status_rn_MASK 0x1
613#define lpfc_sliport_status_rn_WORD word0
614#define lpfc_sliport_status_rdy_SHIFT 23
615#define lpfc_sliport_status_rdy_MASK 0x1
616#define lpfc_sliport_status_rdy_WORD word0
617#define MAX_IF_TYPE_2_RESETS 1000
618
619#define LPFC_CTL_PORT_CTL_OFFSET 0x408
620#define lpfc_sliport_ctrl_end_SHIFT 30
621#define lpfc_sliport_ctrl_end_MASK 0x1
622#define lpfc_sliport_ctrl_end_WORD word0
623#define LPFC_SLIPORT_LITTLE_ENDIAN 0
624#define LPFC_SLIPORT_BIG_ENDIAN 1
625#define lpfc_sliport_ctrl_ip_SHIFT 27
626#define lpfc_sliport_ctrl_ip_MASK 0x1
627#define lpfc_sliport_ctrl_ip_WORD word0
628#define LPFC_SLIPORT_INIT_PORT 1
629
630#define LPFC_CTL_PORT_ER1_OFFSET 0x40C
631#define LPFC_CTL_PORT_ER2_OFFSET 0x410
632
633/* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
634 * reside in BAR 2.
635 */
636#define LPFC_SLIPORT_IF0_SMPHR 0x00AC
637
638#define LPFC_IMR_MASK_ALL 0xFFFFFFFF
639#define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
640
641#define LPFC_HST_ISR0 0x0C18
642#define LPFC_HST_ISR1 0x0C1C
643#define LPFC_HST_ISR2 0x0C20
644#define LPFC_HST_ISR3 0x0C24
645#define LPFC_HST_ISR4 0x0C28
646
647#define LPFC_HST_IMR0 0x0C48
648#define LPFC_HST_IMR1 0x0C4C
649#define LPFC_HST_IMR2 0x0C50
650#define LPFC_HST_IMR3 0x0C54
651#define LPFC_HST_IMR4 0x0C58
652
653#define LPFC_HST_ISCR0 0x0C78
654#define LPFC_HST_ISCR1 0x0C7C
655#define LPFC_HST_ISCR2 0x0C80
656#define LPFC_HST_ISCR3 0x0C84
657#define LPFC_HST_ISCR4 0x0C88
658
659#define LPFC_SLI4_INTR0 BIT0
660#define LPFC_SLI4_INTR1 BIT1
661#define LPFC_SLI4_INTR2 BIT2
662#define LPFC_SLI4_INTR3 BIT3
663#define LPFC_SLI4_INTR4 BIT4
664#define LPFC_SLI4_INTR5 BIT5
665#define LPFC_SLI4_INTR6 BIT6
666#define LPFC_SLI4_INTR7 BIT7
667#define LPFC_SLI4_INTR8 BIT8
668#define LPFC_SLI4_INTR9 BIT9
669#define LPFC_SLI4_INTR10 BIT10
670#define LPFC_SLI4_INTR11 BIT11
671#define LPFC_SLI4_INTR12 BIT12
672#define LPFC_SLI4_INTR13 BIT13
673#define LPFC_SLI4_INTR14 BIT14
674#define LPFC_SLI4_INTR15 BIT15
675#define LPFC_SLI4_INTR16 BIT16
676#define LPFC_SLI4_INTR17 BIT17
677#define LPFC_SLI4_INTR18 BIT18
678#define LPFC_SLI4_INTR19 BIT19
679#define LPFC_SLI4_INTR20 BIT20
680#define LPFC_SLI4_INTR21 BIT21
681#define LPFC_SLI4_INTR22 BIT22
682#define LPFC_SLI4_INTR23 BIT23
683#define LPFC_SLI4_INTR24 BIT24
684#define LPFC_SLI4_INTR25 BIT25
685#define LPFC_SLI4_INTR26 BIT26
686#define LPFC_SLI4_INTR27 BIT27
687#define LPFC_SLI4_INTR28 BIT28
688#define LPFC_SLI4_INTR29 BIT29
689#define LPFC_SLI4_INTR30 BIT30
690#define LPFC_SLI4_INTR31 BIT31
691
692/*
693 * The Doorbell registers defined here exist in different BAR
694 * register sets depending on the UCNA Port's reported if_type
695 * value. For UCNA ports running SLI4 and if_type 0, they reside in
696 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in
697 * BAR0. The offsets are the same so the driver must account for
698 * any base address difference.
699 */
700#define LPFC_RQ_DOORBELL 0x00A0
701#define lpfc_rq_doorbell_num_posted_SHIFT 16
702#define lpfc_rq_doorbell_num_posted_MASK 0x3FFF
703#define lpfc_rq_doorbell_num_posted_WORD word0
704#define lpfc_rq_doorbell_id_SHIFT 0
705#define lpfc_rq_doorbell_id_MASK 0xFFFF
706#define lpfc_rq_doorbell_id_WORD word0
707
708#define LPFC_WQ_DOORBELL 0x0040
709#define lpfc_wq_doorbell_num_posted_SHIFT 24
710#define lpfc_wq_doorbell_num_posted_MASK 0x00FF
711#define lpfc_wq_doorbell_num_posted_WORD word0
712#define lpfc_wq_doorbell_index_SHIFT 16
713#define lpfc_wq_doorbell_index_MASK 0x00FF
714#define lpfc_wq_doorbell_index_WORD word0
715#define lpfc_wq_doorbell_id_SHIFT 0
716#define lpfc_wq_doorbell_id_MASK 0xFFFF
717#define lpfc_wq_doorbell_id_WORD word0
718
719#define LPFC_EQCQ_DOORBELL 0x0120
720#define lpfc_eqcq_doorbell_se_SHIFT 31
721#define lpfc_eqcq_doorbell_se_MASK 0x0001
722#define lpfc_eqcq_doorbell_se_WORD word0
723#define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
724#define LPFC_EQCQ_SOLICIT_ENABLE_ON 1
725#define lpfc_eqcq_doorbell_arm_SHIFT 29
726#define lpfc_eqcq_doorbell_arm_MASK 0x0001
727#define lpfc_eqcq_doorbell_arm_WORD word0
728#define lpfc_eqcq_doorbell_num_released_SHIFT 16
729#define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
730#define lpfc_eqcq_doorbell_num_released_WORD word0
731#define lpfc_eqcq_doorbell_qt_SHIFT 10
732#define lpfc_eqcq_doorbell_qt_MASK 0x0001
733#define lpfc_eqcq_doorbell_qt_WORD word0
734#define LPFC_QUEUE_TYPE_COMPLETION 0
735#define LPFC_QUEUE_TYPE_EVENT 1
736#define lpfc_eqcq_doorbell_eqci_SHIFT 9
737#define lpfc_eqcq_doorbell_eqci_MASK 0x0001
738#define lpfc_eqcq_doorbell_eqci_WORD word0
739#define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
740#define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
741#define lpfc_eqcq_doorbell_cqid_lo_WORD word0
742#define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11
743#define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
744#define lpfc_eqcq_doorbell_cqid_hi_WORD word0
745#define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
746#define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
747#define lpfc_eqcq_doorbell_eqid_lo_WORD word0
748#define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11
749#define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
750#define lpfc_eqcq_doorbell_eqid_hi_WORD word0
751#define LPFC_CQID_HI_FIELD_SHIFT 10
752#define LPFC_EQID_HI_FIELD_SHIFT 9
753
754#define LPFC_BMBX 0x0160
755#define lpfc_bmbx_addr_SHIFT 2
756#define lpfc_bmbx_addr_MASK 0x3FFFFFFF
757#define lpfc_bmbx_addr_WORD word0
758#define lpfc_bmbx_hi_SHIFT 1
759#define lpfc_bmbx_hi_MASK 0x0001
760#define lpfc_bmbx_hi_WORD word0
761#define lpfc_bmbx_rdy_SHIFT 0
762#define lpfc_bmbx_rdy_MASK 0x0001
763#define lpfc_bmbx_rdy_WORD word0
764
765#define LPFC_MQ_DOORBELL 0x0140
766#define lpfc_mq_doorbell_num_posted_SHIFT 16
767#define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
768#define lpfc_mq_doorbell_num_posted_WORD word0
769#define lpfc_mq_doorbell_id_SHIFT 0
770#define lpfc_mq_doorbell_id_MASK 0xFFFF
771#define lpfc_mq_doorbell_id_WORD word0
772
773struct lpfc_sli4_cfg_mhdr {
774 uint32_t word1;
775#define lpfc_mbox_hdr_emb_SHIFT 0
776#define lpfc_mbox_hdr_emb_MASK 0x00000001
777#define lpfc_mbox_hdr_emb_WORD word1
778#define lpfc_mbox_hdr_sge_cnt_SHIFT 3
779#define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
780#define lpfc_mbox_hdr_sge_cnt_WORD word1
781 uint32_t payload_length;
782 uint32_t tag_lo;
783 uint32_t tag_hi;
784 uint32_t reserved5;
785};
786
787union lpfc_sli4_cfg_shdr {
788 struct {
789 uint32_t word6;
790#define lpfc_mbox_hdr_opcode_SHIFT 0
791#define lpfc_mbox_hdr_opcode_MASK 0x000000FF
792#define lpfc_mbox_hdr_opcode_WORD word6
793#define lpfc_mbox_hdr_subsystem_SHIFT 8
794#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
795#define lpfc_mbox_hdr_subsystem_WORD word6
796#define lpfc_mbox_hdr_port_number_SHIFT 16
797#define lpfc_mbox_hdr_port_number_MASK 0x000000FF
798#define lpfc_mbox_hdr_port_number_WORD word6
799#define lpfc_mbox_hdr_domain_SHIFT 24
800#define lpfc_mbox_hdr_domain_MASK 0x000000FF
801#define lpfc_mbox_hdr_domain_WORD word6
802 uint32_t timeout;
803 uint32_t request_length;
804 uint32_t word9;
805#define lpfc_mbox_hdr_version_SHIFT 0
806#define lpfc_mbox_hdr_version_MASK 0x000000FF
807#define lpfc_mbox_hdr_version_WORD word9
808#define lpfc_mbox_hdr_pf_num_SHIFT 16
809#define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
810#define lpfc_mbox_hdr_pf_num_WORD word9
811#define lpfc_mbox_hdr_vh_num_SHIFT 24
812#define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
813#define lpfc_mbox_hdr_vh_num_WORD word9
814#define LPFC_Q_CREATE_VERSION_2 2
815#define LPFC_Q_CREATE_VERSION_1 1
816#define LPFC_Q_CREATE_VERSION_0 0
817#define LPFC_OPCODE_VERSION_0 0
818#define LPFC_OPCODE_VERSION_1 1
819 } request;
820 struct {
821 uint32_t word6;
822#define lpfc_mbox_hdr_opcode_SHIFT 0
823#define lpfc_mbox_hdr_opcode_MASK 0x000000FF
824#define lpfc_mbox_hdr_opcode_WORD word6
825#define lpfc_mbox_hdr_subsystem_SHIFT 8
826#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
827#define lpfc_mbox_hdr_subsystem_WORD word6
828#define lpfc_mbox_hdr_domain_SHIFT 24
829#define lpfc_mbox_hdr_domain_MASK 0x000000FF
830#define lpfc_mbox_hdr_domain_WORD word6
831 uint32_t word7;
832#define lpfc_mbox_hdr_status_SHIFT 0
833#define lpfc_mbox_hdr_status_MASK 0x000000FF
834#define lpfc_mbox_hdr_status_WORD word7
835#define lpfc_mbox_hdr_add_status_SHIFT 8
836#define lpfc_mbox_hdr_add_status_MASK 0x000000FF
837#define lpfc_mbox_hdr_add_status_WORD word7
838 uint32_t response_length;
839 uint32_t actual_response_length;
840 } response;
841};
842
843/* Mailbox Header structures.
844 * struct mbox_header is defined for first generation SLI4_CFG mailbox
845 * calls deployed for BE-based ports.
846 *
847 * struct sli4_mbox_header is defined for second generation SLI4
848 * ports that don't deploy the SLI4_CFG mechanism.
849 */
850struct mbox_header {
851 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
852 union lpfc_sli4_cfg_shdr cfg_shdr;
853};
854
855#define LPFC_EXTENT_LOCAL 0
856#define LPFC_TIMEOUT_DEFAULT 0
857#define LPFC_EXTENT_VERSION_DEFAULT 0
858
859/* Subsystem Definitions */
860#define LPFC_MBOX_SUBSYSTEM_NA 0x0
861#define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
862#define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
863
864/* Device Specific Definitions */
865
866/* The HOST ENDIAN defines are in Big Endian format. */
867#define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
868#define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
869
870/* Common Opcodes */
871#define LPFC_MBOX_OPCODE_NA 0x00
872#define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
873#define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
874#define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
875#define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
876#define LPFC_MBOX_OPCODE_NOP 0x21
877#define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
878#define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
879#define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
880#define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
881#define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
882#define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
883#define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
884#define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
885#define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
886#define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
887#define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
888#define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
889#define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
890#define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
891#define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
892#define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
893#define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
894#define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
895#define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
896#define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
897#define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
898#define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
899
900/* FCoE Opcodes */
901#define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
902#define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
903#define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
904#define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
905#define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
906#define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
907#define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
908#define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
909#define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
910#define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
911#define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
912#define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
913#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
914#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
915
916/* Mailbox command structures */
917struct eq_context {
918 uint32_t word0;
919#define lpfc_eq_context_size_SHIFT 31
920#define lpfc_eq_context_size_MASK 0x00000001
921#define lpfc_eq_context_size_WORD word0
922#define LPFC_EQE_SIZE_4 0x0
923#define LPFC_EQE_SIZE_16 0x1
924#define lpfc_eq_context_valid_SHIFT 29
925#define lpfc_eq_context_valid_MASK 0x00000001
926#define lpfc_eq_context_valid_WORD word0
927 uint32_t word1;
928#define lpfc_eq_context_count_SHIFT 26
929#define lpfc_eq_context_count_MASK 0x00000003
930#define lpfc_eq_context_count_WORD word1
931#define LPFC_EQ_CNT_256 0x0
932#define LPFC_EQ_CNT_512 0x1
933#define LPFC_EQ_CNT_1024 0x2
934#define LPFC_EQ_CNT_2048 0x3
935#define LPFC_EQ_CNT_4096 0x4
936 uint32_t word2;
937#define lpfc_eq_context_delay_multi_SHIFT 13
938#define lpfc_eq_context_delay_multi_MASK 0x000003FF
939#define lpfc_eq_context_delay_multi_WORD word2
940 uint32_t reserved3;
941};
942
943struct sgl_page_pairs {
944 uint32_t sgl_pg0_addr_lo;
945 uint32_t sgl_pg0_addr_hi;
946 uint32_t sgl_pg1_addr_lo;
947 uint32_t sgl_pg1_addr_hi;
948};
949
950struct lpfc_mbx_post_sgl_pages {
951 struct mbox_header header;
952 uint32_t word0;
953#define lpfc_post_sgl_pages_xri_SHIFT 0
954#define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
955#define lpfc_post_sgl_pages_xri_WORD word0
956#define lpfc_post_sgl_pages_xricnt_SHIFT 16
957#define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
958#define lpfc_post_sgl_pages_xricnt_WORD word0
959 struct sgl_page_pairs sgl_pg_pairs[1];
960};
961
962/* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
963struct lpfc_mbx_post_uembed_sgl_page1 {
964 union lpfc_sli4_cfg_shdr cfg_shdr;
965 uint32_t word0;
966 struct sgl_page_pairs sgl_pg_pairs;
967};
968
969struct lpfc_mbx_sge {
970 uint32_t pa_lo;
971 uint32_t pa_hi;
972 uint32_t length;
973};
974
975struct lpfc_mbx_nembed_cmd {
976 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
977#define LPFC_SLI4_MBX_SGE_MAX_PAGES 19
978 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
979};
980
981struct lpfc_mbx_nembed_sge_virt {
982 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
983};
984
985struct lpfc_mbx_eq_create {
986 struct mbox_header header;
987 union {
988 struct {
989 uint32_t word0;
990#define lpfc_mbx_eq_create_num_pages_SHIFT 0
991#define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
992#define lpfc_mbx_eq_create_num_pages_WORD word0
993 struct eq_context context;
994 struct dma_address page[LPFC_MAX_EQ_PAGE];
995 } request;
996 struct {
997 uint32_t word0;
998#define lpfc_mbx_eq_create_q_id_SHIFT 0
999#define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1000#define lpfc_mbx_eq_create_q_id_WORD word0
1001 } response;
1002 } u;
1003};
1004
1005struct lpfc_mbx_eq_destroy {
1006 struct mbox_header header;
1007 union {
1008 struct {
1009 uint32_t word0;
1010#define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1011#define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1012#define lpfc_mbx_eq_destroy_q_id_WORD word0
1013 } request;
1014 struct {
1015 uint32_t word0;
1016 } response;
1017 } u;
1018};
1019
1020struct lpfc_mbx_nop {
1021 struct mbox_header header;
1022 uint32_t context[2];
1023};
1024
1025struct cq_context {
1026 uint32_t word0;
1027#define lpfc_cq_context_event_SHIFT 31
1028#define lpfc_cq_context_event_MASK 0x00000001
1029#define lpfc_cq_context_event_WORD word0
1030#define lpfc_cq_context_valid_SHIFT 29
1031#define lpfc_cq_context_valid_MASK 0x00000001
1032#define lpfc_cq_context_valid_WORD word0
1033#define lpfc_cq_context_count_SHIFT 27
1034#define lpfc_cq_context_count_MASK 0x00000003
1035#define lpfc_cq_context_count_WORD word0
1036#define LPFC_CQ_CNT_256 0x0
1037#define LPFC_CQ_CNT_512 0x1
1038#define LPFC_CQ_CNT_1024 0x2
1039 uint32_t word1;
1040#define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1041#define lpfc_cq_eq_id_MASK 0x000000FF
1042#define lpfc_cq_eq_id_WORD word1
1043#define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1044#define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1045#define lpfc_cq_eq_id_2_WORD word1
1046 uint32_t reserved0;
1047 uint32_t reserved1;
1048};
1049
1050struct lpfc_mbx_cq_create {
1051 struct mbox_header header;
1052 union {
1053 struct {
1054 uint32_t word0;
1055#define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */
1056#define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1057#define lpfc_mbx_cq_create_page_size_WORD word0
1058#define lpfc_mbx_cq_create_num_pages_SHIFT 0
1059#define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1060#define lpfc_mbx_cq_create_num_pages_WORD word0
1061 struct cq_context context;
1062 struct dma_address page[LPFC_MAX_CQ_PAGE];
1063 } request;
1064 struct {
1065 uint32_t word0;
1066#define lpfc_mbx_cq_create_q_id_SHIFT 0
1067#define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1068#define lpfc_mbx_cq_create_q_id_WORD word0
1069 } response;
1070 } u;
1071};
1072
1073struct lpfc_mbx_cq_destroy {
1074 struct mbox_header header;
1075 union {
1076 struct {
1077 uint32_t word0;
1078#define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1079#define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1080#define lpfc_mbx_cq_destroy_q_id_WORD word0
1081 } request;
1082 struct {
1083 uint32_t word0;
1084 } response;
1085 } u;
1086};
1087
1088struct wq_context {
1089 uint32_t reserved0;
1090 uint32_t reserved1;
1091 uint32_t reserved2;
1092 uint32_t reserved3;
1093};
1094
1095struct lpfc_mbx_wq_create {
1096 struct mbox_header header;
1097 union {
1098 struct { /* Version 0 Request */
1099 uint32_t word0;
1100#define lpfc_mbx_wq_create_num_pages_SHIFT 0
1101#define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF
1102#define lpfc_mbx_wq_create_num_pages_WORD word0
1103#define lpfc_mbx_wq_create_cq_id_SHIFT 16
1104#define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1105#define lpfc_mbx_wq_create_cq_id_WORD word0
1106 struct dma_address page[LPFC_MAX_WQ_PAGE];
1107 } request;
1108 struct { /* Version 1 Request */
1109 uint32_t word0; /* Word 0 is the same as in v0 */
1110 uint32_t word1;
1111#define lpfc_mbx_wq_create_page_size_SHIFT 0
1112#define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1113#define lpfc_mbx_wq_create_page_size_WORD word1
1114#define lpfc_mbx_wq_create_wqe_size_SHIFT 8
1115#define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1116#define lpfc_mbx_wq_create_wqe_size_WORD word1
1117#define LPFC_WQ_WQE_SIZE_64 0x5
1118#define LPFC_WQ_WQE_SIZE_128 0x6
1119#define lpfc_mbx_wq_create_wqe_count_SHIFT 16
1120#define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1121#define lpfc_mbx_wq_create_wqe_count_WORD word1
1122 uint32_t word2;
1123 struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1124 } request_1;
1125 struct {
1126 uint32_t word0;
1127#define lpfc_mbx_wq_create_q_id_SHIFT 0
1128#define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1129#define lpfc_mbx_wq_create_q_id_WORD word0
1130 } response;
1131 } u;
1132};
1133
1134struct lpfc_mbx_wq_destroy {
1135 struct mbox_header header;
1136 union {
1137 struct {
1138 uint32_t word0;
1139#define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1140#define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1141#define lpfc_mbx_wq_destroy_q_id_WORD word0
1142 } request;
1143 struct {
1144 uint32_t word0;
1145 } response;
1146 } u;
1147};
1148
1149#define LPFC_HDR_BUF_SIZE 128
1150#define LPFC_DATA_BUF_SIZE 2048
1151struct rq_context {
1152 uint32_t word0;
1153#define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1154#define lpfc_rq_context_rqe_count_MASK 0x0000000F
1155#define lpfc_rq_context_rqe_count_WORD word0
1156#define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */
1157#define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */
1158#define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */
1159#define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */
1160#define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */
1161#define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1162#define lpfc_rq_context_rqe_count_1_WORD word0
1163#define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */
1164#define lpfc_rq_context_rqe_size_MASK 0x0000000F
1165#define lpfc_rq_context_rqe_size_WORD word0
1166#define LPFC_RQE_SIZE_8 2
1167#define LPFC_RQE_SIZE_16 3
1168#define LPFC_RQE_SIZE_32 4
1169#define LPFC_RQE_SIZE_64 5
1170#define LPFC_RQE_SIZE_128 6
1171#define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1172#define lpfc_rq_context_page_size_MASK 0x000000FF
1173#define lpfc_rq_context_page_size_WORD word0
1174 uint32_t reserved1;
1175 uint32_t word2;
1176#define lpfc_rq_context_cq_id_SHIFT 16
1177#define lpfc_rq_context_cq_id_MASK 0x000003FF
1178#define lpfc_rq_context_cq_id_WORD word2
1179#define lpfc_rq_context_buf_size_SHIFT 0
1180#define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1181#define lpfc_rq_context_buf_size_WORD word2
1182 uint32_t buffer_size; /* Version 1 Only */
1183};
1184
1185struct lpfc_mbx_rq_create {
1186 struct mbox_header header;
1187 union {
1188 struct {
1189 uint32_t word0;
1190#define lpfc_mbx_rq_create_num_pages_SHIFT 0
1191#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1192#define lpfc_mbx_rq_create_num_pages_WORD word0
1193 struct rq_context context;
1194 struct dma_address page[LPFC_MAX_WQ_PAGE];
1195 } request;
1196 struct {
1197 uint32_t word0;
1198#define lpfc_mbx_rq_create_q_id_SHIFT 0
1199#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1200#define lpfc_mbx_rq_create_q_id_WORD word0
1201 } response;
1202 } u;
1203};
1204
1205struct lpfc_mbx_rq_destroy {
1206 struct mbox_header header;
1207 union {
1208 struct {
1209 uint32_t word0;
1210#define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1211#define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1212#define lpfc_mbx_rq_destroy_q_id_WORD word0
1213 } request;
1214 struct {
1215 uint32_t word0;
1216 } response;
1217 } u;
1218};
1219
1220struct mq_context {
1221 uint32_t word0;
1222#define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1223#define lpfc_mq_context_cq_id_MASK 0x000003FF
1224#define lpfc_mq_context_cq_id_WORD word0
1225#define lpfc_mq_context_ring_size_SHIFT 16
1226#define lpfc_mq_context_ring_size_MASK 0x0000000F
1227#define lpfc_mq_context_ring_size_WORD word0
1228#define LPFC_MQ_RING_SIZE_16 0x5
1229#define LPFC_MQ_RING_SIZE_32 0x6
1230#define LPFC_MQ_RING_SIZE_64 0x7
1231#define LPFC_MQ_RING_SIZE_128 0x8
1232 uint32_t word1;
1233#define lpfc_mq_context_valid_SHIFT 31
1234#define lpfc_mq_context_valid_MASK 0x00000001
1235#define lpfc_mq_context_valid_WORD word1
1236 uint32_t reserved2;
1237 uint32_t reserved3;
1238};
1239
1240struct lpfc_mbx_mq_create {
1241 struct mbox_header header;
1242 union {
1243 struct {
1244 uint32_t word0;
1245#define lpfc_mbx_mq_create_num_pages_SHIFT 0
1246#define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1247#define lpfc_mbx_mq_create_num_pages_WORD word0
1248 struct mq_context context;
1249 struct dma_address page[LPFC_MAX_MQ_PAGE];
1250 } request;
1251 struct {
1252 uint32_t word0;
1253#define lpfc_mbx_mq_create_q_id_SHIFT 0
1254#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1255#define lpfc_mbx_mq_create_q_id_WORD word0
1256 } response;
1257 } u;
1258};
1259
1260struct lpfc_mbx_mq_create_ext {
1261 struct mbox_header header;
1262 union {
1263 struct {
1264 uint32_t word0;
1265#define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1266#define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1267#define lpfc_mbx_mq_create_ext_num_pages_WORD word0
1268#define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */
1269#define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1270#define lpfc_mbx_mq_create_ext_cq_id_WORD word0
1271 uint32_t async_evt_bmap;
1272#define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK
1273#define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1274#define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap
1275#define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE
1276#define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1277#define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap
1278#define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5
1279#define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1280#define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap
1281#define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC
1282#define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1283#define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap
1284#define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI
1285#define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1286#define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap
1287 struct mq_context context;
1288 struct dma_address page[LPFC_MAX_MQ_PAGE];
1289 } request;
1290 struct {
1291 uint32_t word0;
1292#define lpfc_mbx_mq_create_q_id_SHIFT 0
1293#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1294#define lpfc_mbx_mq_create_q_id_WORD word0
1295 } response;
1296 } u;
1297#define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1298#define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1299#define LPFC_ASYNC_EVENT_GROUP5 0x20
1300};
1301
1302struct lpfc_mbx_mq_destroy {
1303 struct mbox_header header;
1304 union {
1305 struct {
1306 uint32_t word0;
1307#define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1308#define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1309#define lpfc_mbx_mq_destroy_q_id_WORD word0
1310 } request;
1311 struct {
1312 uint32_t word0;
1313 } response;
1314 } u;
1315};
1316
1317/* Start Gen 2 SLI4 Mailbox definitions: */
1318
1319/* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1320#define LPFC_RSC_TYPE_FCOE_VFI 0x20
1321#define LPFC_RSC_TYPE_FCOE_VPI 0x21
1322#define LPFC_RSC_TYPE_FCOE_RPI 0x22
1323#define LPFC_RSC_TYPE_FCOE_XRI 0x23
1324
1325struct lpfc_mbx_get_rsrc_extent_info {
1326 struct mbox_header header;
1327 union {
1328 struct {
1329 uint32_t word4;
1330#define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1331#define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1332#define lpfc_mbx_get_rsrc_extent_info_type_WORD word4
1333 } req;
1334 struct {
1335 uint32_t word4;
1336#define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1337#define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1338#define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4
1339#define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16
1340#define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1341#define lpfc_mbx_get_rsrc_extent_info_size_WORD word4
1342 } rsp;
1343 } u;
1344};
1345
1346struct lpfc_id_range {
1347 uint32_t word5;
1348#define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1349#define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1350#define lpfc_mbx_rsrc_id_word4_0_WORD word5
1351#define lpfc_mbx_rsrc_id_word4_1_SHIFT 16
1352#define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1353#define lpfc_mbx_rsrc_id_word4_1_WORD word5
1354};
1355
1356struct lpfc_mbx_set_link_diag_state {
1357 struct mbox_header header;
1358 union {
1359 struct {
1360 uint32_t word0;
1361#define lpfc_mbx_set_diag_state_diag_SHIFT 0
1362#define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1363#define lpfc_mbx_set_diag_state_diag_WORD word0
1364#define lpfc_mbx_set_diag_state_link_num_SHIFT 16
1365#define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1366#define lpfc_mbx_set_diag_state_link_num_WORD word0
1367#define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1368#define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1369#define lpfc_mbx_set_diag_state_link_type_WORD word0
1370 } req;
1371 struct {
1372 uint32_t word0;
1373 } rsp;
1374 } u;
1375};
1376
1377struct lpfc_mbx_set_link_diag_loopback {
1378 struct mbox_header header;
1379 union {
1380 struct {
1381 uint32_t word0;
1382#define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1383#define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1384#define lpfc_mbx_set_diag_lpbk_type_WORD word0
1385#define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1386#define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1387#define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1388#define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16
1389#define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1390#define lpfc_mbx_set_diag_lpbk_link_num_WORD word0
1391#define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22
1392#define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1393#define lpfc_mbx_set_diag_lpbk_link_type_WORD word0
1394 } req;
1395 struct {
1396 uint32_t word0;
1397 } rsp;
1398 } u;
1399};
1400
1401struct lpfc_mbx_run_link_diag_test {
1402 struct mbox_header header;
1403 union {
1404 struct {
1405 uint32_t word0;
1406#define lpfc_mbx_run_diag_test_link_num_SHIFT 16
1407#define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1408#define lpfc_mbx_run_diag_test_link_num_WORD word0
1409#define lpfc_mbx_run_diag_test_link_type_SHIFT 22
1410#define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1411#define lpfc_mbx_run_diag_test_link_type_WORD word0
1412 uint32_t word1;
1413#define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1414#define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1415#define lpfc_mbx_run_diag_test_test_id_WORD word1
1416#define lpfc_mbx_run_diag_test_loops_SHIFT 16
1417#define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1418#define lpfc_mbx_run_diag_test_loops_WORD word1
1419 uint32_t word2;
1420#define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1421#define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1422#define lpfc_mbx_run_diag_test_test_ver_WORD word2
1423#define lpfc_mbx_run_diag_test_err_act_SHIFT 16
1424#define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
1425#define lpfc_mbx_run_diag_test_err_act_WORD word2
1426 } req;
1427 struct {
1428 uint32_t word0;
1429 } rsp;
1430 } u;
1431};
1432
1433/*
1434 * struct lpfc_mbx_alloc_rsrc_extents:
1435 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1436 * 6 words of header + 4 words of shared subcommand header +
1437 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1438 *
1439 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1440 * for extents payload.
1441 *
1442 * 212/2 (bytes per extent) = 106 extents.
1443 * 106/2 (extents per word) = 53 words.
1444 * lpfc_id_range id is statically size to 53.
1445 *
1446 * This mailbox definition is used for ALLOC or GET_ALLOCATED
1447 * extent ranges. For ALLOC, the type and cnt are required.
1448 * For GET_ALLOCATED, only the type is required.
1449 */
1450struct lpfc_mbx_alloc_rsrc_extents {
1451 struct mbox_header header;
1452 union {
1453 struct {
1454 uint32_t word4;
1455#define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
1456#define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
1457#define lpfc_mbx_alloc_rsrc_extents_type_WORD word4
1458#define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16
1459#define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
1460#define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4
1461 } req;
1462 struct {
1463 uint32_t word4;
1464#define lpfc_mbx_rsrc_cnt_SHIFT 0
1465#define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
1466#define lpfc_mbx_rsrc_cnt_WORD word4
1467 struct lpfc_id_range id[53];
1468 } rsp;
1469 } u;
1470};
1471
1472/*
1473 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1474 * structure shares the same SHIFT/MASK/WORD defines provided in the
1475 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1476 * the structures defined above. This non-embedded structure provides for the
1477 * maximum number of extents supported by the port.
1478 */
1479struct lpfc_mbx_nembed_rsrc_extent {
1480 union lpfc_sli4_cfg_shdr cfg_shdr;
1481 uint32_t word4;
1482 struct lpfc_id_range id;
1483};
1484
1485struct lpfc_mbx_dealloc_rsrc_extents {
1486 struct mbox_header header;
1487 struct {
1488 uint32_t word4;
1489#define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
1490#define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
1491#define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4
1492 } req;
1493
1494};
1495
1496/* Start SLI4 FCoE specific mbox structures. */
1497
1498struct lpfc_mbx_post_hdr_tmpl {
1499 struct mbox_header header;
1500 uint32_t word10;
1501#define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
1502#define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
1503#define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10
1504#define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16
1505#define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
1506#define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10
1507 uint32_t rpi_paddr_lo;
1508 uint32_t rpi_paddr_hi;
1509};
1510
1511struct sli4_sge { /* SLI-4 */
1512 uint32_t addr_hi;
1513 uint32_t addr_lo;
1514
1515 uint32_t word2;
1516#define lpfc_sli4_sge_offset_SHIFT 0
1517#define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
1518#define lpfc_sli4_sge_offset_WORD word2
1519#define lpfc_sli4_sge_type_SHIFT 27
1520#define lpfc_sli4_sge_type_MASK 0x0000000F
1521#define lpfc_sli4_sge_type_WORD word2
1522#define LPFC_SGE_TYPE_DATA 0x0
1523#define LPFC_SGE_TYPE_DIF 0x4
1524#define LPFC_SGE_TYPE_LSP 0x5
1525#define LPFC_SGE_TYPE_PEDIF 0x6
1526#define LPFC_SGE_TYPE_PESEED 0x7
1527#define LPFC_SGE_TYPE_DISEED 0x8
1528#define LPFC_SGE_TYPE_ENC 0x9
1529#define LPFC_SGE_TYPE_ATM 0xA
1530#define LPFC_SGE_TYPE_SKIP 0xC
1531#define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */
1532#define lpfc_sli4_sge_last_MASK 0x00000001
1533#define lpfc_sli4_sge_last_WORD word2
1534 uint32_t sge_len;
1535};
1536
1537struct sli4_sge_diseed { /* SLI-4 */
1538 uint32_t ref_tag;
1539 uint32_t ref_tag_tran;
1540
1541 uint32_t word2;
1542#define lpfc_sli4_sge_dif_apptran_SHIFT 0
1543#define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
1544#define lpfc_sli4_sge_dif_apptran_WORD word2
1545#define lpfc_sli4_sge_dif_af_SHIFT 24
1546#define lpfc_sli4_sge_dif_af_MASK 0x00000001
1547#define lpfc_sli4_sge_dif_af_WORD word2
1548#define lpfc_sli4_sge_dif_na_SHIFT 25
1549#define lpfc_sli4_sge_dif_na_MASK 0x00000001
1550#define lpfc_sli4_sge_dif_na_WORD word2
1551#define lpfc_sli4_sge_dif_hi_SHIFT 26
1552#define lpfc_sli4_sge_dif_hi_MASK 0x00000001
1553#define lpfc_sli4_sge_dif_hi_WORD word2
1554#define lpfc_sli4_sge_dif_type_SHIFT 27
1555#define lpfc_sli4_sge_dif_type_MASK 0x0000000F
1556#define lpfc_sli4_sge_dif_type_WORD word2
1557#define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */
1558#define lpfc_sli4_sge_dif_last_MASK 0x00000001
1559#define lpfc_sli4_sge_dif_last_WORD word2
1560 uint32_t word3;
1561#define lpfc_sli4_sge_dif_apptag_SHIFT 0
1562#define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
1563#define lpfc_sli4_sge_dif_apptag_WORD word3
1564#define lpfc_sli4_sge_dif_bs_SHIFT 16
1565#define lpfc_sli4_sge_dif_bs_MASK 0x00000007
1566#define lpfc_sli4_sge_dif_bs_WORD word3
1567#define lpfc_sli4_sge_dif_ai_SHIFT 19
1568#define lpfc_sli4_sge_dif_ai_MASK 0x00000001
1569#define lpfc_sli4_sge_dif_ai_WORD word3
1570#define lpfc_sli4_sge_dif_me_SHIFT 20
1571#define lpfc_sli4_sge_dif_me_MASK 0x00000001
1572#define lpfc_sli4_sge_dif_me_WORD word3
1573#define lpfc_sli4_sge_dif_re_SHIFT 21
1574#define lpfc_sli4_sge_dif_re_MASK 0x00000001
1575#define lpfc_sli4_sge_dif_re_WORD word3
1576#define lpfc_sli4_sge_dif_ce_SHIFT 22
1577#define lpfc_sli4_sge_dif_ce_MASK 0x00000001
1578#define lpfc_sli4_sge_dif_ce_WORD word3
1579#define lpfc_sli4_sge_dif_nr_SHIFT 23
1580#define lpfc_sli4_sge_dif_nr_MASK 0x00000001
1581#define lpfc_sli4_sge_dif_nr_WORD word3
1582#define lpfc_sli4_sge_dif_oprx_SHIFT 24
1583#define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
1584#define lpfc_sli4_sge_dif_oprx_WORD word3
1585#define lpfc_sli4_sge_dif_optx_SHIFT 28
1586#define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
1587#define lpfc_sli4_sge_dif_optx_WORD word3
1588/* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
1589};
1590
1591struct fcf_record {
1592 uint32_t max_rcv_size;
1593 uint32_t fka_adv_period;
1594 uint32_t fip_priority;
1595 uint32_t word3;
1596#define lpfc_fcf_record_mac_0_SHIFT 0
1597#define lpfc_fcf_record_mac_0_MASK 0x000000FF
1598#define lpfc_fcf_record_mac_0_WORD word3
1599#define lpfc_fcf_record_mac_1_SHIFT 8
1600#define lpfc_fcf_record_mac_1_MASK 0x000000FF
1601#define lpfc_fcf_record_mac_1_WORD word3
1602#define lpfc_fcf_record_mac_2_SHIFT 16
1603#define lpfc_fcf_record_mac_2_MASK 0x000000FF
1604#define lpfc_fcf_record_mac_2_WORD word3
1605#define lpfc_fcf_record_mac_3_SHIFT 24
1606#define lpfc_fcf_record_mac_3_MASK 0x000000FF
1607#define lpfc_fcf_record_mac_3_WORD word3
1608 uint32_t word4;
1609#define lpfc_fcf_record_mac_4_SHIFT 0
1610#define lpfc_fcf_record_mac_4_MASK 0x000000FF
1611#define lpfc_fcf_record_mac_4_WORD word4
1612#define lpfc_fcf_record_mac_5_SHIFT 8
1613#define lpfc_fcf_record_mac_5_MASK 0x000000FF
1614#define lpfc_fcf_record_mac_5_WORD word4
1615#define lpfc_fcf_record_fcf_avail_SHIFT 16
1616#define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
1617#define lpfc_fcf_record_fcf_avail_WORD word4
1618#define lpfc_fcf_record_mac_addr_prov_SHIFT 24
1619#define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
1620#define lpfc_fcf_record_mac_addr_prov_WORD word4
1621#define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */
1622#define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */
1623 uint32_t word5;
1624#define lpfc_fcf_record_fab_name_0_SHIFT 0
1625#define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
1626#define lpfc_fcf_record_fab_name_0_WORD word5
1627#define lpfc_fcf_record_fab_name_1_SHIFT 8
1628#define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
1629#define lpfc_fcf_record_fab_name_1_WORD word5
1630#define lpfc_fcf_record_fab_name_2_SHIFT 16
1631#define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
1632#define lpfc_fcf_record_fab_name_2_WORD word5
1633#define lpfc_fcf_record_fab_name_3_SHIFT 24
1634#define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
1635#define lpfc_fcf_record_fab_name_3_WORD word5
1636 uint32_t word6;
1637#define lpfc_fcf_record_fab_name_4_SHIFT 0
1638#define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
1639#define lpfc_fcf_record_fab_name_4_WORD word6
1640#define lpfc_fcf_record_fab_name_5_SHIFT 8
1641#define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
1642#define lpfc_fcf_record_fab_name_5_WORD word6
1643#define lpfc_fcf_record_fab_name_6_SHIFT 16
1644#define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
1645#define lpfc_fcf_record_fab_name_6_WORD word6
1646#define lpfc_fcf_record_fab_name_7_SHIFT 24
1647#define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
1648#define lpfc_fcf_record_fab_name_7_WORD word6
1649 uint32_t word7;
1650#define lpfc_fcf_record_fc_map_0_SHIFT 0
1651#define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
1652#define lpfc_fcf_record_fc_map_0_WORD word7
1653#define lpfc_fcf_record_fc_map_1_SHIFT 8
1654#define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
1655#define lpfc_fcf_record_fc_map_1_WORD word7
1656#define lpfc_fcf_record_fc_map_2_SHIFT 16
1657#define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
1658#define lpfc_fcf_record_fc_map_2_WORD word7
1659#define lpfc_fcf_record_fcf_valid_SHIFT 24
1660#define lpfc_fcf_record_fcf_valid_MASK 0x000000FF
1661#define lpfc_fcf_record_fcf_valid_WORD word7
1662 uint32_t word8;
1663#define lpfc_fcf_record_fcf_index_SHIFT 0
1664#define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
1665#define lpfc_fcf_record_fcf_index_WORD word8
1666#define lpfc_fcf_record_fcf_state_SHIFT 16
1667#define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
1668#define lpfc_fcf_record_fcf_state_WORD word8
1669 uint8_t vlan_bitmap[512];
1670 uint32_t word137;
1671#define lpfc_fcf_record_switch_name_0_SHIFT 0
1672#define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
1673#define lpfc_fcf_record_switch_name_0_WORD word137
1674#define lpfc_fcf_record_switch_name_1_SHIFT 8
1675#define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
1676#define lpfc_fcf_record_switch_name_1_WORD word137
1677#define lpfc_fcf_record_switch_name_2_SHIFT 16
1678#define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
1679#define lpfc_fcf_record_switch_name_2_WORD word137
1680#define lpfc_fcf_record_switch_name_3_SHIFT 24
1681#define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
1682#define lpfc_fcf_record_switch_name_3_WORD word137
1683 uint32_t word138;
1684#define lpfc_fcf_record_switch_name_4_SHIFT 0
1685#define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
1686#define lpfc_fcf_record_switch_name_4_WORD word138
1687#define lpfc_fcf_record_switch_name_5_SHIFT 8
1688#define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
1689#define lpfc_fcf_record_switch_name_5_WORD word138
1690#define lpfc_fcf_record_switch_name_6_SHIFT 16
1691#define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
1692#define lpfc_fcf_record_switch_name_6_WORD word138
1693#define lpfc_fcf_record_switch_name_7_SHIFT 24
1694#define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
1695#define lpfc_fcf_record_switch_name_7_WORD word138
1696};
1697
1698struct lpfc_mbx_read_fcf_tbl {
1699 union lpfc_sli4_cfg_shdr cfg_shdr;
1700 union {
1701 struct {
1702 uint32_t word10;
1703#define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
1704#define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
1705#define lpfc_mbx_read_fcf_tbl_indx_WORD word10
1706 } request;
1707 struct {
1708 uint32_t eventag;
1709 } response;
1710 } u;
1711 uint32_t word11;
1712#define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
1713#define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
1714#define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11
1715};
1716
1717struct lpfc_mbx_add_fcf_tbl_entry {
1718 union lpfc_sli4_cfg_shdr cfg_shdr;
1719 uint32_t word10;
1720#define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
1721#define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
1722#define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10
1723 struct lpfc_mbx_sge fcf_sge;
1724};
1725
1726struct lpfc_mbx_del_fcf_tbl_entry {
1727 struct mbox_header header;
1728 uint32_t word10;
1729#define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
1730#define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
1731#define lpfc_mbx_del_fcf_tbl_count_WORD word10
1732#define lpfc_mbx_del_fcf_tbl_index_SHIFT 16
1733#define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
1734#define lpfc_mbx_del_fcf_tbl_index_WORD word10
1735};
1736
1737struct lpfc_mbx_redisc_fcf_tbl {
1738 struct mbox_header header;
1739 uint32_t word10;
1740#define lpfc_mbx_redisc_fcf_count_SHIFT 0
1741#define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
1742#define lpfc_mbx_redisc_fcf_count_WORD word10
1743 uint32_t resvd;
1744 uint32_t word12;
1745#define lpfc_mbx_redisc_fcf_index_SHIFT 0
1746#define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
1747#define lpfc_mbx_redisc_fcf_index_WORD word12
1748};
1749
1750struct lpfc_mbx_query_fw_cfg {
1751 struct mbox_header header;
1752 uint32_t config_number;
1753 uint32_t asic_rev;
1754 uint32_t phys_port;
1755 uint32_t function_mode;
1756/* firmware Function Mode */
1757#define lpfc_function_mode_toe_SHIFT 0
1758#define lpfc_function_mode_toe_MASK 0x00000001
1759#define lpfc_function_mode_toe_WORD function_mode
1760#define lpfc_function_mode_nic_SHIFT 1
1761#define lpfc_function_mode_nic_MASK 0x00000001
1762#define lpfc_function_mode_nic_WORD function_mode
1763#define lpfc_function_mode_rdma_SHIFT 2
1764#define lpfc_function_mode_rdma_MASK 0x00000001
1765#define lpfc_function_mode_rdma_WORD function_mode
1766#define lpfc_function_mode_vm_SHIFT 3
1767#define lpfc_function_mode_vm_MASK 0x00000001
1768#define lpfc_function_mode_vm_WORD function_mode
1769#define lpfc_function_mode_iscsi_i_SHIFT 4
1770#define lpfc_function_mode_iscsi_i_MASK 0x00000001
1771#define lpfc_function_mode_iscsi_i_WORD function_mode
1772#define lpfc_function_mode_iscsi_t_SHIFT 5
1773#define lpfc_function_mode_iscsi_t_MASK 0x00000001
1774#define lpfc_function_mode_iscsi_t_WORD function_mode
1775#define lpfc_function_mode_fcoe_i_SHIFT 6
1776#define lpfc_function_mode_fcoe_i_MASK 0x00000001
1777#define lpfc_function_mode_fcoe_i_WORD function_mode
1778#define lpfc_function_mode_fcoe_t_SHIFT 7
1779#define lpfc_function_mode_fcoe_t_MASK 0x00000001
1780#define lpfc_function_mode_fcoe_t_WORD function_mode
1781#define lpfc_function_mode_dal_SHIFT 8
1782#define lpfc_function_mode_dal_MASK 0x00000001
1783#define lpfc_function_mode_dal_WORD function_mode
1784#define lpfc_function_mode_lro_SHIFT 9
1785#define lpfc_function_mode_lro_MASK 0x00000001
1786#define lpfc_function_mode_lro_WORD function_mode
1787#define lpfc_function_mode_flex10_SHIFT 10
1788#define lpfc_function_mode_flex10_MASK 0x00000001
1789#define lpfc_function_mode_flex10_WORD function_mode
1790#define lpfc_function_mode_ncsi_SHIFT 11
1791#define lpfc_function_mode_ncsi_MASK 0x00000001
1792#define lpfc_function_mode_ncsi_WORD function_mode
1793};
1794
1795/* Status field for embedded SLI_CONFIG mailbox command */
1796#define STATUS_SUCCESS 0x0
1797#define STATUS_FAILED 0x1
1798#define STATUS_ILLEGAL_REQUEST 0x2
1799#define STATUS_ILLEGAL_FIELD 0x3
1800#define STATUS_INSUFFICIENT_BUFFER 0x4
1801#define STATUS_UNAUTHORIZED_REQUEST 0x5
1802#define STATUS_FLASHROM_SAVE_FAILED 0x17
1803#define STATUS_FLASHROM_RESTORE_FAILED 0x18
1804#define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
1805#define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
1806#define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
1807#define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
1808#define STATUS_ASSERT_FAILED 0x1e
1809#define STATUS_INVALID_SESSION 0x1f
1810#define STATUS_INVALID_CONNECTION 0x20
1811#define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
1812#define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
1813#define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
1814#define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
1815#define STATUS_FLASHROM_READ_FAILED 0x27
1816#define STATUS_POLL_IOCTL_TIMEOUT 0x28
1817#define STATUS_ERROR_ACITMAIN 0x2a
1818#define STATUS_REBOOT_REQUIRED 0x2c
1819#define STATUS_FCF_IN_USE 0x3a
1820#define STATUS_FCF_TABLE_EMPTY 0x43
1821
1822struct lpfc_mbx_sli4_config {
1823 struct mbox_header header;
1824};
1825
1826struct lpfc_mbx_init_vfi {
1827 uint32_t word1;
1828#define lpfc_init_vfi_vr_SHIFT 31
1829#define lpfc_init_vfi_vr_MASK 0x00000001
1830#define lpfc_init_vfi_vr_WORD word1
1831#define lpfc_init_vfi_vt_SHIFT 30
1832#define lpfc_init_vfi_vt_MASK 0x00000001
1833#define lpfc_init_vfi_vt_WORD word1
1834#define lpfc_init_vfi_vf_SHIFT 29
1835#define lpfc_init_vfi_vf_MASK 0x00000001
1836#define lpfc_init_vfi_vf_WORD word1
1837#define lpfc_init_vfi_vp_SHIFT 28
1838#define lpfc_init_vfi_vp_MASK 0x00000001
1839#define lpfc_init_vfi_vp_WORD word1
1840#define lpfc_init_vfi_vfi_SHIFT 0
1841#define lpfc_init_vfi_vfi_MASK 0x0000FFFF
1842#define lpfc_init_vfi_vfi_WORD word1
1843 uint32_t word2;
1844#define lpfc_init_vfi_vpi_SHIFT 16
1845#define lpfc_init_vfi_vpi_MASK 0x0000FFFF
1846#define lpfc_init_vfi_vpi_WORD word2
1847#define lpfc_init_vfi_fcfi_SHIFT 0
1848#define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
1849#define lpfc_init_vfi_fcfi_WORD word2
1850 uint32_t word3;
1851#define lpfc_init_vfi_pri_SHIFT 13
1852#define lpfc_init_vfi_pri_MASK 0x00000007
1853#define lpfc_init_vfi_pri_WORD word3
1854#define lpfc_init_vfi_vf_id_SHIFT 1
1855#define lpfc_init_vfi_vf_id_MASK 0x00000FFF
1856#define lpfc_init_vfi_vf_id_WORD word3
1857 uint32_t word4;
1858#define lpfc_init_vfi_hop_count_SHIFT 24
1859#define lpfc_init_vfi_hop_count_MASK 0x000000FF
1860#define lpfc_init_vfi_hop_count_WORD word4
1861};
1862#define MBX_VFI_IN_USE 0x9F02
1863
1864
1865struct lpfc_mbx_reg_vfi {
1866 uint32_t word1;
1867#define lpfc_reg_vfi_vp_SHIFT 28
1868#define lpfc_reg_vfi_vp_MASK 0x00000001
1869#define lpfc_reg_vfi_vp_WORD word1
1870#define lpfc_reg_vfi_vfi_SHIFT 0
1871#define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
1872#define lpfc_reg_vfi_vfi_WORD word1
1873 uint32_t word2;
1874#define lpfc_reg_vfi_vpi_SHIFT 16
1875#define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
1876#define lpfc_reg_vfi_vpi_WORD word2
1877#define lpfc_reg_vfi_fcfi_SHIFT 0
1878#define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
1879#define lpfc_reg_vfi_fcfi_WORD word2
1880 uint32_t wwn[2];
1881 struct ulp_bde64 bde;
1882 uint32_t e_d_tov;
1883 uint32_t r_a_tov;
1884 uint32_t word10;
1885#define lpfc_reg_vfi_nport_id_SHIFT 0
1886#define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
1887#define lpfc_reg_vfi_nport_id_WORD word10
1888};
1889
1890struct lpfc_mbx_init_vpi {
1891 uint32_t word1;
1892#define lpfc_init_vpi_vfi_SHIFT 16
1893#define lpfc_init_vpi_vfi_MASK 0x0000FFFF
1894#define lpfc_init_vpi_vfi_WORD word1
1895#define lpfc_init_vpi_vpi_SHIFT 0
1896#define lpfc_init_vpi_vpi_MASK 0x0000FFFF
1897#define lpfc_init_vpi_vpi_WORD word1
1898};
1899
1900struct lpfc_mbx_read_vpi {
1901 uint32_t word1_rsvd;
1902 uint32_t word2;
1903#define lpfc_mbx_read_vpi_vnportid_SHIFT 0
1904#define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
1905#define lpfc_mbx_read_vpi_vnportid_WORD word2
1906 uint32_t word3_rsvd;
1907 uint32_t word4;
1908#define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
1909#define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
1910#define lpfc_mbx_read_vpi_acq_alpa_WORD word4
1911#define lpfc_mbx_read_vpi_pb_SHIFT 15
1912#define lpfc_mbx_read_vpi_pb_MASK 0x00000001
1913#define lpfc_mbx_read_vpi_pb_WORD word4
1914#define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16
1915#define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
1916#define lpfc_mbx_read_vpi_spec_alpa_WORD word4
1917#define lpfc_mbx_read_vpi_ns_SHIFT 30
1918#define lpfc_mbx_read_vpi_ns_MASK 0x00000001
1919#define lpfc_mbx_read_vpi_ns_WORD word4
1920#define lpfc_mbx_read_vpi_hl_SHIFT 31
1921#define lpfc_mbx_read_vpi_hl_MASK 0x00000001
1922#define lpfc_mbx_read_vpi_hl_WORD word4
1923 uint32_t word5_rsvd;
1924 uint32_t word6;
1925#define lpfc_mbx_read_vpi_vpi_SHIFT 0
1926#define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
1927#define lpfc_mbx_read_vpi_vpi_WORD word6
1928 uint32_t word7;
1929#define lpfc_mbx_read_vpi_mac_0_SHIFT 0
1930#define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
1931#define lpfc_mbx_read_vpi_mac_0_WORD word7
1932#define lpfc_mbx_read_vpi_mac_1_SHIFT 8
1933#define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
1934#define lpfc_mbx_read_vpi_mac_1_WORD word7
1935#define lpfc_mbx_read_vpi_mac_2_SHIFT 16
1936#define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
1937#define lpfc_mbx_read_vpi_mac_2_WORD word7
1938#define lpfc_mbx_read_vpi_mac_3_SHIFT 24
1939#define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
1940#define lpfc_mbx_read_vpi_mac_3_WORD word7
1941 uint32_t word8;
1942#define lpfc_mbx_read_vpi_mac_4_SHIFT 0
1943#define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
1944#define lpfc_mbx_read_vpi_mac_4_WORD word8
1945#define lpfc_mbx_read_vpi_mac_5_SHIFT 8
1946#define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
1947#define lpfc_mbx_read_vpi_mac_5_WORD word8
1948#define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16
1949#define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
1950#define lpfc_mbx_read_vpi_vlan_tag_WORD word8
1951#define lpfc_mbx_read_vpi_vv_SHIFT 28
1952#define lpfc_mbx_read_vpi_vv_MASK 0x0000001
1953#define lpfc_mbx_read_vpi_vv_WORD word8
1954};
1955
1956struct lpfc_mbx_unreg_vfi {
1957 uint32_t word1_rsvd;
1958 uint32_t word2;
1959#define lpfc_unreg_vfi_vfi_SHIFT 0
1960#define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
1961#define lpfc_unreg_vfi_vfi_WORD word2
1962};
1963
1964struct lpfc_mbx_resume_rpi {
1965 uint32_t word1;
1966#define lpfc_resume_rpi_index_SHIFT 0
1967#define lpfc_resume_rpi_index_MASK 0x0000FFFF
1968#define lpfc_resume_rpi_index_WORD word1
1969#define lpfc_resume_rpi_ii_SHIFT 30
1970#define lpfc_resume_rpi_ii_MASK 0x00000003
1971#define lpfc_resume_rpi_ii_WORD word1
1972#define RESUME_INDEX_RPI 0
1973#define RESUME_INDEX_VPI 1
1974#define RESUME_INDEX_VFI 2
1975#define RESUME_INDEX_FCFI 3
1976 uint32_t event_tag;
1977};
1978
1979#define REG_FCF_INVALID_QID 0xFFFF
1980struct lpfc_mbx_reg_fcfi {
1981 uint32_t word1;
1982#define lpfc_reg_fcfi_info_index_SHIFT 0
1983#define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
1984#define lpfc_reg_fcfi_info_index_WORD word1
1985#define lpfc_reg_fcfi_fcfi_SHIFT 16
1986#define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
1987#define lpfc_reg_fcfi_fcfi_WORD word1
1988 uint32_t word2;
1989#define lpfc_reg_fcfi_rq_id1_SHIFT 0
1990#define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
1991#define lpfc_reg_fcfi_rq_id1_WORD word2
1992#define lpfc_reg_fcfi_rq_id0_SHIFT 16
1993#define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
1994#define lpfc_reg_fcfi_rq_id0_WORD word2
1995 uint32_t word3;
1996#define lpfc_reg_fcfi_rq_id3_SHIFT 0
1997#define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
1998#define lpfc_reg_fcfi_rq_id3_WORD word3
1999#define lpfc_reg_fcfi_rq_id2_SHIFT 16
2000#define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2001#define lpfc_reg_fcfi_rq_id2_WORD word3
2002 uint32_t word4;
2003#define lpfc_reg_fcfi_type_match0_SHIFT 24
2004#define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2005#define lpfc_reg_fcfi_type_match0_WORD word4
2006#define lpfc_reg_fcfi_type_mask0_SHIFT 16
2007#define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2008#define lpfc_reg_fcfi_type_mask0_WORD word4
2009#define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2010#define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2011#define lpfc_reg_fcfi_rctl_match0_WORD word4
2012#define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2013#define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2014#define lpfc_reg_fcfi_rctl_mask0_WORD word4
2015 uint32_t word5;
2016#define lpfc_reg_fcfi_type_match1_SHIFT 24
2017#define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2018#define lpfc_reg_fcfi_type_match1_WORD word5
2019#define lpfc_reg_fcfi_type_mask1_SHIFT 16
2020#define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2021#define lpfc_reg_fcfi_type_mask1_WORD word5
2022#define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2023#define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2024#define lpfc_reg_fcfi_rctl_match1_WORD word5
2025#define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2026#define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2027#define lpfc_reg_fcfi_rctl_mask1_WORD word5
2028 uint32_t word6;
2029#define lpfc_reg_fcfi_type_match2_SHIFT 24
2030#define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2031#define lpfc_reg_fcfi_type_match2_WORD word6
2032#define lpfc_reg_fcfi_type_mask2_SHIFT 16
2033#define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2034#define lpfc_reg_fcfi_type_mask2_WORD word6
2035#define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2036#define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2037#define lpfc_reg_fcfi_rctl_match2_WORD word6
2038#define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2039#define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2040#define lpfc_reg_fcfi_rctl_mask2_WORD word6
2041 uint32_t word7;
2042#define lpfc_reg_fcfi_type_match3_SHIFT 24
2043#define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2044#define lpfc_reg_fcfi_type_match3_WORD word7
2045#define lpfc_reg_fcfi_type_mask3_SHIFT 16
2046#define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2047#define lpfc_reg_fcfi_type_mask3_WORD word7
2048#define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2049#define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2050#define lpfc_reg_fcfi_rctl_match3_WORD word7
2051#define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2052#define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2053#define lpfc_reg_fcfi_rctl_mask3_WORD word7
2054 uint32_t word8;
2055#define lpfc_reg_fcfi_mam_SHIFT 13
2056#define lpfc_reg_fcfi_mam_MASK 0x00000003
2057#define lpfc_reg_fcfi_mam_WORD word8
2058#define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2059#define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */
2060#define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */
2061#define lpfc_reg_fcfi_vv_SHIFT 12
2062#define lpfc_reg_fcfi_vv_MASK 0x00000001
2063#define lpfc_reg_fcfi_vv_WORD word8
2064#define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2065#define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2066#define lpfc_reg_fcfi_vlan_tag_WORD word8
2067};
2068
2069struct lpfc_mbx_unreg_fcfi {
2070 uint32_t word1_rsv;
2071 uint32_t word2;
2072#define lpfc_unreg_fcfi_SHIFT 0
2073#define lpfc_unreg_fcfi_MASK 0x0000FFFF
2074#define lpfc_unreg_fcfi_WORD word2
2075};
2076
2077struct lpfc_mbx_read_rev {
2078 uint32_t word1;
2079#define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16
2080#define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2081#define lpfc_mbx_rd_rev_sli_lvl_WORD word1
2082#define lpfc_mbx_rd_rev_fcoe_SHIFT 20
2083#define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2084#define lpfc_mbx_rd_rev_fcoe_WORD word1
2085#define lpfc_mbx_rd_rev_cee_ver_SHIFT 21
2086#define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2087#define lpfc_mbx_rd_rev_cee_ver_WORD word1
2088#define LPFC_PREDCBX_CEE_MODE 0
2089#define LPFC_DCBX_CEE_MODE 1
2090#define lpfc_mbx_rd_rev_vpd_SHIFT 29
2091#define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2092#define lpfc_mbx_rd_rev_vpd_WORD word1
2093 uint32_t first_hw_rev;
2094 uint32_t second_hw_rev;
2095 uint32_t word4_rsvd;
2096 uint32_t third_hw_rev;
2097 uint32_t word6;
2098#define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2099#define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2100#define lpfc_mbx_rd_rev_fcph_low_WORD word6
2101#define lpfc_mbx_rd_rev_fcph_high_SHIFT 8
2102#define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2103#define lpfc_mbx_rd_rev_fcph_high_WORD word6
2104#define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16
2105#define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2106#define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6
2107#define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24
2108#define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2109#define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6
2110 uint32_t word7_rsvd;
2111 uint32_t fw_id_rev;
2112 uint8_t fw_name[16];
2113 uint32_t ulp_fw_id_rev;
2114 uint8_t ulp_fw_name[16];
2115 uint32_t word18_47_rsvd[30];
2116 uint32_t word48;
2117#define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2118#define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2119#define lpfc_mbx_rd_rev_avail_len_WORD word48
2120 uint32_t vpd_paddr_low;
2121 uint32_t vpd_paddr_high;
2122 uint32_t avail_vpd_len;
2123 uint32_t rsvd_52_63[12];
2124};
2125
2126struct lpfc_mbx_read_config {
2127 uint32_t word1;
2128#define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31
2129#define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2130#define lpfc_mbx_rd_conf_extnts_inuse_WORD word1
2131 uint32_t word2;
2132#define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2133#define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2134#define lpfc_mbx_rd_conf_lnk_numb_WORD word2
2135#define lpfc_mbx_rd_conf_lnk_type_SHIFT 6
2136#define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2137#define lpfc_mbx_rd_conf_lnk_type_WORD word2
2138#define LPFC_LNK_TYPE_GE 0
2139#define LPFC_LNK_TYPE_FC 1
2140#define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8
2141#define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2142#define lpfc_mbx_rd_conf_lnk_ldv_WORD word2
2143#define lpfc_mbx_rd_conf_topology_SHIFT 24
2144#define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2145#define lpfc_mbx_rd_conf_topology_WORD word2
2146 uint32_t rsvd_3;
2147 uint32_t word4;
2148#define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2149#define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2150#define lpfc_mbx_rd_conf_e_d_tov_WORD word4
2151 uint32_t rsvd_5;
2152 uint32_t word6;
2153#define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2154#define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2155#define lpfc_mbx_rd_conf_r_a_tov_WORD word6
2156 uint32_t rsvd_7;
2157 uint32_t rsvd_8;
2158 uint32_t word9;
2159#define lpfc_mbx_rd_conf_lmt_SHIFT 0
2160#define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2161#define lpfc_mbx_rd_conf_lmt_WORD word9
2162 uint32_t rsvd_10;
2163 uint32_t rsvd_11;
2164 uint32_t word12;
2165#define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2166#define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2167#define lpfc_mbx_rd_conf_xri_base_WORD word12
2168#define lpfc_mbx_rd_conf_xri_count_SHIFT 16
2169#define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2170#define lpfc_mbx_rd_conf_xri_count_WORD word12
2171 uint32_t word13;
2172#define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2173#define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2174#define lpfc_mbx_rd_conf_rpi_base_WORD word13
2175#define lpfc_mbx_rd_conf_rpi_count_SHIFT 16
2176#define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2177#define lpfc_mbx_rd_conf_rpi_count_WORD word13
2178 uint32_t word14;
2179#define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2180#define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2181#define lpfc_mbx_rd_conf_vpi_base_WORD word14
2182#define lpfc_mbx_rd_conf_vpi_count_SHIFT 16
2183#define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2184#define lpfc_mbx_rd_conf_vpi_count_WORD word14
2185 uint32_t word15;
2186#define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2187#define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2188#define lpfc_mbx_rd_conf_vfi_base_WORD word15
2189#define lpfc_mbx_rd_conf_vfi_count_SHIFT 16
2190#define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2191#define lpfc_mbx_rd_conf_vfi_count_WORD word15
2192 uint32_t word16;
2193#define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16
2194#define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2195#define lpfc_mbx_rd_conf_fcfi_count_WORD word16
2196 uint32_t word17;
2197#define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2198#define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2199#define lpfc_mbx_rd_conf_rq_count_WORD word17
2200#define lpfc_mbx_rd_conf_eq_count_SHIFT 16
2201#define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2202#define lpfc_mbx_rd_conf_eq_count_WORD word17
2203 uint32_t word18;
2204#define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2205#define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2206#define lpfc_mbx_rd_conf_wq_count_WORD word18
2207#define lpfc_mbx_rd_conf_cq_count_SHIFT 16
2208#define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2209#define lpfc_mbx_rd_conf_cq_count_WORD word18
2210};
2211
2212struct lpfc_mbx_request_features {
2213 uint32_t word1;
2214#define lpfc_mbx_rq_ftr_qry_SHIFT 0
2215#define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2216#define lpfc_mbx_rq_ftr_qry_WORD word1
2217 uint32_t word2;
2218#define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2219#define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2220#define lpfc_mbx_rq_ftr_rq_iaab_WORD word2
2221#define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1
2222#define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2223#define lpfc_mbx_rq_ftr_rq_npiv_WORD word2
2224#define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2
2225#define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2226#define lpfc_mbx_rq_ftr_rq_dif_WORD word2
2227#define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3
2228#define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2229#define lpfc_mbx_rq_ftr_rq_vf_WORD word2
2230#define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4
2231#define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2232#define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2
2233#define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5
2234#define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2235#define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2
2236#define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6
2237#define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2238#define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2
2239#define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7
2240#define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2241#define lpfc_mbx_rq_ftr_rq_ifip_WORD word2
2242#define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11
2243#define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
2244#define lpfc_mbx_rq_ftr_rq_perfh_WORD word2
2245 uint32_t word3;
2246#define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
2247#define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
2248#define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3
2249#define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1
2250#define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
2251#define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3
2252#define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2
2253#define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
2254#define lpfc_mbx_rq_ftr_rsp_dif_WORD word3
2255#define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3
2256#define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
2257#define lpfc_mbx_rq_ftr_rsp_vf_WORD word3
2258#define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4
2259#define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
2260#define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3
2261#define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5
2262#define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
2263#define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3
2264#define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6
2265#define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
2266#define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3
2267#define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7
2268#define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
2269#define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3
2270#define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11
2271#define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
2272#define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3
2273};
2274
2275struct lpfc_mbx_supp_pages {
2276 uint32_t word1;
2277#define qs_SHIFT 0
2278#define qs_MASK 0x00000001
2279#define qs_WORD word1
2280#define wr_SHIFT 1
2281#define wr_MASK 0x00000001
2282#define wr_WORD word1
2283#define pf_SHIFT 8
2284#define pf_MASK 0x000000ff
2285#define pf_WORD word1
2286#define cpn_SHIFT 16
2287#define cpn_MASK 0x000000ff
2288#define cpn_WORD word1
2289 uint32_t word2;
2290#define list_offset_SHIFT 0
2291#define list_offset_MASK 0x000000ff
2292#define list_offset_WORD word2
2293#define next_offset_SHIFT 8
2294#define next_offset_MASK 0x000000ff
2295#define next_offset_WORD word2
2296#define elem_cnt_SHIFT 16
2297#define elem_cnt_MASK 0x000000ff
2298#define elem_cnt_WORD word2
2299 uint32_t word3;
2300#define pn_0_SHIFT 24
2301#define pn_0_MASK 0x000000ff
2302#define pn_0_WORD word3
2303#define pn_1_SHIFT 16
2304#define pn_1_MASK 0x000000ff
2305#define pn_1_WORD word3
2306#define pn_2_SHIFT 8
2307#define pn_2_MASK 0x000000ff
2308#define pn_2_WORD word3
2309#define pn_3_SHIFT 0
2310#define pn_3_MASK 0x000000ff
2311#define pn_3_WORD word3
2312 uint32_t word4;
2313#define pn_4_SHIFT 24
2314#define pn_4_MASK 0x000000ff
2315#define pn_4_WORD word4
2316#define pn_5_SHIFT 16
2317#define pn_5_MASK 0x000000ff
2318#define pn_5_WORD word4
2319#define pn_6_SHIFT 8
2320#define pn_6_MASK 0x000000ff
2321#define pn_6_WORD word4
2322#define pn_7_SHIFT 0
2323#define pn_7_MASK 0x000000ff
2324#define pn_7_WORD word4
2325 uint32_t rsvd[27];
2326#define LPFC_SUPP_PAGES 0
2327#define LPFC_BLOCK_GUARD_PROFILES 1
2328#define LPFC_SLI4_PARAMETERS 2
2329};
2330
2331struct lpfc_mbx_pc_sli4_params {
2332 uint32_t word1;
2333#define qs_SHIFT 0
2334#define qs_MASK 0x00000001
2335#define qs_WORD word1
2336#define wr_SHIFT 1
2337#define wr_MASK 0x00000001
2338#define wr_WORD word1
2339#define pf_SHIFT 8
2340#define pf_MASK 0x000000ff
2341#define pf_WORD word1
2342#define cpn_SHIFT 16
2343#define cpn_MASK 0x000000ff
2344#define cpn_WORD word1
2345 uint32_t word2;
2346#define if_type_SHIFT 0
2347#define if_type_MASK 0x00000007
2348#define if_type_WORD word2
2349#define sli_rev_SHIFT 4
2350#define sli_rev_MASK 0x0000000f
2351#define sli_rev_WORD word2
2352#define sli_family_SHIFT 8
2353#define sli_family_MASK 0x000000ff
2354#define sli_family_WORD word2
2355#define featurelevel_1_SHIFT 16
2356#define featurelevel_1_MASK 0x000000ff
2357#define featurelevel_1_WORD word2
2358#define featurelevel_2_SHIFT 24
2359#define featurelevel_2_MASK 0x0000001f
2360#define featurelevel_2_WORD word2
2361 uint32_t word3;
2362#define fcoe_SHIFT 0
2363#define fcoe_MASK 0x00000001
2364#define fcoe_WORD word3
2365#define fc_SHIFT 1
2366#define fc_MASK 0x00000001
2367#define fc_WORD word3
2368#define nic_SHIFT 2
2369#define nic_MASK 0x00000001
2370#define nic_WORD word3
2371#define iscsi_SHIFT 3
2372#define iscsi_MASK 0x00000001
2373#define iscsi_WORD word3
2374#define rdma_SHIFT 4
2375#define rdma_MASK 0x00000001
2376#define rdma_WORD word3
2377 uint32_t sge_supp_len;
2378#define SLI4_PAGE_SIZE 4096
2379 uint32_t word5;
2380#define if_page_sz_SHIFT 0
2381#define if_page_sz_MASK 0x0000ffff
2382#define if_page_sz_WORD word5
2383#define loopbk_scope_SHIFT 24
2384#define loopbk_scope_MASK 0x0000000f
2385#define loopbk_scope_WORD word5
2386#define rq_db_window_SHIFT 28
2387#define rq_db_window_MASK 0x0000000f
2388#define rq_db_window_WORD word5
2389 uint32_t word6;
2390#define eq_pages_SHIFT 0
2391#define eq_pages_MASK 0x0000000f
2392#define eq_pages_WORD word6
2393#define eqe_size_SHIFT 8
2394#define eqe_size_MASK 0x000000ff
2395#define eqe_size_WORD word6
2396 uint32_t word7;
2397#define cq_pages_SHIFT 0
2398#define cq_pages_MASK 0x0000000f
2399#define cq_pages_WORD word7
2400#define cqe_size_SHIFT 8
2401#define cqe_size_MASK 0x000000ff
2402#define cqe_size_WORD word7
2403 uint32_t word8;
2404#define mq_pages_SHIFT 0
2405#define mq_pages_MASK 0x0000000f
2406#define mq_pages_WORD word8
2407#define mqe_size_SHIFT 8
2408#define mqe_size_MASK 0x000000ff
2409#define mqe_size_WORD word8
2410#define mq_elem_cnt_SHIFT 16
2411#define mq_elem_cnt_MASK 0x000000ff
2412#define mq_elem_cnt_WORD word8
2413 uint32_t word9;
2414#define wq_pages_SHIFT 0
2415#define wq_pages_MASK 0x0000ffff
2416#define wq_pages_WORD word9
2417#define wqe_size_SHIFT 8
2418#define wqe_size_MASK 0x000000ff
2419#define wqe_size_WORD word9
2420 uint32_t word10;
2421#define rq_pages_SHIFT 0
2422#define rq_pages_MASK 0x0000ffff
2423#define rq_pages_WORD word10
2424#define rqe_size_SHIFT 8
2425#define rqe_size_MASK 0x000000ff
2426#define rqe_size_WORD word10
2427 uint32_t word11;
2428#define hdr_pages_SHIFT 0
2429#define hdr_pages_MASK 0x0000000f
2430#define hdr_pages_WORD word11
2431#define hdr_size_SHIFT 8
2432#define hdr_size_MASK 0x0000000f
2433#define hdr_size_WORD word11
2434#define hdr_pp_align_SHIFT 16
2435#define hdr_pp_align_MASK 0x0000ffff
2436#define hdr_pp_align_WORD word11
2437 uint32_t word12;
2438#define sgl_pages_SHIFT 0
2439#define sgl_pages_MASK 0x0000000f
2440#define sgl_pages_WORD word12
2441#define sgl_pp_align_SHIFT 16
2442#define sgl_pp_align_MASK 0x0000ffff
2443#define sgl_pp_align_WORD word12
2444 uint32_t rsvd_13_63[51];
2445};
2446#define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
2447 &(~((SLI4_PAGE_SIZE)-1)))
2448
2449struct lpfc_sli4_parameters {
2450 uint32_t word0;
2451#define cfg_prot_type_SHIFT 0
2452#define cfg_prot_type_MASK 0x000000FF
2453#define cfg_prot_type_WORD word0
2454 uint32_t word1;
2455#define cfg_ft_SHIFT 0
2456#define cfg_ft_MASK 0x00000001
2457#define cfg_ft_WORD word1
2458#define cfg_sli_rev_SHIFT 4
2459#define cfg_sli_rev_MASK 0x0000000f
2460#define cfg_sli_rev_WORD word1
2461#define cfg_sli_family_SHIFT 8
2462#define cfg_sli_family_MASK 0x0000000f
2463#define cfg_sli_family_WORD word1
2464#define cfg_if_type_SHIFT 12
2465#define cfg_if_type_MASK 0x0000000f
2466#define cfg_if_type_WORD word1
2467#define cfg_sli_hint_1_SHIFT 16
2468#define cfg_sli_hint_1_MASK 0x000000ff
2469#define cfg_sli_hint_1_WORD word1
2470#define cfg_sli_hint_2_SHIFT 24
2471#define cfg_sli_hint_2_MASK 0x0000001f
2472#define cfg_sli_hint_2_WORD word1
2473 uint32_t word2;
2474 uint32_t word3;
2475 uint32_t word4;
2476#define cfg_cqv_SHIFT 14
2477#define cfg_cqv_MASK 0x00000003
2478#define cfg_cqv_WORD word4
2479 uint32_t word5;
2480 uint32_t word6;
2481#define cfg_mqv_SHIFT 14
2482#define cfg_mqv_MASK 0x00000003
2483#define cfg_mqv_WORD word6
2484 uint32_t word7;
2485 uint32_t word8;
2486#define cfg_wqv_SHIFT 14
2487#define cfg_wqv_MASK 0x00000003
2488#define cfg_wqv_WORD word8
2489 uint32_t word9;
2490 uint32_t word10;
2491#define cfg_rqv_SHIFT 14
2492#define cfg_rqv_MASK 0x00000003
2493#define cfg_rqv_WORD word10
2494 uint32_t word11;
2495#define cfg_rq_db_window_SHIFT 28
2496#define cfg_rq_db_window_MASK 0x0000000f
2497#define cfg_rq_db_window_WORD word11
2498 uint32_t word12;
2499#define cfg_fcoe_SHIFT 0
2500#define cfg_fcoe_MASK 0x00000001
2501#define cfg_fcoe_WORD word12
2502#define cfg_ext_SHIFT 1
2503#define cfg_ext_MASK 0x00000001
2504#define cfg_ext_WORD word12
2505#define cfg_hdrr_SHIFT 2
2506#define cfg_hdrr_MASK 0x00000001
2507#define cfg_hdrr_WORD word12
2508#define cfg_phwq_SHIFT 15
2509#define cfg_phwq_MASK 0x00000001
2510#define cfg_phwq_WORD word12
2511#define cfg_loopbk_scope_SHIFT 28
2512#define cfg_loopbk_scope_MASK 0x0000000f
2513#define cfg_loopbk_scope_WORD word12
2514 uint32_t sge_supp_len;
2515 uint32_t word14;
2516#define cfg_sgl_page_cnt_SHIFT 0
2517#define cfg_sgl_page_cnt_MASK 0x0000000f
2518#define cfg_sgl_page_cnt_WORD word14
2519#define cfg_sgl_page_size_SHIFT 8
2520#define cfg_sgl_page_size_MASK 0x000000ff
2521#define cfg_sgl_page_size_WORD word14
2522#define cfg_sgl_pp_align_SHIFT 16
2523#define cfg_sgl_pp_align_MASK 0x000000ff
2524#define cfg_sgl_pp_align_WORD word14
2525 uint32_t word15;
2526 uint32_t word16;
2527 uint32_t word17;
2528 uint32_t word18;
2529 uint32_t word19;
2530};
2531
2532struct lpfc_mbx_get_sli4_parameters {
2533 struct mbox_header header;
2534 struct lpfc_sli4_parameters sli4_parameters;
2535};
2536
2537struct lpfc_rscr_desc_generic {
2538#define LPFC_RSRC_DESC_WSIZE 18
2539 uint32_t desc[LPFC_RSRC_DESC_WSIZE];
2540};
2541
2542struct lpfc_rsrc_desc_pcie {
2543 uint32_t word0;
2544#define lpfc_rsrc_desc_pcie_type_SHIFT 0
2545#define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
2546#define lpfc_rsrc_desc_pcie_type_WORD word0
2547#define LPFC_RSRC_DESC_TYPE_PCIE 0x40
2548 uint32_t word1;
2549#define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
2550#define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
2551#define lpfc_rsrc_desc_pcie_pfnum_WORD word1
2552 uint32_t reserved;
2553 uint32_t word3;
2554#define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
2555#define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
2556#define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3
2557#define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8
2558#define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
2559#define lpfc_rsrc_desc_pcie_pf_sta_WORD word3
2560#define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16
2561#define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
2562#define lpfc_rsrc_desc_pcie_pf_type_WORD word3
2563 uint32_t word4;
2564#define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
2565#define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
2566#define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4
2567};
2568
2569struct lpfc_rsrc_desc_fcfcoe {
2570 uint32_t word0;
2571#define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
2572#define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
2573#define lpfc_rsrc_desc_fcfcoe_type_WORD word0
2574#define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
2575 uint32_t word1;
2576#define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
2577#define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
2578#define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1
2579#define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16
2580#define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
2581#define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1
2582 uint32_t word2;
2583#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
2584#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
2585#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2
2586#define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16
2587#define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
2588#define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2
2589 uint32_t word3;
2590#define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
2591#define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
2592#define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3
2593#define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16
2594#define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
2595#define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3
2596 uint32_t word4;
2597#define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
2598#define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
2599#define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4
2600#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16
2601#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
2602#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4
2603 uint32_t word5;
2604#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
2605#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
2606#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5
2607#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16
2608#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
2609#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5
2610 uint32_t word6;
2611 uint32_t word7;
2612 uint32_t word8;
2613 uint32_t word9;
2614 uint32_t word10;
2615 uint32_t word11;
2616 uint32_t word12;
2617 uint32_t word13;
2618#define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
2619#define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
2620#define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13
2621#define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6
2622#define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
2623#define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13
2624#define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8
2625#define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
2626#define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13
2627#define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9
2628#define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
2629#define lpfc_rsrc_desc_fcfcoe_lld_WORD word13
2630#define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16
2631#define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
2632#define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13
2633};
2634
2635struct lpfc_func_cfg {
2636#define LPFC_RSRC_DESC_MAX_NUM 2
2637 uint32_t rsrc_desc_count;
2638 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
2639};
2640
2641struct lpfc_mbx_get_func_cfg {
2642 struct mbox_header header;
2643#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
2644#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
2645#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
2646 struct lpfc_func_cfg func_cfg;
2647};
2648
2649struct lpfc_prof_cfg {
2650#define LPFC_RSRC_DESC_MAX_NUM 2
2651 uint32_t rsrc_desc_count;
2652 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
2653};
2654
2655struct lpfc_mbx_get_prof_cfg {
2656 struct mbox_header header;
2657#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
2658#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
2659#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
2660 union {
2661 struct {
2662 uint32_t word10;
2663#define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
2664#define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
2665#define lpfc_mbx_get_prof_cfg_prof_id_WORD word10
2666#define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8
2667#define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
2668#define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10
2669 } request;
2670 struct {
2671 struct lpfc_prof_cfg prof_cfg;
2672 } response;
2673 } u;
2674};
2675
2676struct lpfc_controller_attribute {
2677 uint32_t version_string[8];
2678 uint32_t manufacturer_name[8];
2679 uint32_t supported_modes;
2680 uint32_t word17;
2681#define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
2682#define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
2683#define lpfc_cntl_attr_eprom_ver_lo_WORD word17
2684#define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8
2685#define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
2686#define lpfc_cntl_attr_eprom_ver_hi_WORD word17
2687 uint32_t mbx_da_struct_ver;
2688 uint32_t ep_fw_da_struct_ver;
2689 uint32_t ncsi_ver_str[3];
2690 uint32_t dflt_ext_timeout;
2691 uint32_t model_number[8];
2692 uint32_t description[16];
2693 uint32_t serial_number[8];
2694 uint32_t ip_ver_str[8];
2695 uint32_t fw_ver_str[8];
2696 uint32_t bios_ver_str[8];
2697 uint32_t redboot_ver_str[8];
2698 uint32_t driver_ver_str[8];
2699 uint32_t flash_fw_ver_str[8];
2700 uint32_t functionality;
2701 uint32_t word105;
2702#define lpfc_cntl_attr_max_cbd_len_SHIFT 0
2703#define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
2704#define lpfc_cntl_attr_max_cbd_len_WORD word105
2705#define lpfc_cntl_attr_asic_rev_SHIFT 16
2706#define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
2707#define lpfc_cntl_attr_asic_rev_WORD word105
2708#define lpfc_cntl_attr_gen_guid0_SHIFT 24
2709#define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
2710#define lpfc_cntl_attr_gen_guid0_WORD word105
2711 uint32_t gen_guid1_12[3];
2712 uint32_t word109;
2713#define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
2714#define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
2715#define lpfc_cntl_attr_gen_guid13_14_WORD word109
2716#define lpfc_cntl_attr_gen_guid15_SHIFT 16
2717#define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
2718#define lpfc_cntl_attr_gen_guid15_WORD word109
2719#define lpfc_cntl_attr_hba_port_cnt_SHIFT 24
2720#define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
2721#define lpfc_cntl_attr_hba_port_cnt_WORD word109
2722 uint32_t word110;
2723#define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
2724#define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
2725#define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110
2726#define lpfc_cntl_attr_multi_func_dev_SHIFT 24
2727#define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
2728#define lpfc_cntl_attr_multi_func_dev_WORD word110
2729 uint32_t word111;
2730#define lpfc_cntl_attr_cache_valid_SHIFT 0
2731#define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
2732#define lpfc_cntl_attr_cache_valid_WORD word111
2733#define lpfc_cntl_attr_hba_status_SHIFT 8
2734#define lpfc_cntl_attr_hba_status_MASK 0x000000ff
2735#define lpfc_cntl_attr_hba_status_WORD word111
2736#define lpfc_cntl_attr_max_domain_SHIFT 16
2737#define lpfc_cntl_attr_max_domain_MASK 0x000000ff
2738#define lpfc_cntl_attr_max_domain_WORD word111
2739#define lpfc_cntl_attr_lnk_numb_SHIFT 24
2740#define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
2741#define lpfc_cntl_attr_lnk_numb_WORD word111
2742#define lpfc_cntl_attr_lnk_type_SHIFT 30
2743#define lpfc_cntl_attr_lnk_type_MASK 0x00000003
2744#define lpfc_cntl_attr_lnk_type_WORD word111
2745 uint32_t fw_post_status;
2746 uint32_t hba_mtu[8];
2747 uint32_t word121;
2748 uint32_t reserved1[3];
2749 uint32_t word125;
2750#define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
2751#define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
2752#define lpfc_cntl_attr_pci_vendor_id_WORD word125
2753#define lpfc_cntl_attr_pci_device_id_SHIFT 16
2754#define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
2755#define lpfc_cntl_attr_pci_device_id_WORD word125
2756 uint32_t word126;
2757#define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
2758#define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
2759#define lpfc_cntl_attr_pci_subvdr_id_WORD word126
2760#define lpfc_cntl_attr_pci_subsys_id_SHIFT 16
2761#define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
2762#define lpfc_cntl_attr_pci_subsys_id_WORD word126
2763 uint32_t word127;
2764#define lpfc_cntl_attr_pci_bus_num_SHIFT 0
2765#define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
2766#define lpfc_cntl_attr_pci_bus_num_WORD word127
2767#define lpfc_cntl_attr_pci_dev_num_SHIFT 8
2768#define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
2769#define lpfc_cntl_attr_pci_dev_num_WORD word127
2770#define lpfc_cntl_attr_pci_fnc_num_SHIFT 16
2771#define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
2772#define lpfc_cntl_attr_pci_fnc_num_WORD word127
2773#define lpfc_cntl_attr_inf_type_SHIFT 24
2774#define lpfc_cntl_attr_inf_type_MASK 0x000000ff
2775#define lpfc_cntl_attr_inf_type_WORD word127
2776 uint32_t unique_id[2];
2777 uint32_t word130;
2778#define lpfc_cntl_attr_num_netfil_SHIFT 0
2779#define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
2780#define lpfc_cntl_attr_num_netfil_WORD word130
2781 uint32_t reserved2[4];
2782};
2783
2784struct lpfc_mbx_get_cntl_attributes {
2785 union lpfc_sli4_cfg_shdr cfg_shdr;
2786 struct lpfc_controller_attribute cntl_attr;
2787};
2788
2789struct lpfc_mbx_get_port_name {
2790 struct mbox_header header;
2791 union {
2792 struct {
2793 uint32_t word4;
2794#define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
2795#define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
2796#define lpfc_mbx_get_port_name_lnk_type_WORD word4
2797 } request;
2798 struct {
2799 uint32_t word4;
2800#define lpfc_mbx_get_port_name_name0_SHIFT 0
2801#define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
2802#define lpfc_mbx_get_port_name_name0_WORD word4
2803#define lpfc_mbx_get_port_name_name1_SHIFT 8
2804#define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
2805#define lpfc_mbx_get_port_name_name1_WORD word4
2806#define lpfc_mbx_get_port_name_name2_SHIFT 16
2807#define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
2808#define lpfc_mbx_get_port_name_name2_WORD word4
2809#define lpfc_mbx_get_port_name_name3_SHIFT 24
2810#define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
2811#define lpfc_mbx_get_port_name_name3_WORD word4
2812#define LPFC_LINK_NUMBER_0 0
2813#define LPFC_LINK_NUMBER_1 1
2814#define LPFC_LINK_NUMBER_2 2
2815#define LPFC_LINK_NUMBER_3 3
2816 } response;
2817 } u;
2818};
2819
2820/* Mailbox Completion Queue Error Messages */
2821#define MB_CQE_STATUS_SUCCESS 0x0
2822#define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
2823#define MB_CQE_STATUS_INVALID_PARAMETER 0x2
2824#define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
2825#define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
2826#define MB_CQE_STATUS_DMA_FAILED 0x5
2827
2828#define LPFC_MBX_WR_CONFIG_MAX_BDE 8
2829struct lpfc_mbx_wr_object {
2830 struct mbox_header header;
2831 union {
2832 struct {
2833 uint32_t word4;
2834#define lpfc_wr_object_eof_SHIFT 31
2835#define lpfc_wr_object_eof_MASK 0x00000001
2836#define lpfc_wr_object_eof_WORD word4
2837#define lpfc_wr_object_write_length_SHIFT 0
2838#define lpfc_wr_object_write_length_MASK 0x00FFFFFF
2839#define lpfc_wr_object_write_length_WORD word4
2840 uint32_t write_offset;
2841 uint32_t object_name[26];
2842 uint32_t bde_count;
2843 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
2844 } request;
2845 struct {
2846 uint32_t actual_write_length;
2847 } response;
2848 } u;
2849};
2850
2851/* mailbox queue entry structure */
2852struct lpfc_mqe {
2853 uint32_t word0;
2854#define lpfc_mqe_status_SHIFT 16
2855#define lpfc_mqe_status_MASK 0x0000FFFF
2856#define lpfc_mqe_status_WORD word0
2857#define lpfc_mqe_command_SHIFT 8
2858#define lpfc_mqe_command_MASK 0x000000FF
2859#define lpfc_mqe_command_WORD word0
2860 union {
2861 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
2862 /* sli4 mailbox commands */
2863 struct lpfc_mbx_sli4_config sli4_config;
2864 struct lpfc_mbx_init_vfi init_vfi;
2865 struct lpfc_mbx_reg_vfi reg_vfi;
2866 struct lpfc_mbx_reg_vfi unreg_vfi;
2867 struct lpfc_mbx_init_vpi init_vpi;
2868 struct lpfc_mbx_resume_rpi resume_rpi;
2869 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
2870 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
2871 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
2872 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
2873 struct lpfc_mbx_reg_fcfi reg_fcfi;
2874 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
2875 struct lpfc_mbx_mq_create mq_create;
2876 struct lpfc_mbx_mq_create_ext mq_create_ext;
2877 struct lpfc_mbx_eq_create eq_create;
2878 struct lpfc_mbx_cq_create cq_create;
2879 struct lpfc_mbx_wq_create wq_create;
2880 struct lpfc_mbx_rq_create rq_create;
2881 struct lpfc_mbx_mq_destroy mq_destroy;
2882 struct lpfc_mbx_eq_destroy eq_destroy;
2883 struct lpfc_mbx_cq_destroy cq_destroy;
2884 struct lpfc_mbx_wq_destroy wq_destroy;
2885 struct lpfc_mbx_rq_destroy rq_destroy;
2886 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
2887 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
2888 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
2889 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
2890 struct lpfc_mbx_nembed_cmd nembed_cmd;
2891 struct lpfc_mbx_read_rev read_rev;
2892 struct lpfc_mbx_read_vpi read_vpi;
2893 struct lpfc_mbx_read_config rd_config;
2894 struct lpfc_mbx_request_features req_ftrs;
2895 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
2896 struct lpfc_mbx_query_fw_cfg query_fw_cfg;
2897 struct lpfc_mbx_supp_pages supp_pages;
2898 struct lpfc_mbx_pc_sli4_params sli4_params;
2899 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
2900 struct lpfc_mbx_set_link_diag_state link_diag_state;
2901 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
2902 struct lpfc_mbx_run_link_diag_test link_diag_test;
2903 struct lpfc_mbx_get_func_cfg get_func_cfg;
2904 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
2905 struct lpfc_mbx_wr_object wr_object;
2906 struct lpfc_mbx_get_port_name get_port_name;
2907 struct lpfc_mbx_nop nop;
2908 } un;
2909};
2910
2911struct lpfc_mcqe {
2912 uint32_t word0;
2913#define lpfc_mcqe_status_SHIFT 0
2914#define lpfc_mcqe_status_MASK 0x0000FFFF
2915#define lpfc_mcqe_status_WORD word0
2916#define lpfc_mcqe_ext_status_SHIFT 16
2917#define lpfc_mcqe_ext_status_MASK 0x0000FFFF
2918#define lpfc_mcqe_ext_status_WORD word0
2919 uint32_t mcqe_tag0;
2920 uint32_t mcqe_tag1;
2921 uint32_t trailer;
2922#define lpfc_trailer_valid_SHIFT 31
2923#define lpfc_trailer_valid_MASK 0x00000001
2924#define lpfc_trailer_valid_WORD trailer
2925#define lpfc_trailer_async_SHIFT 30
2926#define lpfc_trailer_async_MASK 0x00000001
2927#define lpfc_trailer_async_WORD trailer
2928#define lpfc_trailer_hpi_SHIFT 29
2929#define lpfc_trailer_hpi_MASK 0x00000001
2930#define lpfc_trailer_hpi_WORD trailer
2931#define lpfc_trailer_completed_SHIFT 28
2932#define lpfc_trailer_completed_MASK 0x00000001
2933#define lpfc_trailer_completed_WORD trailer
2934#define lpfc_trailer_consumed_SHIFT 27
2935#define lpfc_trailer_consumed_MASK 0x00000001
2936#define lpfc_trailer_consumed_WORD trailer
2937#define lpfc_trailer_type_SHIFT 16
2938#define lpfc_trailer_type_MASK 0x000000FF
2939#define lpfc_trailer_type_WORD trailer
2940#define lpfc_trailer_code_SHIFT 8
2941#define lpfc_trailer_code_MASK 0x000000FF
2942#define lpfc_trailer_code_WORD trailer
2943#define LPFC_TRAILER_CODE_LINK 0x1
2944#define LPFC_TRAILER_CODE_FCOE 0x2
2945#define LPFC_TRAILER_CODE_DCBX 0x3
2946#define LPFC_TRAILER_CODE_GRP5 0x5
2947#define LPFC_TRAILER_CODE_FC 0x10
2948#define LPFC_TRAILER_CODE_SLI 0x11
2949};
2950
2951struct lpfc_acqe_link {
2952 uint32_t word0;
2953#define lpfc_acqe_link_speed_SHIFT 24
2954#define lpfc_acqe_link_speed_MASK 0x000000FF
2955#define lpfc_acqe_link_speed_WORD word0
2956#define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
2957#define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
2958#define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
2959#define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
2960#define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
2961#define lpfc_acqe_link_duplex_SHIFT 16
2962#define lpfc_acqe_link_duplex_MASK 0x000000FF
2963#define lpfc_acqe_link_duplex_WORD word0
2964#define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
2965#define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
2966#define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
2967#define lpfc_acqe_link_status_SHIFT 8
2968#define lpfc_acqe_link_status_MASK 0x000000FF
2969#define lpfc_acqe_link_status_WORD word0
2970#define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
2971#define LPFC_ASYNC_LINK_STATUS_UP 0x1
2972#define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
2973#define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
2974#define lpfc_acqe_link_type_SHIFT 6
2975#define lpfc_acqe_link_type_MASK 0x00000003
2976#define lpfc_acqe_link_type_WORD word0
2977#define lpfc_acqe_link_number_SHIFT 0
2978#define lpfc_acqe_link_number_MASK 0x0000003F
2979#define lpfc_acqe_link_number_WORD word0
2980 uint32_t word1;
2981#define lpfc_acqe_link_fault_SHIFT 0
2982#define lpfc_acqe_link_fault_MASK 0x000000FF
2983#define lpfc_acqe_link_fault_WORD word1
2984#define LPFC_ASYNC_LINK_FAULT_NONE 0x0
2985#define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
2986#define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
2987#define lpfc_acqe_logical_link_speed_SHIFT 16
2988#define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
2989#define lpfc_acqe_logical_link_speed_WORD word1
2990 uint32_t event_tag;
2991 uint32_t trailer;
2992#define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
2993#define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
2994};
2995
2996struct lpfc_acqe_fip {
2997 uint32_t index;
2998 uint32_t word1;
2999#define lpfc_acqe_fip_fcf_count_SHIFT 0
3000#define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
3001#define lpfc_acqe_fip_fcf_count_WORD word1
3002#define lpfc_acqe_fip_event_type_SHIFT 16
3003#define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
3004#define lpfc_acqe_fip_event_type_WORD word1
3005 uint32_t event_tag;
3006 uint32_t trailer;
3007#define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
3008#define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
3009#define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
3010#define LPFC_FIP_EVENT_TYPE_CVL 0x4
3011#define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
3012};
3013
3014struct lpfc_acqe_dcbx {
3015 uint32_t tlv_ttl;
3016 uint32_t reserved;
3017 uint32_t event_tag;
3018 uint32_t trailer;
3019};
3020
3021struct lpfc_acqe_grp5 {
3022 uint32_t word0;
3023#define lpfc_acqe_grp5_type_SHIFT 6
3024#define lpfc_acqe_grp5_type_MASK 0x00000003
3025#define lpfc_acqe_grp5_type_WORD word0
3026#define lpfc_acqe_grp5_number_SHIFT 0
3027#define lpfc_acqe_grp5_number_MASK 0x0000003F
3028#define lpfc_acqe_grp5_number_WORD word0
3029 uint32_t word1;
3030#define lpfc_acqe_grp5_llink_spd_SHIFT 16
3031#define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
3032#define lpfc_acqe_grp5_llink_spd_WORD word1
3033 uint32_t event_tag;
3034 uint32_t trailer;
3035};
3036
3037struct lpfc_acqe_fc_la {
3038 uint32_t word0;
3039#define lpfc_acqe_fc_la_speed_SHIFT 24
3040#define lpfc_acqe_fc_la_speed_MASK 0x000000FF
3041#define lpfc_acqe_fc_la_speed_WORD word0
3042#define LPFC_FC_LA_SPEED_UNKOWN 0x0
3043#define LPFC_FC_LA_SPEED_1G 0x1
3044#define LPFC_FC_LA_SPEED_2G 0x2
3045#define LPFC_FC_LA_SPEED_4G 0x4
3046#define LPFC_FC_LA_SPEED_8G 0x8
3047#define LPFC_FC_LA_SPEED_10G 0xA
3048#define LPFC_FC_LA_SPEED_16G 0x10
3049#define lpfc_acqe_fc_la_topology_SHIFT 16
3050#define lpfc_acqe_fc_la_topology_MASK 0x000000FF
3051#define lpfc_acqe_fc_la_topology_WORD word0
3052#define LPFC_FC_LA_TOP_UNKOWN 0x0
3053#define LPFC_FC_LA_TOP_P2P 0x1
3054#define LPFC_FC_LA_TOP_FCAL 0x2
3055#define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
3056#define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
3057#define lpfc_acqe_fc_la_att_type_SHIFT 8
3058#define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
3059#define lpfc_acqe_fc_la_att_type_WORD word0
3060#define LPFC_FC_LA_TYPE_LINK_UP 0x1
3061#define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
3062#define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
3063#define lpfc_acqe_fc_la_port_type_SHIFT 6
3064#define lpfc_acqe_fc_la_port_type_MASK 0x00000003
3065#define lpfc_acqe_fc_la_port_type_WORD word0
3066#define LPFC_LINK_TYPE_ETHERNET 0x0
3067#define LPFC_LINK_TYPE_FC 0x1
3068#define lpfc_acqe_fc_la_port_number_SHIFT 0
3069#define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
3070#define lpfc_acqe_fc_la_port_number_WORD word0
3071 uint32_t word1;
3072#define lpfc_acqe_fc_la_llink_spd_SHIFT 16
3073#define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
3074#define lpfc_acqe_fc_la_llink_spd_WORD word1
3075#define lpfc_acqe_fc_la_fault_SHIFT 0
3076#define lpfc_acqe_fc_la_fault_MASK 0x000000FF
3077#define lpfc_acqe_fc_la_fault_WORD word1
3078#define LPFC_FC_LA_FAULT_NONE 0x0
3079#define LPFC_FC_LA_FAULT_LOCAL 0x1
3080#define LPFC_FC_LA_FAULT_REMOTE 0x2
3081 uint32_t event_tag;
3082 uint32_t trailer;
3083#define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
3084#define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
3085};
3086
3087struct lpfc_acqe_sli {
3088 uint32_t event_data1;
3089 uint32_t event_data2;
3090 uint32_t reserved;
3091 uint32_t trailer;
3092#define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
3093#define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
3094#define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
3095#define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
3096#define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
3097};
3098
3099/*
3100 * Define the bootstrap mailbox (bmbx) region used to communicate
3101 * mailbox command between the host and port. The mailbox consists
3102 * of a payload area of 256 bytes and a completion queue of length
3103 * 16 bytes.
3104 */
3105struct lpfc_bmbx_create {
3106 struct lpfc_mqe mqe;
3107 struct lpfc_mcqe mcqe;
3108};
3109
3110#define SGL_ALIGN_SZ 64
3111#define SGL_PAGE_SIZE 4096
3112/* align SGL addr on a size boundary - adjust address up */
3113#define NO_XRI 0xffff
3114
3115struct wqe_common {
3116 uint32_t word6;
3117#define wqe_xri_tag_SHIFT 0
3118#define wqe_xri_tag_MASK 0x0000FFFF
3119#define wqe_xri_tag_WORD word6
3120#define wqe_ctxt_tag_SHIFT 16
3121#define wqe_ctxt_tag_MASK 0x0000FFFF
3122#define wqe_ctxt_tag_WORD word6
3123 uint32_t word7;
3124#define wqe_dif_SHIFT 0
3125#define wqe_dif_MASK 0x00000003
3126#define wqe_dif_WORD word7
3127#define wqe_ct_SHIFT 2
3128#define wqe_ct_MASK 0x00000003
3129#define wqe_ct_WORD word7
3130#define wqe_status_SHIFT 4
3131#define wqe_status_MASK 0x0000000f
3132#define wqe_status_WORD word7
3133#define wqe_cmnd_SHIFT 8
3134#define wqe_cmnd_MASK 0x000000ff
3135#define wqe_cmnd_WORD word7
3136#define wqe_class_SHIFT 16
3137#define wqe_class_MASK 0x00000007
3138#define wqe_class_WORD word7
3139#define wqe_ar_SHIFT 19
3140#define wqe_ar_MASK 0x00000001
3141#define wqe_ar_WORD word7
3142#define wqe_ag_SHIFT wqe_ar_SHIFT
3143#define wqe_ag_MASK wqe_ar_MASK
3144#define wqe_ag_WORD wqe_ar_WORD
3145#define wqe_pu_SHIFT 20
3146#define wqe_pu_MASK 0x00000003
3147#define wqe_pu_WORD word7
3148#define wqe_erp_SHIFT 22
3149#define wqe_erp_MASK 0x00000001
3150#define wqe_erp_WORD word7
3151#define wqe_conf_SHIFT wqe_erp_SHIFT
3152#define wqe_conf_MASK wqe_erp_MASK
3153#define wqe_conf_WORD wqe_erp_WORD
3154#define wqe_lnk_SHIFT 23
3155#define wqe_lnk_MASK 0x00000001
3156#define wqe_lnk_WORD word7
3157#define wqe_tmo_SHIFT 24
3158#define wqe_tmo_MASK 0x000000ff
3159#define wqe_tmo_WORD word7
3160 uint32_t abort_tag; /* word 8 in WQE */
3161 uint32_t word9;
3162#define wqe_reqtag_SHIFT 0
3163#define wqe_reqtag_MASK 0x0000FFFF
3164#define wqe_reqtag_WORD word9
3165#define wqe_temp_rpi_SHIFT 16
3166#define wqe_temp_rpi_MASK 0x0000FFFF
3167#define wqe_temp_rpi_WORD word9
3168#define wqe_rcvoxid_SHIFT 16
3169#define wqe_rcvoxid_MASK 0x0000FFFF
3170#define wqe_rcvoxid_WORD word9
3171 uint32_t word10;
3172#define wqe_ebde_cnt_SHIFT 0
3173#define wqe_ebde_cnt_MASK 0x0000000f
3174#define wqe_ebde_cnt_WORD word10
3175#define wqe_lenloc_SHIFT 7
3176#define wqe_lenloc_MASK 0x00000003
3177#define wqe_lenloc_WORD word10
3178#define LPFC_WQE_LENLOC_NONE 0
3179#define LPFC_WQE_LENLOC_WORD3 1
3180#define LPFC_WQE_LENLOC_WORD12 2
3181#define LPFC_WQE_LENLOC_WORD4 3
3182#define wqe_qosd_SHIFT 9
3183#define wqe_qosd_MASK 0x00000001
3184#define wqe_qosd_WORD word10
3185#define wqe_xbl_SHIFT 11
3186#define wqe_xbl_MASK 0x00000001
3187#define wqe_xbl_WORD word10
3188#define wqe_iod_SHIFT 13
3189#define wqe_iod_MASK 0x00000001
3190#define wqe_iod_WORD word10
3191#define LPFC_WQE_IOD_WRITE 0
3192#define LPFC_WQE_IOD_READ 1
3193#define wqe_dbde_SHIFT 14
3194#define wqe_dbde_MASK 0x00000001
3195#define wqe_dbde_WORD word10
3196#define wqe_wqes_SHIFT 15
3197#define wqe_wqes_MASK 0x00000001
3198#define wqe_wqes_WORD word10
3199/* Note that this field overlaps above fields */
3200#define wqe_wqid_SHIFT 1
3201#define wqe_wqid_MASK 0x00007fff
3202#define wqe_wqid_WORD word10
3203#define wqe_pri_SHIFT 16
3204#define wqe_pri_MASK 0x00000007
3205#define wqe_pri_WORD word10
3206#define wqe_pv_SHIFT 19
3207#define wqe_pv_MASK 0x00000001
3208#define wqe_pv_WORD word10
3209#define wqe_xc_SHIFT 21
3210#define wqe_xc_MASK 0x00000001
3211#define wqe_xc_WORD word10
3212#define wqe_sr_SHIFT 22
3213#define wqe_sr_MASK 0x00000001
3214#define wqe_sr_WORD word10
3215#define wqe_ccpe_SHIFT 23
3216#define wqe_ccpe_MASK 0x00000001
3217#define wqe_ccpe_WORD word10
3218#define wqe_ccp_SHIFT 24
3219#define wqe_ccp_MASK 0x000000ff
3220#define wqe_ccp_WORD word10
3221 uint32_t word11;
3222#define wqe_cmd_type_SHIFT 0
3223#define wqe_cmd_type_MASK 0x0000000f
3224#define wqe_cmd_type_WORD word11
3225#define wqe_els_id_SHIFT 4
3226#define wqe_els_id_MASK 0x00000003
3227#define wqe_els_id_WORD word11
3228#define LPFC_ELS_ID_FLOGI 3
3229#define LPFC_ELS_ID_FDISC 2
3230#define LPFC_ELS_ID_LOGO 1
3231#define LPFC_ELS_ID_DEFAULT 0
3232#define wqe_wqec_SHIFT 7
3233#define wqe_wqec_MASK 0x00000001
3234#define wqe_wqec_WORD word11
3235#define wqe_cqid_SHIFT 16
3236#define wqe_cqid_MASK 0x0000ffff
3237#define wqe_cqid_WORD word11
3238#define LPFC_WQE_CQ_ID_DEFAULT 0xffff
3239};
3240
3241struct wqe_did {
3242 uint32_t word5;
3243#define wqe_els_did_SHIFT 0
3244#define wqe_els_did_MASK 0x00FFFFFF
3245#define wqe_els_did_WORD word5
3246#define wqe_xmit_bls_pt_SHIFT 28
3247#define wqe_xmit_bls_pt_MASK 0x00000003
3248#define wqe_xmit_bls_pt_WORD word5
3249#define wqe_xmit_bls_ar_SHIFT 30
3250#define wqe_xmit_bls_ar_MASK 0x00000001
3251#define wqe_xmit_bls_ar_WORD word5
3252#define wqe_xmit_bls_xo_SHIFT 31
3253#define wqe_xmit_bls_xo_MASK 0x00000001
3254#define wqe_xmit_bls_xo_WORD word5
3255};
3256
3257struct lpfc_wqe_generic{
3258 struct ulp_bde64 bde;
3259 uint32_t word3;
3260 uint32_t word4;
3261 uint32_t word5;
3262 struct wqe_common wqe_com;
3263 uint32_t payload[4];
3264};
3265
3266struct els_request64_wqe {
3267 struct ulp_bde64 bde;
3268 uint32_t payload_len;
3269 uint32_t word4;
3270#define els_req64_sid_SHIFT 0
3271#define els_req64_sid_MASK 0x00FFFFFF
3272#define els_req64_sid_WORD word4
3273#define els_req64_sp_SHIFT 24
3274#define els_req64_sp_MASK 0x00000001
3275#define els_req64_sp_WORD word4
3276#define els_req64_vf_SHIFT 25
3277#define els_req64_vf_MASK 0x00000001
3278#define els_req64_vf_WORD word4
3279 struct wqe_did wqe_dest;
3280 struct wqe_common wqe_com; /* words 6-11 */
3281 uint32_t word12;
3282#define els_req64_vfid_SHIFT 1
3283#define els_req64_vfid_MASK 0x00000FFF
3284#define els_req64_vfid_WORD word12
3285#define els_req64_pri_SHIFT 13
3286#define els_req64_pri_MASK 0x00000007
3287#define els_req64_pri_WORD word12
3288 uint32_t word13;
3289#define els_req64_hopcnt_SHIFT 24
3290#define els_req64_hopcnt_MASK 0x000000ff
3291#define els_req64_hopcnt_WORD word13
3292 uint32_t reserved[2];
3293};
3294
3295struct xmit_els_rsp64_wqe {
3296 struct ulp_bde64 bde;
3297 uint32_t response_payload_len;
3298 uint32_t word4;
3299#define els_rsp64_sid_SHIFT 0
3300#define els_rsp64_sid_MASK 0x00FFFFFF
3301#define els_rsp64_sid_WORD word4
3302#define els_rsp64_sp_SHIFT 24
3303#define els_rsp64_sp_MASK 0x00000001
3304#define els_rsp64_sp_WORD word4
3305 struct wqe_did wqe_dest;
3306 struct wqe_common wqe_com; /* words 6-11 */
3307 uint32_t word12;
3308#define wqe_rsp_temp_rpi_SHIFT 0
3309#define wqe_rsp_temp_rpi_MASK 0x0000FFFF
3310#define wqe_rsp_temp_rpi_WORD word12
3311 uint32_t rsvd_13_15[3];
3312};
3313
3314struct xmit_bls_rsp64_wqe {
3315 uint32_t payload0;
3316/* Payload0 for BA_ACC */
3317#define xmit_bls_rsp64_acc_seq_id_SHIFT 16
3318#define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
3319#define xmit_bls_rsp64_acc_seq_id_WORD payload0
3320#define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24
3321#define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
3322#define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0
3323/* Payload0 for BA_RJT */
3324#define xmit_bls_rsp64_rjt_vspec_SHIFT 0
3325#define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
3326#define xmit_bls_rsp64_rjt_vspec_WORD payload0
3327#define xmit_bls_rsp64_rjt_expc_SHIFT 8
3328#define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
3329#define xmit_bls_rsp64_rjt_expc_WORD payload0
3330#define xmit_bls_rsp64_rjt_rsnc_SHIFT 16
3331#define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
3332#define xmit_bls_rsp64_rjt_rsnc_WORD payload0
3333 uint32_t word1;
3334#define xmit_bls_rsp64_rxid_SHIFT 0
3335#define xmit_bls_rsp64_rxid_MASK 0x0000ffff
3336#define xmit_bls_rsp64_rxid_WORD word1
3337#define xmit_bls_rsp64_oxid_SHIFT 16
3338#define xmit_bls_rsp64_oxid_MASK 0x0000ffff
3339#define xmit_bls_rsp64_oxid_WORD word1
3340 uint32_t word2;
3341#define xmit_bls_rsp64_seqcnthi_SHIFT 0
3342#define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
3343#define xmit_bls_rsp64_seqcnthi_WORD word2
3344#define xmit_bls_rsp64_seqcntlo_SHIFT 16
3345#define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
3346#define xmit_bls_rsp64_seqcntlo_WORD word2
3347 uint32_t rsrvd3;
3348 uint32_t rsrvd4;
3349 struct wqe_did wqe_dest;
3350 struct wqe_common wqe_com; /* words 6-11 */
3351 uint32_t word12;
3352#define xmit_bls_rsp64_temprpi_SHIFT 0
3353#define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
3354#define xmit_bls_rsp64_temprpi_WORD word12
3355 uint32_t rsvd_13_15[3];
3356};
3357
3358struct wqe_rctl_dfctl {
3359 uint32_t word5;
3360#define wqe_si_SHIFT 2
3361#define wqe_si_MASK 0x000000001
3362#define wqe_si_WORD word5
3363#define wqe_la_SHIFT 3
3364#define wqe_la_MASK 0x000000001
3365#define wqe_la_WORD word5
3366#define wqe_xo_SHIFT 6
3367#define wqe_xo_MASK 0x000000001
3368#define wqe_xo_WORD word5
3369#define wqe_ls_SHIFT 7
3370#define wqe_ls_MASK 0x000000001
3371#define wqe_ls_WORD word5
3372#define wqe_dfctl_SHIFT 8
3373#define wqe_dfctl_MASK 0x0000000ff
3374#define wqe_dfctl_WORD word5
3375#define wqe_type_SHIFT 16
3376#define wqe_type_MASK 0x0000000ff
3377#define wqe_type_WORD word5
3378#define wqe_rctl_SHIFT 24
3379#define wqe_rctl_MASK 0x0000000ff
3380#define wqe_rctl_WORD word5
3381};
3382
3383struct xmit_seq64_wqe {
3384 struct ulp_bde64 bde;
3385 uint32_t rsvd3;
3386 uint32_t relative_offset;
3387 struct wqe_rctl_dfctl wge_ctl;
3388 struct wqe_common wqe_com; /* words 6-11 */
3389 uint32_t xmit_len;
3390 uint32_t rsvd_12_15[3];
3391};
3392struct xmit_bcast64_wqe {
3393 struct ulp_bde64 bde;
3394 uint32_t seq_payload_len;
3395 uint32_t rsvd4;
3396 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
3397 struct wqe_common wqe_com; /* words 6-11 */
3398 uint32_t rsvd_12_15[4];
3399};
3400
3401struct gen_req64_wqe {
3402 struct ulp_bde64 bde;
3403 uint32_t request_payload_len;
3404 uint32_t relative_offset;
3405 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
3406 struct wqe_common wqe_com; /* words 6-11 */
3407 uint32_t rsvd_12_15[4];
3408};
3409
3410struct create_xri_wqe {
3411 uint32_t rsrvd[5]; /* words 0-4 */
3412 struct wqe_did wqe_dest; /* word 5 */
3413 struct wqe_common wqe_com; /* words 6-11 */
3414 uint32_t rsvd_12_15[4]; /* word 12-15 */
3415};
3416
3417#define T_REQUEST_TAG 3
3418#define T_XRI_TAG 1
3419
3420struct abort_cmd_wqe {
3421 uint32_t rsrvd[3];
3422 uint32_t word3;
3423#define abort_cmd_ia_SHIFT 0
3424#define abort_cmd_ia_MASK 0x000000001
3425#define abort_cmd_ia_WORD word3
3426#define abort_cmd_criteria_SHIFT 8
3427#define abort_cmd_criteria_MASK 0x0000000ff
3428#define abort_cmd_criteria_WORD word3
3429 uint32_t rsrvd4;
3430 uint32_t rsrvd5;
3431 struct wqe_common wqe_com; /* words 6-11 */
3432 uint32_t rsvd_12_15[4]; /* word 12-15 */
3433};
3434
3435struct fcp_iwrite64_wqe {
3436 struct ulp_bde64 bde;
3437 uint32_t payload_offset_len;
3438 uint32_t total_xfer_len;
3439 uint32_t initial_xfer_len;
3440 struct wqe_common wqe_com; /* words 6-11 */
3441 uint32_t rsrvd12;
3442 struct ulp_bde64 ph_bde; /* words 13-15 */
3443};
3444
3445struct fcp_iread64_wqe {
3446 struct ulp_bde64 bde;
3447 uint32_t payload_offset_len; /* word 3 */
3448 uint32_t total_xfer_len; /* word 4 */
3449 uint32_t rsrvd5; /* word 5 */
3450 struct wqe_common wqe_com; /* words 6-11 */
3451 uint32_t rsrvd12;
3452 struct ulp_bde64 ph_bde; /* words 13-15 */
3453};
3454
3455struct fcp_icmnd64_wqe {
3456 struct ulp_bde64 bde; /* words 0-2 */
3457 uint32_t rsrvd3; /* word 3 */
3458 uint32_t rsrvd4; /* word 4 */
3459 uint32_t rsrvd5; /* word 5 */
3460 struct wqe_common wqe_com; /* words 6-11 */
3461 uint32_t rsvd_12_15[4]; /* word 12-15 */
3462};
3463
3464
3465union lpfc_wqe {
3466 uint32_t words[16];
3467 struct lpfc_wqe_generic generic;
3468 struct fcp_icmnd64_wqe fcp_icmd;
3469 struct fcp_iread64_wqe fcp_iread;
3470 struct fcp_iwrite64_wqe fcp_iwrite;
3471 struct abort_cmd_wqe abort_cmd;
3472 struct create_xri_wqe create_xri;
3473 struct xmit_bcast64_wqe xmit_bcast64;
3474 struct xmit_seq64_wqe xmit_sequence;
3475 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
3476 struct xmit_els_rsp64_wqe xmit_els_rsp;
3477 struct els_request64_wqe els_req;
3478 struct gen_req64_wqe gen_req;
3479};
3480
3481#define LPFC_GROUP_OJECT_MAGIC_NUM 0xfeaa0001
3482#define LPFC_FILE_TYPE_GROUP 0xf7
3483#define LPFC_FILE_ID_GROUP 0xa2
3484struct lpfc_grp_hdr {
3485 uint32_t size;
3486 uint32_t magic_number;
3487 uint32_t word2;
3488#define lpfc_grp_hdr_file_type_SHIFT 24
3489#define lpfc_grp_hdr_file_type_MASK 0x000000FF
3490#define lpfc_grp_hdr_file_type_WORD word2
3491#define lpfc_grp_hdr_id_SHIFT 16
3492#define lpfc_grp_hdr_id_MASK 0x000000FF
3493#define lpfc_grp_hdr_id_WORD word2
3494 uint8_t rev_name[128];
3495 uint8_t date[12];
3496 uint8_t revision[32];
3497};
3498
3499#define FCP_COMMAND 0x0
3500#define FCP_COMMAND_DATA_OUT 0x1
3501#define ELS_COMMAND_NON_FIP 0xC
3502#define ELS_COMMAND_FIP 0xD
3503#define OTHER_COMMAND 0x8
3504
3505#define LPFC_FW_DUMP 1
3506#define LPFC_FW_RESET 2
3507#define LPFC_DV_RESET 3