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1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29#include <linux/etherdevice.h>
30#include <linux/slab.h>
31#include <linux/sched.h>
32
33#include "iwl-debug.h"
34#include "iwl-csr.h"
35#include "iwl-prph.h"
36#include "iwl-io.h"
37#include "iwl-agn-hw.h"
38#include "iwl-op-mode.h"
39#include "iwl-trans-pcie-int.h"
40/* FIXME: need to abstract out TX command (once we know what it looks like) */
41#include "iwl-commands.h"
42
43#define IWL_TX_CRC_SIZE 4
44#define IWL_TX_DELIMITER_SIZE 4
45
46/**
47 * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
48 */
49void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
50 struct iwl_tx_queue *txq,
51 u16 byte_cnt)
52{
53 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
54 struct iwl_trans_pcie *trans_pcie =
55 IWL_TRANS_GET_PCIE_TRANS(trans);
56 int write_ptr = txq->q.write_ptr;
57 int txq_id = txq->q.id;
58 u8 sec_ctl = 0;
59 u8 sta_id = 0;
60 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
61 __le16 bc_ent;
62 struct iwl_tx_cmd *tx_cmd =
63 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
64
65 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
66
67 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
68
69 sta_id = tx_cmd->sta_id;
70 sec_ctl = tx_cmd->sec_ctl;
71
72 switch (sec_ctl & TX_CMD_SEC_MSK) {
73 case TX_CMD_SEC_CCM:
74 len += CCMP_MIC_LEN;
75 break;
76 case TX_CMD_SEC_TKIP:
77 len += TKIP_ICV_LEN;
78 break;
79 case TX_CMD_SEC_WEP:
80 len += WEP_IV_LEN + WEP_ICV_LEN;
81 break;
82 }
83
84 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
85
86 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
87
88 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
89 scd_bc_tbl[txq_id].
90 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
91}
92
93/**
94 * iwl_txq_update_write_ptr - Send new write index to hardware
95 */
96void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
97{
98 u32 reg = 0;
99 int txq_id = txq->q.id;
100
101 if (txq->need_update == 0)
102 return;
103
104 if (trans->cfg->base_params->shadow_reg_enable) {
105 /* shadow register enabled */
106 iwl_write32(trans, HBUS_TARG_WRPTR,
107 txq->q.write_ptr | (txq_id << 8));
108 } else {
109 struct iwl_trans_pcie *trans_pcie =
110 IWL_TRANS_GET_PCIE_TRANS(trans);
111 /* if we're trying to save power */
112 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
113 /* wake up nic if it's powered down ...
114 * uCode will wake up, and interrupt us again, so next
115 * time we'll skip this part. */
116 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
117
118 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
119 IWL_DEBUG_INFO(trans,
120 "Tx queue %d requesting wakeup,"
121 " GP1 = 0x%x\n", txq_id, reg);
122 iwl_set_bit(trans, CSR_GP_CNTRL,
123 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
124 return;
125 }
126
127 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
128 txq->q.write_ptr | (txq_id << 8));
129
130 /*
131 * else not in power-save mode,
132 * uCode will never sleep when we're
133 * trying to tx (during RFKILL, we're not trying to tx).
134 */
135 } else
136 iwl_write32(trans, HBUS_TARG_WRPTR,
137 txq->q.write_ptr | (txq_id << 8));
138 }
139 txq->need_update = 0;
140}
141
142static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
143{
144 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
145
146 dma_addr_t addr = get_unaligned_le32(&tb->lo);
147 if (sizeof(dma_addr_t) > sizeof(u32))
148 addr |=
149 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
150
151 return addr;
152}
153
154static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
155{
156 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
157
158 return le16_to_cpu(tb->hi_n_len) >> 4;
159}
160
161static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
162 dma_addr_t addr, u16 len)
163{
164 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
165 u16 hi_n_len = len << 4;
166
167 put_unaligned_le32(addr, &tb->lo);
168 if (sizeof(dma_addr_t) > sizeof(u32))
169 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
170
171 tb->hi_n_len = cpu_to_le16(hi_n_len);
172
173 tfd->num_tbs = idx + 1;
174}
175
176static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
177{
178 return tfd->num_tbs & 0x1f;
179}
180
181static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
182 struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
183{
184 int i;
185 int num_tbs;
186
187 /* Sanity check on number of chunks */
188 num_tbs = iwl_tfd_get_num_tbs(tfd);
189
190 if (num_tbs >= IWL_NUM_OF_TBS) {
191 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
192 /* @todo issue fatal error, it is quite serious situation */
193 return;
194 }
195
196 /* Unmap tx_cmd */
197 if (num_tbs)
198 dma_unmap_single(trans->dev,
199 dma_unmap_addr(meta, mapping),
200 dma_unmap_len(meta, len),
201 DMA_BIDIRECTIONAL);
202
203 /* Unmap chunks, if any. */
204 for (i = 1; i < num_tbs; i++)
205 dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i),
206 iwl_tfd_tb_get_len(tfd, i), dma_dir);
207
208 tfd->num_tbs = 0;
209}
210
211/**
212 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
213 * @trans - transport private data
214 * @txq - tx queue
215 * @dma_dir - the direction of the DMA mapping
216 *
217 * Does NOT advance any TFD circular buffer read/write indexes
218 * Does NOT free the TFD itself (which is within circular buffer)
219 */
220void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
221 enum dma_data_direction dma_dir)
222{
223 struct iwl_tfd *tfd_tmp = txq->tfds;
224
225 /* rd_ptr is bounded by n_bd and idx is bounded by n_window */
226 int rd_ptr = txq->q.read_ptr;
227 int idx = get_cmd_index(&txq->q, rd_ptr);
228
229 lockdep_assert_held(&txq->lock);
230
231 /* We have only q->n_window txq->entries, but we use q->n_bd tfds */
232 iwlagn_unmap_tfd(trans, &txq->entries[idx].meta,
233 &tfd_tmp[rd_ptr], dma_dir);
234
235 /* free SKB */
236 if (txq->entries) {
237 struct sk_buff *skb;
238
239 skb = txq->entries[idx].skb;
240
241 /* Can be called from irqs-disabled context
242 * If skb is not NULL, it means that the whole queue is being
243 * freed and that the queue is not empty - free the skb
244 */
245 if (skb) {
246 iwl_op_mode_free_skb(trans->op_mode, skb);
247 txq->entries[idx].skb = NULL;
248 }
249 }
250}
251
252int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
253 struct iwl_tx_queue *txq,
254 dma_addr_t addr, u16 len,
255 u8 reset)
256{
257 struct iwl_queue *q;
258 struct iwl_tfd *tfd, *tfd_tmp;
259 u32 num_tbs;
260
261 q = &txq->q;
262 tfd_tmp = txq->tfds;
263 tfd = &tfd_tmp[q->write_ptr];
264
265 if (reset)
266 memset(tfd, 0, sizeof(*tfd));
267
268 num_tbs = iwl_tfd_get_num_tbs(tfd);
269
270 /* Each TFD can point to a maximum 20 Tx buffers */
271 if (num_tbs >= IWL_NUM_OF_TBS) {
272 IWL_ERR(trans, "Error can not send more than %d chunks\n",
273 IWL_NUM_OF_TBS);
274 return -EINVAL;
275 }
276
277 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
278 return -EINVAL;
279
280 if (unlikely(addr & ~IWL_TX_DMA_MASK))
281 IWL_ERR(trans, "Unaligned address = %llx\n",
282 (unsigned long long)addr);
283
284 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
285
286 return 0;
287}
288
289/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
290 * DMA services
291 *
292 * Theory of operation
293 *
294 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
295 * of buffer descriptors, each of which points to one or more data buffers for
296 * the device to read from or fill. Driver and device exchange status of each
297 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
298 * entries in each circular buffer, to protect against confusing empty and full
299 * queue states.
300 *
301 * The device reads or writes the data in the queues via the device's several
302 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
303 *
304 * For Tx queue, there are low mark and high mark limits. If, after queuing
305 * the packet for Tx, free space become < low mark, Tx queue stopped. When
306 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
307 * Tx queue resumed.
308 *
309 ***************************************************/
310
311int iwl_queue_space(const struct iwl_queue *q)
312{
313 int s = q->read_ptr - q->write_ptr;
314
315 if (q->read_ptr > q->write_ptr)
316 s -= q->n_bd;
317
318 if (s <= 0)
319 s += q->n_window;
320 /* keep some reserve to not confuse empty and full situations */
321 s -= 2;
322 if (s < 0)
323 s = 0;
324 return s;
325}
326
327/**
328 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
329 */
330int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
331{
332 q->n_bd = count;
333 q->n_window = slots_num;
334 q->id = id;
335
336 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
337 * and iwl_queue_dec_wrap are broken. */
338 if (WARN_ON(!is_power_of_2(count)))
339 return -EINVAL;
340
341 /* slots_num must be power-of-two size, otherwise
342 * get_cmd_index is broken. */
343 if (WARN_ON(!is_power_of_2(slots_num)))
344 return -EINVAL;
345
346 q->low_mark = q->n_window / 4;
347 if (q->low_mark < 4)
348 q->low_mark = 4;
349
350 q->high_mark = q->n_window / 8;
351 if (q->high_mark < 2)
352 q->high_mark = 2;
353
354 q->write_ptr = q->read_ptr = 0;
355
356 return 0;
357}
358
359static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
360 struct iwl_tx_queue *txq)
361{
362 struct iwl_trans_pcie *trans_pcie =
363 IWL_TRANS_GET_PCIE_TRANS(trans);
364 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
365 int txq_id = txq->q.id;
366 int read_ptr = txq->q.read_ptr;
367 u8 sta_id = 0;
368 __le16 bc_ent;
369 struct iwl_tx_cmd *tx_cmd =
370 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
371
372 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
373
374 if (txq_id != trans_pcie->cmd_queue)
375 sta_id = tx_cmd->sta_id;
376
377 bc_ent = cpu_to_le16(1 | (sta_id << 12));
378 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
379
380 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
381 scd_bc_tbl[txq_id].
382 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
383}
384
385static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
386 u16 txq_id)
387{
388 u32 tbl_dw_addr;
389 u32 tbl_dw;
390 u16 scd_q2ratid;
391
392 struct iwl_trans_pcie *trans_pcie =
393 IWL_TRANS_GET_PCIE_TRANS(trans);
394
395 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
396
397 tbl_dw_addr = trans_pcie->scd_base_addr +
398 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
399
400 tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr);
401
402 if (txq_id & 0x1)
403 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
404 else
405 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
406
407 iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw);
408
409 return 0;
410}
411
412static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
413{
414 /* Simply stop the queue, but don't change any configuration;
415 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
416 iwl_write_prph(trans,
417 SCD_QUEUE_STATUS_BITS(txq_id),
418 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
419 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
420}
421
422void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
423 int txq_id, u32 index)
424{
425 IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d\n", txq_id, index & 0xff);
426 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
427 (index & 0xff) | (txq_id << 8));
428 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index);
429}
430
431void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
432 struct iwl_tx_queue *txq,
433 int tx_fifo_id, bool active)
434{
435 int txq_id = txq->q.id;
436
437 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
438 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
439 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
440 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
441 SCD_QUEUE_STTS_REG_MSK);
442
443 if (active)
444 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d\n",
445 txq_id, tx_fifo_id);
446 else
447 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
448}
449
450void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans, int txq_id, int fifo,
451 int sta_id, int tid, int frame_limit, u16 ssn)
452{
453 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
454 unsigned long flags;
455 u16 ra_tid = BUILD_RAxTID(sta_id, tid);
456
457 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
458 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
459
460 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
461
462 /* Stop this Tx queue before configuring it */
463 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
464
465 /* Map receiver-address / traffic-ID to this queue */
466 iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
467
468 /* Set this queue as a chain-building queue */
469 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
470
471 /* enable aggregations for the queue */
472 iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
473
474 /* Place first TFD at index corresponding to start sequence number.
475 * Assumes that ssn_idx is valid (!= 0xFFF) */
476 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
477 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
478 iwl_trans_set_wr_ptrs(trans, txq_id, ssn);
479
480 /* Set up Tx window size and frame limit for this queue */
481 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
482 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
483 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
484 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
485 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
486 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
487
488 iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
489
490 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
491 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
492 fifo, true);
493
494 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
495}
496
497void iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int txq_id)
498{
499 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
500
501 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
502 WARN_ONCE(1, "queue %d not used", txq_id);
503 return;
504 }
505
506 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
507
508 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
509
510 trans_pcie->txq[txq_id].q.read_ptr = 0;
511 trans_pcie->txq[txq_id].q.write_ptr = 0;
512 iwl_trans_set_wr_ptrs(trans, txq_id, 0);
513
514 iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, BIT(txq_id));
515
516 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
517 0, false);
518}
519
520/*************** HOST COMMAND QUEUE FUNCTIONS *****/
521
522/**
523 * iwl_enqueue_hcmd - enqueue a uCode command
524 * @priv: device private data point
525 * @cmd: a point to the ucode command structure
526 *
527 * The function returns < 0 values to indicate the operation is
528 * failed. On success, it turns the index (> 0) of command in the
529 * command queue.
530 */
531static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
532{
533 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
534 struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
535 struct iwl_queue *q = &txq->q;
536 struct iwl_device_cmd *out_cmd;
537 struct iwl_cmd_meta *out_meta;
538 dma_addr_t phys_addr;
539 u32 idx;
540 u16 copy_size, cmd_size;
541 bool had_nocopy = false;
542 int i;
543 u8 *cmd_dest;
544#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
545 const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
546 int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
547 int trace_idx;
548#endif
549
550 copy_size = sizeof(out_cmd->hdr);
551 cmd_size = sizeof(out_cmd->hdr);
552
553 /* need one for the header if the first is NOCOPY */
554 BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
555
556 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
557 if (!cmd->len[i])
558 continue;
559 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
560 had_nocopy = true;
561 } else {
562 /* NOCOPY must not be followed by normal! */
563 if (WARN_ON(had_nocopy))
564 return -EINVAL;
565 copy_size += cmd->len[i];
566 }
567 cmd_size += cmd->len[i];
568 }
569
570 /*
571 * If any of the command structures end up being larger than
572 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
573 * allocated into separate TFDs, then we will need to
574 * increase the size of the buffers.
575 */
576 if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
577 return -EINVAL;
578
579 spin_lock_bh(&txq->lock);
580
581 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
582 spin_unlock_bh(&txq->lock);
583
584 IWL_ERR(trans, "No space in command queue\n");
585 iwl_op_mode_cmd_queue_full(trans->op_mode);
586 return -ENOSPC;
587 }
588
589 idx = get_cmd_index(q, q->write_ptr);
590 out_cmd = txq->entries[idx].cmd;
591 out_meta = &txq->entries[idx].meta;
592
593 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
594 if (cmd->flags & CMD_WANT_SKB)
595 out_meta->source = cmd;
596
597 /* set up the header */
598
599 out_cmd->hdr.cmd = cmd->id;
600 out_cmd->hdr.flags = 0;
601 out_cmd->hdr.sequence =
602 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
603 INDEX_TO_SEQ(q->write_ptr));
604
605 /* and copy the data that needs to be copied */
606
607 cmd_dest = out_cmd->payload;
608 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
609 if (!cmd->len[i])
610 continue;
611 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
612 break;
613 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
614 cmd_dest += cmd->len[i];
615 }
616
617 IWL_DEBUG_HC(trans,
618 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
619 trans_pcie_get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
620 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
621 q->write_ptr, idx, trans_pcie->cmd_queue);
622
623 phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size,
624 DMA_BIDIRECTIONAL);
625 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
626 idx = -ENOMEM;
627 goto out;
628 }
629
630 dma_unmap_addr_set(out_meta, mapping, phys_addr);
631 dma_unmap_len_set(out_meta, len, copy_size);
632
633 iwlagn_txq_attach_buf_to_tfd(trans, txq,
634 phys_addr, copy_size, 1);
635#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
636 trace_bufs[0] = &out_cmd->hdr;
637 trace_lens[0] = copy_size;
638 trace_idx = 1;
639#endif
640
641 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
642 if (!cmd->len[i])
643 continue;
644 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
645 continue;
646 phys_addr = dma_map_single(trans->dev,
647 (void *)cmd->data[i],
648 cmd->len[i], DMA_BIDIRECTIONAL);
649 if (dma_mapping_error(trans->dev, phys_addr)) {
650 iwlagn_unmap_tfd(trans, out_meta,
651 &txq->tfds[q->write_ptr],
652 DMA_BIDIRECTIONAL);
653 idx = -ENOMEM;
654 goto out;
655 }
656
657 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
658 cmd->len[i], 0);
659#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
660 trace_bufs[trace_idx] = cmd->data[i];
661 trace_lens[trace_idx] = cmd->len[i];
662 trace_idx++;
663#endif
664 }
665
666 out_meta->flags = cmd->flags;
667
668 txq->need_update = 1;
669
670 /* check that tracing gets all possible blocks */
671 BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
672#ifdef CONFIG_IWLWIFI_DEVICE_TRACING
673 trace_iwlwifi_dev_hcmd(trans->dev, cmd->flags,
674 trace_bufs[0], trace_lens[0],
675 trace_bufs[1], trace_lens[1],
676 trace_bufs[2], trace_lens[2]);
677#endif
678
679 /* start timer if queue currently empty */
680 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
681 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
682
683 /* Increment and update queue's write index */
684 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
685 iwl_txq_update_write_ptr(trans, txq);
686
687 out:
688 spin_unlock_bh(&txq->lock);
689 return idx;
690}
691
692static inline void iwl_queue_progress(struct iwl_trans_pcie *trans_pcie,
693 struct iwl_tx_queue *txq)
694{
695 if (!trans_pcie->wd_timeout)
696 return;
697
698 /*
699 * if empty delete timer, otherwise move timer forward
700 * since we're making progress on this queue
701 */
702 if (txq->q.read_ptr == txq->q.write_ptr)
703 del_timer(&txq->stuck_timer);
704 else
705 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
706}
707
708/**
709 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
710 *
711 * When FW advances 'R' index, all entries between old and new 'R' index
712 * need to be reclaimed. As result, some free space forms. If there is
713 * enough free space (> low mark), wake the stack that feeds us.
714 */
715static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id,
716 int idx)
717{
718 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
719 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
720 struct iwl_queue *q = &txq->q;
721 int nfreed = 0;
722
723 lockdep_assert_held(&txq->lock);
724
725 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
726 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
727 "index %d is out of range [0-%d] %d %d.\n", __func__,
728 txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
729 return;
730 }
731
732 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
733 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
734
735 if (nfreed++ > 0) {
736 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx,
737 q->write_ptr, q->read_ptr);
738 iwl_op_mode_nic_error(trans->op_mode);
739 }
740
741 }
742
743 iwl_queue_progress(trans_pcie, txq);
744}
745
746/**
747 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
748 * @rxb: Rx buffer to reclaim
749 * @handler_status: return value of the handler of the command
750 * (put in setup_rx_handlers)
751 *
752 * If an Rx buffer has an async callback associated with it the callback
753 * will be executed. The attached skb (if present) will only be freed
754 * if the callback returns 1
755 */
756void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_cmd_buffer *rxb,
757 int handler_status)
758{
759 struct iwl_rx_packet *pkt = rxb_addr(rxb);
760 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
761 int txq_id = SEQ_TO_QUEUE(sequence);
762 int index = SEQ_TO_INDEX(sequence);
763 int cmd_index;
764 struct iwl_device_cmd *cmd;
765 struct iwl_cmd_meta *meta;
766 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
767 struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
768
769 /* If a Tx command is being handled and it isn't in the actual
770 * command queue then there a command routing bug has been introduced
771 * in the queue management code. */
772 if (WARN(txq_id != trans_pcie->cmd_queue,
773 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
774 txq_id, trans_pcie->cmd_queue, sequence,
775 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
776 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
777 iwl_print_hex_error(trans, pkt, 32);
778 return;
779 }
780
781 spin_lock(&txq->lock);
782
783 cmd_index = get_cmd_index(&txq->q, index);
784 cmd = txq->entries[cmd_index].cmd;
785 meta = &txq->entries[cmd_index].meta;
786
787 iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
788 DMA_BIDIRECTIONAL);
789
790 /* Input error checking is done when commands are added to queue. */
791 if (meta->flags & CMD_WANT_SKB) {
792 struct page *p = rxb_steal_page(rxb);
793
794 meta->source->resp_pkt = pkt;
795 meta->source->_rx_page_addr = (unsigned long)page_address(p);
796 meta->source->_rx_page_order = trans_pcie->rx_page_order;
797 meta->source->handler_status = handler_status;
798 }
799
800 iwl_hcmd_queue_reclaim(trans, txq_id, index);
801
802 if (!(meta->flags & CMD_ASYNC)) {
803 if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
804 IWL_WARN(trans,
805 "HCMD_ACTIVE already clear for command %s\n",
806 trans_pcie_get_cmd_string(trans_pcie,
807 cmd->hdr.cmd));
808 }
809 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
810 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
811 trans_pcie_get_cmd_string(trans_pcie,
812 cmd->hdr.cmd));
813 wake_up(&trans->wait_command_queue);
814 }
815
816 meta->flags = 0;
817
818 spin_unlock(&txq->lock);
819}
820
821#define HOST_COMPLETE_TIMEOUT (2 * HZ)
822
823static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
824{
825 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
826 int ret;
827
828 /* An asynchronous command can not expect an SKB to be set. */
829 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
830 return -EINVAL;
831
832
833 ret = iwl_enqueue_hcmd(trans, cmd);
834 if (ret < 0) {
835 IWL_ERR(trans,
836 "Error sending %s: enqueue_hcmd failed: %d\n",
837 trans_pcie_get_cmd_string(trans_pcie, cmd->id), ret);
838 return ret;
839 }
840 return 0;
841}
842
843static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
844{
845 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
846 int cmd_idx;
847 int ret;
848
849 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
850 trans_pcie_get_cmd_string(trans_pcie, cmd->id));
851
852 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE,
853 &trans_pcie->status))) {
854 IWL_ERR(trans, "Command %s: a command is already active!\n",
855 trans_pcie_get_cmd_string(trans_pcie, cmd->id));
856 return -EIO;
857 }
858
859 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
860 trans_pcie_get_cmd_string(trans_pcie, cmd->id));
861
862 cmd_idx = iwl_enqueue_hcmd(trans, cmd);
863 if (cmd_idx < 0) {
864 ret = cmd_idx;
865 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
866 IWL_ERR(trans,
867 "Error sending %s: enqueue_hcmd failed: %d\n",
868 trans_pcie_get_cmd_string(trans_pcie, cmd->id), ret);
869 return ret;
870 }
871
872 ret = wait_event_timeout(trans->wait_command_queue,
873 !test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status),
874 HOST_COMPLETE_TIMEOUT);
875 if (!ret) {
876 if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) {
877 struct iwl_tx_queue *txq =
878 &trans_pcie->txq[trans_pcie->cmd_queue];
879 struct iwl_queue *q = &txq->q;
880
881 IWL_ERR(trans,
882 "Error sending %s: time out after %dms.\n",
883 trans_pcie_get_cmd_string(trans_pcie, cmd->id),
884 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
885
886 IWL_ERR(trans,
887 "Current CMD queue read_ptr %d write_ptr %d\n",
888 q->read_ptr, q->write_ptr);
889
890 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
891 IWL_DEBUG_INFO(trans,
892 "Clearing HCMD_ACTIVE for command %s\n",
893 trans_pcie_get_cmd_string(trans_pcie,
894 cmd->id));
895 ret = -ETIMEDOUT;
896 goto cancel;
897 }
898 }
899
900 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
901 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
902 trans_pcie_get_cmd_string(trans_pcie, cmd->id));
903 ret = -EIO;
904 goto cancel;
905 }
906
907 return 0;
908
909cancel:
910 if (cmd->flags & CMD_WANT_SKB) {
911 /*
912 * Cancel the CMD_WANT_SKB flag for the cmd in the
913 * TX cmd queue. Otherwise in case the cmd comes
914 * in later, it will possibly set an invalid
915 * address (cmd->meta.source).
916 */
917 trans_pcie->txq[trans_pcie->cmd_queue].
918 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
919 }
920
921 if (cmd->resp_pkt) {
922 iwl_free_resp(cmd);
923 cmd->resp_pkt = NULL;
924 }
925
926 return ret;
927}
928
929int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
930{
931 if (cmd->flags & CMD_ASYNC)
932 return iwl_send_cmd_async(trans, cmd);
933
934 return iwl_send_cmd_sync(trans, cmd);
935}
936
937/* Frees buffers until index _not_ inclusive */
938int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
939 struct sk_buff_head *skbs)
940{
941 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
942 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
943 struct iwl_queue *q = &txq->q;
944 int last_to_free;
945 int freed = 0;
946
947 /* This function is not meant to release cmd queue*/
948 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
949 return 0;
950
951 lockdep_assert_held(&txq->lock);
952
953 /*Since we free until index _not_ inclusive, the one before index is
954 * the last we will free. This one must be used */
955 last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
956
957 if ((index >= q->n_bd) ||
958 (iwl_queue_used(q, last_to_free) == 0)) {
959 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
960 "last_to_free %d is out of range [0-%d] %d %d.\n",
961 __func__, txq_id, last_to_free, q->n_bd,
962 q->write_ptr, q->read_ptr);
963 return 0;
964 }
965
966 if (WARN_ON(!skb_queue_empty(skbs)))
967 return 0;
968
969 for (;
970 q->read_ptr != index;
971 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
972
973 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
974 continue;
975
976 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
977
978 txq->entries[txq->q.read_ptr].skb = NULL;
979
980 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
981
982 iwlagn_txq_free_tfd(trans, txq, DMA_TO_DEVICE);
983 freed++;
984 }
985
986 iwl_queue_progress(trans_pcie, txq);
987
988 return freed;
989}