Loading...
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/pci_ids.h>
20#include <linux/if_ether.h>
21#include <net/mac80211.h>
22#include <brcm_hw_ids.h>
23#include <aiutils.h>
24#include <chipcommon.h>
25#include "rate.h"
26#include "scb.h"
27#include "phy/phy_hal.h"
28#include "channel.h"
29#include "antsel.h"
30#include "stf.h"
31#include "ampdu.h"
32#include "mac80211_if.h"
33#include "ucode_loader.h"
34#include "main.h"
35#include "soc.h"
36
37/*
38 * Indication for txflowcontrol that all priority bits in
39 * TXQ_STOP_FOR_PRIOFC_MASK are to be considered.
40 */
41#define ALLPRIO -1
42
43/* watchdog timer, in unit of ms */
44#define TIMER_INTERVAL_WATCHDOG 1000
45/* radio monitor timer, in unit of ms */
46#define TIMER_INTERVAL_RADIOCHK 800
47
48/* beacon interval, in unit of 1024TU */
49#define BEACON_INTERVAL_DEFAULT 100
50
51/* n-mode support capability */
52/* 2x2 includes both 1x1 & 2x2 devices
53 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
54 * control it independently
55 */
56#define WL_11N_2x2 1
57#define WL_11N_3x3 3
58#define WL_11N_4x4 4
59
60#define EDCF_ACI_MASK 0x60
61#define EDCF_ACI_SHIFT 5
62#define EDCF_ECWMIN_MASK 0x0f
63#define EDCF_ECWMAX_SHIFT 4
64#define EDCF_AIFSN_MASK 0x0f
65#define EDCF_AIFSN_MAX 15
66#define EDCF_ECWMAX_MASK 0xf0
67
68#define EDCF_AC_BE_TXOP_STA 0x0000
69#define EDCF_AC_BK_TXOP_STA 0x0000
70#define EDCF_AC_VO_ACI_STA 0x62
71#define EDCF_AC_VO_ECW_STA 0x32
72#define EDCF_AC_VI_ACI_STA 0x42
73#define EDCF_AC_VI_ECW_STA 0x43
74#define EDCF_AC_BK_ECW_STA 0xA4
75#define EDCF_AC_VI_TXOP_STA 0x005e
76#define EDCF_AC_VO_TXOP_STA 0x002f
77#define EDCF_AC_BE_ACI_STA 0x03
78#define EDCF_AC_BE_ECW_STA 0xA4
79#define EDCF_AC_BK_ACI_STA 0x27
80#define EDCF_AC_VO_TXOP_AP 0x002f
81
82#define EDCF_TXOP2USEC(txop) ((txop) << 5)
83#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
84
85#define APHY_SYMBOL_TIME 4
86#define APHY_PREAMBLE_TIME 16
87#define APHY_SIGNAL_TIME 4
88#define APHY_SIFS_TIME 16
89#define APHY_SERVICE_NBITS 16
90#define APHY_TAIL_NBITS 6
91#define BPHY_SIFS_TIME 10
92#define BPHY_PLCP_SHORT_TIME 96
93
94#define PREN_PREAMBLE 24
95#define PREN_MM_EXT 12
96#define PREN_PREAMBLE_EXT 4
97
98#define DOT11_MAC_HDR_LEN 24
99#define DOT11_ACK_LEN 10
100#define DOT11_BA_LEN 4
101#define DOT11_OFDM_SIGNAL_EXTENSION 6
102#define DOT11_MIN_FRAG_LEN 256
103#define DOT11_RTS_LEN 16
104#define DOT11_CTS_LEN 10
105#define DOT11_BA_BITMAP_LEN 128
106#define DOT11_MIN_BEACON_PERIOD 1
107#define DOT11_MAX_BEACON_PERIOD 0xFFFF
108#define DOT11_MAXNUMFRAGS 16
109#define DOT11_MAX_FRAG_LEN 2346
110
111#define BPHY_PLCP_TIME 192
112#define RIFS_11N_TIME 2
113
114/* length of the BCN template area */
115#define BCN_TMPL_LEN 512
116
117/* brcms_bss_info flag bit values */
118#define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
119
120/* chip rx buffer offset */
121#define BRCMS_HWRXOFF 38
122
123/* rfdisable delay timer 500 ms, runs of ALP clock */
124#define RFDISABLE_DEFAULT 10000000
125
126#define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
127
128/* precedences numbers for wlc queues. These are twice as may levels as
129 * 802.1D priorities.
130 * Odd numbers are used for HI priority traffic at same precedence levels
131 * These constants are used ONLY by wlc_prio2prec_map. Do not use them
132 * elsewhere.
133 */
134#define _BRCMS_PREC_NONE 0 /* None = - */
135#define _BRCMS_PREC_BK 2 /* BK - Background */
136#define _BRCMS_PREC_BE 4 /* BE - Best-effort */
137#define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */
138#define _BRCMS_PREC_CL 8 /* CL - Controlled Load */
139#define _BRCMS_PREC_VI 10 /* Vi - Video */
140#define _BRCMS_PREC_VO 12 /* Vo - Voice */
141#define _BRCMS_PREC_NC 14 /* NC - Network Control */
142
143/* synthpu_dly times in us */
144#define SYNTHPU_DLY_APHY_US 3700
145#define SYNTHPU_DLY_BPHY_US 1050
146#define SYNTHPU_DLY_NPHY_US 2048
147#define SYNTHPU_DLY_LPPHY_US 300
148
149#define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
150
151/* Per-AC retry limit register definitions; uses defs.h bitfield macros */
152#define EDCF_SHORT_S 0
153#define EDCF_SFB_S 4
154#define EDCF_LONG_S 8
155#define EDCF_LFB_S 12
156#define EDCF_SHORT_M BITFIELD_MASK(4)
157#define EDCF_SFB_M BITFIELD_MASK(4)
158#define EDCF_LONG_M BITFIELD_MASK(4)
159#define EDCF_LFB_M BITFIELD_MASK(4)
160
161#define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
162#define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
163#define RETRY_LONG_DEF 4 /* Default Long retry count */
164#define RETRY_SHORT_FB 3 /* Short count for fb rate */
165#define RETRY_LONG_FB 2 /* Long count for fb rate */
166
167#define APHY_CWMIN 15
168#define PHY_CWMAX 1023
169
170#define EDCF_AIFSN_MIN 1
171
172#define FRAGNUM_MASK 0xF
173
174#define APHY_SLOT_TIME 9
175#define BPHY_SLOT_TIME 20
176
177#define WL_SPURAVOID_OFF 0
178#define WL_SPURAVOID_ON1 1
179#define WL_SPURAVOID_ON2 2
180
181/* invalid core flags, use the saved coreflags */
182#define BRCMS_USE_COREFLAGS 0xffffffff
183
184/* values for PLCPHdr_override */
185#define BRCMS_PLCP_AUTO -1
186#define BRCMS_PLCP_SHORT 0
187#define BRCMS_PLCP_LONG 1
188
189/* values for g_protection_override and n_protection_override */
190#define BRCMS_PROTECTION_AUTO -1
191#define BRCMS_PROTECTION_OFF 0
192#define BRCMS_PROTECTION_ON 1
193#define BRCMS_PROTECTION_MMHDR_ONLY 2
194#define BRCMS_PROTECTION_CTS_ONLY 3
195
196/* values for g_protection_control and n_protection_control */
197#define BRCMS_PROTECTION_CTL_OFF 0
198#define BRCMS_PROTECTION_CTL_LOCAL 1
199#define BRCMS_PROTECTION_CTL_OVERLAP 2
200
201/* values for n_protection */
202#define BRCMS_N_PROTECTION_OFF 0
203#define BRCMS_N_PROTECTION_OPTIONAL 1
204#define BRCMS_N_PROTECTION_20IN40 2
205#define BRCMS_N_PROTECTION_MIXEDMODE 3
206
207/* values for band specific 40MHz capabilities */
208#define BRCMS_N_BW_20ALL 0
209#define BRCMS_N_BW_40ALL 1
210#define BRCMS_N_BW_20IN2G_40IN5G 2
211
212/* bitflags for SGI support (sgi_rx iovar) */
213#define BRCMS_N_SGI_20 0x01
214#define BRCMS_N_SGI_40 0x02
215
216/* defines used by the nrate iovar */
217/* MSC in use,indicates b0-6 holds an mcs */
218#define NRATE_MCS_INUSE 0x00000080
219/* rate/mcs value */
220#define NRATE_RATE_MASK 0x0000007f
221/* stf mode mask: siso, cdd, stbc, sdm */
222#define NRATE_STF_MASK 0x0000ff00
223/* stf mode shift */
224#define NRATE_STF_SHIFT 8
225/* bit indicate to override mcs only */
226#define NRATE_OVERRIDE_MCS_ONLY 0x40000000
227#define NRATE_SGI_MASK 0x00800000 /* sgi mode */
228#define NRATE_SGI_SHIFT 23 /* sgi mode */
229#define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
230#define NRATE_LDPC_SHIFT 22 /* ldpc shift */
231
232#define NRATE_STF_SISO 0 /* stf mode SISO */
233#define NRATE_STF_CDD 1 /* stf mode CDD */
234#define NRATE_STF_STBC 2 /* stf mode STBC */
235#define NRATE_STF_SDM 3 /* stf mode SDM */
236
237#define MAX_DMA_SEGS 4
238
239/* Max # of entries in Tx FIFO based on 4kb page size */
240#define NTXD 256
241/* Max # of entries in Rx FIFO based on 4kb page size */
242#define NRXD 256
243
244/* try to keep this # rbufs posted to the chip */
245#define NRXBUFPOST 32
246
247/* data msg txq hiwat mark */
248#define BRCMS_DATAHIWAT 50
249
250/* max # frames to process in brcms_c_recv() */
251#define RXBND 8
252/* max # tx status to process in wlc_txstatus() */
253#define TXSBND 8
254
255/* brcmu_format_flags() bit description structure */
256struct brcms_c_bit_desc {
257 u32 bit;
258 const char *name;
259};
260
261/*
262 * The following table lists the buffer memory allocated to xmt fifos in HW.
263 * the size is in units of 256bytes(one block), total size is HW dependent
264 * ucode has default fifo partition, sw can overwrite if necessary
265 *
266 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
267 * the twiki is updated before making changes.
268 */
269
270/* Starting corerev for the fifo size table */
271#define XMTFIFOTBL_STARTREV 20
272
273struct d11init {
274 __le16 addr;
275 __le16 size;
276 __le32 value;
277};
278
279struct edcf_acparam {
280 u8 ACI;
281 u8 ECW;
282 u16 TXOP;
283} __packed;
284
285const u8 prio2fifo[NUMPRIO] = {
286 TX_AC_BE_FIFO, /* 0 BE AC_BE Best Effort */
287 TX_AC_BK_FIFO, /* 1 BK AC_BK Background */
288 TX_AC_BK_FIFO, /* 2 -- AC_BK Background */
289 TX_AC_BE_FIFO, /* 3 EE AC_BE Best Effort */
290 TX_AC_VI_FIFO, /* 4 CL AC_VI Video */
291 TX_AC_VI_FIFO, /* 5 VI AC_VI Video */
292 TX_AC_VO_FIFO, /* 6 VO AC_VO Voice */
293 TX_AC_VO_FIFO /* 7 NC AC_VO Voice */
294};
295
296/* debug/trace */
297uint brcm_msg_level =
298#if defined(DEBUG)
299 LOG_ERROR_VAL;
300#else
301 0;
302#endif /* DEBUG */
303
304/* TX FIFO number to WME/802.1E Access Category */
305static const u8 wme_fifo2ac[] = {
306 IEEE80211_AC_BK,
307 IEEE80211_AC_BE,
308 IEEE80211_AC_VI,
309 IEEE80211_AC_VO,
310 IEEE80211_AC_BE,
311 IEEE80211_AC_BE
312};
313
314/* ieee80211 Access Category to TX FIFO number */
315static const u8 wme_ac2fifo[] = {
316 TX_AC_VO_FIFO,
317 TX_AC_VI_FIFO,
318 TX_AC_BE_FIFO,
319 TX_AC_BK_FIFO
320};
321
322/* 802.1D Priority to precedence queue mapping */
323const u8 wlc_prio2prec_map[] = {
324 _BRCMS_PREC_BE, /* 0 BE - Best-effort */
325 _BRCMS_PREC_BK, /* 1 BK - Background */
326 _BRCMS_PREC_NONE, /* 2 None = - */
327 _BRCMS_PREC_EE, /* 3 EE - Excellent-effort */
328 _BRCMS_PREC_CL, /* 4 CL - Controlled Load */
329 _BRCMS_PREC_VI, /* 5 Vi - Video */
330 _BRCMS_PREC_VO, /* 6 Vo - Voice */
331 _BRCMS_PREC_NC, /* 7 NC - Network Control */
332};
333
334static const u16 xmtfifo_sz[][NFIFO] = {
335 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
336 {20, 192, 192, 21, 17, 5},
337 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
338 {9, 58, 22, 14, 14, 5},
339 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
340 {20, 192, 192, 21, 17, 5},
341 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
342 {20, 192, 192, 21, 17, 5},
343 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
344 {9, 58, 22, 14, 14, 5},
345};
346
347#ifdef DEBUG
348static const char * const fifo_names[] = {
349 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
350#else
351static const char fifo_names[6][0];
352#endif
353
354#ifdef DEBUG
355/* pointer to most recently allocated wl/wlc */
356static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
357#endif
358
359/* Find basic rate for a given rate */
360static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
361{
362 if (is_mcs_rate(rspec))
363 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
364 .leg_ofdm];
365 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
366}
367
368static u16 frametype(u32 rspec, u8 mimoframe)
369{
370 if (is_mcs_rate(rspec))
371 return mimoframe;
372 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
373}
374
375/* currently the best mechanism for determining SIFS is the band in use */
376static u16 get_sifs(struct brcms_band *band)
377{
378 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
379 BPHY_SIFS_TIME;
380}
381
382/*
383 * Detect Card removed.
384 * Even checking an sbconfig register read will not false trigger when the core
385 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
386 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
387 * reg with fixed 0/1 pattern (some platforms return all 0).
388 * If clocks are present, call the sb routine which will figure out if the
389 * device is removed.
390 */
391static bool brcms_deviceremoved(struct brcms_c_info *wlc)
392{
393 u32 macctrl;
394
395 if (!wlc->hw->clk)
396 return ai_deviceremoved(wlc->hw->sih);
397 macctrl = bcma_read32(wlc->hw->d11core,
398 D11REGOFFS(maccontrol));
399 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
400}
401
402/* sum the individual fifo tx pending packet counts */
403static s16 brcms_txpktpendtot(struct brcms_c_info *wlc)
404{
405 return wlc->core->txpktpend[0] + wlc->core->txpktpend[1] +
406 wlc->core->txpktpend[2] + wlc->core->txpktpend[3];
407}
408
409static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
410{
411 return wlc->pub->_nbands > 1 && !wlc->bandlocked;
412}
413
414static int brcms_chspec_bw(u16 chanspec)
415{
416 if (CHSPEC_IS40(chanspec))
417 return BRCMS_40_MHZ;
418 if (CHSPEC_IS20(chanspec))
419 return BRCMS_20_MHZ;
420
421 return BRCMS_10_MHZ;
422}
423
424static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
425{
426 if (cfg == NULL)
427 return;
428
429 kfree(cfg->current_bss);
430 kfree(cfg);
431}
432
433static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
434{
435 if (wlc == NULL)
436 return;
437
438 brcms_c_bsscfg_mfree(wlc->bsscfg);
439 kfree(wlc->pub);
440 kfree(wlc->modulecb);
441 kfree(wlc->default_bss);
442 kfree(wlc->protection);
443 kfree(wlc->stf);
444 kfree(wlc->bandstate[0]);
445 kfree(wlc->corestate->macstat_snapshot);
446 kfree(wlc->corestate);
447 kfree(wlc->hw->bandstate[0]);
448 kfree(wlc->hw);
449
450 /* free the wlc */
451 kfree(wlc);
452 wlc = NULL;
453}
454
455static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
456{
457 struct brcms_bss_cfg *cfg;
458
459 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
460 if (cfg == NULL)
461 goto fail;
462
463 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
464 if (cfg->current_bss == NULL)
465 goto fail;
466
467 return cfg;
468
469 fail:
470 brcms_c_bsscfg_mfree(cfg);
471 return NULL;
472}
473
474static struct brcms_c_info *
475brcms_c_attach_malloc(uint unit, uint *err, uint devid)
476{
477 struct brcms_c_info *wlc;
478
479 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
480 if (wlc == NULL) {
481 *err = 1002;
482 goto fail;
483 }
484
485 /* allocate struct brcms_c_pub state structure */
486 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
487 if (wlc->pub == NULL) {
488 *err = 1003;
489 goto fail;
490 }
491 wlc->pub->wlc = wlc;
492
493 /* allocate struct brcms_hardware state structure */
494
495 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
496 if (wlc->hw == NULL) {
497 *err = 1005;
498 goto fail;
499 }
500 wlc->hw->wlc = wlc;
501
502 wlc->hw->bandstate[0] =
503 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
504 if (wlc->hw->bandstate[0] == NULL) {
505 *err = 1006;
506 goto fail;
507 } else {
508 int i;
509
510 for (i = 1; i < MAXBANDS; i++)
511 wlc->hw->bandstate[i] = (struct brcms_hw_band *)
512 ((unsigned long)wlc->hw->bandstate[0] +
513 (sizeof(struct brcms_hw_band) * i));
514 }
515
516 wlc->modulecb =
517 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
518 if (wlc->modulecb == NULL) {
519 *err = 1009;
520 goto fail;
521 }
522
523 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
524 if (wlc->default_bss == NULL) {
525 *err = 1010;
526 goto fail;
527 }
528
529 wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
530 if (wlc->bsscfg == NULL) {
531 *err = 1011;
532 goto fail;
533 }
534
535 wlc->protection = kzalloc(sizeof(struct brcms_protection),
536 GFP_ATOMIC);
537 if (wlc->protection == NULL) {
538 *err = 1016;
539 goto fail;
540 }
541
542 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
543 if (wlc->stf == NULL) {
544 *err = 1017;
545 goto fail;
546 }
547
548 wlc->bandstate[0] =
549 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
550 if (wlc->bandstate[0] == NULL) {
551 *err = 1025;
552 goto fail;
553 } else {
554 int i;
555
556 for (i = 1; i < MAXBANDS; i++)
557 wlc->bandstate[i] = (struct brcms_band *)
558 ((unsigned long)wlc->bandstate[0]
559 + (sizeof(struct brcms_band)*i));
560 }
561
562 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
563 if (wlc->corestate == NULL) {
564 *err = 1026;
565 goto fail;
566 }
567
568 wlc->corestate->macstat_snapshot =
569 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
570 if (wlc->corestate->macstat_snapshot == NULL) {
571 *err = 1027;
572 goto fail;
573 }
574
575 return wlc;
576
577 fail:
578 brcms_c_detach_mfree(wlc);
579 return NULL;
580}
581
582/*
583 * Update the slot timing for standard 11b/g (20us slots)
584 * or shortslot 11g (9us slots)
585 * The PSM needs to be suspended for this call.
586 */
587static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
588 bool shortslot)
589{
590 struct bcma_device *core = wlc_hw->d11core;
591
592 if (shortslot) {
593 /* 11g short slot: 11a timing */
594 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
595 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
596 } else {
597 /* 11g long slot: 11b timing */
598 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
599 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
600 }
601}
602
603/*
604 * calculate frame duration of a given rate and length, return
605 * time in usec unit
606 */
607static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
608 u8 preamble_type, uint mac_len)
609{
610 uint nsyms, dur = 0, Ndps, kNdps;
611 uint rate = rspec2rate(ratespec);
612
613 if (rate == 0) {
614 wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
615 wlc->pub->unit);
616 rate = BRCM_RATE_1M;
617 }
618
619 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
620 wlc->pub->unit, ratespec, preamble_type, mac_len);
621
622 if (is_mcs_rate(ratespec)) {
623 uint mcs = ratespec & RSPEC_RATE_MASK;
624 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
625
626 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
627 if (preamble_type == BRCMS_MM_PREAMBLE)
628 dur += PREN_MM_EXT;
629 /* 1000Ndbps = kbps * 4 */
630 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
631 rspec_issgi(ratespec)) * 4;
632
633 if (rspec_stc(ratespec) == 0)
634 nsyms =
635 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
636 APHY_TAIL_NBITS) * 1000, kNdps);
637 else
638 /* STBC needs to have even number of symbols */
639 nsyms =
640 2 *
641 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
642 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
643
644 dur += APHY_SYMBOL_TIME * nsyms;
645 if (wlc->band->bandtype == BRCM_BAND_2G)
646 dur += DOT11_OFDM_SIGNAL_EXTENSION;
647 } else if (is_ofdm_rate(rate)) {
648 dur = APHY_PREAMBLE_TIME;
649 dur += APHY_SIGNAL_TIME;
650 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
651 Ndps = rate * 2;
652 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
653 nsyms =
654 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
655 Ndps);
656 dur += APHY_SYMBOL_TIME * nsyms;
657 if (wlc->band->bandtype == BRCM_BAND_2G)
658 dur += DOT11_OFDM_SIGNAL_EXTENSION;
659 } else {
660 /*
661 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
662 * will divide out
663 */
664 mac_len = mac_len * 8 * 2;
665 /* calc ceiling of bits/rate = microseconds of air time */
666 dur = (mac_len + rate - 1) / rate;
667 if (preamble_type & BRCMS_SHORT_PREAMBLE)
668 dur += BPHY_PLCP_SHORT_TIME;
669 else
670 dur += BPHY_PLCP_TIME;
671 }
672 return dur;
673}
674
675static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
676 const struct d11init *inits)
677{
678 struct bcma_device *core = wlc_hw->d11core;
679 int i;
680 uint offset;
681 u16 size;
682 u32 value;
683
684 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
685
686 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
687 size = le16_to_cpu(inits[i].size);
688 offset = le16_to_cpu(inits[i].addr);
689 value = le32_to_cpu(inits[i].value);
690 if (size == 2)
691 bcma_write16(core, offset, value);
692 else if (size == 4)
693 bcma_write32(core, offset, value);
694 else
695 break;
696 }
697}
698
699static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
700{
701 u8 idx;
702 u16 addr[] = {
703 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
704 M_HOST_FLAGS5
705 };
706
707 for (idx = 0; idx < MHFMAX; idx++)
708 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
709}
710
711static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
712{
713 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
714 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
715
716 /* init microcode host flags */
717 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
718
719 /* do band-specific ucode IHR, SHM, and SCR inits */
720 if (D11REV_IS(wlc_hw->corerev, 23)) {
721 if (BRCMS_ISNPHY(wlc_hw->band))
722 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
723 else
724 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
725 " %d\n", __func__, wlc_hw->unit,
726 wlc_hw->corerev);
727 } else {
728 if (D11REV_IS(wlc_hw->corerev, 24)) {
729 if (BRCMS_ISLCNPHY(wlc_hw->band))
730 brcms_c_write_inits(wlc_hw,
731 ucode->d11lcn0bsinitvals24);
732 else
733 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
734 " core rev %d\n", __func__,
735 wlc_hw->unit, wlc_hw->corerev);
736 } else {
737 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
738 __func__, wlc_hw->unit, wlc_hw->corerev);
739 }
740 }
741}
742
743static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
744{
745 struct bcma_device *core = wlc_hw->d11core;
746 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
747
748 bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
749}
750
751static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
752{
753 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
754
755 wlc_hw->phyclk = clk;
756
757 if (OFF == clk) { /* clear gmode bit, put phy into reset */
758
759 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
760 (SICF_PRST | SICF_FGC));
761 udelay(1);
762 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
763 udelay(1);
764
765 } else { /* take phy out of reset */
766
767 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
768 udelay(1);
769 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
770 udelay(1);
771
772 }
773}
774
775/* low-level band switch utility routine */
776static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
777{
778 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
779 bandunit);
780
781 wlc_hw->band = wlc_hw->bandstate[bandunit];
782
783 /*
784 * BMAC_NOTE:
785 * until we eliminate need for wlc->band refs in low level code
786 */
787 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
788
789 /* set gmode core flag */
790 if (wlc_hw->sbclk && !wlc_hw->noreset) {
791 u32 gmode = 0;
792
793 if (bandunit == 0)
794 gmode = SICF_GMODE;
795
796 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
797 }
798}
799
800/* switch to new band but leave it inactive */
801static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
802{
803 struct brcms_hardware *wlc_hw = wlc->hw;
804 u32 macintmask;
805 u32 macctrl;
806
807 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
808 macctrl = bcma_read32(wlc_hw->d11core,
809 D11REGOFFS(maccontrol));
810 WARN_ON((macctrl & MCTL_EN_MAC) != 0);
811
812 /* disable interrupts */
813 macintmask = brcms_intrsoff(wlc->wl);
814
815 /* radio off */
816 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
817
818 brcms_b_core_phy_clk(wlc_hw, OFF);
819
820 brcms_c_setxband(wlc_hw, bandunit);
821
822 return macintmask;
823}
824
825/* process an individual struct tx_status */
826static bool
827brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
828{
829 struct sk_buff *p;
830 uint queue;
831 struct d11txh *txh;
832 struct scb *scb = NULL;
833 bool free_pdu;
834 int tx_rts, tx_frame_count, tx_rts_count;
835 uint totlen, supr_status;
836 bool lastframe;
837 struct ieee80211_hdr *h;
838 u16 mcl;
839 struct ieee80211_tx_info *tx_info;
840 struct ieee80211_tx_rate *txrate;
841 int i;
842
843 /* discard intermediate indications for ucode with one legitimate case:
844 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
845 * but the subsequent tx of DATA failed. so it will start rts/cts
846 * from the beginning (resetting the rts transmission count)
847 */
848 if (!(txs->status & TX_STATUS_AMPDU)
849 && (txs->status & TX_STATUS_INTERMEDIATE)) {
850 BCMMSG(wlc->wiphy, "INTERMEDIATE but not AMPDU\n");
851 return false;
852 }
853
854 queue = txs->frameid & TXFID_QUEUE_MASK;
855 if (queue >= NFIFO) {
856 p = NULL;
857 goto fatal;
858 }
859
860 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
861 if (p == NULL)
862 goto fatal;
863
864 txh = (struct d11txh *) (p->data);
865 mcl = le16_to_cpu(txh->MacTxControlLow);
866
867 if (txs->phyerr) {
868 if (brcm_msg_level & LOG_ERROR_VAL) {
869 wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
870 txs->phyerr, txh->MainRates);
871 brcms_c_print_txdesc(txh);
872 }
873 brcms_c_print_txstatus(txs);
874 }
875
876 if (txs->frameid != le16_to_cpu(txh->TxFrameID))
877 goto fatal;
878 tx_info = IEEE80211_SKB_CB(p);
879 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
880
881 if (tx_info->control.sta)
882 scb = &wlc->pri_scb;
883
884 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
885 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
886 return false;
887 }
888
889 supr_status = txs->status & TX_STATUS_SUPR_MASK;
890 if (supr_status == TX_STATUS_SUPR_BADCH)
891 BCMMSG(wlc->wiphy,
892 "%s: Pkt tx suppressed, possibly channel %d\n",
893 __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
894
895 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
896 tx_frame_count =
897 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
898 tx_rts_count =
899 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
900
901 lastframe = !ieee80211_has_morefrags(h->frame_control);
902
903 if (!lastframe) {
904 wiphy_err(wlc->wiphy, "Not last frame!\n");
905 } else {
906 /*
907 * Set information to be consumed by Minstrel ht.
908 *
909 * The "fallback limit" is the number of tx attempts a given
910 * MPDU is sent at the "primary" rate. Tx attempts beyond that
911 * limit are sent at the "secondary" rate.
912 * A 'short frame' does not exceed RTS treshold.
913 */
914 u16 sfbl, /* Short Frame Rate Fallback Limit */
915 lfbl, /* Long Frame Rate Fallback Limit */
916 fbl;
917
918 if (queue < IEEE80211_NUM_ACS) {
919 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
920 EDCF_SFB);
921 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
922 EDCF_LFB);
923 } else {
924 sfbl = wlc->SFBL;
925 lfbl = wlc->LFBL;
926 }
927
928 txrate = tx_info->status.rates;
929 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
930 fbl = lfbl;
931 else
932 fbl = sfbl;
933
934 ieee80211_tx_info_clear_status(tx_info);
935
936 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
937 /*
938 * rate selection requested a fallback rate
939 * and we used it
940 */
941 txrate[0].count = fbl;
942 txrate[1].count = tx_frame_count - fbl;
943 } else {
944 /*
945 * rate selection did not request fallback rate, or
946 * we didn't need it
947 */
948 txrate[0].count = tx_frame_count;
949 /*
950 * rc80211_minstrel.c:minstrel_tx_status() expects
951 * unused rates to be marked with idx = -1
952 */
953 txrate[1].idx = -1;
954 txrate[1].count = 0;
955 }
956
957 /* clear the rest of the rates */
958 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
959 txrate[i].idx = -1;
960 txrate[i].count = 0;
961 }
962
963 if (txs->status & TX_STATUS_ACK_RCV)
964 tx_info->flags |= IEEE80211_TX_STAT_ACK;
965 }
966
967 totlen = p->len;
968 free_pdu = true;
969
970 brcms_c_txfifo_complete(wlc, queue, 1);
971
972 if (lastframe) {
973 /* remove PLCP & Broadcom tx descriptor header */
974 skb_pull(p, D11_PHY_HDR_LEN);
975 skb_pull(p, D11_TXH_LEN);
976 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
977 } else {
978 wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
979 "tx_status\n", __func__);
980 }
981
982 return false;
983
984 fatal:
985 if (p)
986 brcmu_pkt_buf_free_skb(p);
987
988 return true;
989
990}
991
992/* process tx completion events in BMAC
993 * Return true if more tx status need to be processed. false otherwise.
994 */
995static bool
996brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
997{
998 bool morepending = false;
999 struct brcms_c_info *wlc = wlc_hw->wlc;
1000 struct bcma_device *core;
1001 struct tx_status txstatus, *txs;
1002 u32 s1, s2;
1003 uint n = 0;
1004 /*
1005 * Param 'max_tx_num' indicates max. # tx status to process before
1006 * break out.
1007 */
1008 uint max_tx_num = bound ? TXSBND : -1;
1009
1010 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
1011
1012 txs = &txstatus;
1013 core = wlc_hw->d11core;
1014 *fatal = false;
1015 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1016 while (!(*fatal)
1017 && (s1 & TXS_V)) {
1018
1019 if (s1 == 0xffffffff) {
1020 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
1021 wlc_hw->unit, __func__);
1022 return morepending;
1023 }
1024 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1025
1026 txs->status = s1 & TXS_STATUS_MASK;
1027 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1028 txs->sequence = s2 & TXS_SEQ_MASK;
1029 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1030 txs->lasttxtime = 0;
1031
1032 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1033
1034 /* !give others some time to run! */
1035 if (++n >= max_tx_num)
1036 break;
1037 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1038 }
1039
1040 if (*fatal)
1041 return 0;
1042
1043 if (n >= max_tx_num)
1044 morepending = true;
1045
1046 if (!pktq_empty(&wlc->pkt_queue->q))
1047 brcms_c_send_q(wlc);
1048
1049 return morepending;
1050}
1051
1052static void brcms_c_tbtt(struct brcms_c_info *wlc)
1053{
1054 if (!wlc->bsscfg->BSS)
1055 /*
1056 * DirFrmQ is now valid...defer setting until end
1057 * of ATIM window
1058 */
1059 wlc->qvalid |= MCMD_DIRFRMQVAL;
1060}
1061
1062/* set initial host flags value */
1063static void
1064brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1065{
1066 struct brcms_hardware *wlc_hw = wlc->hw;
1067
1068 memset(mhfs, 0, MHFMAX * sizeof(u16));
1069
1070 mhfs[MHF2] |= mhf2_init;
1071
1072 /* prohibit use of slowclock on multifunction boards */
1073 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1074 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1075
1076 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1077 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1078 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1079 }
1080}
1081
1082static uint
1083dmareg(uint direction, uint fifonum)
1084{
1085 if (direction == DMA_TX)
1086 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1087 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1088}
1089
1090static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1091{
1092 uint i;
1093 char name[8];
1094 /*
1095 * ucode host flag 2 needed for pio mode, independent of band and fifo
1096 */
1097 u16 pio_mhf2 = 0;
1098 struct brcms_hardware *wlc_hw = wlc->hw;
1099 uint unit = wlc_hw->unit;
1100 struct wiphy *wiphy = wlc->wiphy;
1101
1102 /* name and offsets for dma_attach */
1103 snprintf(name, sizeof(name), "wl%d", unit);
1104
1105 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
1106 int dma_attach_err = 0;
1107
1108 /*
1109 * FIFO 0
1110 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1111 * RX: RX_FIFO (RX data packets)
1112 */
1113 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1114 (wme ? dmareg(DMA_TX, 0) : 0),
1115 dmareg(DMA_RX, 0),
1116 (wme ? NTXD : 0), NRXD,
1117 RXBUFSZ, -1, NRXBUFPOST,
1118 BRCMS_HWRXOFF, &brcm_msg_level);
1119 dma_attach_err |= (NULL == wlc_hw->di[0]);
1120
1121 /*
1122 * FIFO 1
1123 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1124 * (legacy) TX_DATA_FIFO (TX data packets)
1125 * RX: UNUSED
1126 */
1127 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1128 dmareg(DMA_TX, 1), 0,
1129 NTXD, 0, 0, -1, 0, 0,
1130 &brcm_msg_level);
1131 dma_attach_err |= (NULL == wlc_hw->di[1]);
1132
1133 /*
1134 * FIFO 2
1135 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1136 * RX: UNUSED
1137 */
1138 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1139 dmareg(DMA_TX, 2), 0,
1140 NTXD, 0, 0, -1, 0, 0,
1141 &brcm_msg_level);
1142 dma_attach_err |= (NULL == wlc_hw->di[2]);
1143 /*
1144 * FIFO 3
1145 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1146 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1147 */
1148 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1149 dmareg(DMA_TX, 3),
1150 0, NTXD, 0, 0, -1,
1151 0, 0, &brcm_msg_level);
1152 dma_attach_err |= (NULL == wlc_hw->di[3]);
1153/* Cleaner to leave this as if with AP defined */
1154
1155 if (dma_attach_err) {
1156 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
1157 "\n", unit);
1158 return false;
1159 }
1160
1161 /* get pointer to dma engine tx flow control variable */
1162 for (i = 0; i < NFIFO; i++)
1163 if (wlc_hw->di[i])
1164 wlc_hw->txavail[i] =
1165 (uint *) dma_getvar(wlc_hw->di[i],
1166 "&txavail");
1167 }
1168
1169 /* initial ucode host flags */
1170 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1171
1172 return true;
1173}
1174
1175static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1176{
1177 uint j;
1178
1179 for (j = 0; j < NFIFO; j++) {
1180 if (wlc_hw->di[j]) {
1181 dma_detach(wlc_hw->di[j]);
1182 wlc_hw->di[j] = NULL;
1183 }
1184 }
1185}
1186
1187/*
1188 * Initialize brcms_c_info default values ...
1189 * may get overrides later in this function
1190 * BMAC_NOTES, move low out and resolve the dangling ones
1191 */
1192static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1193{
1194 struct brcms_c_info *wlc = wlc_hw->wlc;
1195
1196 /* set default sw macintmask value */
1197 wlc->defmacintmask = DEF_MACINTMASK;
1198
1199 /* various 802.11g modes */
1200 wlc_hw->shortslot = false;
1201
1202 wlc_hw->SFBL = RETRY_SHORT_FB;
1203 wlc_hw->LFBL = RETRY_LONG_FB;
1204
1205 /* default mac retry limits */
1206 wlc_hw->SRL = RETRY_SHORT_DEF;
1207 wlc_hw->LRL = RETRY_LONG_DEF;
1208 wlc_hw->chanspec = ch20mhz_chspec(1);
1209}
1210
1211static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1212{
1213 /* delay before first read of ucode state */
1214 udelay(40);
1215
1216 /* wait until ucode is no longer asleep */
1217 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1218 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1219}
1220
1221/* control chip clock to save power, enable dynamic clock or force fast clock */
1222static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1223{
1224 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1225 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1226 * on backplane, but mac core will still run on ALP(not HT) when
1227 * it enters powersave mode, which means the FCA bit may not be
1228 * set. Should wakeup mac if driver wants it to run on HT.
1229 */
1230
1231 if (wlc_hw->clk) {
1232 if (mode == BCMA_CLKMODE_FAST) {
1233 bcma_set32(wlc_hw->d11core,
1234 D11REGOFFS(clk_ctl_st),
1235 CCS_FORCEHT);
1236
1237 udelay(64);
1238
1239 SPINWAIT(
1240 ((bcma_read32(wlc_hw->d11core,
1241 D11REGOFFS(clk_ctl_st)) &
1242 CCS_HTAVAIL) == 0),
1243 PMU_MAX_TRANSITION_DLY);
1244 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1245 D11REGOFFS(clk_ctl_st)) &
1246 CCS_HTAVAIL));
1247 } else {
1248 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1249 (bcma_read32(wlc_hw->d11core,
1250 D11REGOFFS(clk_ctl_st)) &
1251 (CCS_FORCEHT | CCS_HTAREQ)))
1252 SPINWAIT(
1253 ((bcma_read32(wlc_hw->d11core,
1254 offsetof(struct d11regs,
1255 clk_ctl_st)) &
1256 CCS_HTAVAIL) == 0),
1257 PMU_MAX_TRANSITION_DLY);
1258 bcma_mask32(wlc_hw->d11core,
1259 D11REGOFFS(clk_ctl_st),
1260 ~CCS_FORCEHT);
1261 }
1262 }
1263 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1264 } else {
1265
1266 /* old chips w/o PMU, force HT through cc,
1267 * then use FCA to verify mac is running fast clock
1268 */
1269
1270 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1271
1272 /* check fast clock is available (if core is not in reset) */
1273 if (wlc_hw->forcefastclk && wlc_hw->clk)
1274 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1275 SISF_FCLKA));
1276
1277 /*
1278 * keep the ucode wake bit on if forcefastclk is on since we
1279 * do not want ucode to put us back to slow clock when it dozes
1280 * for PM mode. Code below matches the wake override bit with
1281 * current forcefastclk state. Only setting bit in wake_override
1282 * instead of waking ucode immediately since old code had this
1283 * behavior. Older code set wlc->forcefastclk but only had the
1284 * wake happen if the wakup_ucode work (protected by an up
1285 * check) was executed just below.
1286 */
1287 if (wlc_hw->forcefastclk)
1288 mboolset(wlc_hw->wake_override,
1289 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1290 else
1291 mboolclr(wlc_hw->wake_override,
1292 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1293 }
1294}
1295
1296/* set or clear ucode host flag bits
1297 * it has an optimization for no-change write
1298 * it only writes through shared memory when the core has clock;
1299 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1300 *
1301 *
1302 * bands values are: BRCM_BAND_AUTO <--- Current band only
1303 * BRCM_BAND_5G <--- 5G band only
1304 * BRCM_BAND_2G <--- 2G band only
1305 * BRCM_BAND_ALL <--- All bands
1306 */
1307void
1308brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1309 int bands)
1310{
1311 u16 save;
1312 u16 addr[MHFMAX] = {
1313 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1314 M_HOST_FLAGS5
1315 };
1316 struct brcms_hw_band *band;
1317
1318 if ((val & ~mask) || idx >= MHFMAX)
1319 return; /* error condition */
1320
1321 switch (bands) {
1322 /* Current band only or all bands,
1323 * then set the band to current band
1324 */
1325 case BRCM_BAND_AUTO:
1326 case BRCM_BAND_ALL:
1327 band = wlc_hw->band;
1328 break;
1329 case BRCM_BAND_5G:
1330 band = wlc_hw->bandstate[BAND_5G_INDEX];
1331 break;
1332 case BRCM_BAND_2G:
1333 band = wlc_hw->bandstate[BAND_2G_INDEX];
1334 break;
1335 default:
1336 band = NULL; /* error condition */
1337 }
1338
1339 if (band) {
1340 save = band->mhfs[idx];
1341 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1342
1343 /* optimization: only write through if changed, and
1344 * changed band is the current band
1345 */
1346 if (wlc_hw->clk && (band->mhfs[idx] != save)
1347 && (band == wlc_hw->band))
1348 brcms_b_write_shm(wlc_hw, addr[idx],
1349 (u16) band->mhfs[idx]);
1350 }
1351
1352 if (bands == BRCM_BAND_ALL) {
1353 wlc_hw->bandstate[0]->mhfs[idx] =
1354 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1355 wlc_hw->bandstate[1]->mhfs[idx] =
1356 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1357 }
1358}
1359
1360/* set the maccontrol register to desired reset state and
1361 * initialize the sw cache of the register
1362 */
1363static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1364{
1365 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1366 wlc_hw->maccontrol = 0;
1367 wlc_hw->suspended_fifos = 0;
1368 wlc_hw->wake_override = 0;
1369 wlc_hw->mute_override = 0;
1370 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1371}
1372
1373/*
1374 * write the software state of maccontrol and
1375 * overrides to the maccontrol register
1376 */
1377static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1378{
1379 u32 maccontrol = wlc_hw->maccontrol;
1380
1381 /* OR in the wake bit if overridden */
1382 if (wlc_hw->wake_override)
1383 maccontrol |= MCTL_WAKE;
1384
1385 /* set AP and INFRA bits for mute if needed */
1386 if (wlc_hw->mute_override) {
1387 maccontrol &= ~(MCTL_AP);
1388 maccontrol |= MCTL_INFRA;
1389 }
1390
1391 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1392 maccontrol);
1393}
1394
1395/* set or clear maccontrol bits */
1396void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1397{
1398 u32 maccontrol;
1399 u32 new_maccontrol;
1400
1401 if (val & ~mask)
1402 return; /* error condition */
1403 maccontrol = wlc_hw->maccontrol;
1404 new_maccontrol = (maccontrol & ~mask) | val;
1405
1406 /* if the new maccontrol value is the same as the old, nothing to do */
1407 if (new_maccontrol == maccontrol)
1408 return;
1409
1410 /* something changed, cache the new value */
1411 wlc_hw->maccontrol = new_maccontrol;
1412
1413 /* write the new values with overrides applied */
1414 brcms_c_mctrl_write(wlc_hw);
1415}
1416
1417void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1418 u32 override_bit)
1419{
1420 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1421 mboolset(wlc_hw->wake_override, override_bit);
1422 return;
1423 }
1424
1425 mboolset(wlc_hw->wake_override, override_bit);
1426
1427 brcms_c_mctrl_write(wlc_hw);
1428 brcms_b_wait_for_wake(wlc_hw);
1429}
1430
1431void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1432 u32 override_bit)
1433{
1434 mboolclr(wlc_hw->wake_override, override_bit);
1435
1436 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1437 return;
1438
1439 brcms_c_mctrl_write(wlc_hw);
1440}
1441
1442/* When driver needs ucode to stop beaconing, it has to make sure that
1443 * MCTL_AP is clear and MCTL_INFRA is set
1444 * Mode MCTL_AP MCTL_INFRA
1445 * AP 1 1
1446 * STA 0 1 <--- This will ensure no beacons
1447 * IBSS 0 0
1448 */
1449static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1450{
1451 wlc_hw->mute_override = 1;
1452
1453 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1454 * override, then there is no change to write
1455 */
1456 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1457 return;
1458
1459 brcms_c_mctrl_write(wlc_hw);
1460}
1461
1462/* Clear the override on AP and INFRA bits */
1463static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1464{
1465 if (wlc_hw->mute_override == 0)
1466 return;
1467
1468 wlc_hw->mute_override = 0;
1469
1470 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1471 * override, then there is no change to write
1472 */
1473 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1474 return;
1475
1476 brcms_c_mctrl_write(wlc_hw);
1477}
1478
1479/*
1480 * Write a MAC address to the given match reg offset in the RXE match engine.
1481 */
1482static void
1483brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1484 const u8 *addr)
1485{
1486 struct bcma_device *core = wlc_hw->d11core;
1487 u16 mac_l;
1488 u16 mac_m;
1489 u16 mac_h;
1490
1491 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
1492 wlc_hw->unit);
1493
1494 mac_l = addr[0] | (addr[1] << 8);
1495 mac_m = addr[2] | (addr[3] << 8);
1496 mac_h = addr[4] | (addr[5] << 8);
1497
1498 /* enter the MAC addr into the RXE match registers */
1499 bcma_write16(core, D11REGOFFS(rcm_ctl),
1500 RCM_INC_DATA | match_reg_offset);
1501 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1502 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1503 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1504}
1505
1506void
1507brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1508 void *buf)
1509{
1510 struct bcma_device *core = wlc_hw->d11core;
1511 u32 word;
1512 __le32 word_le;
1513 __be32 word_be;
1514 bool be_bit;
1515 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1516
1517 bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1518
1519 /* if MCTL_BIGEND bit set in mac control register,
1520 * the chip swaps data in fifo, as well as data in
1521 * template ram
1522 */
1523 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1524
1525 while (len > 0) {
1526 memcpy(&word, buf, sizeof(u32));
1527
1528 if (be_bit) {
1529 word_be = cpu_to_be32(word);
1530 word = *(u32 *)&word_be;
1531 } else {
1532 word_le = cpu_to_le32(word);
1533 word = *(u32 *)&word_le;
1534 }
1535
1536 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1537
1538 buf = (u8 *) buf + sizeof(u32);
1539 len -= sizeof(u32);
1540 }
1541}
1542
1543static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1544{
1545 wlc_hw->band->CWmin = newmin;
1546
1547 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1548 OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1549 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1550 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1551}
1552
1553static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1554{
1555 wlc_hw->band->CWmax = newmax;
1556
1557 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1558 OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1559 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1560 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1561}
1562
1563void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1564{
1565 bool fastclk;
1566
1567 /* request FAST clock if not on */
1568 fastclk = wlc_hw->forcefastclk;
1569 if (!fastclk)
1570 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1571
1572 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1573
1574 brcms_b_phy_reset(wlc_hw);
1575 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1576
1577 /* restore the clk */
1578 if (!fastclk)
1579 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1580}
1581
1582static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1583{
1584 u16 v;
1585 struct brcms_c_info *wlc = wlc_hw->wlc;
1586 /* update SYNTHPU_DLY */
1587
1588 if (BRCMS_ISLCNPHY(wlc->band))
1589 v = SYNTHPU_DLY_LPPHY_US;
1590 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1591 v = SYNTHPU_DLY_NPHY_US;
1592 else
1593 v = SYNTHPU_DLY_BPHY_US;
1594
1595 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1596}
1597
1598static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1599{
1600 u16 phyctl;
1601 u16 phytxant = wlc_hw->bmac_phytxant;
1602 u16 mask = PHY_TXC_ANT_MASK;
1603
1604 /* set the Probe Response frame phy control word */
1605 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1606 phyctl = (phyctl & ~mask) | phytxant;
1607 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1608
1609 /* set the Response (ACK/CTS) frame phy control word */
1610 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1611 phyctl = (phyctl & ~mask) | phytxant;
1612 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1613}
1614
1615static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1616 u8 rate)
1617{
1618 uint i;
1619 u8 plcp_rate = 0;
1620 struct plcp_signal_rate_lookup {
1621 u8 rate;
1622 u8 signal_rate;
1623 };
1624 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1625 const struct plcp_signal_rate_lookup rate_lookup[] = {
1626 {BRCM_RATE_6M, 0xB},
1627 {BRCM_RATE_9M, 0xF},
1628 {BRCM_RATE_12M, 0xA},
1629 {BRCM_RATE_18M, 0xE},
1630 {BRCM_RATE_24M, 0x9},
1631 {BRCM_RATE_36M, 0xD},
1632 {BRCM_RATE_48M, 0x8},
1633 {BRCM_RATE_54M, 0xC}
1634 };
1635
1636 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1637 if (rate == rate_lookup[i].rate) {
1638 plcp_rate = rate_lookup[i].signal_rate;
1639 break;
1640 }
1641 }
1642
1643 /* Find the SHM pointer to the rate table entry by looking in the
1644 * Direct-map Table
1645 */
1646 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1647}
1648
1649static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1650{
1651 u8 rate;
1652 u8 rates[8] = {
1653 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1654 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1655 };
1656 u16 entry_ptr;
1657 u16 pctl1;
1658 uint i;
1659
1660 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1661 return;
1662
1663 /* walk the phy rate table and update the entries */
1664 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1665 rate = rates[i];
1666
1667 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1668
1669 /* read the SHM Rate Table entry OFDM PCTL1 values */
1670 pctl1 =
1671 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1672
1673 /* modify the value */
1674 pctl1 &= ~PHY_TXC1_MODE_MASK;
1675 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1676
1677 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1678 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1679 pctl1);
1680 }
1681}
1682
1683/* band-specific init */
1684static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1685{
1686 struct brcms_hardware *wlc_hw = wlc->hw;
1687
1688 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1689 wlc_hw->band->bandunit);
1690
1691 brcms_c_ucode_bsinit(wlc_hw);
1692
1693 wlc_phy_init(wlc_hw->band->pi, chanspec);
1694
1695 brcms_c_ucode_txant_set(wlc_hw);
1696
1697 /*
1698 * cwmin is band-specific, update hardware
1699 * with value for current band
1700 */
1701 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1702 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1703
1704 brcms_b_update_slot_timing(wlc_hw,
1705 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1706 true : wlc_hw->shortslot);
1707
1708 /* write phytype and phyvers */
1709 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1710 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1711
1712 /*
1713 * initialize the txphyctl1 rate table since
1714 * shmem is shared between bands
1715 */
1716 brcms_upd_ofdm_pctl1_table(wlc_hw);
1717
1718 brcms_b_upd_synthpu(wlc_hw);
1719}
1720
1721/* Perform a soft reset of the PHY PLL */
1722void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1723{
1724 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1725
1726 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1727 ~0, 0);
1728 udelay(1);
1729 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1730 0x4, 0);
1731 udelay(1);
1732 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1733 0x4, 4);
1734 udelay(1);
1735 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1736 0x4, 0);
1737 udelay(1);
1738}
1739
1740/* light way to turn on phy clock without reset for NPHY only
1741 * refer to brcms_b_core_phy_clk for full version
1742 */
1743void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1744{
1745 /* support(necessary for NPHY and HYPHY) only */
1746 if (!BRCMS_ISNPHY(wlc_hw->band))
1747 return;
1748
1749 if (ON == clk)
1750 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1751 else
1752 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1753
1754}
1755
1756void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1757{
1758 if (ON == clk)
1759 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1760 else
1761 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1762}
1763
1764void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1765{
1766 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1767 u32 phy_bw_clkbits;
1768 bool phy_in_reset = false;
1769
1770 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1771
1772 if (pih == NULL)
1773 return;
1774
1775 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1776
1777 /* Specific reset sequence required for NPHY rev 3 and 4 */
1778 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1779 NREV_LE(wlc_hw->band->phyrev, 4)) {
1780 /* Set the PHY bandwidth */
1781 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1782
1783 udelay(1);
1784
1785 /* Perform a soft reset of the PHY PLL */
1786 brcms_b_core_phypll_reset(wlc_hw);
1787
1788 /* reset the PHY */
1789 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1790 (SICF_PRST | SICF_PCLKE));
1791 phy_in_reset = true;
1792 } else {
1793 brcms_b_core_ioctl(wlc_hw,
1794 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1795 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1796 }
1797
1798 udelay(2);
1799 brcms_b_core_phy_clk(wlc_hw, ON);
1800
1801 if (pih)
1802 wlc_phy_anacore(pih, ON);
1803}
1804
1805/* switch to and initialize new band */
1806static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1807 u16 chanspec) {
1808 struct brcms_c_info *wlc = wlc_hw->wlc;
1809 u32 macintmask;
1810
1811 /* Enable the d11 core before accessing it */
1812 if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1813 bcma_core_enable(wlc_hw->d11core, 0);
1814 brcms_c_mctrl_reset(wlc_hw);
1815 }
1816
1817 macintmask = brcms_c_setband_inact(wlc, bandunit);
1818
1819 if (!wlc_hw->up)
1820 return;
1821
1822 brcms_b_core_phy_clk(wlc_hw, ON);
1823
1824 /* band-specific initializations */
1825 brcms_b_bsinit(wlc, chanspec);
1826
1827 /*
1828 * If there are any pending software interrupt bits,
1829 * then replace these with a harmless nonzero value
1830 * so brcms_c_dpc() will re-enable interrupts when done.
1831 */
1832 if (wlc->macintstatus)
1833 wlc->macintstatus = MI_DMAINT;
1834
1835 /* restore macintmask */
1836 brcms_intrsrestore(wlc->wl, macintmask);
1837
1838 /* ucode should still be suspended.. */
1839 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1840 MCTL_EN_MAC) != 0);
1841}
1842
1843static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1844{
1845
1846 /* reject unsupported corerev */
1847 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1848 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1849 wlc_hw->corerev);
1850 return false;
1851 }
1852
1853 return true;
1854}
1855
1856/* Validate some board info parameters */
1857static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1858{
1859 uint boardrev = wlc_hw->boardrev;
1860
1861 /* 4 bits each for board type, major, minor, and tiny version */
1862 uint brt = (boardrev & 0xf000) >> 12;
1863 uint b0 = (boardrev & 0xf00) >> 8;
1864 uint b1 = (boardrev & 0xf0) >> 4;
1865 uint b2 = boardrev & 0xf;
1866
1867 /* voards from other vendors are always considered valid */
1868 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1869 return true;
1870
1871 /* do some boardrev sanity checks when boardvendor is Broadcom */
1872 if (boardrev == 0)
1873 return false;
1874
1875 if (boardrev <= 0xff)
1876 return true;
1877
1878 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1879 || (b2 > 9))
1880 return false;
1881
1882 return true;
1883}
1884
1885static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1886{
1887 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1888
1889 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1890 if (!is_zero_ether_addr(sprom->il0mac)) {
1891 memcpy(etheraddr, sprom->il0mac, 6);
1892 return;
1893 }
1894
1895 if (wlc_hw->_nbands > 1)
1896 memcpy(etheraddr, sprom->et1mac, 6);
1897 else
1898 memcpy(etheraddr, sprom->il0mac, 6);
1899}
1900
1901/* power both the pll and external oscillator on/off */
1902static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1903{
1904 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
1905
1906 /*
1907 * dont power down if plldown is false or
1908 * we must poll hw radio disable
1909 */
1910 if (!want && wlc_hw->pllreq)
1911 return;
1912
1913 wlc_hw->sbclk = want;
1914 if (!wlc_hw->sbclk) {
1915 wlc_hw->clk = false;
1916 if (wlc_hw->band && wlc_hw->band->pi)
1917 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1918 }
1919}
1920
1921/*
1922 * Return true if radio is disabled, otherwise false.
1923 * hw radio disable signal is an external pin, users activate it asynchronously
1924 * this function could be called when driver is down and w/o clock
1925 * it operates on different registers depending on corerev and boardflag.
1926 */
1927static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1928{
1929 bool v, clk, xtal;
1930 u32 flags = 0;
1931
1932 xtal = wlc_hw->sbclk;
1933 if (!xtal)
1934 brcms_b_xtal(wlc_hw, ON);
1935
1936 /* may need to take core out of reset first */
1937 clk = wlc_hw->clk;
1938 if (!clk) {
1939 /*
1940 * mac no longer enables phyclk automatically when driver
1941 * accesses phyreg throughput mac. This can be skipped since
1942 * only mac reg is accessed below
1943 */
1944 flags |= SICF_PCLKE;
1945
1946 /*
1947 * TODO: test suspend/resume
1948 *
1949 * AI chip doesn't restore bar0win2 on
1950 * hibernation/resume, need sw fixup
1951 */
1952
1953 bcma_core_enable(wlc_hw->d11core, flags);
1954 brcms_c_mctrl_reset(wlc_hw);
1955 }
1956
1957 v = ((bcma_read32(wlc_hw->d11core,
1958 D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1959
1960 /* put core back into reset */
1961 if (!clk)
1962 bcma_core_disable(wlc_hw->d11core, 0);
1963
1964 if (!xtal)
1965 brcms_b_xtal(wlc_hw, OFF);
1966
1967 return v;
1968}
1969
1970static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1971{
1972 struct dma_pub *di = wlc_hw->di[fifo];
1973 return dma_rxreset(di);
1974}
1975
1976/* d11 core reset
1977 * ensure fask clock during reset
1978 * reset dma
1979 * reset d11(out of reset)
1980 * reset phy(out of reset)
1981 * clear software macintstatus for fresh new start
1982 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1983 */
1984void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
1985{
1986 uint i;
1987 bool fastclk;
1988
1989 if (flags == BRCMS_USE_COREFLAGS)
1990 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
1991
1992 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1993
1994 /* request FAST clock if not on */
1995 fastclk = wlc_hw->forcefastclk;
1996 if (!fastclk)
1997 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1998
1999 /* reset the dma engines except first time thru */
2000 if (bcma_core_is_enabled(wlc_hw->d11core)) {
2001 for (i = 0; i < NFIFO; i++)
2002 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2003 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2004 "dma_txreset[%d]: cannot stop dma\n",
2005 wlc_hw->unit, __func__, i);
2006
2007 if ((wlc_hw->di[RX_FIFO])
2008 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2009 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2010 "[%d]: cannot stop dma\n",
2011 wlc_hw->unit, __func__, RX_FIFO);
2012 }
2013 /* if noreset, just stop the psm and return */
2014 if (wlc_hw->noreset) {
2015 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2016 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2017 return;
2018 }
2019
2020 /*
2021 * mac no longer enables phyclk automatically when driver accesses
2022 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2023 * band->pi is invalid. need to enable PHY CLK
2024 */
2025 flags |= SICF_PCLKE;
2026
2027 /*
2028 * reset the core
2029 * In chips with PMU, the fastclk request goes through d11 core
2030 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2031 *
2032 * This adds some delay and we can optimize it by also requesting
2033 * fastclk through chipcommon during this period if necessary. But
2034 * that has to work coordinate with other driver like mips/arm since
2035 * they may touch chipcommon as well.
2036 */
2037 wlc_hw->clk = false;
2038 bcma_core_enable(wlc_hw->d11core, flags);
2039 wlc_hw->clk = true;
2040 if (wlc_hw->band && wlc_hw->band->pi)
2041 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2042
2043 brcms_c_mctrl_reset(wlc_hw);
2044
2045 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2046 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2047
2048 brcms_b_phy_reset(wlc_hw);
2049
2050 /* turn on PHY_PLL */
2051 brcms_b_core_phypll_ctl(wlc_hw, true);
2052
2053 /* clear sw intstatus */
2054 wlc_hw->wlc->macintstatus = 0;
2055
2056 /* restore the clk setting */
2057 if (!fastclk)
2058 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2059}
2060
2061/* txfifo sizes needs to be modified(increased) since the newer cores
2062 * have more memory.
2063 */
2064static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2065{
2066 struct bcma_device *core = wlc_hw->d11core;
2067 u16 fifo_nu;
2068 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2069 u16 txfifo_def, txfifo_def1;
2070 u16 txfifo_cmd;
2071
2072 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2073 txfifo_startblk = TXFIFO_START_BLK;
2074
2075 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2076 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2077
2078 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2079 txfifo_def = (txfifo_startblk & 0xff) |
2080 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2081 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2082 ((((txfifo_endblk -
2083 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2084 txfifo_cmd =
2085 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2086
2087 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2088 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2089 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2090
2091 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2092
2093 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2094 }
2095 /*
2096 * need to propagate to shm location to be in sync since ucode/hw won't
2097 * do this
2098 */
2099 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2100 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2101 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2102 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2103 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2104 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2105 xmtfifo_sz[TX_AC_BK_FIFO]));
2106 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2107 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2108 xmtfifo_sz[TX_BCMC_FIFO]));
2109}
2110
2111/* This function is used for changing the tsf frac register
2112 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2113 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2114 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2115 * HTPHY Formula is 2^26/freq(MHz) e.g.
2116 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2117 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2118 * For spuron: 123MHz -> 2^26/123 = 545600.5
2119 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2120 * For spur off: 120MHz -> 2^26/120 = 559240.5
2121 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2122 */
2123
2124void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2125{
2126 struct bcma_device *core = wlc_hw->d11core;
2127
2128 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
2129 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) {
2130 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2131 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2132 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2133 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2134 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2135 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2136 } else { /* 120Mhz */
2137 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2138 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2139 }
2140 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2141 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2142 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2143 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2144 } else { /* 80Mhz */
2145 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2146 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2147 }
2148 }
2149}
2150
2151/* Initialize GPIOs that are controlled by D11 core */
2152static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2153{
2154 struct brcms_hardware *wlc_hw = wlc->hw;
2155 u32 gc, gm;
2156
2157 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2158 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2159
2160 /*
2161 * Common GPIO setup:
2162 * G0 = LED 0 = WLAN Activity
2163 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2164 * G2 = LED 2 = WLAN 5 GHz Radio State
2165 * G4 = radio disable input (HI enabled, LO disabled)
2166 */
2167
2168 gc = gm = 0;
2169
2170 /* Allocate GPIOs for mimo antenna diversity feature */
2171 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2172 /* Enable antenna diversity, use 2x3 mode */
2173 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2174 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2175 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2176 MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2177
2178 /* init superswitch control */
2179 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2180
2181 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2182 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2183 /*
2184 * The board itself is powered by these GPIOs
2185 * (when not sending pattern) so set them high
2186 */
2187 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2188 (BOARD_GPIO_12 | BOARD_GPIO_13));
2189 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2190 (BOARD_GPIO_12 | BOARD_GPIO_13));
2191
2192 /* Enable antenna diversity, use 2x4 mode */
2193 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2194 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2195 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2196 BRCM_BAND_ALL);
2197
2198 /* Configure the desired clock to be 4Mhz */
2199 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2200 ANTSEL_CLKDIV_4MHZ);
2201 }
2202
2203 /*
2204 * gpio 9 controls the PA. ucode is responsible
2205 * for wiggling out and oe
2206 */
2207 if (wlc_hw->boardflags & BFL_PACTRL)
2208 gm |= gc |= BOARD_GPIO_PACTRL;
2209
2210 /* apply to gpiocontrol register */
2211 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2212}
2213
2214static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2215 const __le32 ucode[], const size_t nbytes)
2216{
2217 struct bcma_device *core = wlc_hw->d11core;
2218 uint i;
2219 uint count;
2220
2221 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2222
2223 count = (nbytes / sizeof(u32));
2224
2225 bcma_write32(core, D11REGOFFS(objaddr),
2226 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2227 (void)bcma_read32(core, D11REGOFFS(objaddr));
2228 for (i = 0; i < count; i++)
2229 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2230
2231}
2232
2233static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2234{
2235 struct brcms_c_info *wlc;
2236 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2237
2238 wlc = wlc_hw->wlc;
2239
2240 if (wlc_hw->ucode_loaded)
2241 return;
2242
2243 if (D11REV_IS(wlc_hw->corerev, 23)) {
2244 if (BRCMS_ISNPHY(wlc_hw->band)) {
2245 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2246 ucode->bcm43xx_16_mimosz);
2247 wlc_hw->ucode_loaded = true;
2248 } else
2249 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2250 "corerev %d\n",
2251 __func__, wlc_hw->unit, wlc_hw->corerev);
2252 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2253 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2254 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2255 ucode->bcm43xx_24_lcnsz);
2256 wlc_hw->ucode_loaded = true;
2257 } else {
2258 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2259 "corerev %d\n",
2260 __func__, wlc_hw->unit, wlc_hw->corerev);
2261 }
2262 }
2263}
2264
2265void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2266{
2267 /* update sw state */
2268 wlc_hw->bmac_phytxant = phytxant;
2269
2270 /* push to ucode if up */
2271 if (!wlc_hw->up)
2272 return;
2273 brcms_c_ucode_txant_set(wlc_hw);
2274
2275}
2276
2277u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2278{
2279 return (u16) wlc_hw->wlc->stf->txant;
2280}
2281
2282void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2283{
2284 wlc_hw->antsel_type = antsel_type;
2285
2286 /* Update the antsel type for phy module to use */
2287 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2288}
2289
2290static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2291{
2292 bool fatal = false;
2293 uint unit;
2294 uint intstatus, idx;
2295 struct bcma_device *core = wlc_hw->d11core;
2296 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2297
2298 unit = wlc_hw->unit;
2299
2300 for (idx = 0; idx < NFIFO; idx++) {
2301 /* read intstatus register and ignore any non-error bits */
2302 intstatus =
2303 bcma_read32(core,
2304 D11REGOFFS(intctrlregs[idx].intstatus)) &
2305 I_ERRORS;
2306 if (!intstatus)
2307 continue;
2308
2309 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2310 unit, idx, intstatus);
2311
2312 if (intstatus & I_RO) {
2313 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2314 "overflow\n", unit, idx);
2315 fatal = true;
2316 }
2317
2318 if (intstatus & I_PC) {
2319 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2320 unit, idx);
2321 fatal = true;
2322 }
2323
2324 if (intstatus & I_PD) {
2325 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2326 idx);
2327 fatal = true;
2328 }
2329
2330 if (intstatus & I_DE) {
2331 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2332 "error\n", unit, idx);
2333 fatal = true;
2334 }
2335
2336 if (intstatus & I_RU)
2337 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2338 "underflow\n", idx, unit);
2339
2340 if (intstatus & I_XU) {
2341 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2342 "underflow\n", idx, unit);
2343 fatal = true;
2344 }
2345
2346 if (fatal) {
2347 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2348 break;
2349 } else
2350 bcma_write32(core,
2351 D11REGOFFS(intctrlregs[idx].intstatus),
2352 intstatus);
2353 }
2354}
2355
2356void brcms_c_intrson(struct brcms_c_info *wlc)
2357{
2358 struct brcms_hardware *wlc_hw = wlc->hw;
2359 wlc->macintmask = wlc->defmacintmask;
2360 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2361}
2362
2363u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2364{
2365 struct brcms_hardware *wlc_hw = wlc->hw;
2366 u32 macintmask;
2367
2368 if (!wlc_hw->clk)
2369 return 0;
2370
2371 macintmask = wlc->macintmask; /* isr can still happen */
2372
2373 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2374 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2375 udelay(1); /* ensure int line is no longer driven */
2376 wlc->macintmask = 0;
2377
2378 /* return previous macintmask; resolve race between us and our isr */
2379 return wlc->macintstatus ? 0 : macintmask;
2380}
2381
2382void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2383{
2384 struct brcms_hardware *wlc_hw = wlc->hw;
2385 if (!wlc_hw->clk)
2386 return;
2387
2388 wlc->macintmask = macintmask;
2389 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2390}
2391
2392/* assumes that the d11 MAC is enabled */
2393static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2394 uint tx_fifo)
2395{
2396 u8 fifo = 1 << tx_fifo;
2397
2398 /* Two clients of this code, 11h Quiet period and scanning. */
2399
2400 /* only suspend if not already suspended */
2401 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2402 return;
2403
2404 /* force the core awake only if not already */
2405 if (wlc_hw->suspended_fifos == 0)
2406 brcms_c_ucode_wake_override_set(wlc_hw,
2407 BRCMS_WAKE_OVERRIDE_TXFIFO);
2408
2409 wlc_hw->suspended_fifos |= fifo;
2410
2411 if (wlc_hw->di[tx_fifo]) {
2412 /*
2413 * Suspending AMPDU transmissions in the middle can cause
2414 * underflow which may result in mismatch between ucode and
2415 * driver so suspend the mac before suspending the FIFO
2416 */
2417 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2418 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2419
2420 dma_txsuspend(wlc_hw->di[tx_fifo]);
2421
2422 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2423 brcms_c_enable_mac(wlc_hw->wlc);
2424 }
2425}
2426
2427static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2428 uint tx_fifo)
2429{
2430 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2431 * but need to be done here for PIO otherwise the watchdog will catch
2432 * the inconsistency and fire
2433 */
2434 /* Two clients of this code, 11h Quiet period and scanning. */
2435 if (wlc_hw->di[tx_fifo])
2436 dma_txresume(wlc_hw->di[tx_fifo]);
2437
2438 /* allow core to sleep again */
2439 if (wlc_hw->suspended_fifos == 0)
2440 return;
2441 else {
2442 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2443 if (wlc_hw->suspended_fifos == 0)
2444 brcms_c_ucode_wake_override_clear(wlc_hw,
2445 BRCMS_WAKE_OVERRIDE_TXFIFO);
2446 }
2447}
2448
2449/* precondition: requires the mac core to be enabled */
2450static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2451{
2452 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2453
2454 if (mute_tx) {
2455 /* suspend tx fifos */
2456 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2457 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2458 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2459 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2460
2461 /* zero the address match register so we do not send ACKs */
2462 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2463 null_ether_addr);
2464 } else {
2465 /* resume tx fifos */
2466 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2467 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2468 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2469 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2470
2471 /* Restore address */
2472 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2473 wlc_hw->etheraddr);
2474 }
2475
2476 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2477
2478 if (mute_tx)
2479 brcms_c_ucode_mute_override_set(wlc_hw);
2480 else
2481 brcms_c_ucode_mute_override_clear(wlc_hw);
2482}
2483
2484void
2485brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2486{
2487 brcms_b_mute(wlc->hw, mute_tx);
2488}
2489
2490/*
2491 * Read and clear macintmask and macintstatus and intstatus registers.
2492 * This routine should be called with interrupts off
2493 * Return:
2494 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2495 * 0 if the interrupt is not for us, or we are in some special cases;
2496 * device interrupt status bits otherwise.
2497 */
2498static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2499{
2500 struct brcms_hardware *wlc_hw = wlc->hw;
2501 struct bcma_device *core = wlc_hw->d11core;
2502 u32 macintstatus;
2503
2504 /* macintstatus includes a DMA interrupt summary bit */
2505 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2506
2507 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2508 macintstatus);
2509
2510 /* detect cardbus removed, in power down(suspend) and in reset */
2511 if (brcms_deviceremoved(wlc))
2512 return -1;
2513
2514 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2515 * handle that case here.
2516 */
2517 if (macintstatus == 0xffffffff)
2518 return 0;
2519
2520 /* defer unsolicited interrupts */
2521 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2522
2523 /* if not for us */
2524 if (macintstatus == 0)
2525 return 0;
2526
2527 /* interrupts are already turned off for CFE build
2528 * Caution: For CFE Turning off the interrupts again has some undesired
2529 * consequences
2530 */
2531 /* turn off the interrupts */
2532 bcma_write32(core, D11REGOFFS(macintmask), 0);
2533 (void)bcma_read32(core, D11REGOFFS(macintmask));
2534 wlc->macintmask = 0;
2535
2536 /* clear device interrupts */
2537 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2538
2539 /* MI_DMAINT is indication of non-zero intstatus */
2540 if (macintstatus & MI_DMAINT)
2541 /*
2542 * only fifo interrupt enabled is I_RI in
2543 * RX_FIFO. If MI_DMAINT is set, assume it
2544 * is set and clear the interrupt.
2545 */
2546 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2547 DEF_RXINTMASK);
2548
2549 return macintstatus;
2550}
2551
2552/* Update wlc->macintstatus and wlc->intstatus[]. */
2553/* Return true if they are updated successfully. false otherwise */
2554bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2555{
2556 u32 macintstatus;
2557
2558 /* read and clear macintstatus and intstatus registers */
2559 macintstatus = wlc_intstatus(wlc, false);
2560
2561 /* device is removed */
2562 if (macintstatus == 0xffffffff)
2563 return false;
2564
2565 /* update interrupt status in software */
2566 wlc->macintstatus |= macintstatus;
2567
2568 return true;
2569}
2570
2571/*
2572 * First-level interrupt processing.
2573 * Return true if this was our interrupt, false otherwise.
2574 * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
2575 * false otherwise.
2576 */
2577bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
2578{
2579 struct brcms_hardware *wlc_hw = wlc->hw;
2580 u32 macintstatus;
2581
2582 *wantdpc = false;
2583
2584 if (!wlc_hw->up || !wlc->macintmask)
2585 return false;
2586
2587 /* read and clear macintstatus and intstatus registers */
2588 macintstatus = wlc_intstatus(wlc, true);
2589
2590 if (macintstatus == 0xffffffff)
2591 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2592 " path\n");
2593
2594 /* it is not for us */
2595 if (macintstatus == 0)
2596 return false;
2597
2598 *wantdpc = true;
2599
2600 /* save interrupt status bits */
2601 wlc->macintstatus = macintstatus;
2602
2603 return true;
2604
2605}
2606
2607void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2608{
2609 struct brcms_hardware *wlc_hw = wlc->hw;
2610 struct bcma_device *core = wlc_hw->d11core;
2611 u32 mc, mi;
2612 struct wiphy *wiphy = wlc->wiphy;
2613
2614 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2615 wlc_hw->band->bandunit);
2616
2617 /*
2618 * Track overlapping suspend requests
2619 */
2620 wlc_hw->mac_suspend_depth++;
2621 if (wlc_hw->mac_suspend_depth > 1)
2622 return;
2623
2624 /* force the core awake */
2625 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2626
2627 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2628
2629 if (mc == 0xffffffff) {
2630 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2631 __func__);
2632 brcms_down(wlc->wl);
2633 return;
2634 }
2635 WARN_ON(mc & MCTL_PSM_JMP_0);
2636 WARN_ON(!(mc & MCTL_PSM_RUN));
2637 WARN_ON(!(mc & MCTL_EN_MAC));
2638
2639 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2640 if (mi == 0xffffffff) {
2641 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2642 __func__);
2643 brcms_down(wlc->wl);
2644 return;
2645 }
2646 WARN_ON(mi & MI_MACSSPNDD);
2647
2648 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2649
2650 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2651 BRCMS_MAX_MAC_SUSPEND);
2652
2653 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2654 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2655 " and MI_MACSSPNDD is still not on.\n",
2656 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2657 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2658 "psm_brc 0x%04x\n", wlc_hw->unit,
2659 bcma_read32(core, D11REGOFFS(psmdebug)),
2660 bcma_read32(core, D11REGOFFS(phydebug)),
2661 bcma_read16(core, D11REGOFFS(psm_brc)));
2662 }
2663
2664 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2665 if (mc == 0xffffffff) {
2666 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2667 __func__);
2668 brcms_down(wlc->wl);
2669 return;
2670 }
2671 WARN_ON(mc & MCTL_PSM_JMP_0);
2672 WARN_ON(!(mc & MCTL_PSM_RUN));
2673 WARN_ON(mc & MCTL_EN_MAC);
2674}
2675
2676void brcms_c_enable_mac(struct brcms_c_info *wlc)
2677{
2678 struct brcms_hardware *wlc_hw = wlc->hw;
2679 struct bcma_device *core = wlc_hw->d11core;
2680 u32 mc, mi;
2681
2682 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2683 wlc->band->bandunit);
2684
2685 /*
2686 * Track overlapping suspend requests
2687 */
2688 wlc_hw->mac_suspend_depth--;
2689 if (wlc_hw->mac_suspend_depth > 0)
2690 return;
2691
2692 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2693 WARN_ON(mc & MCTL_PSM_JMP_0);
2694 WARN_ON(mc & MCTL_EN_MAC);
2695 WARN_ON(!(mc & MCTL_PSM_RUN));
2696
2697 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2698 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2699
2700 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2701 WARN_ON(mc & MCTL_PSM_JMP_0);
2702 WARN_ON(!(mc & MCTL_EN_MAC));
2703 WARN_ON(!(mc & MCTL_PSM_RUN));
2704
2705 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2706 WARN_ON(mi & MI_MACSSPNDD);
2707
2708 brcms_c_ucode_wake_override_clear(wlc_hw,
2709 BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2710}
2711
2712void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2713{
2714 wlc_hw->hw_stf_ss_opmode = stf_mode;
2715
2716 if (wlc_hw->clk)
2717 brcms_upd_ofdm_pctl1_table(wlc_hw);
2718}
2719
2720static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2721{
2722 struct bcma_device *core = wlc_hw->d11core;
2723 u32 w, val;
2724 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2725
2726 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
2727
2728 /* Validate dchip register access */
2729
2730 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2731 (void)bcma_read32(core, D11REGOFFS(objaddr));
2732 w = bcma_read32(core, D11REGOFFS(objdata));
2733
2734 /* Can we write and read back a 32bit register? */
2735 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2736 (void)bcma_read32(core, D11REGOFFS(objaddr));
2737 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2738
2739 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2740 (void)bcma_read32(core, D11REGOFFS(objaddr));
2741 val = bcma_read32(core, D11REGOFFS(objdata));
2742 if (val != (u32) 0xaa5555aa) {
2743 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2744 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2745 return false;
2746 }
2747
2748 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2749 (void)bcma_read32(core, D11REGOFFS(objaddr));
2750 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2751
2752 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2753 (void)bcma_read32(core, D11REGOFFS(objaddr));
2754 val = bcma_read32(core, D11REGOFFS(objdata));
2755 if (val != (u32) 0x55aaaa55) {
2756 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2757 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2758 return false;
2759 }
2760
2761 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2762 (void)bcma_read32(core, D11REGOFFS(objaddr));
2763 bcma_write32(core, D11REGOFFS(objdata), w);
2764
2765 /* clear CFPStart */
2766 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2767
2768 w = bcma_read32(core, D11REGOFFS(maccontrol));
2769 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2770 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2771 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2772 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2773 (MCTL_IHR_EN | MCTL_WAKE),
2774 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2775 return false;
2776 }
2777
2778 return true;
2779}
2780
2781#define PHYPLL_WAIT_US 100000
2782
2783void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2784{
2785 struct bcma_device *core = wlc_hw->d11core;
2786 u32 tmp;
2787
2788 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2789
2790 tmp = 0;
2791
2792 if (on) {
2793 if ((ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
2794 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2795 CCS_ERSRC_REQ_HT |
2796 CCS_ERSRC_REQ_D11PLL |
2797 CCS_ERSRC_REQ_PHYPLL);
2798 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2799 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2800 PHYPLL_WAIT_US);
2801
2802 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2803 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2804 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
2805 " PLL failed\n", __func__);
2806 } else {
2807 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2808 tmp | CCS_ERSRC_REQ_D11PLL |
2809 CCS_ERSRC_REQ_PHYPLL);
2810 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2811 (CCS_ERSRC_AVAIL_D11PLL |
2812 CCS_ERSRC_AVAIL_PHYPLL)) !=
2813 (CCS_ERSRC_AVAIL_D11PLL |
2814 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2815
2816 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2817 if ((tmp &
2818 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2819 !=
2820 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2821 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
2822 "PHY PLL failed\n", __func__);
2823 }
2824 } else {
2825 /*
2826 * Since the PLL may be shared, other cores can still
2827 * be requesting it; so we'll deassert the request but
2828 * not wait for status to comply.
2829 */
2830 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2831 ~CCS_ERSRC_REQ_PHYPLL);
2832 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2833 }
2834}
2835
2836static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2837{
2838 bool dev_gone;
2839
2840 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2841
2842 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2843
2844 if (dev_gone)
2845 return;
2846
2847 if (wlc_hw->noreset)
2848 return;
2849
2850 /* radio off */
2851 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2852
2853 /* turn off analog core */
2854 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2855
2856 /* turn off PHYPLL to save power */
2857 brcms_b_core_phypll_ctl(wlc_hw, false);
2858
2859 wlc_hw->clk = false;
2860 bcma_core_disable(wlc_hw->d11core, 0);
2861 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2862}
2863
2864static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2865{
2866 struct brcms_hardware *wlc_hw = wlc->hw;
2867 uint i;
2868
2869 /* free any posted tx packets */
2870 for (i = 0; i < NFIFO; i++)
2871 if (wlc_hw->di[i]) {
2872 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2873 wlc->core->txpktpend[i] = 0;
2874 BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
2875 }
2876
2877 /* free any posted rx packets */
2878 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2879}
2880
2881static u16
2882brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2883{
2884 struct bcma_device *core = wlc_hw->d11core;
2885 u16 objoff = D11REGOFFS(objdata);
2886
2887 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2888 (void)bcma_read32(core, D11REGOFFS(objaddr));
2889 if (offset & 2)
2890 objoff += 2;
2891
2892 return bcma_read16(core, objoff);
2893}
2894
2895static void
2896brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2897 u32 sel)
2898{
2899 struct bcma_device *core = wlc_hw->d11core;
2900 u16 objoff = D11REGOFFS(objdata);
2901
2902 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2903 (void)bcma_read32(core, D11REGOFFS(objaddr));
2904 if (offset & 2)
2905 objoff += 2;
2906
2907 bcma_write16(core, objoff, v);
2908}
2909
2910/*
2911 * Read a single u16 from shared memory.
2912 * SHM 'offset' needs to be an even address
2913 */
2914u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2915{
2916 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2917}
2918
2919/*
2920 * Write a single u16 to shared memory.
2921 * SHM 'offset' needs to be an even address
2922 */
2923void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2924{
2925 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2926}
2927
2928/*
2929 * Copy a buffer to shared memory of specified type .
2930 * SHM 'offset' needs to be an even address and
2931 * Buffer length 'len' must be an even number of bytes
2932 * 'sel' selects the type of memory
2933 */
2934void
2935brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2936 const void *buf, int len, u32 sel)
2937{
2938 u16 v;
2939 const u8 *p = (const u8 *)buf;
2940 int i;
2941
2942 if (len <= 0 || (offset & 1) || (len & 1))
2943 return;
2944
2945 for (i = 0; i < len; i += 2) {
2946 v = p[i] | (p[i + 1] << 8);
2947 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2948 }
2949}
2950
2951/*
2952 * Copy a piece of shared memory of specified type to a buffer .
2953 * SHM 'offset' needs to be an even address and
2954 * Buffer length 'len' must be an even number of bytes
2955 * 'sel' selects the type of memory
2956 */
2957void
2958brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2959 int len, u32 sel)
2960{
2961 u16 v;
2962 u8 *p = (u8 *) buf;
2963 int i;
2964
2965 if (len <= 0 || (offset & 1) || (len & 1))
2966 return;
2967
2968 for (i = 0; i < len; i += 2) {
2969 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2970 p[i] = v & 0xFF;
2971 p[i + 1] = (v >> 8) & 0xFF;
2972 }
2973}
2974
2975/* Copy a buffer to shared memory.
2976 * SHM 'offset' needs to be an even address and
2977 * Buffer length 'len' must be an even number of bytes
2978 */
2979static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2980 const void *buf, int len)
2981{
2982 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
2983}
2984
2985static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
2986 u16 SRL, u16 LRL)
2987{
2988 wlc_hw->SRL = SRL;
2989 wlc_hw->LRL = LRL;
2990
2991 /* write retry limit to SCR, shouldn't need to suspend */
2992 if (wlc_hw->up) {
2993 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
2994 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2995 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
2996 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
2997 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
2998 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2999 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3000 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3001 }
3002}
3003
3004static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3005{
3006 if (set) {
3007 if (mboolisset(wlc_hw->pllreq, req_bit))
3008 return;
3009
3010 mboolset(wlc_hw->pllreq, req_bit);
3011
3012 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3013 if (!wlc_hw->sbclk)
3014 brcms_b_xtal(wlc_hw, ON);
3015 }
3016 } else {
3017 if (!mboolisset(wlc_hw->pllreq, req_bit))
3018 return;
3019
3020 mboolclr(wlc_hw->pllreq, req_bit);
3021
3022 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3023 if (wlc_hw->sbclk)
3024 brcms_b_xtal(wlc_hw, OFF);
3025 }
3026 }
3027}
3028
3029static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3030{
3031 wlc_hw->antsel_avail = antsel_avail;
3032}
3033
3034/*
3035 * conditions under which the PM bit should be set in outgoing frames
3036 * and STAY_AWAKE is meaningful
3037 */
3038static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3039{
3040 struct brcms_bss_cfg *cfg = wlc->bsscfg;
3041
3042 /* disallow PS when one of the following global conditions meets */
3043 if (!wlc->pub->associated)
3044 return false;
3045
3046 /* disallow PS when one of these meets when not scanning */
3047 if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3048 return false;
3049
3050 if (cfg->associated) {
3051 /*
3052 * disallow PS when one of the following
3053 * bsscfg specific conditions meets
3054 */
3055 if (!cfg->BSS)
3056 return false;
3057
3058 return false;
3059 }
3060
3061 return true;
3062}
3063
3064static void brcms_c_statsupd(struct brcms_c_info *wlc)
3065{
3066 int i;
3067 struct macstat macstats;
3068#ifdef DEBUG
3069 u16 delta;
3070 u16 rxf0ovfl;
3071 u16 txfunfl[NFIFO];
3072#endif /* DEBUG */
3073
3074 /* if driver down, make no sense to update stats */
3075 if (!wlc->pub->up)
3076 return;
3077
3078#ifdef DEBUG
3079 /* save last rx fifo 0 overflow count */
3080 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3081
3082 /* save last tx fifo underflow count */
3083 for (i = 0; i < NFIFO; i++)
3084 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3085#endif /* DEBUG */
3086
3087 /* Read mac stats from contiguous shared memory */
3088 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3089 sizeof(struct macstat), OBJADDR_SHM_SEL);
3090
3091#ifdef DEBUG
3092 /* check for rx fifo 0 overflow */
3093 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3094 if (delta)
3095 wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
3096 wlc->pub->unit, delta);
3097
3098 /* check for tx fifo underflows */
3099 for (i = 0; i < NFIFO; i++) {
3100 delta =
3101 (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3102 txfunfl[i]);
3103 if (delta)
3104 wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
3105 "\n", wlc->pub->unit, delta, i);
3106 }
3107#endif /* DEBUG */
3108
3109 /* merge counters from dma module */
3110 for (i = 0; i < NFIFO; i++) {
3111 if (wlc->hw->di[i])
3112 dma_counterreset(wlc->hw->di[i]);
3113 }
3114}
3115
3116static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3117{
3118 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3119
3120 /* reset the core */
3121 if (!brcms_deviceremoved(wlc_hw->wlc))
3122 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3123
3124 /* purge the dma rings */
3125 brcms_c_flushqueues(wlc_hw->wlc);
3126}
3127
3128void brcms_c_reset(struct brcms_c_info *wlc)
3129{
3130 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3131
3132 /* slurp up hw mac counters before core reset */
3133 brcms_c_statsupd(wlc);
3134
3135 /* reset our snapshot of macstat counters */
3136 memset((char *)wlc->core->macstat_snapshot, 0,
3137 sizeof(struct macstat));
3138
3139 brcms_b_reset(wlc->hw);
3140}
3141
3142/* Return the channel the driver should initialize during brcms_c_init.
3143 * the channel may have to be changed from the currently configured channel
3144 * if other configurations are in conflict (bandlocked, 11n mode disabled,
3145 * invalid channel for current country, etc.)
3146 */
3147static u16 brcms_c_init_chanspec(struct brcms_c_info *wlc)
3148{
3149 u16 chanspec =
3150 1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE |
3151 WL_CHANSPEC_BAND_2G;
3152
3153 return chanspec;
3154}
3155
3156void brcms_c_init_scb(struct scb *scb)
3157{
3158 int i;
3159
3160 memset(scb, 0, sizeof(struct scb));
3161 scb->flags = SCB_WMECAP | SCB_HTCAP;
3162 for (i = 0; i < NUMPRIO; i++) {
3163 scb->seqnum[i] = 0;
3164 scb->seqctl[i] = 0xFFFF;
3165 }
3166
3167 scb->seqctl_nonqos = 0xFFFF;
3168 scb->magic = SCB_MAGIC;
3169}
3170
3171/* d11 core init
3172 * reset PSM
3173 * download ucode/PCM
3174 * let ucode run to suspended
3175 * download ucode inits
3176 * config other core registers
3177 * init dma
3178 */
3179static void brcms_b_coreinit(struct brcms_c_info *wlc)
3180{
3181 struct brcms_hardware *wlc_hw = wlc->hw;
3182 struct bcma_device *core = wlc_hw->d11core;
3183 u32 sflags;
3184 u32 bcnint_us;
3185 uint i = 0;
3186 bool fifosz_fixup = false;
3187 int err = 0;
3188 u16 buf[NFIFO];
3189 struct wiphy *wiphy = wlc->wiphy;
3190 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3191
3192 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3193
3194 /* reset PSM */
3195 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3196
3197 brcms_ucode_download(wlc_hw);
3198 /*
3199 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3200 */
3201 fifosz_fixup = true;
3202
3203 /* let the PSM run to the suspended state, set mode to BSS STA */
3204 bcma_write32(core, D11REGOFFS(macintstatus), -1);
3205 brcms_b_mctrl(wlc_hw, ~0,
3206 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3207
3208 /* wait for ucode to self-suspend after auto-init */
3209 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3210 MI_MACSSPNDD) == 0), 1000 * 1000);
3211 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3212 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
3213 "suspend!\n", wlc_hw->unit);
3214
3215 brcms_c_gpio_init(wlc);
3216
3217 sflags = bcma_aread32(core, BCMA_IOST);
3218
3219 if (D11REV_IS(wlc_hw->corerev, 23)) {
3220 if (BRCMS_ISNPHY(wlc_hw->band))
3221 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3222 else
3223 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3224 " %d\n", __func__, wlc_hw->unit,
3225 wlc_hw->corerev);
3226 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3227 if (BRCMS_ISLCNPHY(wlc_hw->band))
3228 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3229 else
3230 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3231 " %d\n", __func__, wlc_hw->unit,
3232 wlc_hw->corerev);
3233 } else {
3234 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
3235 __func__, wlc_hw->unit, wlc_hw->corerev);
3236 }
3237
3238 /* For old ucode, txfifo sizes needs to be modified(increased) */
3239 if (fifosz_fixup)
3240 brcms_b_corerev_fifofixup(wlc_hw);
3241
3242 /* check txfifo allocations match between ucode and driver */
3243 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3244 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3245 i = TX_AC_BE_FIFO;
3246 err = -1;
3247 }
3248 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3249 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3250 i = TX_AC_VI_FIFO;
3251 err = -1;
3252 }
3253 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3254 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3255 buf[TX_AC_BK_FIFO] &= 0xff;
3256 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3257 i = TX_AC_BK_FIFO;
3258 err = -1;
3259 }
3260 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3261 i = TX_AC_VO_FIFO;
3262 err = -1;
3263 }
3264 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3265 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3266 buf[TX_BCMC_FIFO] &= 0xff;
3267 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3268 i = TX_BCMC_FIFO;
3269 err = -1;
3270 }
3271 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3272 i = TX_ATIM_FIFO;
3273 err = -1;
3274 }
3275 if (err != 0)
3276 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
3277 " driver size %d index %d\n", buf[i],
3278 wlc_hw->xmtfifo_sz[i], i);
3279
3280 /* make sure we can still talk to the mac */
3281 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3282
3283 /* band-specific inits done by wlc_bsinit() */
3284
3285 /* Set up frame burst size and antenna swap threshold init values */
3286 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3287 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3288
3289 /* enable one rx interrupt per received frame */
3290 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3291
3292 /* set the station mode (BSS STA) */
3293 brcms_b_mctrl(wlc_hw,
3294 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3295 (MCTL_INFRA | MCTL_DISCARD_PMQ));
3296
3297 /* set up Beacon interval */
3298 bcnint_us = 0x8000 << 10;
3299 bcma_write32(core, D11REGOFFS(tsf_cfprep),
3300 (bcnint_us << CFPREP_CBI_SHIFT));
3301 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3302 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3303
3304 /* write interrupt mask */
3305 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3306 DEF_RXINTMASK);
3307
3308 /* allow the MAC to control the PHY clock (dynamic on/off) */
3309 brcms_b_macphyclk_set(wlc_hw, ON);
3310
3311 /* program dynamic clock control fast powerup delay register */
3312 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3313 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3314
3315 /* tell the ucode the corerev */
3316 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3317
3318 /* tell the ucode MAC capabilities */
3319 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3320 (u16) (wlc_hw->machwcap & 0xffff));
3321 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3322 (u16) ((wlc_hw->
3323 machwcap >> 16) & 0xffff));
3324
3325 /* write retry limits to SCR, this done after PSM init */
3326 bcma_write32(core, D11REGOFFS(objaddr),
3327 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3328 (void)bcma_read32(core, D11REGOFFS(objaddr));
3329 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3330 bcma_write32(core, D11REGOFFS(objaddr),
3331 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3332 (void)bcma_read32(core, D11REGOFFS(objaddr));
3333 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3334
3335 /* write rate fallback retry limits */
3336 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3337 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3338
3339 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3340 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3341
3342 /* init the tx dma engines */
3343 for (i = 0; i < NFIFO; i++) {
3344 if (wlc_hw->di[i])
3345 dma_txinit(wlc_hw->di[i]);
3346 }
3347
3348 /* init the rx dma engine(s) and post receive buffers */
3349 dma_rxinit(wlc_hw->di[RX_FIFO]);
3350 dma_rxfill(wlc_hw->di[RX_FIFO]);
3351}
3352
3353void
3354static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3355 u32 macintmask;
3356 bool fastclk;
3357 struct brcms_c_info *wlc = wlc_hw->wlc;
3358
3359 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3360
3361 /* request FAST clock if not on */
3362 fastclk = wlc_hw->forcefastclk;
3363 if (!fastclk)
3364 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3365
3366 /* disable interrupts */
3367 macintmask = brcms_intrsoff(wlc->wl);
3368
3369 /* set up the specified band and chanspec */
3370 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3371 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3372
3373 /* do one-time phy inits and calibration */
3374 wlc_phy_cal_init(wlc_hw->band->pi);
3375
3376 /* core-specific initialization */
3377 brcms_b_coreinit(wlc);
3378
3379 /* band-specific inits */
3380 brcms_b_bsinit(wlc, chanspec);
3381
3382 /* restore macintmask */
3383 brcms_intrsrestore(wlc->wl, macintmask);
3384
3385 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3386 * is suspended and brcms_c_enable_mac() will clear this override bit.
3387 */
3388 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3389
3390 /*
3391 * initialize mac_suspend_depth to 1 to match ucode
3392 * initial suspended state
3393 */
3394 wlc_hw->mac_suspend_depth = 1;
3395
3396 /* restore the clk */
3397 if (!fastclk)
3398 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3399}
3400
3401static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3402 u16 chanspec)
3403{
3404 /* Save our copy of the chanspec */
3405 wlc->chanspec = chanspec;
3406
3407 /* Set the chanspec and power limits for this locale */
3408 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3409
3410 if (wlc->stf->ss_algosel_auto)
3411 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3412 chanspec);
3413
3414 brcms_c_stf_ss_update(wlc, wlc->band);
3415}
3416
3417static void
3418brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3419{
3420 brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3421 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3422 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3423 brcms_chspec_bw(wlc->default_bss->chanspec),
3424 wlc->stf->txstreams);
3425}
3426
3427/* derive wlc->band->basic_rate[] table from 'rateset' */
3428static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3429 struct brcms_c_rateset *rateset)
3430{
3431 u8 rate;
3432 u8 mandatory;
3433 u8 cck_basic = 0;
3434 u8 ofdm_basic = 0;
3435 u8 *br = wlc->band->basic_rate;
3436 uint i;
3437
3438 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3439 memset(br, 0, BRCM_MAXRATE + 1);
3440
3441 /* For each basic rate in the rates list, make an entry in the
3442 * best basic lookup.
3443 */
3444 for (i = 0; i < rateset->count; i++) {
3445 /* only make an entry for a basic rate */
3446 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3447 continue;
3448
3449 /* mask off basic bit */
3450 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3451
3452 if (rate > BRCM_MAXRATE) {
3453 wiphy_err(wlc->wiphy, "brcms_c_rate_lookup_init: "
3454 "invalid rate 0x%X in rate set\n",
3455 rateset->rates[i]);
3456 continue;
3457 }
3458
3459 br[rate] = rate;
3460 }
3461
3462 /* The rate lookup table now has non-zero entries for each
3463 * basic rate, equal to the basic rate: br[basicN] = basicN
3464 *
3465 * To look up the best basic rate corresponding to any
3466 * particular rate, code can use the basic_rate table
3467 * like this
3468 *
3469 * basic_rate = wlc->band->basic_rate[tx_rate]
3470 *
3471 * Make sure there is a best basic rate entry for
3472 * every rate by walking up the table from low rates
3473 * to high, filling in holes in the lookup table
3474 */
3475
3476 for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3477 rate = wlc->band->hw_rateset.rates[i];
3478
3479 if (br[rate] != 0) {
3480 /* This rate is a basic rate.
3481 * Keep track of the best basic rate so far by
3482 * modulation type.
3483 */
3484 if (is_ofdm_rate(rate))
3485 ofdm_basic = rate;
3486 else
3487 cck_basic = rate;
3488
3489 continue;
3490 }
3491
3492 /* This rate is not a basic rate so figure out the
3493 * best basic rate less than this rate and fill in
3494 * the hole in the table
3495 */
3496
3497 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3498
3499 if (br[rate] != 0)
3500 continue;
3501
3502 if (is_ofdm_rate(rate)) {
3503 /*
3504 * In 11g and 11a, the OFDM mandatory rates
3505 * are 6, 12, and 24 Mbps
3506 */
3507 if (rate >= BRCM_RATE_24M)
3508 mandatory = BRCM_RATE_24M;
3509 else if (rate >= BRCM_RATE_12M)
3510 mandatory = BRCM_RATE_12M;
3511 else
3512 mandatory = BRCM_RATE_6M;
3513 } else {
3514 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3515 mandatory = rate;
3516 }
3517
3518 br[rate] = mandatory;
3519 }
3520}
3521
3522static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3523 u16 chanspec)
3524{
3525 struct brcms_c_rateset default_rateset;
3526 uint parkband;
3527 uint i, band_order[2];
3528
3529 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3530 /*
3531 * We might have been bandlocked during down and the chip
3532 * power-cycled (hibernate). Figure out the right band to park on
3533 */
3534 if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3535 /* updated in brcms_c_bandlock() */
3536 parkband = wlc->band->bandunit;
3537 band_order[0] = band_order[1] = parkband;
3538 } else {
3539 /* park on the band of the specified chanspec */
3540 parkband = chspec_bandunit(chanspec);
3541
3542 /* order so that parkband initialize last */
3543 band_order[0] = parkband ^ 1;
3544 band_order[1] = parkband;
3545 }
3546
3547 /* make each band operational, software state init */
3548 for (i = 0; i < wlc->pub->_nbands; i++) {
3549 uint j = band_order[i];
3550
3551 wlc->band = wlc->bandstate[j];
3552
3553 brcms_default_rateset(wlc, &default_rateset);
3554
3555 /* fill in hw_rate */
3556 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3557 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3558 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3559
3560 /* init basic rate lookup */
3561 brcms_c_rate_lookup_init(wlc, &default_rateset);
3562 }
3563
3564 /* sync up phy/radio chanspec */
3565 brcms_c_set_phy_chanspec(wlc, chanspec);
3566}
3567
3568/*
3569 * Set or clear filtering related maccontrol bits based on
3570 * specified filter flags
3571 */
3572void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3573{
3574 u32 promisc_bits = 0;
3575
3576 wlc->filter_flags = filter_flags;
3577
3578 if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3579 promisc_bits |= MCTL_PROMISC;
3580
3581 if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3582 promisc_bits |= MCTL_BCNS_PROMISC;
3583
3584 if (filter_flags & FIF_FCSFAIL)
3585 promisc_bits |= MCTL_KEEPBADFCS;
3586
3587 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3588 promisc_bits |= MCTL_KEEPCONTROL;
3589
3590 brcms_b_mctrl(wlc->hw,
3591 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3592 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3593 promisc_bits);
3594}
3595
3596/*
3597 * ucode, hwmac update
3598 * Channel dependent updates for ucode and hw
3599 */
3600static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3601{
3602 /* enable or disable any active IBSSs depending on whether or not
3603 * we are on the home channel
3604 */
3605 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3606 if (wlc->pub->associated) {
3607 /*
3608 * BMAC_NOTE: This is something that should be fixed
3609 * in ucode inits. I think that the ucode inits set
3610 * up the bcn templates and shm values with a bogus
3611 * beacon. This should not be done in the inits. If
3612 * ucode needs to set up a beacon for testing, the
3613 * test routines should write it down, not expect the
3614 * inits to populate a bogus beacon.
3615 */
3616 if (BRCMS_PHY_11N_CAP(wlc->band))
3617 brcms_b_write_shm(wlc->hw,
3618 M_BCN_TXTSF_OFFSET, 0);
3619 }
3620 } else {
3621 /* disable an active IBSS if we are not on the home channel */
3622 }
3623}
3624
3625static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3626 u8 basic_rate)
3627{
3628 u8 phy_rate, index;
3629 u8 basic_phy_rate, basic_index;
3630 u16 dir_table, basic_table;
3631 u16 basic_ptr;
3632
3633 /* Shared memory address for the table we are reading */
3634 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3635
3636 /* Shared memory address for the table we are writing */
3637 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3638
3639 /*
3640 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3641 * the index into the rate table.
3642 */
3643 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3644 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3645 index = phy_rate & 0xf;
3646 basic_index = basic_phy_rate & 0xf;
3647
3648 /* Find the SHM pointer to the ACK rate entry by looking in the
3649 * Direct-map Table
3650 */
3651 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3652
3653 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3654 * to the correct basic rate for the given incoming rate
3655 */
3656 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3657}
3658
3659static const struct brcms_c_rateset *
3660brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3661{
3662 const struct brcms_c_rateset *rs_dflt;
3663
3664 if (BRCMS_PHY_11N_CAP(wlc->band)) {
3665 if (wlc->band->bandtype == BRCM_BAND_5G)
3666 rs_dflt = &ofdm_mimo_rates;
3667 else
3668 rs_dflt = &cck_ofdm_mimo_rates;
3669 } else if (wlc->band->gmode)
3670 rs_dflt = &cck_ofdm_rates;
3671 else
3672 rs_dflt = &cck_rates;
3673
3674 return rs_dflt;
3675}
3676
3677static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3678{
3679 const struct brcms_c_rateset *rs_dflt;
3680 struct brcms_c_rateset rs;
3681 u8 rate, basic_rate;
3682 uint i;
3683
3684 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3685
3686 brcms_c_rateset_copy(rs_dflt, &rs);
3687 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3688
3689 /* walk the phy rate table and update SHM basic rate lookup table */
3690 for (i = 0; i < rs.count; i++) {
3691 rate = rs.rates[i] & BRCMS_RATE_MASK;
3692
3693 /* for a given rate brcms_basic_rate returns the rate at
3694 * which a response ACK/CTS should be sent.
3695 */
3696 basic_rate = brcms_basic_rate(wlc, rate);
3697 if (basic_rate == 0)
3698 /* This should only happen if we are using a
3699 * restricted rateset.
3700 */
3701 basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3702
3703 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3704 }
3705}
3706
3707/* band-specific init */
3708static void brcms_c_bsinit(struct brcms_c_info *wlc)
3709{
3710 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
3711 wlc->pub->unit, wlc->band->bandunit);
3712
3713 /* write ucode ACK/CTS rate table */
3714 brcms_c_set_ratetable(wlc);
3715
3716 /* update some band specific mac configuration */
3717 brcms_c_ucode_mac_upd(wlc);
3718
3719 /* init antenna selection */
3720 brcms_c_antsel_init(wlc->asi);
3721
3722}
3723
3724/* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3725static int
3726brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3727 bool writeToShm)
3728{
3729 int idle_busy_ratio_x_16 = 0;
3730 uint offset =
3731 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3732 M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3733 if (duty_cycle > 100 || duty_cycle < 0) {
3734 wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n",
3735 wlc->pub->unit);
3736 return -EINVAL;
3737 }
3738 if (duty_cycle)
3739 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3740 /* Only write to shared memory when wl is up */
3741 if (writeToShm)
3742 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3743
3744 if (isOFDM)
3745 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3746 else
3747 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3748
3749 return 0;
3750}
3751
3752/*
3753 * Initialize the base precedence map for dequeueing
3754 * from txq based on WME settings
3755 */
3756static void brcms_c_tx_prec_map_init(struct brcms_c_info *wlc)
3757{
3758 wlc->tx_prec_map = BRCMS_PREC_BMP_ALL;
3759 memset(wlc->fifo2prec_map, 0, NFIFO * sizeof(u16));
3760
3761 wlc->fifo2prec_map[TX_AC_BK_FIFO] = BRCMS_PREC_BMP_AC_BK;
3762 wlc->fifo2prec_map[TX_AC_BE_FIFO] = BRCMS_PREC_BMP_AC_BE;
3763 wlc->fifo2prec_map[TX_AC_VI_FIFO] = BRCMS_PREC_BMP_AC_VI;
3764 wlc->fifo2prec_map[TX_AC_VO_FIFO] = BRCMS_PREC_BMP_AC_VO;
3765}
3766
3767static void
3768brcms_c_txflowcontrol_signal(struct brcms_c_info *wlc,
3769 struct brcms_txq_info *qi, bool on, int prio)
3770{
3771 /* transmit flowcontrol is not yet implemented */
3772}
3773
3774static void brcms_c_txflowcontrol_reset(struct brcms_c_info *wlc)
3775{
3776 struct brcms_txq_info *qi;
3777
3778 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
3779 if (qi->stopped) {
3780 brcms_c_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
3781 qi->stopped = 0;
3782 }
3783 }
3784}
3785
3786/* push sw hps and wake state through hardware */
3787static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3788{
3789 u32 v1, v2;
3790 bool hps;
3791 bool awake_before;
3792
3793 hps = brcms_c_ps_allowed(wlc);
3794
3795 BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
3796
3797 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3798 v2 = MCTL_WAKE;
3799 if (hps)
3800 v2 |= MCTL_HPS;
3801
3802 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3803
3804 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3805
3806 if (!awake_before)
3807 brcms_b_wait_for_wake(wlc->hw);
3808}
3809
3810/*
3811 * Write this BSS config's MAC address to core.
3812 * Updates RXE match engine.
3813 */
3814static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3815{
3816 int err = 0;
3817 struct brcms_c_info *wlc = bsscfg->wlc;
3818
3819 /* enter the MAC addr into the RXE match registers */
3820 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3821
3822 brcms_c_ampdu_macaddr_upd(wlc);
3823
3824 return err;
3825}
3826
3827/* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3828 * Updates RXE match engine.
3829 */
3830static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3831{
3832 /* we need to update BSSID in RXE match registers */
3833 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3834}
3835
3836static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3837{
3838 wlc_hw->shortslot = shortslot;
3839
3840 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3841 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3842 brcms_b_update_slot_timing(wlc_hw, shortslot);
3843 brcms_c_enable_mac(wlc_hw->wlc);
3844 }
3845}
3846
3847/*
3848 * Suspend the the MAC and update the slot timing
3849 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3850 */
3851static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3852{
3853 /* use the override if it is set */
3854 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3855 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3856
3857 if (wlc->shortslot == shortslot)
3858 return;
3859
3860 wlc->shortslot = shortslot;
3861
3862 brcms_b_set_shortslot(wlc->hw, shortslot);
3863}
3864
3865static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3866{
3867 if (wlc->home_chanspec != chanspec) {
3868 wlc->home_chanspec = chanspec;
3869
3870 if (wlc->bsscfg->associated)
3871 wlc->bsscfg->current_bss->chanspec = chanspec;
3872 }
3873}
3874
3875void
3876brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3877 bool mute_tx, struct txpwr_limits *txpwr)
3878{
3879 uint bandunit;
3880
3881 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
3882
3883 wlc_hw->chanspec = chanspec;
3884
3885 /* Switch bands if necessary */
3886 if (wlc_hw->_nbands > 1) {
3887 bandunit = chspec_bandunit(chanspec);
3888 if (wlc_hw->band->bandunit != bandunit) {
3889 /* brcms_b_setband disables other bandunit,
3890 * use light band switch if not up yet
3891 */
3892 if (wlc_hw->up) {
3893 wlc_phy_chanspec_radio_set(wlc_hw->
3894 bandstate[bandunit]->
3895 pi, chanspec);
3896 brcms_b_setband(wlc_hw, bandunit, chanspec);
3897 } else {
3898 brcms_c_setxband(wlc_hw, bandunit);
3899 }
3900 }
3901 }
3902
3903 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3904
3905 if (!wlc_hw->up) {
3906 if (wlc_hw->clk)
3907 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3908 chanspec);
3909 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3910 } else {
3911 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3912 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3913
3914 /* Update muting of the channel */
3915 brcms_b_mute(wlc_hw, mute_tx);
3916 }
3917}
3918
3919/* switch to and initialize new band */
3920static void brcms_c_setband(struct brcms_c_info *wlc,
3921 uint bandunit)
3922{
3923 wlc->band = wlc->bandstate[bandunit];
3924
3925 if (!wlc->pub->up)
3926 return;
3927
3928 /* wait for at least one beacon before entering sleeping state */
3929 brcms_c_set_ps_ctrl(wlc);
3930
3931 /* band-specific initializations */
3932 brcms_c_bsinit(wlc);
3933}
3934
3935static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3936{
3937 uint bandunit;
3938 bool switchband = false;
3939 u16 old_chanspec = wlc->chanspec;
3940
3941 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3942 wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
3943 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3944 return;
3945 }
3946
3947 /* Switch bands if necessary */
3948 if (wlc->pub->_nbands > 1) {
3949 bandunit = chspec_bandunit(chanspec);
3950 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3951 switchband = true;
3952 if (wlc->bandlocked) {
3953 wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
3954 "band is locked!\n",
3955 wlc->pub->unit, __func__,
3956 CHSPEC_CHANNEL(chanspec));
3957 return;
3958 }
3959 /*
3960 * should the setband call come after the
3961 * brcms_b_chanspec() ? if the setband updates
3962 * (brcms_c_bsinit) use low level calls to inspect and
3963 * set state, the state inspected may be from the wrong
3964 * band, or the following brcms_b_set_chanspec() may
3965 * undo the work.
3966 */
3967 brcms_c_setband(wlc, bandunit);
3968 }
3969 }
3970
3971 /* sync up phy/radio chanspec */
3972 brcms_c_set_phy_chanspec(wlc, chanspec);
3973
3974 /* init antenna selection */
3975 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3976 brcms_c_antsel_init(wlc->asi);
3977
3978 /* Fix the hardware rateset based on bw.
3979 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3980 */
3981 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3982 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3983 }
3984
3985 /* update some mac configuration since chanspec changed */
3986 brcms_c_ucode_mac_upd(wlc);
3987}
3988
3989/*
3990 * This function changes the phytxctl for beacon based on current
3991 * beacon ratespec AND txant setting as per this table:
3992 * ratespec CCK ant = wlc->stf->txant
3993 * OFDM ant = 3
3994 */
3995void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3996 u32 bcn_rspec)
3997{
3998 u16 phyctl;
3999 u16 phytxant = wlc->stf->phytxant;
4000 u16 mask = PHY_TXC_ANT_MASK;
4001
4002 /* for non-siso rates or default setting, use the available chains */
4003 if (BRCMS_PHY_11N_CAP(wlc->band))
4004 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
4005
4006 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
4007 phyctl = (phyctl & ~mask) | phytxant;
4008 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
4009}
4010
4011/*
4012 * centralized protection config change function to simplify debugging, no
4013 * consistency checking this should be called only on changes to avoid overhead
4014 * in periodic function
4015 */
4016void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
4017{
4018 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
4019
4020 switch (idx) {
4021 case BRCMS_PROT_G_SPEC:
4022 wlc->protection->_g = (bool) val;
4023 break;
4024 case BRCMS_PROT_G_OVR:
4025 wlc->protection->g_override = (s8) val;
4026 break;
4027 case BRCMS_PROT_G_USER:
4028 wlc->protection->gmode_user = (u8) val;
4029 break;
4030 case BRCMS_PROT_OVERLAP:
4031 wlc->protection->overlap = (s8) val;
4032 break;
4033 case BRCMS_PROT_N_USER:
4034 wlc->protection->nmode_user = (s8) val;
4035 break;
4036 case BRCMS_PROT_N_CFG:
4037 wlc->protection->n_cfg = (s8) val;
4038 break;
4039 case BRCMS_PROT_N_CFG_OVR:
4040 wlc->protection->n_cfg_override = (s8) val;
4041 break;
4042 case BRCMS_PROT_N_NONGF:
4043 wlc->protection->nongf = (bool) val;
4044 break;
4045 case BRCMS_PROT_N_NONGF_OVR:
4046 wlc->protection->nongf_override = (s8) val;
4047 break;
4048 case BRCMS_PROT_N_PAM_OVR:
4049 wlc->protection->n_pam_override = (s8) val;
4050 break;
4051 case BRCMS_PROT_N_OBSS:
4052 wlc->protection->n_obss = (bool) val;
4053 break;
4054
4055 default:
4056 break;
4057 }
4058
4059}
4060
4061static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4062{
4063 if (wlc->pub->up) {
4064 brcms_c_update_beacon(wlc);
4065 brcms_c_update_probe_resp(wlc, true);
4066 }
4067}
4068
4069static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4070{
4071 wlc->stf->ldpc = val;
4072
4073 if (wlc->pub->up) {
4074 brcms_c_update_beacon(wlc);
4075 brcms_c_update_probe_resp(wlc, true);
4076 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4077 }
4078}
4079
4080void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4081 const struct ieee80211_tx_queue_params *params,
4082 bool suspend)
4083{
4084 int i;
4085 struct shm_acparams acp_shm;
4086 u16 *shm_entry;
4087
4088 /* Only apply params if the core is out of reset and has clocks */
4089 if (!wlc->clk) {
4090 wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
4091 __func__);
4092 return;
4093 }
4094
4095 memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
4096 /* fill in shm ac params struct */
4097 acp_shm.txop = params->txop;
4098 /* convert from units of 32us to us for ucode */
4099 wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4100 EDCF_TXOP2USEC(acp_shm.txop);
4101 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4102
4103 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4104 && acp_shm.aifs < EDCF_AIFSN_MAX)
4105 acp_shm.aifs++;
4106
4107 if (acp_shm.aifs < EDCF_AIFSN_MIN
4108 || acp_shm.aifs > EDCF_AIFSN_MAX) {
4109 wiphy_err(wlc->wiphy, "wl%d: edcf_setparams: bad "
4110 "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4111 } else {
4112 acp_shm.cwmin = params->cw_min;
4113 acp_shm.cwmax = params->cw_max;
4114 acp_shm.cwcur = acp_shm.cwmin;
4115 acp_shm.bslots =
4116 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4117 acp_shm.cwcur;
4118 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4119 /* Indicate the new params to the ucode */
4120 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4121 wme_ac2fifo[aci] *
4122 M_EDCF_QLEN +
4123 M_EDCF_STATUS_OFF));
4124 acp_shm.status |= WME_STATUS_NEWAC;
4125
4126 /* Fill in shm acparam table */
4127 shm_entry = (u16 *) &acp_shm;
4128 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4129 brcms_b_write_shm(wlc->hw,
4130 M_EDCF_QINFO +
4131 wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4132 *shm_entry++);
4133 }
4134
4135 if (suspend) {
4136 brcms_c_suspend_mac_and_wait(wlc);
4137 brcms_c_enable_mac(wlc);
4138 }
4139}
4140
4141static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4142{
4143 u16 aci;
4144 int i_ac;
4145 struct ieee80211_tx_queue_params txq_pars;
4146 static const struct edcf_acparam default_edcf_acparams[] = {
4147 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4148 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4149 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4150 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4151 }; /* ucode needs these parameters during its initialization */
4152 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4153
4154 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4155 /* find out which ac this set of params applies to */
4156 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4157
4158 /* fill in shm ac params struct */
4159 txq_pars.txop = edcf_acp->TXOP;
4160 txq_pars.aifs = edcf_acp->ACI;
4161
4162 /* CWmin = 2^(ECWmin) - 1 */
4163 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4164 /* CWmax = 2^(ECWmax) - 1 */
4165 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4166 >> EDCF_ECWMAX_SHIFT);
4167 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4168 }
4169
4170 if (suspend) {
4171 brcms_c_suspend_mac_and_wait(wlc);
4172 brcms_c_enable_mac(wlc);
4173 }
4174}
4175
4176static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4177{
4178 /* Don't start the timer if HWRADIO feature is disabled */
4179 if (wlc->radio_monitor)
4180 return;
4181
4182 wlc->radio_monitor = true;
4183 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4184 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4185}
4186
4187static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4188{
4189 if (!wlc->radio_monitor)
4190 return true;
4191
4192 wlc->radio_monitor = false;
4193 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4194 return brcms_del_timer(wlc->radio_timer);
4195}
4196
4197/* read hwdisable state and propagate to wlc flag */
4198static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4199{
4200 if (wlc->pub->hw_off)
4201 return;
4202
4203 if (brcms_b_radio_read_hwdisabled(wlc->hw))
4204 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4205 else
4206 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4207}
4208
4209/* update hwradio status and return it */
4210bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4211{
4212 brcms_c_radio_hwdisable_upd(wlc);
4213
4214 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4215 true : false;
4216}
4217
4218/* periodical query hw radio button while driver is "down" */
4219static void brcms_c_radio_timer(void *arg)
4220{
4221 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4222
4223 if (brcms_deviceremoved(wlc)) {
4224 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4225 __func__);
4226 brcms_down(wlc->wl);
4227 return;
4228 }
4229
4230 brcms_c_radio_hwdisable_upd(wlc);
4231}
4232
4233/* common low-level watchdog code */
4234static void brcms_b_watchdog(void *arg)
4235{
4236 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4237 struct brcms_hardware *wlc_hw = wlc->hw;
4238
4239 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
4240
4241 if (!wlc_hw->up)
4242 return;
4243
4244 /* increment second count */
4245 wlc_hw->now++;
4246
4247 /* Check for FIFO error interrupts */
4248 brcms_b_fifoerrors(wlc_hw);
4249
4250 /* make sure RX dma has buffers */
4251 dma_rxfill(wlc->hw->di[RX_FIFO]);
4252
4253 wlc_phy_watchdog(wlc_hw->band->pi);
4254}
4255
4256/* common watchdog code */
4257static void brcms_c_watchdog(void *arg)
4258{
4259 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4260
4261 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4262
4263 if (!wlc->pub->up)
4264 return;
4265
4266 if (brcms_deviceremoved(wlc)) {
4267 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4268 __func__);
4269 brcms_down(wlc->wl);
4270 return;
4271 }
4272
4273 /* increment second count */
4274 wlc->pub->now++;
4275
4276 brcms_c_radio_hwdisable_upd(wlc);
4277 /* if radio is disable, driver may be down, quit here */
4278 if (wlc->pub->radio_disabled)
4279 return;
4280
4281 brcms_b_watchdog(wlc);
4282
4283 /*
4284 * occasionally sample mac stat counters to
4285 * detect 16-bit counter wrap
4286 */
4287 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4288 brcms_c_statsupd(wlc);
4289
4290 if (BRCMS_ISNPHY(wlc->band) &&
4291 ((wlc->pub->now - wlc->tempsense_lasttime) >=
4292 BRCMS_TEMPSENSE_PERIOD)) {
4293 wlc->tempsense_lasttime = wlc->pub->now;
4294 brcms_c_tempsense_upd(wlc);
4295 }
4296}
4297
4298static void brcms_c_watchdog_by_timer(void *arg)
4299{
4300 brcms_c_watchdog(arg);
4301}
4302
4303static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4304{
4305 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4306 wlc, "watchdog");
4307 if (!wlc->wdtimer) {
4308 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
4309 "failed\n", unit);
4310 goto fail;
4311 }
4312
4313 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4314 wlc, "radio");
4315 if (!wlc->radio_timer) {
4316 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
4317 "failed\n", unit);
4318 goto fail;
4319 }
4320
4321 return true;
4322
4323 fail:
4324 return false;
4325}
4326
4327/*
4328 * Initialize brcms_c_info default values ...
4329 * may get overrides later in this function
4330 */
4331static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4332{
4333 int i;
4334
4335 /* Save our copy of the chanspec */
4336 wlc->chanspec = ch20mhz_chspec(1);
4337
4338 /* various 802.11g modes */
4339 wlc->shortslot = false;
4340 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4341
4342 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4343 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4344
4345 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4346 BRCMS_PROTECTION_AUTO);
4347 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4348 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4349 BRCMS_PROTECTION_AUTO);
4350 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4351 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4352
4353 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4354 BRCMS_PROTECTION_CTL_OVERLAP);
4355
4356 /* 802.11g draft 4.0 NonERP elt advertisement */
4357 wlc->include_legacy_erp = true;
4358
4359 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4360 wlc->stf->txant = ANT_TX_DEF;
4361
4362 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4363
4364 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4365 for (i = 0; i < NFIFO; i++)
4366 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4367 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4368
4369 /* default rate fallback retry limits */
4370 wlc->SFBL = RETRY_SHORT_FB;
4371 wlc->LFBL = RETRY_LONG_FB;
4372
4373 /* default mac retry limits */
4374 wlc->SRL = RETRY_SHORT_DEF;
4375 wlc->LRL = RETRY_LONG_DEF;
4376
4377 /* WME QoS mode is Auto by default */
4378 wlc->pub->_ampdu = AMPDU_AGG_HOST;
4379 wlc->pub->bcmerror = 0;
4380}
4381
4382static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4383{
4384 uint err = 0;
4385 uint unit;
4386 unit = wlc->pub->unit;
4387
4388 wlc->asi = brcms_c_antsel_attach(wlc);
4389 if (wlc->asi == NULL) {
4390 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4391 "failed\n", unit);
4392 err = 44;
4393 goto fail;
4394 }
4395
4396 wlc->ampdu = brcms_c_ampdu_attach(wlc);
4397 if (wlc->ampdu == NULL) {
4398 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4399 "failed\n", unit);
4400 err = 50;
4401 goto fail;
4402 }
4403
4404 if ((brcms_c_stf_attach(wlc) != 0)) {
4405 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4406 "failed\n", unit);
4407 err = 68;
4408 goto fail;
4409 }
4410 fail:
4411 return err;
4412}
4413
4414struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4415{
4416 return wlc->pub;
4417}
4418
4419/* low level attach
4420 * run backplane attach, init nvram
4421 * run phy attach
4422 * initialize software state for each core and band
4423 * put the whole chip in reset(driver down state), no clock
4424 */
4425static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4426 uint unit, bool piomode)
4427{
4428 struct brcms_hardware *wlc_hw;
4429 uint err = 0;
4430 uint j;
4431 bool wme = false;
4432 struct shared_phy_params sha_params;
4433 struct wiphy *wiphy = wlc->wiphy;
4434 struct pci_dev *pcidev = core->bus->host_pci;
4435 struct ssb_sprom *sprom = &core->bus->sprom;
4436
4437 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4438 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4439 pcidev->vendor,
4440 pcidev->device);
4441 else
4442 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4443 core->bus->boardinfo.vendor,
4444 core->bus->boardinfo.type);
4445
4446 wme = true;
4447
4448 wlc_hw = wlc->hw;
4449 wlc_hw->wlc = wlc;
4450 wlc_hw->unit = unit;
4451 wlc_hw->band = wlc_hw->bandstate[0];
4452 wlc_hw->_piomode = piomode;
4453
4454 /* populate struct brcms_hardware with default values */
4455 brcms_b_info_init(wlc_hw);
4456
4457 /*
4458 * Do the hardware portion of the attach. Also initialize software
4459 * state that depends on the particular hardware we are running.
4460 */
4461 wlc_hw->sih = ai_attach(core->bus);
4462 if (wlc_hw->sih == NULL) {
4463 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4464 unit);
4465 err = 11;
4466 goto fail;
4467 }
4468
4469 /* verify again the device is supported */
4470 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI &&
4471 !brcms_c_chipmatch(pcidev->vendor, pcidev->device)) {
4472 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
4473 "vendor/device (0x%x/0x%x)\n",
4474 unit, pcidev->vendor, pcidev->device);
4475 err = 12;
4476 goto fail;
4477 }
4478
4479 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4480 wlc_hw->vendorid = pcidev->vendor;
4481 wlc_hw->deviceid = pcidev->device;
4482 } else {
4483 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4484 wlc_hw->deviceid = core->bus->boardinfo.type;
4485 }
4486
4487 wlc_hw->d11core = core;
4488 wlc_hw->corerev = core->id.rev;
4489
4490 /* validate chip, chiprev and corerev */
4491 if (!brcms_c_isgoodchip(wlc_hw)) {
4492 err = 13;
4493 goto fail;
4494 }
4495
4496 /* initialize power control registers */
4497 ai_clkctl_init(wlc_hw->sih);
4498
4499 /* request fastclock and force fastclock for the rest of attach
4500 * bring the d11 core out of reset.
4501 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4502 * is still false; But it will be called again inside wlc_corereset,
4503 * after d11 is out of reset.
4504 */
4505 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4506 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4507
4508 if (!brcms_b_validate_chip_access(wlc_hw)) {
4509 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4510 "failed\n", unit);
4511 err = 14;
4512 goto fail;
4513 }
4514
4515 /* get the board rev, used just below */
4516 j = sprom->board_rev;
4517 /* promote srom boardrev of 0xFF to 1 */
4518 if (j == BOARDREV_PROMOTABLE)
4519 j = BOARDREV_PROMOTED;
4520 wlc_hw->boardrev = (u16) j;
4521 if (!brcms_c_validboardtype(wlc_hw)) {
4522 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4523 "board type (0x%x)" " or revision level (0x%x)\n",
4524 unit, ai_get_boardtype(wlc_hw->sih),
4525 wlc_hw->boardrev);
4526 err = 15;
4527 goto fail;
4528 }
4529 wlc_hw->sromrev = sprom->revision;
4530 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4531 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4532
4533 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4534 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4535
4536 /* check device id(srom, nvram etc.) to set bands */
4537 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4538 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1)
4539 /* Dualband boards */
4540 wlc_hw->_nbands = 2;
4541 else
4542 wlc_hw->_nbands = 1;
4543
4544 if ((ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
4545 wlc_hw->_nbands = 1;
4546
4547 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4548 * unconditionally does the init of these values
4549 */
4550 wlc->vendorid = wlc_hw->vendorid;
4551 wlc->deviceid = wlc_hw->deviceid;
4552 wlc->pub->sih = wlc_hw->sih;
4553 wlc->pub->corerev = wlc_hw->corerev;
4554 wlc->pub->sromrev = wlc_hw->sromrev;
4555 wlc->pub->boardrev = wlc_hw->boardrev;
4556 wlc->pub->boardflags = wlc_hw->boardflags;
4557 wlc->pub->boardflags2 = wlc_hw->boardflags2;
4558 wlc->pub->_nbands = wlc_hw->_nbands;
4559
4560 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4561
4562 if (wlc_hw->physhim == NULL) {
4563 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4564 "failed\n", unit);
4565 err = 25;
4566 goto fail;
4567 }
4568
4569 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4570 sha_params.sih = wlc_hw->sih;
4571 sha_params.physhim = wlc_hw->physhim;
4572 sha_params.unit = unit;
4573 sha_params.corerev = wlc_hw->corerev;
4574 sha_params.vid = wlc_hw->vendorid;
4575 sha_params.did = wlc_hw->deviceid;
4576 sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4577 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4578 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4579 sha_params.sromrev = wlc_hw->sromrev;
4580 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4581 sha_params.boardrev = wlc_hw->boardrev;
4582 sha_params.boardflags = wlc_hw->boardflags;
4583 sha_params.boardflags2 = wlc_hw->boardflags2;
4584
4585 /* alloc and save pointer to shared phy state area */
4586 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4587 if (!wlc_hw->phy_sh) {
4588 err = 16;
4589 goto fail;
4590 }
4591
4592 /* initialize software state for each core and band */
4593 for (j = 0; j < wlc_hw->_nbands; j++) {
4594 /*
4595 * band0 is always 2.4Ghz
4596 * band1, if present, is 5Ghz
4597 */
4598
4599 brcms_c_setxband(wlc_hw, j);
4600
4601 wlc_hw->band->bandunit = j;
4602 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4603 wlc->band->bandunit = j;
4604 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4605 wlc->core->coreidx = core->core_index;
4606
4607 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4608 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4609
4610 /* init tx fifo size */
4611 wlc_hw->xmtfifo_sz =
4612 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4613
4614 /* Get a phy for this band */
4615 wlc_hw->band->pi =
4616 wlc_phy_attach(wlc_hw->phy_sh, core,
4617 wlc_hw->band->bandtype,
4618 wlc->wiphy);
4619 if (wlc_hw->band->pi == NULL) {
4620 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4621 "attach failed\n", unit);
4622 err = 17;
4623 goto fail;
4624 }
4625
4626 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4627
4628 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4629 &wlc_hw->band->phyrev,
4630 &wlc_hw->band->radioid,
4631 &wlc_hw->band->radiorev);
4632 wlc_hw->band->abgphy_encore =
4633 wlc_phy_get_encore(wlc_hw->band->pi);
4634 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4635 wlc_hw->band->core_flags =
4636 wlc_phy_get_coreflags(wlc_hw->band->pi);
4637
4638 /* verify good phy_type & supported phy revision */
4639 if (BRCMS_ISNPHY(wlc_hw->band)) {
4640 if (NCONF_HAS(wlc_hw->band->phyrev))
4641 goto good_phy;
4642 else
4643 goto bad_phy;
4644 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4645 if (LCNCONF_HAS(wlc_hw->band->phyrev))
4646 goto good_phy;
4647 else
4648 goto bad_phy;
4649 } else {
4650 bad_phy:
4651 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4652 "phy type/rev (%d/%d)\n", unit,
4653 wlc_hw->band->phytype, wlc_hw->band->phyrev);
4654 err = 18;
4655 goto fail;
4656 }
4657
4658 good_phy:
4659 /*
4660 * BMAC_NOTE: wlc->band->pi should not be set below and should
4661 * be done in the high level attach. However we can not make
4662 * that change until all low level access is changed to
4663 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4664 * keeping wlc_hw->band->pi as well for incremental update of
4665 * low level fns, and cut over low only init when all fns
4666 * updated.
4667 */
4668 wlc->band->pi = wlc_hw->band->pi;
4669 wlc->band->phytype = wlc_hw->band->phytype;
4670 wlc->band->phyrev = wlc_hw->band->phyrev;
4671 wlc->band->radioid = wlc_hw->band->radioid;
4672 wlc->band->radiorev = wlc_hw->band->radiorev;
4673
4674 /* default contention windows size limits */
4675 wlc_hw->band->CWmin = APHY_CWMIN;
4676 wlc_hw->band->CWmax = PHY_CWMAX;
4677
4678 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4679 err = 19;
4680 goto fail;
4681 }
4682 }
4683
4684 /* disable core to match driver "down" state */
4685 brcms_c_coredisable(wlc_hw);
4686
4687 /* Match driver "down" state */
4688 ai_pci_down(wlc_hw->sih);
4689
4690 /* turn off pll and xtal to match driver "down" state */
4691 brcms_b_xtal(wlc_hw, OFF);
4692
4693 /* *******************************************************************
4694 * The hardware is in the DOWN state at this point. D11 core
4695 * or cores are in reset with clocks off, and the board PLLs
4696 * are off if possible.
4697 *
4698 * Beyond this point, wlc->sbclk == false and chip registers
4699 * should not be touched.
4700 *********************************************************************
4701 */
4702
4703 /* init etheraddr state variables */
4704 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4705
4706 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4707 is_zero_ether_addr(wlc_hw->etheraddr)) {
4708 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4709 unit);
4710 err = 22;
4711 goto fail;
4712 }
4713
4714 BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x\n",
4715 wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih));
4716
4717 return err;
4718
4719 fail:
4720 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4721 err);
4722 return err;
4723}
4724
4725static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4726{
4727 uint unit;
4728 unit = wlc->pub->unit;
4729
4730 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4731 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4732 wlc->band->antgain = 8;
4733 } else if (wlc->band->antgain == -1) {
4734 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4735 " srom, using 2dB\n", unit, __func__);
4736 wlc->band->antgain = 8;
4737 } else {
4738 s8 gain, fract;
4739 /* Older sroms specified gain in whole dbm only. In order
4740 * be able to specify qdbm granularity and remain backward
4741 * compatible the whole dbms are now encoded in only
4742 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4743 * 6 bit signed number ranges from -32 - 31.
4744 *
4745 * Examples:
4746 * 0x1 = 1 db,
4747 * 0xc1 = 1.75 db (1 + 3 quarters),
4748 * 0x3f = -1 (-1 + 0 quarters),
4749 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4750 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4751 */
4752 gain = wlc->band->antgain & 0x3f;
4753 gain <<= 2; /* Sign extend */
4754 gain >>= 2;
4755 fract = (wlc->band->antgain & 0xc0) >> 6;
4756 wlc->band->antgain = 4 * gain + fract;
4757 }
4758}
4759
4760static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4761{
4762 int aa;
4763 uint unit;
4764 int bandtype;
4765 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4766
4767 unit = wlc->pub->unit;
4768 bandtype = wlc->band->bandtype;
4769
4770 /* get antennas available */
4771 if (bandtype == BRCM_BAND_5G)
4772 aa = sprom->ant_available_a;
4773 else
4774 aa = sprom->ant_available_bg;
4775
4776 if ((aa < 1) || (aa > 15)) {
4777 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4778 " srom (0x%x), using 3\n", unit, __func__, aa);
4779 aa = 3;
4780 }
4781
4782 /* reset the defaults if we have a single antenna */
4783 if (aa == 1) {
4784 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4785 wlc->stf->txant = ANT_TX_FORCE_0;
4786 } else if (aa == 2) {
4787 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4788 wlc->stf->txant = ANT_TX_FORCE_1;
4789 } else {
4790 }
4791
4792 /* Compute Antenna Gain */
4793 if (bandtype == BRCM_BAND_5G)
4794 wlc->band->antgain = sprom->antenna_gain.a1;
4795 else
4796 wlc->band->antgain = sprom->antenna_gain.a0;
4797
4798 brcms_c_attach_antgain_init(wlc);
4799
4800 return true;
4801}
4802
4803static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4804{
4805 u16 chanspec;
4806 struct brcms_band *band;
4807 struct brcms_bss_info *bi = wlc->default_bss;
4808
4809 /* init default and target BSS with some sane initial values */
4810 memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
4811 bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4812
4813 /* fill the default channel as the first valid channel
4814 * starting from the 2G channels
4815 */
4816 chanspec = ch20mhz_chspec(1);
4817 wlc->home_chanspec = bi->chanspec = chanspec;
4818
4819 /* find the band of our default channel */
4820 band = wlc->band;
4821 if (wlc->pub->_nbands > 1 &&
4822 band->bandunit != chspec_bandunit(chanspec))
4823 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4824
4825 /* init bss rates to the band specific default rate set */
4826 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4827 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4828 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4829 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4830
4831 if (wlc->pub->_n_enab & SUPPORT_11N)
4832 bi->flags |= BRCMS_BSS_HT;
4833}
4834
4835static struct brcms_txq_info *brcms_c_txq_alloc(struct brcms_c_info *wlc)
4836{
4837 struct brcms_txq_info *qi, *p;
4838
4839 qi = kzalloc(sizeof(struct brcms_txq_info), GFP_ATOMIC);
4840 if (qi != NULL) {
4841 /*
4842 * Have enough room for control packets along with HI watermark
4843 * Also, add room to txq for total psq packets if all the SCBs
4844 * leave PS mode. The watermark for flowcontrol to OS packets
4845 * will remain the same
4846 */
4847 brcmu_pktq_init(&qi->q, BRCMS_PREC_COUNT,
4848 2 * BRCMS_DATAHIWAT + PKTQ_LEN_DEFAULT);
4849
4850 /* add this queue to the the global list */
4851 p = wlc->tx_queues;
4852 if (p == NULL) {
4853 wlc->tx_queues = qi;
4854 } else {
4855 while (p->next != NULL)
4856 p = p->next;
4857 p->next = qi;
4858 }
4859 }
4860 return qi;
4861}
4862
4863static void brcms_c_txq_free(struct brcms_c_info *wlc,
4864 struct brcms_txq_info *qi)
4865{
4866 struct brcms_txq_info *p;
4867
4868 if (qi == NULL)
4869 return;
4870
4871 /* remove the queue from the linked list */
4872 p = wlc->tx_queues;
4873 if (p == qi)
4874 wlc->tx_queues = p->next;
4875 else {
4876 while (p != NULL && p->next != qi)
4877 p = p->next;
4878 if (p != NULL)
4879 p->next = p->next->next;
4880 }
4881
4882 kfree(qi);
4883}
4884
4885static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4886{
4887 uint i;
4888 struct brcms_band *band;
4889
4890 for (i = 0; i < wlc->pub->_nbands; i++) {
4891 band = wlc->bandstate[i];
4892 if (band->bandtype == BRCM_BAND_5G) {
4893 if ((bwcap == BRCMS_N_BW_40ALL)
4894 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4895 band->mimo_cap_40 = true;
4896 else
4897 band->mimo_cap_40 = false;
4898 } else {
4899 if (bwcap == BRCMS_N_BW_40ALL)
4900 band->mimo_cap_40 = true;
4901 else
4902 band->mimo_cap_40 = false;
4903 }
4904 }
4905}
4906
4907static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4908{
4909 /* free timer state */
4910 if (wlc->wdtimer) {
4911 brcms_free_timer(wlc->wdtimer);
4912 wlc->wdtimer = NULL;
4913 }
4914 if (wlc->radio_timer) {
4915 brcms_free_timer(wlc->radio_timer);
4916 wlc->radio_timer = NULL;
4917 }
4918}
4919
4920static void brcms_c_detach_module(struct brcms_c_info *wlc)
4921{
4922 if (wlc->asi) {
4923 brcms_c_antsel_detach(wlc->asi);
4924 wlc->asi = NULL;
4925 }
4926
4927 if (wlc->ampdu) {
4928 brcms_c_ampdu_detach(wlc->ampdu);
4929 wlc->ampdu = NULL;
4930 }
4931
4932 brcms_c_stf_detach(wlc);
4933}
4934
4935/*
4936 * low level detach
4937 */
4938static int brcms_b_detach(struct brcms_c_info *wlc)
4939{
4940 uint i;
4941 struct brcms_hw_band *band;
4942 struct brcms_hardware *wlc_hw = wlc->hw;
4943 int callbacks;
4944
4945 callbacks = 0;
4946
4947 brcms_b_detach_dmapio(wlc_hw);
4948
4949 band = wlc_hw->band;
4950 for (i = 0; i < wlc_hw->_nbands; i++) {
4951 if (band->pi) {
4952 /* Detach this band's phy */
4953 wlc_phy_detach(band->pi);
4954 band->pi = NULL;
4955 }
4956 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4957 }
4958
4959 /* Free shared phy state */
4960 kfree(wlc_hw->phy_sh);
4961
4962 wlc_phy_shim_detach(wlc_hw->physhim);
4963
4964 if (wlc_hw->sih) {
4965 ai_detach(wlc_hw->sih);
4966 wlc_hw->sih = NULL;
4967 }
4968
4969 return callbacks;
4970
4971}
4972
4973/*
4974 * Return a count of the number of driver callbacks still pending.
4975 *
4976 * General policy is that brcms_c_detach can only dealloc/free software states.
4977 * It can NOT touch hardware registers since the d11core may be in reset and
4978 * clock may not be available.
4979 * One exception is sb register access, which is possible if crystal is turned
4980 * on after "down" state, driver should avoid software timer with the exception
4981 * of radio_monitor.
4982 */
4983uint brcms_c_detach(struct brcms_c_info *wlc)
4984{
4985 uint callbacks = 0;
4986
4987 if (wlc == NULL)
4988 return 0;
4989
4990 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4991
4992 callbacks += brcms_b_detach(wlc);
4993
4994 /* delete software timers */
4995 if (!brcms_c_radio_monitor_stop(wlc))
4996 callbacks++;
4997
4998 brcms_c_channel_mgr_detach(wlc->cmi);
4999
5000 brcms_c_timers_deinit(wlc);
5001
5002 brcms_c_detach_module(wlc);
5003
5004
5005 while (wlc->tx_queues != NULL)
5006 brcms_c_txq_free(wlc, wlc->tx_queues);
5007
5008 brcms_c_detach_mfree(wlc);
5009 return callbacks;
5010}
5011
5012/* update state that depends on the current value of "ap" */
5013static void brcms_c_ap_upd(struct brcms_c_info *wlc)
5014{
5015 /* STA-BSS; short capable */
5016 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
5017}
5018
5019/* Initialize just the hardware when coming out of POR or S3/S5 system states */
5020static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
5021{
5022 if (wlc_hw->wlc->pub->hw_up)
5023 return;
5024
5025 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5026
5027 /*
5028 * Enable pll and xtal, initialize the power control registers,
5029 * and force fastclock for the remainder of brcms_c_up().
5030 */
5031 brcms_b_xtal(wlc_hw, ON);
5032 ai_clkctl_init(wlc_hw->sih);
5033 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5034
5035 /*
5036 * TODO: test suspend/resume
5037 *
5038 * AI chip doesn't restore bar0win2 on
5039 * hibernation/resume, need sw fixup
5040 */
5041
5042 /*
5043 * Inform phy that a POR reset has occurred so
5044 * it does a complete phy init
5045 */
5046 wlc_phy_por_inform(wlc_hw->band->pi);
5047
5048 wlc_hw->ucode_loaded = false;
5049 wlc_hw->wlc->pub->hw_up = true;
5050
5051 if ((wlc_hw->boardflags & BFL_FEM)
5052 && (ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
5053 if (!
5054 (wlc_hw->boardrev >= 0x1250
5055 && (wlc_hw->boardflags & BFL_FEM_BT)))
5056 ai_epa_4313war(wlc_hw->sih);
5057 }
5058}
5059
5060static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
5061{
5062 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5063
5064 /*
5065 * Enable pll and xtal, initialize the power control registers,
5066 * and force fastclock for the remainder of brcms_c_up().
5067 */
5068 brcms_b_xtal(wlc_hw, ON);
5069 ai_clkctl_init(wlc_hw->sih);
5070 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5071
5072 /*
5073 * Configure pci/pcmcia here instead of in brcms_c_attach()
5074 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
5075 */
5076 bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
5077 true);
5078
5079 /*
5080 * Need to read the hwradio status here to cover the case where the
5081 * system is loaded with the hw radio disabled. We do not want to
5082 * bring the driver up in this case.
5083 */
5084 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
5085 /* put SB PCI in down state again */
5086 ai_pci_down(wlc_hw->sih);
5087 brcms_b_xtal(wlc_hw, OFF);
5088 return -ENOMEDIUM;
5089 }
5090
5091 ai_pci_up(wlc_hw->sih);
5092
5093 /* reset the d11 core */
5094 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5095
5096 return 0;
5097}
5098
5099static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5100{
5101 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5102
5103 wlc_hw->up = true;
5104 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5105
5106 /* FULLY enable dynamic power control and d11 core interrupt */
5107 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5108 brcms_intrson(wlc_hw->wlc->wl);
5109 return 0;
5110}
5111
5112/*
5113 * Write WME tunable parameters for retransmit/max rate
5114 * from wlc struct to ucode
5115 */
5116static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5117{
5118 int ac;
5119
5120 /* Need clock to do this */
5121 if (!wlc->clk)
5122 return;
5123
5124 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5125 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5126 wlc->wme_retries[ac]);
5127}
5128
5129/* make interface operational */
5130int brcms_c_up(struct brcms_c_info *wlc)
5131{
5132 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5133
5134 /* HW is turned off so don't try to access it */
5135 if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5136 return -ENOMEDIUM;
5137
5138 if (!wlc->pub->hw_up) {
5139 brcms_b_hw_up(wlc->hw);
5140 wlc->pub->hw_up = true;
5141 }
5142
5143 if ((wlc->pub->boardflags & BFL_FEM)
5144 && (ai_get_chip_id(wlc->hw->sih) == BCM4313_CHIP_ID)) {
5145 if (wlc->pub->boardrev >= 0x1250
5146 && (wlc->pub->boardflags & BFL_FEM_BT))
5147 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5148 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5149 else
5150 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5151 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5152 }
5153
5154 /*
5155 * Need to read the hwradio status here to cover the case where the
5156 * system is loaded with the hw radio disabled. We do not want to bring
5157 * the driver up in this case. If radio is disabled, abort up, lower
5158 * power, start radio timer and return 0(for NDIS) don't call
5159 * radio_update to avoid looping brcms_c_up.
5160 *
5161 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5162 */
5163 if (!wlc->pub->radio_disabled) {
5164 int status = brcms_b_up_prep(wlc->hw);
5165 if (status == -ENOMEDIUM) {
5166 if (!mboolisset
5167 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5168 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5169 mboolset(wlc->pub->radio_disabled,
5170 WL_RADIO_HW_DISABLE);
5171
5172 if (bsscfg->enable && bsscfg->BSS)
5173 wiphy_err(wlc->wiphy, "wl%d: up"
5174 ": rfdisable -> "
5175 "bsscfg_disable()\n",
5176 wlc->pub->unit);
5177 }
5178 }
5179 }
5180
5181 if (wlc->pub->radio_disabled) {
5182 brcms_c_radio_monitor_start(wlc);
5183 return 0;
5184 }
5185
5186 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5187 wlc->clk = true;
5188
5189 brcms_c_radio_monitor_stop(wlc);
5190
5191 /* Set EDCF hostflags */
5192 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5193
5194 brcms_init(wlc->wl);
5195 wlc->pub->up = true;
5196
5197 if (wlc->bandinit_pending) {
5198 brcms_c_suspend_mac_and_wait(wlc);
5199 brcms_c_set_chanspec(wlc, wlc->default_bss->chanspec);
5200 wlc->bandinit_pending = false;
5201 brcms_c_enable_mac(wlc);
5202 }
5203
5204 brcms_b_up_finish(wlc->hw);
5205
5206 /* Program the TX wme params with the current settings */
5207 brcms_c_wme_retries_write(wlc);
5208
5209 /* start one second watchdog timer */
5210 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5211 wlc->WDarmed = true;
5212
5213 /* ensure antenna config is up to date */
5214 brcms_c_stf_phy_txant_upd(wlc);
5215 /* ensure LDPC config is in sync */
5216 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5217
5218 return 0;
5219}
5220
5221static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5222{
5223 uint callbacks = 0;
5224
5225 return callbacks;
5226}
5227
5228static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5229{
5230 bool dev_gone;
5231 uint callbacks = 0;
5232
5233 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5234
5235 if (!wlc_hw->up)
5236 return callbacks;
5237
5238 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5239
5240 /* disable interrupts */
5241 if (dev_gone)
5242 wlc_hw->wlc->macintmask = 0;
5243 else {
5244 /* now disable interrupts */
5245 brcms_intrsoff(wlc_hw->wlc->wl);
5246
5247 /* ensure we're running on the pll clock again */
5248 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5249 }
5250 /* down phy at the last of this stage */
5251 callbacks += wlc_phy_down(wlc_hw->band->pi);
5252
5253 return callbacks;
5254}
5255
5256static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5257{
5258 uint callbacks = 0;
5259 bool dev_gone;
5260
5261 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5262
5263 if (!wlc_hw->up)
5264 return callbacks;
5265
5266 wlc_hw->up = false;
5267 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5268
5269 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5270
5271 if (dev_gone) {
5272 wlc_hw->sbclk = false;
5273 wlc_hw->clk = false;
5274 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5275
5276 /* reclaim any posted packets */
5277 brcms_c_flushqueues(wlc_hw->wlc);
5278 } else {
5279
5280 /* Reset and disable the core */
5281 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5282 if (bcma_read32(wlc_hw->d11core,
5283 D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5284 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5285 callbacks += brcms_reset(wlc_hw->wlc->wl);
5286 brcms_c_coredisable(wlc_hw);
5287 }
5288
5289 /* turn off primary xtal and pll */
5290 if (!wlc_hw->noreset) {
5291 ai_pci_down(wlc_hw->sih);
5292 brcms_b_xtal(wlc_hw, OFF);
5293 }
5294 }
5295
5296 return callbacks;
5297}
5298
5299/*
5300 * Mark the interface nonoperational, stop the software mechanisms,
5301 * disable the hardware, free any transient buffer state.
5302 * Return a count of the number of driver callbacks still pending.
5303 */
5304uint brcms_c_down(struct brcms_c_info *wlc)
5305{
5306
5307 uint callbacks = 0;
5308 int i;
5309 bool dev_gone = false;
5310 struct brcms_txq_info *qi;
5311
5312 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5313
5314 /* check if we are already in the going down path */
5315 if (wlc->going_down) {
5316 wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
5317 "\n", wlc->pub->unit, __func__);
5318 return 0;
5319 }
5320 if (!wlc->pub->up)
5321 return callbacks;
5322
5323 wlc->going_down = true;
5324
5325 callbacks += brcms_b_bmac_down_prep(wlc->hw);
5326
5327 dev_gone = brcms_deviceremoved(wlc);
5328
5329 /* Call any registered down handlers */
5330 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5331 if (wlc->modulecb[i].down_fn)
5332 callbacks +=
5333 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5334 }
5335
5336 /* cancel the watchdog timer */
5337 if (wlc->WDarmed) {
5338 if (!brcms_del_timer(wlc->wdtimer))
5339 callbacks++;
5340 wlc->WDarmed = false;
5341 }
5342 /* cancel all other timers */
5343 callbacks += brcms_c_down_del_timer(wlc);
5344
5345 wlc->pub->up = false;
5346
5347 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5348
5349 /* clear txq flow control */
5350 brcms_c_txflowcontrol_reset(wlc);
5351
5352 /* flush tx queues */
5353 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next)
5354 brcmu_pktq_flush(&qi->q, true, NULL, NULL);
5355
5356 callbacks += brcms_b_down_finish(wlc->hw);
5357
5358 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5359 wlc->clk = false;
5360
5361 wlc->going_down = false;
5362 return callbacks;
5363}
5364
5365/* Set the current gmode configuration */
5366int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5367{
5368 int ret = 0;
5369 uint i;
5370 struct brcms_c_rateset rs;
5371 /* Default to 54g Auto */
5372 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5373 s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5374 bool shortslot_restrict = false; /* Restrict association to stations
5375 * that support shortslot
5376 */
5377 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
5378 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5379 int preamble = BRCMS_PLCP_LONG;
5380 bool preamble_restrict = false; /* Restrict association to stations
5381 * that support short preambles
5382 */
5383 struct brcms_band *band;
5384
5385 /* if N-support is enabled, allow Gmode set as long as requested
5386 * Gmode is not GMODE_LEGACY_B
5387 */
5388 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5389 return -ENOTSUPP;
5390
5391 /* verify that we are dealing with 2G band and grab the band pointer */
5392 if (wlc->band->bandtype == BRCM_BAND_2G)
5393 band = wlc->band;
5394 else if ((wlc->pub->_nbands > 1) &&
5395 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5396 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5397 else
5398 return -EINVAL;
5399
5400 /* Legacy or bust when no OFDM is supported by regulatory */
5401 if ((brcms_c_channel_locale_flags_in_band(wlc->cmi, band->bandunit) &
5402 BRCMS_NO_OFDM) && (gmode != GMODE_LEGACY_B))
5403 return -EINVAL;
5404
5405 /* update configuration value */
5406 if (config)
5407 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5408
5409 /* Clear rateset override */
5410 memset(&rs, 0, sizeof(struct brcms_c_rateset));
5411
5412 switch (gmode) {
5413 case GMODE_LEGACY_B:
5414 shortslot = BRCMS_SHORTSLOT_OFF;
5415 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5416
5417 break;
5418
5419 case GMODE_LRS:
5420 break;
5421
5422 case GMODE_AUTO:
5423 /* Accept defaults */
5424 break;
5425
5426 case GMODE_ONLY:
5427 ofdm_basic = true;
5428 preamble = BRCMS_PLCP_SHORT;
5429 preamble_restrict = true;
5430 break;
5431
5432 case GMODE_PERFORMANCE:
5433 shortslot = BRCMS_SHORTSLOT_ON;
5434 shortslot_restrict = true;
5435 ofdm_basic = true;
5436 preamble = BRCMS_PLCP_SHORT;
5437 preamble_restrict = true;
5438 break;
5439
5440 default:
5441 /* Error */
5442 wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
5443 wlc->pub->unit, __func__, gmode);
5444 return -ENOTSUPP;
5445 }
5446
5447 band->gmode = gmode;
5448
5449 wlc->shortslot_override = shortslot;
5450
5451 /* Use the default 11g rateset */
5452 if (!rs.count)
5453 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5454
5455 if (ofdm_basic) {
5456 for (i = 0; i < rs.count; i++) {
5457 if (rs.rates[i] == BRCM_RATE_6M
5458 || rs.rates[i] == BRCM_RATE_12M
5459 || rs.rates[i] == BRCM_RATE_24M)
5460 rs.rates[i] |= BRCMS_RATE_FLAG;
5461 }
5462 }
5463
5464 /* Set default bss rateset */
5465 wlc->default_bss->rateset.count = rs.count;
5466 memcpy(wlc->default_bss->rateset.rates, rs.rates,
5467 sizeof(wlc->default_bss->rateset.rates));
5468
5469 return ret;
5470}
5471
5472int brcms_c_set_nmode(struct brcms_c_info *wlc)
5473{
5474 uint i;
5475 s32 nmode = AUTO;
5476
5477 if (wlc->stf->txstreams == WL_11N_3x3)
5478 nmode = WL_11N_3x3;
5479 else
5480 nmode = WL_11N_2x2;
5481
5482 /* force GMODE_AUTO if NMODE is ON */
5483 brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5484 if (nmode == WL_11N_3x3)
5485 wlc->pub->_n_enab = SUPPORT_HT;
5486 else
5487 wlc->pub->_n_enab = SUPPORT_11N;
5488 wlc->default_bss->flags |= BRCMS_BSS_HT;
5489 /* add the mcs rates to the default and hw ratesets */
5490 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5491 wlc->stf->txstreams);
5492 for (i = 0; i < wlc->pub->_nbands; i++)
5493 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5494 wlc->default_bss->rateset.mcs, MCSSET_LEN);
5495
5496 return 0;
5497}
5498
5499static int
5500brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5501 struct brcms_c_rateset *rs_arg)
5502{
5503 struct brcms_c_rateset rs, new;
5504 uint bandunit;
5505
5506 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5507
5508 /* check for bad count value */
5509 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5510 return -EINVAL;
5511
5512 /* try the current band */
5513 bandunit = wlc->band->bandunit;
5514 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5515 if (brcms_c_rate_hwrs_filter_sort_validate
5516 (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5517 wlc->stf->txstreams))
5518 goto good;
5519
5520 /* try the other band */
5521 if (brcms_is_mband_unlocked(wlc)) {
5522 bandunit = OTHERBANDUNIT(wlc);
5523 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5524 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5525 &wlc->
5526 bandstate[bandunit]->
5527 hw_rateset, true,
5528 wlc->stf->txstreams))
5529 goto good;
5530 }
5531
5532 return -EBADE;
5533
5534 good:
5535 /* apply new rateset */
5536 memcpy(&wlc->default_bss->rateset, &new,
5537 sizeof(struct brcms_c_rateset));
5538 memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5539 sizeof(struct brcms_c_rateset));
5540 return 0;
5541}
5542
5543static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5544{
5545 u8 r;
5546 bool war = false;
5547
5548 if (wlc->bsscfg->associated)
5549 r = wlc->bsscfg->current_bss->rateset.rates[0];
5550 else
5551 r = wlc->default_bss->rateset.rates[0];
5552
5553 wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5554}
5555
5556int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5557{
5558 u16 chspec = ch20mhz_chspec(channel);
5559
5560 if (channel < 0 || channel > MAXCHANNEL)
5561 return -EINVAL;
5562
5563 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5564 return -EINVAL;
5565
5566
5567 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5568 if (wlc->band->bandunit != chspec_bandunit(chspec))
5569 wlc->bandinit_pending = true;
5570 else
5571 wlc->bandinit_pending = false;
5572 }
5573
5574 wlc->default_bss->chanspec = chspec;
5575 /* brcms_c_BSSinit() will sanitize the rateset before
5576 * using it.. */
5577 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5578 brcms_c_set_home_chanspec(wlc, chspec);
5579 brcms_c_suspend_mac_and_wait(wlc);
5580 brcms_c_set_chanspec(wlc, chspec);
5581 brcms_c_enable_mac(wlc);
5582 }
5583 return 0;
5584}
5585
5586int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5587{
5588 int ac;
5589
5590 if (srl < 1 || srl > RETRY_SHORT_MAX ||
5591 lrl < 1 || lrl > RETRY_SHORT_MAX)
5592 return -EINVAL;
5593
5594 wlc->SRL = srl;
5595 wlc->LRL = lrl;
5596
5597 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5598
5599 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5600 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5601 EDCF_SHORT, wlc->SRL);
5602 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5603 EDCF_LONG, wlc->LRL);
5604 }
5605 brcms_c_wme_retries_write(wlc);
5606
5607 return 0;
5608}
5609
5610void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5611 struct brcm_rateset *currs)
5612{
5613 struct brcms_c_rateset *rs;
5614
5615 if (wlc->pub->associated)
5616 rs = &wlc->bsscfg->current_bss->rateset;
5617 else
5618 rs = &wlc->default_bss->rateset;
5619
5620 /* Copy only legacy rateset section */
5621 currs->count = rs->count;
5622 memcpy(&currs->rates, &rs->rates, rs->count);
5623}
5624
5625int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5626{
5627 struct brcms_c_rateset internal_rs;
5628 int bcmerror;
5629
5630 if (rs->count > BRCMS_NUMRATES)
5631 return -ENOBUFS;
5632
5633 memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
5634
5635 /* Copy only legacy rateset section */
5636 internal_rs.count = rs->count;
5637 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5638
5639 /* merge rateset coming in with the current mcsset */
5640 if (wlc->pub->_n_enab & SUPPORT_11N) {
5641 struct brcms_bss_info *mcsset_bss;
5642 if (wlc->bsscfg->associated)
5643 mcsset_bss = wlc->bsscfg->current_bss;
5644 else
5645 mcsset_bss = wlc->default_bss;
5646 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5647 MCSSET_LEN);
5648 }
5649
5650 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5651 if (!bcmerror)
5652 brcms_c_ofdm_rateset_war(wlc);
5653
5654 return bcmerror;
5655}
5656
5657int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5658{
5659 if (period < DOT11_MIN_BEACON_PERIOD ||
5660 period > DOT11_MAX_BEACON_PERIOD)
5661 return -EINVAL;
5662
5663 wlc->default_bss->beacon_period = period;
5664 return 0;
5665}
5666
5667u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5668{
5669 return wlc->band->phytype;
5670}
5671
5672void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5673{
5674 wlc->shortslot_override = sslot_override;
5675
5676 /*
5677 * shortslot is an 11g feature, so no more work if we are
5678 * currently on the 5G band
5679 */
5680 if (wlc->band->bandtype == BRCM_BAND_5G)
5681 return;
5682
5683 if (wlc->pub->up && wlc->pub->associated) {
5684 /* let watchdog or beacon processing update shortslot */
5685 } else if (wlc->pub->up) {
5686 /* unassociated shortslot is off */
5687 brcms_c_switch_shortslot(wlc, false);
5688 } else {
5689 /* driver is down, so just update the brcms_c_info
5690 * value */
5691 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5692 wlc->shortslot = false;
5693 else
5694 wlc->shortslot =
5695 (wlc->shortslot_override ==
5696 BRCMS_SHORTSLOT_ON);
5697 }
5698}
5699
5700/*
5701 * register watchdog and down handlers.
5702 */
5703int brcms_c_module_register(struct brcms_pub *pub,
5704 const char *name, struct brcms_info *hdl,
5705 int (*d_fn)(void *handle))
5706{
5707 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5708 int i;
5709
5710 /* find an empty entry and just add, no duplication check! */
5711 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5712 if (wlc->modulecb[i].name[0] == '\0') {
5713 strncpy(wlc->modulecb[i].name, name,
5714 sizeof(wlc->modulecb[i].name) - 1);
5715 wlc->modulecb[i].hdl = hdl;
5716 wlc->modulecb[i].down_fn = d_fn;
5717 return 0;
5718 }
5719 }
5720
5721 return -ENOSR;
5722}
5723
5724/* unregister module callbacks */
5725int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5726 struct brcms_info *hdl)
5727{
5728 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5729 int i;
5730
5731 if (wlc == NULL)
5732 return -ENODATA;
5733
5734 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5735 if (!strcmp(wlc->modulecb[i].name, name) &&
5736 (wlc->modulecb[i].hdl == hdl)) {
5737 memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
5738 return 0;
5739 }
5740 }
5741
5742 /* table not found! */
5743 return -ENODATA;
5744}
5745
5746void brcms_c_print_txstatus(struct tx_status *txs)
5747{
5748 pr_debug("\ntxpkt (MPDU) Complete\n");
5749
5750 pr_debug("FrameID: %04x TxStatus: %04x\n", txs->frameid, txs->status);
5751
5752 pr_debug("[15:12] %d frame attempts\n",
5753 (txs->status & TX_STATUS_FRM_RTX_MASK) >>
5754 TX_STATUS_FRM_RTX_SHIFT);
5755 pr_debug(" [11:8] %d rts attempts\n",
5756 (txs->status & TX_STATUS_RTS_RTX_MASK) >>
5757 TX_STATUS_RTS_RTX_SHIFT);
5758 pr_debug(" [7] %d PM mode indicated\n",
5759 txs->status & TX_STATUS_PMINDCTD ? 1 : 0);
5760 pr_debug(" [6] %d intermediate status\n",
5761 txs->status & TX_STATUS_INTERMEDIATE ? 1 : 0);
5762 pr_debug(" [5] %d AMPDU\n",
5763 txs->status & TX_STATUS_AMPDU ? 1 : 0);
5764 pr_debug(" [4:2] %d Frame Suppressed Reason (%s)\n",
5765 (txs->status & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT,
5766 (const char *[]) {
5767 "None",
5768 "PMQ Entry",
5769 "Flush request",
5770 "Previous frag failure",
5771 "Channel mismatch",
5772 "Lifetime Expiry",
5773 "Underflow"
5774 } [(txs->status & TX_STATUS_SUPR_MASK) >>
5775 TX_STATUS_SUPR_SHIFT]);
5776 pr_debug(" [1] %d acked\n",
5777 txs->status & TX_STATUS_ACK_RCV ? 1 : 0);
5778
5779 pr_debug("LastTxTime: %04x Seq: %04x PHYTxStatus: %04x RxAckRSSI: %04x RxAckSQ: %04x\n",
5780 txs->lasttxtime, txs->sequence, txs->phyerr,
5781 (txs->ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT,
5782 (txs->ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
5783}
5784
5785bool brcms_c_chipmatch(u16 vendor, u16 device)
5786{
5787 if (vendor != PCI_VENDOR_ID_BROADCOM) {
5788 pr_err("unknown vendor id %04x\n", vendor);
5789 return false;
5790 }
5791
5792 if (device == BCM43224_D11N_ID_VEN1)
5793 return true;
5794 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5795 return true;
5796 if (device == BCM4313_D11N2G_ID)
5797 return true;
5798 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5799 return true;
5800
5801 pr_err("unknown device id %04x\n", device);
5802 return false;
5803}
5804
5805#if defined(DEBUG)
5806void brcms_c_print_txdesc(struct d11txh *txh)
5807{
5808 u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
5809 u16 mtch = le16_to_cpu(txh->MacTxControlHigh);
5810 u16 mfc = le16_to_cpu(txh->MacFrameControl);
5811 u16 tfest = le16_to_cpu(txh->TxFesTimeNormal);
5812 u16 ptcw = le16_to_cpu(txh->PhyTxControlWord);
5813 u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1);
5814 u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr);
5815 u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts);
5816 u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts);
5817 u16 mainrates = le16_to_cpu(txh->MainRates);
5818 u16 xtraft = le16_to_cpu(txh->XtraFrameTypes);
5819 u8 *iv = txh->IV;
5820 u8 *ra = txh->TxFrameRA;
5821 u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback);
5822 u8 *rtspfb = txh->RTSPLCPFallback;
5823 u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback);
5824 u8 *fragpfb = txh->FragPLCPFallback;
5825 u16 fragdfb = le16_to_cpu(txh->FragDurFallback);
5826 u16 mmodelen = le16_to_cpu(txh->MModeLen);
5827 u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen);
5828 u16 tfid = le16_to_cpu(txh->TxFrameID);
5829 u16 txs = le16_to_cpu(txh->TxStatus);
5830 u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus);
5831 u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT);
5832 u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR);
5833 u16 mmbyte = le16_to_cpu(txh->MinMBytes);
5834
5835 u8 *rtsph = txh->RTSPhyHeader;
5836 struct ieee80211_rts rts = txh->rts_frame;
5837
5838 /* add plcp header along with txh descriptor */
5839 brcmu_dbg_hex_dump(txh, sizeof(struct d11txh) + 48,
5840 "Raw TxDesc + plcp header:\n");
5841
5842 pr_debug("TxCtlLow: %04x ", mtcl);
5843 pr_debug("TxCtlHigh: %04x ", mtch);
5844 pr_debug("FC: %04x ", mfc);
5845 pr_debug("FES Time: %04x\n", tfest);
5846 pr_debug("PhyCtl: %04x%s ", ptcw,
5847 (ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
5848 pr_debug("PhyCtl_1: %04x ", ptcw_1);
5849 pr_debug("PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
5850 pr_debug("PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
5851 pr_debug("PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
5852 pr_debug("MainRates: %04x ", mainrates);
5853 pr_debug("XtraFrameTypes: %04x ", xtraft);
5854 pr_debug("\n");
5855
5856 print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV));
5857 print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET,
5858 ra, sizeof(txh->TxFrameRA));
5859
5860 pr_debug("Fb FES Time: %04x ", tfestfb);
5861 print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET,
5862 rtspfb, sizeof(txh->RTSPLCPFallback));
5863 pr_debug("RTS DUR: %04x ", rtsdfb);
5864 print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET,
5865 fragpfb, sizeof(txh->FragPLCPFallback));
5866 pr_debug("DUR: %04x", fragdfb);
5867 pr_debug("\n");
5868
5869 pr_debug("MModeLen: %04x ", mmodelen);
5870 pr_debug("MModeFbrLen: %04x\n", mmodefbrlen);
5871
5872 pr_debug("FrameID: %04x\n", tfid);
5873 pr_debug("TxStatus: %04x\n", txs);
5874
5875 pr_debug("MaxNumMpdu: %04x\n", mnmpdu);
5876 pr_debug("MaxAggbyte: %04x\n", mabyte);
5877 pr_debug("MaxAggbyte_fb: %04x\n", mabyte_f);
5878 pr_debug("MinByte: %04x\n", mmbyte);
5879
5880 print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET,
5881 rtsph, sizeof(txh->RTSPhyHeader));
5882 print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET,
5883 (u8 *)&rts, sizeof(txh->rts_frame));
5884 pr_debug("\n");
5885}
5886#endif /* defined(DEBUG) */
5887
5888#if defined(DEBUG)
5889static int
5890brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf,
5891 int len)
5892{
5893 int i;
5894 char *p = buf;
5895 char hexstr[16];
5896 int slen = 0, nlen = 0;
5897 u32 bit;
5898 const char *name;
5899
5900 if (len < 2 || !buf)
5901 return 0;
5902
5903 buf[0] = '\0';
5904
5905 for (i = 0; flags != 0; i++) {
5906 bit = bd[i].bit;
5907 name = bd[i].name;
5908 if (bit == 0 && flags != 0) {
5909 /* print any unnamed bits */
5910 snprintf(hexstr, 16, "0x%X", flags);
5911 name = hexstr;
5912 flags = 0; /* exit loop */
5913 } else if ((flags & bit) == 0)
5914 continue;
5915 flags &= ~bit;
5916 nlen = strlen(name);
5917 slen += nlen;
5918 /* count btwn flag space */
5919 if (flags != 0)
5920 slen += 1;
5921 /* need NULL char as well */
5922 if (len <= slen)
5923 break;
5924 /* copy NULL char but don't count it */
5925 strncpy(p, name, nlen + 1);
5926 p += nlen;
5927 /* copy btwn flag space and NULL char */
5928 if (flags != 0)
5929 p += snprintf(p, 2, " ");
5930 len -= slen;
5931 }
5932
5933 /* indicate the str was too short */
5934 if (flags != 0) {
5935 if (len < 2)
5936 p -= 2 - len; /* overwrite last char */
5937 p += snprintf(p, 2, ">");
5938 }
5939
5940 return (int)(p - buf);
5941}
5942#endif /* defined(DEBUG) */
5943
5944#if defined(DEBUG)
5945void brcms_c_print_rxh(struct d11rxhdr *rxh)
5946{
5947 u16 len = rxh->RxFrameSize;
5948 u16 phystatus_0 = rxh->PhyRxStatus_0;
5949 u16 phystatus_1 = rxh->PhyRxStatus_1;
5950 u16 phystatus_2 = rxh->PhyRxStatus_2;
5951 u16 phystatus_3 = rxh->PhyRxStatus_3;
5952 u16 macstatus1 = rxh->RxStatus1;
5953 u16 macstatus2 = rxh->RxStatus2;
5954 char flagstr[64];
5955 char lenbuf[20];
5956 static const struct brcms_c_bit_desc macstat_flags[] = {
5957 {RXS_FCSERR, "FCSErr"},
5958 {RXS_RESPFRAMETX, "Reply"},
5959 {RXS_PBPRES, "PADDING"},
5960 {RXS_DECATMPT, "DeCr"},
5961 {RXS_DECERR, "DeCrErr"},
5962 {RXS_BCNSENT, "Bcn"},
5963 {0, NULL}
5964 };
5965
5966 brcmu_dbg_hex_dump(rxh, sizeof(struct d11rxhdr), "Raw RxDesc:\n");
5967
5968 brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64);
5969
5970 snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
5971
5972 pr_debug("RxFrameSize: %6s (%d)%s\n", lenbuf, len,
5973 (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
5974 pr_debug("RxPHYStatus: %04x %04x %04x %04x\n",
5975 phystatus_0, phystatus_1, phystatus_2, phystatus_3);
5976 pr_debug("RxMACStatus: %x %s\n", macstatus1, flagstr);
5977 pr_debug("RXMACaggtype: %x\n",
5978 (macstatus2 & RXS_AGGTYPE_MASK));
5979 pr_debug("RxTSFTime: %04x\n", rxh->RxTSFTime);
5980}
5981#endif /* defined(DEBUG) */
5982
5983u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5984{
5985 u16 table_ptr;
5986 u8 phy_rate, index;
5987
5988 /* get the phy specific rate encoding for the PLCP SIGNAL field */
5989 if (is_ofdm_rate(rate))
5990 table_ptr = M_RT_DIRMAP_A;
5991 else
5992 table_ptr = M_RT_DIRMAP_B;
5993
5994 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5995 * the index into the rate table.
5996 */
5997 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5998 index = phy_rate & 0xf;
5999
6000 /* Find the SHM pointer to the rate table entry by looking in the
6001 * Direct-map Table
6002 */
6003 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
6004}
6005
6006static bool
6007brcms_c_prec_enq_head(struct brcms_c_info *wlc, struct pktq *q,
6008 struct sk_buff *pkt, int prec, bool head)
6009{
6010 struct sk_buff *p;
6011 int eprec = -1; /* precedence to evict from */
6012
6013 /* Determine precedence from which to evict packet, if any */
6014 if (pktq_pfull(q, prec))
6015 eprec = prec;
6016 else if (pktq_full(q)) {
6017 p = brcmu_pktq_peek_tail(q, &eprec);
6018 if (eprec > prec) {
6019 wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d"
6020 "\n", __func__, eprec, prec);
6021 return false;
6022 }
6023 }
6024
6025 /* Evict if needed */
6026 if (eprec >= 0) {
6027 bool discard_oldest;
6028
6029 discard_oldest = ac_bitmap_tst(0, eprec);
6030
6031 /* Refuse newer packet unless configured to discard oldest */
6032 if (eprec == prec && !discard_oldest) {
6033 wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d"
6034 "\n", __func__, prec);
6035 return false;
6036 }
6037
6038 /* Evict packet according to discard policy */
6039 p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
6040 brcmu_pktq_pdeq_tail(q, eprec);
6041 brcmu_pkt_buf_free_skb(p);
6042 }
6043
6044 /* Enqueue */
6045 if (head)
6046 p = brcmu_pktq_penq_head(q, prec, pkt);
6047 else
6048 p = brcmu_pktq_penq(q, prec, pkt);
6049
6050 return true;
6051}
6052
6053/*
6054 * Attempts to queue a packet onto a multiple-precedence queue,
6055 * if necessary evicting a lower precedence packet from the queue.
6056 *
6057 * 'prec' is the precedence number that has already been mapped
6058 * from the packet priority.
6059 *
6060 * Returns true if packet consumed (queued), false if not.
6061 */
6062static bool brcms_c_prec_enq(struct brcms_c_info *wlc, struct pktq *q,
6063 struct sk_buff *pkt, int prec)
6064{
6065 return brcms_c_prec_enq_head(wlc, q, pkt, prec, false);
6066}
6067
6068void brcms_c_txq_enq(struct brcms_c_info *wlc, struct scb *scb,
6069 struct sk_buff *sdu, uint prec)
6070{
6071 struct brcms_txq_info *qi = wlc->pkt_queue; /* Check me */
6072 struct pktq *q = &qi->q;
6073 int prio;
6074
6075 prio = sdu->priority;
6076
6077 if (!brcms_c_prec_enq(wlc, q, sdu, prec)) {
6078 /*
6079 * we might hit this condtion in case
6080 * packet flooding from mac80211 stack
6081 */
6082 brcmu_pkt_buf_free_skb(sdu);
6083 }
6084}
6085
6086/*
6087 * bcmc_fid_generate:
6088 * Generate frame ID for a BCMC packet. The frag field is not used
6089 * for MC frames so is used as part of the sequence number.
6090 */
6091static inline u16
6092bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
6093 struct d11txh *txh)
6094{
6095 u16 frameid;
6096
6097 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
6098 TXFID_QUEUE_MASK);
6099 frameid |=
6100 (((wlc->
6101 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6102 TX_BCMC_FIFO;
6103
6104 return frameid;
6105}
6106
6107static uint
6108brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
6109 u8 preamble_type)
6110{
6111 uint dur = 0;
6112
6113 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n",
6114 wlc->pub->unit, rspec, preamble_type);
6115 /*
6116 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
6117 * is less than or equal to the rate of the immediately previous
6118 * frame in the FES
6119 */
6120 rspec = brcms_basic_rate(wlc, rspec);
6121 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
6122 dur =
6123 brcms_c_calc_frame_time(wlc, rspec, preamble_type,
6124 (DOT11_ACK_LEN + FCS_LEN));
6125 return dur;
6126}
6127
6128static uint
6129brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
6130 u8 preamble_type)
6131{
6132 BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n",
6133 wlc->pub->unit, rspec, preamble_type);
6134 return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
6135}
6136
6137static uint
6138brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
6139 u8 preamble_type)
6140{
6141 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, "
6142 "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type);
6143 /*
6144 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
6145 * is less than or equal to the rate of the immediately previous
6146 * frame in the FES
6147 */
6148 rspec = brcms_basic_rate(wlc, rspec);
6149 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
6150 return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
6151 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
6152 FCS_LEN));
6153}
6154
6155/* brcms_c_compute_frame_dur()
6156 *
6157 * Calculate the 802.11 MAC header DUR field for MPDU
6158 * DUR for a single frame = 1 SIFS + 1 ACK
6159 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
6160 *
6161 * rate MPDU rate in unit of 500kbps
6162 * next_frag_len next MPDU length in bytes
6163 * preamble_type use short/GF or long/MM PLCP header
6164 */
6165static u16
6166brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
6167 u8 preamble_type, uint next_frag_len)
6168{
6169 u16 dur, sifs;
6170
6171 sifs = get_sifs(wlc->band);
6172
6173 dur = sifs;
6174 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
6175
6176 if (next_frag_len) {
6177 /* Double the current DUR to get 2 SIFS + 2 ACKs */
6178 dur *= 2;
6179 /* add another SIFS and the frag time */
6180 dur += sifs;
6181 dur +=
6182 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
6183 next_frag_len);
6184 }
6185 return dur;
6186}
6187
6188/* The opposite of brcms_c_calc_frame_time */
6189static uint
6190brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
6191 u8 preamble_type, uint dur)
6192{
6193 uint nsyms, mac_len, Ndps, kNdps;
6194 uint rate = rspec2rate(ratespec);
6195
6196 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
6197 wlc->pub->unit, ratespec, preamble_type, dur);
6198
6199 if (is_mcs_rate(ratespec)) {
6200 uint mcs = ratespec & RSPEC_RATE_MASK;
6201 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
6202 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
6203 /* payload calculation matches that of regular ofdm */
6204 if (wlc->band->bandtype == BRCM_BAND_2G)
6205 dur -= DOT11_OFDM_SIGNAL_EXTENSION;
6206 /* kNdbps = kbps * 4 */
6207 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
6208 rspec_issgi(ratespec)) * 4;
6209 nsyms = dur / APHY_SYMBOL_TIME;
6210 mac_len =
6211 ((nsyms * kNdps) -
6212 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
6213 } else if (is_ofdm_rate(ratespec)) {
6214 dur -= APHY_PREAMBLE_TIME;
6215 dur -= APHY_SIGNAL_TIME;
6216 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
6217 Ndps = rate * 2;
6218 nsyms = dur / APHY_SYMBOL_TIME;
6219 mac_len =
6220 ((nsyms * Ndps) -
6221 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
6222 } else {
6223 if (preamble_type & BRCMS_SHORT_PREAMBLE)
6224 dur -= BPHY_PLCP_SHORT_TIME;
6225 else
6226 dur -= BPHY_PLCP_TIME;
6227 mac_len = dur * rate;
6228 /* divide out factor of 2 in rate (1/2 mbps) */
6229 mac_len = mac_len / 8 / 2;
6230 }
6231 return mac_len;
6232}
6233
6234/*
6235 * Return true if the specified rate is supported by the specified band.
6236 * BRCM_BAND_AUTO indicates the current band.
6237 */
6238static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
6239 bool verbose)
6240{
6241 struct brcms_c_rateset *hw_rateset;
6242 uint i;
6243
6244 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
6245 hw_rateset = &wlc->band->hw_rateset;
6246 else if (wlc->pub->_nbands > 1)
6247 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
6248 else
6249 /* other band specified and we are a single band device */
6250 return false;
6251
6252 /* check if this is a mimo rate */
6253 if (is_mcs_rate(rspec)) {
6254 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
6255 goto error;
6256
6257 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
6258 }
6259
6260 for (i = 0; i < hw_rateset->count; i++)
6261 if (hw_rateset->rates[i] == rspec2rate(rspec))
6262 return true;
6263 error:
6264 if (verbose)
6265 wiphy_err(wlc->wiphy, "wl%d: valid_rate: rate spec 0x%x "
6266 "not in hw_rateset\n", wlc->pub->unit, rspec);
6267
6268 return false;
6269}
6270
6271static u32
6272mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
6273 u32 int_val)
6274{
6275 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
6276 u8 rate = int_val & NRATE_RATE_MASK;
6277 u32 rspec;
6278 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
6279 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
6280 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
6281 == NRATE_OVERRIDE_MCS_ONLY);
6282 int bcmerror = 0;
6283
6284 if (!ismcs)
6285 return (u32) rate;
6286
6287 /* validate the combination of rate/mcs/stf is allowed */
6288 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
6289 /* mcs only allowed when nmode */
6290 if (stf > PHY_TXC1_MODE_SDM) {
6291 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n",
6292 wlc->pub->unit, __func__);
6293 bcmerror = -EINVAL;
6294 goto done;
6295 }
6296
6297 /* mcs 32 is a special case, DUP mode 40 only */
6298 if (rate == 32) {
6299 if (!CHSPEC_IS40(wlc->home_chanspec) ||
6300 ((stf != PHY_TXC1_MODE_SISO)
6301 && (stf != PHY_TXC1_MODE_CDD))) {
6302 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs "
6303 "32\n", wlc->pub->unit, __func__);
6304 bcmerror = -EINVAL;
6305 goto done;
6306 }
6307 /* mcs > 7 must use stf SDM */
6308 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
6309 /* mcs > 7 must use stf SDM */
6310 if (stf != PHY_TXC1_MODE_SDM) {
6311 BCMMSG(wlc->wiphy, "wl%d: enabling "
6312 "SDM mode for mcs %d\n",
6313 wlc->pub->unit, rate);
6314 stf = PHY_TXC1_MODE_SDM;
6315 }
6316 } else {
6317 /*
6318 * MCS 0-7 may use SISO, CDD, and for
6319 * phy_rev >= 3 STBC
6320 */
6321 if ((stf > PHY_TXC1_MODE_STBC) ||
6322 (!BRCMS_STBC_CAP_PHY(wlc)
6323 && (stf == PHY_TXC1_MODE_STBC))) {
6324 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC"
6325 "\n", wlc->pub->unit, __func__);
6326 bcmerror = -EINVAL;
6327 goto done;
6328 }
6329 }
6330 } else if (is_ofdm_rate(rate)) {
6331 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
6332 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n",
6333 wlc->pub->unit, __func__);
6334 bcmerror = -EINVAL;
6335 goto done;
6336 }
6337 } else if (is_cck_rate(rate)) {
6338 if ((cur_band->bandtype != BRCM_BAND_2G)
6339 || (stf != PHY_TXC1_MODE_SISO)) {
6340 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n",
6341 wlc->pub->unit, __func__);
6342 bcmerror = -EINVAL;
6343 goto done;
6344 }
6345 } else {
6346 wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n",
6347 wlc->pub->unit, __func__);
6348 bcmerror = -EINVAL;
6349 goto done;
6350 }
6351 /* make sure multiple antennae are available for non-siso rates */
6352 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
6353 wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO "
6354 "request\n", wlc->pub->unit, __func__);
6355 bcmerror = -EINVAL;
6356 goto done;
6357 }
6358
6359 rspec = rate;
6360 if (ismcs) {
6361 rspec |= RSPEC_MIMORATE;
6362 /* For STBC populate the STC field of the ratespec */
6363 if (stf == PHY_TXC1_MODE_STBC) {
6364 u8 stc;
6365 stc = 1; /* Nss for single stream is always 1 */
6366 rspec |= (stc << RSPEC_STC_SHIFT);
6367 }
6368 }
6369
6370 rspec |= (stf << RSPEC_STF_SHIFT);
6371
6372 if (override_mcs_only)
6373 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
6374
6375 if (issgi)
6376 rspec |= RSPEC_SHORT_GI;
6377
6378 if ((rate != 0)
6379 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6380 return rate;
6381
6382 return rspec;
6383done:
6384 return rate;
6385}
6386
6387/*
6388 * Compute PLCP, but only requires actual rate and length of pkt.
6389 * Rate is given in the driver standard multiple of 500 kbps.
6390 * le is set for 11 Mbps rate if necessary.
6391 * Broken out for PRQ.
6392 */
6393
6394static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6395 uint length, u8 *plcp)
6396{
6397 u16 usec = 0;
6398 u8 le = 0;
6399
6400 switch (rate_500) {
6401 case BRCM_RATE_1M:
6402 usec = length << 3;
6403 break;
6404 case BRCM_RATE_2M:
6405 usec = length << 2;
6406 break;
6407 case BRCM_RATE_5M5:
6408 usec = (length << 4) / 11;
6409 if ((length << 4) - (usec * 11) > 0)
6410 usec++;
6411 break;
6412 case BRCM_RATE_11M:
6413 usec = (length << 3) / 11;
6414 if ((length << 3) - (usec * 11) > 0) {
6415 usec++;
6416 if ((usec * 11) - (length << 3) >= 8)
6417 le = D11B_PLCP_SIGNAL_LE;
6418 }
6419 break;
6420
6421 default:
6422 wiphy_err(wlc->wiphy,
6423 "brcms_c_cck_plcp_set: unsupported rate %d\n",
6424 rate_500);
6425 rate_500 = BRCM_RATE_1M;
6426 usec = length << 3;
6427 break;
6428 }
6429 /* PLCP signal byte */
6430 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6431 /* PLCP service byte */
6432 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6433 /* PLCP length u16, little endian */
6434 plcp[2] = usec & 0xff;
6435 plcp[3] = (usec >> 8) & 0xff;
6436 /* PLCP CRC16 */
6437 plcp[4] = 0;
6438 plcp[5] = 0;
6439}
6440
6441/* Rate: 802.11 rate code, length: PSDU length in octets */
6442static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6443{
6444 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6445 plcp[0] = mcs;
6446 if (rspec_is40mhz(rspec) || (mcs == 32))
6447 plcp[0] |= MIMO_PLCP_40MHZ;
6448 BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6449 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6450 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6451 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6452 plcp[5] = 0;
6453}
6454
6455/* Rate: 802.11 rate code, length: PSDU length in octets */
6456static void
6457brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6458{
6459 u8 rate_signal;
6460 u32 tmp = 0;
6461 int rate = rspec2rate(rspec);
6462
6463 /*
6464 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6465 * transmitted first
6466 */
6467 rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6468 memset(plcp, 0, D11_PHY_HDR_LEN);
6469 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6470
6471 tmp = (length & 0xfff) << 5;
6472 plcp[2] |= (tmp >> 16) & 0xff;
6473 plcp[1] |= (tmp >> 8) & 0xff;
6474 plcp[0] |= tmp & 0xff;
6475}
6476
6477/* Rate: 802.11 rate code, length: PSDU length in octets */
6478static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6479 uint length, u8 *plcp)
6480{
6481 int rate = rspec2rate(rspec);
6482
6483 brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6484}
6485
6486static void
6487brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6488 uint length, u8 *plcp)
6489{
6490 if (is_mcs_rate(rspec))
6491 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6492 else if (is_ofdm_rate(rspec))
6493 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6494 else
6495 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6496}
6497
6498/* brcms_c_compute_rtscts_dur()
6499 *
6500 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6501 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6502 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
6503 *
6504 * cts cts-to-self or rts/cts
6505 * rts_rate rts or cts rate in unit of 500kbps
6506 * rate next MPDU rate in unit of 500kbps
6507 * frame_len next MPDU frame length in bytes
6508 */
6509u16
6510brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6511 u32 rts_rate,
6512 u32 frame_rate, u8 rts_preamble_type,
6513 u8 frame_preamble_type, uint frame_len, bool ba)
6514{
6515 u16 dur, sifs;
6516
6517 sifs = get_sifs(wlc->band);
6518
6519 if (!cts_only) {
6520 /* RTS/CTS */
6521 dur = 3 * sifs;
6522 dur +=
6523 (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6524 rts_preamble_type);
6525 } else {
6526 /* CTS-TO-SELF */
6527 dur = 2 * sifs;
6528 }
6529
6530 dur +=
6531 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6532 frame_len);
6533 if (ba)
6534 dur +=
6535 (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6536 BRCMS_SHORT_PREAMBLE);
6537 else
6538 dur +=
6539 (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6540 frame_preamble_type);
6541 return dur;
6542}
6543
6544static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6545{
6546 u16 phyctl1 = 0;
6547 u16 bw;
6548
6549 if (BRCMS_ISLCNPHY(wlc->band)) {
6550 bw = PHY_TXC1_BW_20MHZ;
6551 } else {
6552 bw = rspec_get_bw(rspec);
6553 /* 10Mhz is not supported yet */
6554 if (bw < PHY_TXC1_BW_20MHZ) {
6555 wiphy_err(wlc->wiphy, "phytxctl1_calc: bw %d is "
6556 "not supported yet, set to 20L\n", bw);
6557 bw = PHY_TXC1_BW_20MHZ;
6558 }
6559 }
6560
6561 if (is_mcs_rate(rspec)) {
6562 uint mcs = rspec & RSPEC_RATE_MASK;
6563
6564 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6565 phyctl1 = rspec_phytxbyte2(rspec);
6566 /* set the upper byte of phyctl1 */
6567 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6568 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6569 && !BRCMS_ISSSLPNPHY(wlc->band)) {
6570 /*
6571 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6572 * Data Rate. Eventually MIMOPHY would also be converted to
6573 * this format
6574 */
6575 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6576 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6577 } else { /* legacy OFDM/CCK */
6578 s16 phycfg;
6579 /* get the phyctl byte from rate phycfg table */
6580 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6581 if (phycfg == -1) {
6582 wiphy_err(wlc->wiphy, "phytxctl1_calc: wrong "
6583 "legacy OFDM/CCK rate\n");
6584 phycfg = 0;
6585 }
6586 /* set the upper byte of phyctl1 */
6587 phyctl1 =
6588 (bw | (phycfg << 8) |
6589 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6590 }
6591 return phyctl1;
6592}
6593
6594/*
6595 * Add struct d11txh, struct cck_phy_hdr.
6596 *
6597 * 'p' data must start with 802.11 MAC header
6598 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6599 *
6600 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6601 *
6602 */
6603static u16
6604brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6605 struct sk_buff *p, struct scb *scb, uint frag,
6606 uint nfrags, uint queue, uint next_frag_len)
6607{
6608 struct ieee80211_hdr *h;
6609 struct d11txh *txh;
6610 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6611 int len, phylen, rts_phylen;
6612 u16 mch, phyctl, xfts, mainrates;
6613 u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6614 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6615 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6616 bool use_rts = false;
6617 bool use_cts = false;
6618 bool use_rifs = false;
6619 bool short_preamble[2] = { false, false };
6620 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6621 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6622 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6623 struct ieee80211_rts *rts = NULL;
6624 bool qos;
6625 uint ac;
6626 bool hwtkmic = false;
6627 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6628#define ANTCFG_NONE 0xFF
6629 u8 antcfg = ANTCFG_NONE;
6630 u8 fbantcfg = ANTCFG_NONE;
6631 uint phyctl1_stf = 0;
6632 u16 durid = 0;
6633 struct ieee80211_tx_rate *txrate[2];
6634 int k;
6635 struct ieee80211_tx_info *tx_info;
6636 bool is_mcs;
6637 u16 mimo_txbw;
6638 u8 mimo_preamble_type;
6639
6640 /* locate 802.11 MAC header */
6641 h = (struct ieee80211_hdr *)(p->data);
6642 qos = ieee80211_is_data_qos(h->frame_control);
6643
6644 /* compute length of frame in bytes for use in PLCP computations */
6645 len = p->len;
6646 phylen = len + FCS_LEN;
6647
6648 /* Get tx_info */
6649 tx_info = IEEE80211_SKB_CB(p);
6650
6651 /* add PLCP */
6652 plcp = skb_push(p, D11_PHY_HDR_LEN);
6653
6654 /* add Broadcom tx descriptor header */
6655 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6656 memset(txh, 0, D11_TXH_LEN);
6657
6658 /* setup frameid */
6659 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6660 /* non-AP STA should never use BCMC queue */
6661 if (queue == TX_BCMC_FIFO) {
6662 wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == "
6663 "TX_BCMC!\n", wlc->pub->unit, __func__);
6664 frameid = bcmc_fid_generate(wlc, NULL, txh);
6665 } else {
6666 /* Increment the counter for first fragment */
6667 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6668 scb->seqnum[p->priority]++;
6669
6670 /* extract fragment number from frame first */
6671 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6672 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6673 h->seq_ctrl = cpu_to_le16(seq);
6674
6675 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6676 (queue & TXFID_QUEUE_MASK);
6677 }
6678 }
6679 frameid |= queue & TXFID_QUEUE_MASK;
6680
6681 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6682 if (ieee80211_is_beacon(h->frame_control))
6683 mcl |= TXC_IGNOREPMQ;
6684
6685 txrate[0] = tx_info->control.rates;
6686 txrate[1] = txrate[0] + 1;
6687
6688 /*
6689 * if rate control algorithm didn't give us a fallback
6690 * rate, use the primary rate
6691 */
6692 if (txrate[1]->idx < 0)
6693 txrate[1] = txrate[0];
6694
6695 for (k = 0; k < hw->max_rates; k++) {
6696 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6697 if (!is_mcs) {
6698 if ((txrate[k]->idx >= 0)
6699 && (txrate[k]->idx <
6700 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6701 rspec[k] =
6702 hw->wiphy->bands[tx_info->band]->
6703 bitrates[txrate[k]->idx].hw_value;
6704 short_preamble[k] =
6705 txrate[k]->
6706 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6707 true : false;
6708 } else {
6709 rspec[k] = BRCM_RATE_1M;
6710 }
6711 } else {
6712 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6713 NRATE_MCS_INUSE | txrate[k]->idx);
6714 }
6715
6716 /*
6717 * Currently only support same setting for primay and
6718 * fallback rates. Unify flags for each rate into a
6719 * single value for the frame
6720 */
6721 use_rts |=
6722 txrate[k]->
6723 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6724 use_cts |=
6725 txrate[k]->
6726 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6727
6728
6729 /*
6730 * (1) RATE:
6731 * determine and validate primary rate
6732 * and fallback rates
6733 */
6734 if (!rspec_active(rspec[k])) {
6735 rspec[k] = BRCM_RATE_1M;
6736 } else {
6737 if (!is_multicast_ether_addr(h->addr1)) {
6738 /* set tx antenna config */
6739 brcms_c_antsel_antcfg_get(wlc->asi, false,
6740 false, 0, 0, &antcfg, &fbantcfg);
6741 }
6742 }
6743 }
6744
6745 phyctl1_stf = wlc->stf->ss_opmode;
6746
6747 if (wlc->pub->_n_enab & SUPPORT_11N) {
6748 for (k = 0; k < hw->max_rates; k++) {
6749 /*
6750 * apply siso/cdd to single stream mcs's or ofdm
6751 * if rspec is auto selected
6752 */
6753 if (((is_mcs_rate(rspec[k]) &&
6754 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6755 is_ofdm_rate(rspec[k]))
6756 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6757 || !(rspec[k] & RSPEC_OVERRIDE))) {
6758 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6759
6760 /* For SISO MCS use STBC if possible */
6761 if (is_mcs_rate(rspec[k])
6762 && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6763 u8 stc;
6764
6765 /* Nss for single stream is always 1 */
6766 stc = 1;
6767 rspec[k] |= (PHY_TXC1_MODE_STBC <<
6768 RSPEC_STF_SHIFT) |
6769 (stc << RSPEC_STC_SHIFT);
6770 } else
6771 rspec[k] |=
6772 (phyctl1_stf << RSPEC_STF_SHIFT);
6773 }
6774
6775 /*
6776 * Is the phy configured to use 40MHZ frames? If
6777 * so then pick the desired txbw
6778 */
6779 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6780 /* default txbw is 20in40 SB */
6781 mimo_ctlchbw = mimo_txbw =
6782 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6783 wlc->band->pi))
6784 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6785
6786 if (is_mcs_rate(rspec[k])) {
6787 /* mcs 32 must be 40b/w DUP */
6788 if ((rspec[k] & RSPEC_RATE_MASK)
6789 == 32) {
6790 mimo_txbw =
6791 PHY_TXC1_BW_40MHZ_DUP;
6792 /* use override */
6793 } else if (wlc->mimo_40txbw != AUTO)
6794 mimo_txbw = wlc->mimo_40txbw;
6795 /* else check if dst is using 40 Mhz */
6796 else if (scb->flags & SCB_IS40)
6797 mimo_txbw = PHY_TXC1_BW_40MHZ;
6798 } else if (is_ofdm_rate(rspec[k])) {
6799 if (wlc->ofdm_40txbw != AUTO)
6800 mimo_txbw = wlc->ofdm_40txbw;
6801 } else if (wlc->cck_40txbw != AUTO) {
6802 mimo_txbw = wlc->cck_40txbw;
6803 }
6804 } else {
6805 /*
6806 * mcs32 is 40 b/w only.
6807 * This is possible for probe packets on
6808 * a STA during SCAN
6809 */
6810 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6811 /* mcs 0 */
6812 rspec[k] = RSPEC_MIMORATE;
6813
6814 mimo_txbw = PHY_TXC1_BW_20MHZ;
6815 }
6816
6817 /* Set channel width */
6818 rspec[k] &= ~RSPEC_BW_MASK;
6819 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6820 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6821 else
6822 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6823
6824 /* Disable short GI, not supported yet */
6825 rspec[k] &= ~RSPEC_SHORT_GI;
6826
6827 mimo_preamble_type = BRCMS_MM_PREAMBLE;
6828 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6829 mimo_preamble_type = BRCMS_GF_PREAMBLE;
6830
6831 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6832 && (!is_mcs_rate(rspec[k]))) {
6833 wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_"
6834 "RC_MCS != is_mcs_rate(rspec)\n",
6835 wlc->pub->unit, __func__);
6836 }
6837
6838 if (is_mcs_rate(rspec[k])) {
6839 preamble_type[k] = mimo_preamble_type;
6840
6841 /*
6842 * if SGI is selected, then forced mm
6843 * for single stream
6844 */
6845 if ((rspec[k] & RSPEC_SHORT_GI)
6846 && is_single_stream(rspec[k] &
6847 RSPEC_RATE_MASK))
6848 preamble_type[k] = BRCMS_MM_PREAMBLE;
6849 }
6850
6851 /* should be better conditionalized */
6852 if (!is_mcs_rate(rspec[0])
6853 && (tx_info->control.rates[0].
6854 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6855 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6856 }
6857 } else {
6858 for (k = 0; k < hw->max_rates; k++) {
6859 /* Set ctrlchbw as 20Mhz */
6860 rspec[k] &= ~RSPEC_BW_MASK;
6861 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6862
6863 /* for nphy, stf of ofdm frames must follow policies */
6864 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6865 rspec[k] &= ~RSPEC_STF_MASK;
6866 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6867 }
6868 }
6869 }
6870
6871 /* Reset these for use with AMPDU's */
6872 txrate[0]->count = 0;
6873 txrate[1]->count = 0;
6874
6875 /* (2) PROTECTION, may change rspec */
6876 if ((ieee80211_is_data(h->frame_control) ||
6877 ieee80211_is_mgmt(h->frame_control)) &&
6878 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6879 use_rts = true;
6880
6881 /* (3) PLCP: determine PLCP header and MAC duration,
6882 * fill struct d11txh */
6883 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6884 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6885 memcpy(&txh->FragPLCPFallback,
6886 plcp_fallback, sizeof(txh->FragPLCPFallback));
6887
6888 /* Length field now put in CCK FBR CRC field */
6889 if (is_cck_rate(rspec[1])) {
6890 txh->FragPLCPFallback[4] = phylen & 0xff;
6891 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6892 }
6893
6894 /* MIMO-RATE: need validation ?? */
6895 mainrates = is_ofdm_rate(rspec[0]) ?
6896 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6897 plcp[0];
6898
6899 /* DUR field for main rate */
6900 if (!ieee80211_is_pspoll(h->frame_control) &&
6901 !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6902 durid =
6903 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6904 next_frag_len);
6905 h->duration_id = cpu_to_le16(durid);
6906 } else if (use_rifs) {
6907 /* NAV protect to end of next max packet size */
6908 durid =
6909 (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6910 preamble_type[0],
6911 DOT11_MAX_FRAG_LEN);
6912 durid += RIFS_11N_TIME;
6913 h->duration_id = cpu_to_le16(durid);
6914 }
6915
6916 /* DUR field for fallback rate */
6917 if (ieee80211_is_pspoll(h->frame_control))
6918 txh->FragDurFallback = h->duration_id;
6919 else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6920 txh->FragDurFallback = 0;
6921 else {
6922 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6923 preamble_type[1], next_frag_len);
6924 txh->FragDurFallback = cpu_to_le16(durid);
6925 }
6926
6927 /* (4) MAC-HDR: MacTxControlLow */
6928 if (frag == 0)
6929 mcl |= TXC_STARTMSDU;
6930
6931 if (!is_multicast_ether_addr(h->addr1))
6932 mcl |= TXC_IMMEDACK;
6933
6934 if (wlc->band->bandtype == BRCM_BAND_5G)
6935 mcl |= TXC_FREQBAND_5G;
6936
6937 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6938 mcl |= TXC_BW_40;
6939
6940 /* set AMIC bit if using hardware TKIP MIC */
6941 if (hwtkmic)
6942 mcl |= TXC_AMIC;
6943
6944 txh->MacTxControlLow = cpu_to_le16(mcl);
6945
6946 /* MacTxControlHigh */
6947 mch = 0;
6948
6949 /* Set fallback rate preamble type */
6950 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6951 (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6952 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6953 mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6954 }
6955
6956 /* MacFrameControl */
6957 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6958 txh->TxFesTimeNormal = cpu_to_le16(0);
6959
6960 txh->TxFesTimeFallback = cpu_to_le16(0);
6961
6962 /* TxFrameRA */
6963 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6964
6965 /* TxFrameID */
6966 txh->TxFrameID = cpu_to_le16(frameid);
6967
6968 /*
6969 * TxStatus, Note the case of recreating the first frag of a suppressed
6970 * frame then we may need to reset the retry cnt's via the status reg
6971 */
6972 txh->TxStatus = cpu_to_le16(status);
6973
6974 /*
6975 * extra fields for ucode AMPDU aggregation, the new fields are added to
6976 * the END of previous structure so that it's compatible in driver.
6977 */
6978 txh->MaxNMpdus = cpu_to_le16(0);
6979 txh->MaxABytes_MRT = cpu_to_le16(0);
6980 txh->MaxABytes_FBR = cpu_to_le16(0);
6981 txh->MinMBytes = cpu_to_le16(0);
6982
6983 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6984 * furnish struct d11txh */
6985 /* RTS PLCP header and RTS frame */
6986 if (use_rts || use_cts) {
6987 if (use_rts && use_cts)
6988 use_cts = false;
6989
6990 for (k = 0; k < 2; k++) {
6991 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6992 false,
6993 mimo_ctlchbw);
6994 }
6995
6996 if (!is_ofdm_rate(rts_rspec[0]) &&
6997 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6998 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6999 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
7000 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
7001 }
7002
7003 if (!is_ofdm_rate(rts_rspec[1]) &&
7004 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
7005 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
7006 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
7007 mch |= TXC_PREAMBLE_RTS_FB_SHORT;
7008 }
7009
7010 /* RTS/CTS additions to MacTxControlLow */
7011 if (use_cts) {
7012 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
7013 } else {
7014 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
7015 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
7016 }
7017
7018 /* RTS PLCP header */
7019 rts_plcp = txh->RTSPhyHeader;
7020 if (use_cts)
7021 rts_phylen = DOT11_CTS_LEN + FCS_LEN;
7022 else
7023 rts_phylen = DOT11_RTS_LEN + FCS_LEN;
7024
7025 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
7026
7027 /* fallback rate version of RTS PLCP header */
7028 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
7029 rts_plcp_fallback);
7030 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
7031 sizeof(txh->RTSPLCPFallback));
7032
7033 /* RTS frame fields... */
7034 rts = (struct ieee80211_rts *)&txh->rts_frame;
7035
7036 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
7037 rspec[0], rts_preamble_type[0],
7038 preamble_type[0], phylen, false);
7039 rts->duration = cpu_to_le16(durid);
7040 /* fallback rate version of RTS DUR field */
7041 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
7042 rts_rspec[1], rspec[1],
7043 rts_preamble_type[1],
7044 preamble_type[1], phylen, false);
7045 txh->RTSDurFallback = cpu_to_le16(durid);
7046
7047 if (use_cts) {
7048 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
7049 IEEE80211_STYPE_CTS);
7050
7051 memcpy(&rts->ra, &h->addr2, ETH_ALEN);
7052 } else {
7053 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
7054 IEEE80211_STYPE_RTS);
7055
7056 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
7057 }
7058
7059 /* mainrate
7060 * low 8 bits: main frag rate/mcs,
7061 * high 8 bits: rts/cts rate/mcs
7062 */
7063 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
7064 D11A_PHY_HDR_GRATE(
7065 (struct ofdm_phy_hdr *) rts_plcp) :
7066 rts_plcp[0]) << 8;
7067 } else {
7068 memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
7069 memset((char *)&txh->rts_frame, 0,
7070 sizeof(struct ieee80211_rts));
7071 memset((char *)txh->RTSPLCPFallback, 0,
7072 sizeof(txh->RTSPLCPFallback));
7073 txh->RTSDurFallback = 0;
7074 }
7075
7076#ifdef SUPPORT_40MHZ
7077 /* add null delimiter count */
7078 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
7079 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
7080 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
7081
7082#endif
7083
7084 /*
7085 * Now that RTS/RTS FB preamble types are updated, write
7086 * the final value
7087 */
7088 txh->MacTxControlHigh = cpu_to_le16(mch);
7089
7090 /*
7091 * MainRates (both the rts and frag plcp rates have
7092 * been calculated now)
7093 */
7094 txh->MainRates = cpu_to_le16(mainrates);
7095
7096 /* XtraFrameTypes */
7097 xfts = frametype(rspec[1], wlc->mimoft);
7098 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
7099 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
7100 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
7101 XFTS_CHANNEL_SHIFT;
7102 txh->XtraFrameTypes = cpu_to_le16(xfts);
7103
7104 /* PhyTxControlWord */
7105 phyctl = frametype(rspec[0], wlc->mimoft);
7106 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
7107 (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
7108 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
7109 phyctl |= PHY_TXC_SHORT_HDR;
7110 }
7111
7112 /* phytxant is properly bit shifted */
7113 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
7114 txh->PhyTxControlWord = cpu_to_le16(phyctl);
7115
7116 /* PhyTxControlWord_1 */
7117 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7118 u16 phyctl1 = 0;
7119
7120 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
7121 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
7122 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
7123 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
7124
7125 if (use_rts || use_cts) {
7126 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
7127 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
7128 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
7129 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
7130 }
7131
7132 /*
7133 * For mcs frames, if mixedmode(overloaded with long preamble)
7134 * is going to be set, fill in non-zero MModeLen and/or
7135 * MModeFbrLen it will be unnecessary if they are separated
7136 */
7137 if (is_mcs_rate(rspec[0]) &&
7138 (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
7139 u16 mmodelen =
7140 brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
7141 txh->MModeLen = cpu_to_le16(mmodelen);
7142 }
7143
7144 if (is_mcs_rate(rspec[1]) &&
7145 (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
7146 u16 mmodefbrlen =
7147 brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
7148 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
7149 }
7150 }
7151
7152 ac = skb_get_queue_mapping(p);
7153 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
7154 uint frag_dur, dur, dur_fallback;
7155
7156 /* WME: Update TXOP threshold */
7157 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
7158 frag_dur =
7159 brcms_c_calc_frame_time(wlc, rspec[0],
7160 preamble_type[0], phylen);
7161
7162 if (rts) {
7163 /* 1 RTS or CTS-to-self frame */
7164 dur =
7165 brcms_c_calc_cts_time(wlc, rts_rspec[0],
7166 rts_preamble_type[0]);
7167 dur_fallback =
7168 brcms_c_calc_cts_time(wlc, rts_rspec[1],
7169 rts_preamble_type[1]);
7170 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
7171 dur += le16_to_cpu(rts->duration);
7172 dur_fallback +=
7173 le16_to_cpu(txh->RTSDurFallback);
7174 } else if (use_rifs) {
7175 dur = frag_dur;
7176 dur_fallback = 0;
7177 } else {
7178 /* frame + SIFS + ACK */
7179 dur = frag_dur;
7180 dur +=
7181 brcms_c_compute_frame_dur(wlc, rspec[0],
7182 preamble_type[0], 0);
7183
7184 dur_fallback =
7185 brcms_c_calc_frame_time(wlc, rspec[1],
7186 preamble_type[1],
7187 phylen);
7188 dur_fallback +=
7189 brcms_c_compute_frame_dur(wlc, rspec[1],
7190 preamble_type[1], 0);
7191 }
7192 /* NEED to set TxFesTimeNormal (hard) */
7193 txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
7194 /*
7195 * NEED to set fallback rate version of
7196 * TxFesTimeNormal (hard)
7197 */
7198 txh->TxFesTimeFallback =
7199 cpu_to_le16((u16) dur_fallback);
7200
7201 /*
7202 * update txop byte threshold (txop minus intraframe
7203 * overhead)
7204 */
7205 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
7206 uint newfragthresh;
7207
7208 newfragthresh =
7209 brcms_c_calc_frame_len(wlc,
7210 rspec[0], preamble_type[0],
7211 (wlc->edcf_txop[ac] -
7212 (dur - frag_dur)));
7213 /* range bound the fragthreshold */
7214 if (newfragthresh < DOT11_MIN_FRAG_LEN)
7215 newfragthresh =
7216 DOT11_MIN_FRAG_LEN;
7217 else if (newfragthresh >
7218 wlc->usr_fragthresh)
7219 newfragthresh =
7220 wlc->usr_fragthresh;
7221 /* update the fragthresh and do txc update */
7222 if (wlc->fragthresh[queue] !=
7223 (u16) newfragthresh)
7224 wlc->fragthresh[queue] =
7225 (u16) newfragthresh;
7226 } else {
7227 wiphy_err(wlc->wiphy, "wl%d: %s txop invalid "
7228 "for rate %d\n",
7229 wlc->pub->unit, fifo_names[queue],
7230 rspec2rate(rspec[0]));
7231 }
7232
7233 if (dur > wlc->edcf_txop[ac])
7234 wiphy_err(wlc->wiphy, "wl%d: %s: %s txop "
7235 "exceeded phylen %d/%d dur %d/%d\n",
7236 wlc->pub->unit, __func__,
7237 fifo_names[queue],
7238 phylen, wlc->fragthresh[queue],
7239 dur, wlc->edcf_txop[ac]);
7240 }
7241 }
7242
7243 return 0;
7244}
7245
7246void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
7247 struct ieee80211_hw *hw)
7248{
7249 u8 prio;
7250 uint fifo;
7251 struct scb *scb = &wlc->pri_scb;
7252 struct ieee80211_hdr *d11_header = (struct ieee80211_hdr *)(sdu->data);
7253
7254 /*
7255 * 802.11 standard requires management traffic
7256 * to go at highest priority
7257 */
7258 prio = ieee80211_is_data(d11_header->frame_control) ? sdu->priority :
7259 MAXPRIO;
7260 fifo = prio2fifo[prio];
7261 if (brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0))
7262 return;
7263 brcms_c_txq_enq(wlc, scb, sdu, BRCMS_PRIO_TO_PREC(prio));
7264 brcms_c_send_q(wlc);
7265}
7266
7267void brcms_c_send_q(struct brcms_c_info *wlc)
7268{
7269 struct sk_buff *pkt[DOT11_MAXNUMFRAGS];
7270 int prec;
7271 u16 prec_map;
7272 int err = 0, i, count;
7273 uint fifo;
7274 struct brcms_txq_info *qi = wlc->pkt_queue;
7275 struct pktq *q = &qi->q;
7276 struct ieee80211_tx_info *tx_info;
7277
7278 prec_map = wlc->tx_prec_map;
7279
7280 /* Send all the enq'd pkts that we can.
7281 * Dequeue packets with precedence with empty HW fifo only
7282 */
7283 while (prec_map && (pkt[0] = brcmu_pktq_mdeq(q, prec_map, &prec))) {
7284 tx_info = IEEE80211_SKB_CB(pkt[0]);
7285 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
7286 err = brcms_c_sendampdu(wlc->ampdu, qi, pkt, prec);
7287 } else {
7288 count = 1;
7289 err = brcms_c_prep_pdu(wlc, pkt[0], &fifo);
7290 if (!err) {
7291 for (i = 0; i < count; i++)
7292 brcms_c_txfifo(wlc, fifo, pkt[i], true,
7293 1);
7294 }
7295 }
7296
7297 if (err == -EBUSY) {
7298 brcmu_pktq_penq_head(q, prec, pkt[0]);
7299 /*
7300 * If send failed due to any other reason than a
7301 * change in HW FIFO condition, quit. Otherwise,
7302 * read the new prec_map!
7303 */
7304 if (prec_map == wlc->tx_prec_map)
7305 break;
7306 prec_map = wlc->tx_prec_map;
7307 }
7308 }
7309}
7310
7311void
7312brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p,
7313 bool commit, s8 txpktpend)
7314{
7315 u16 frameid = INVALIDFID;
7316 struct d11txh *txh;
7317
7318 txh = (struct d11txh *) (p->data);
7319
7320 /* When a BC/MC frame is being committed to the BCMC fifo
7321 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
7322 */
7323 if (fifo == TX_BCMC_FIFO)
7324 frameid = le16_to_cpu(txh->TxFrameID);
7325
7326 /*
7327 * Bump up pending count for if not using rpc. If rpc is
7328 * used, this will be handled in brcms_b_txfifo()
7329 */
7330 if (commit) {
7331 wlc->core->txpktpend[fifo] += txpktpend;
7332 BCMMSG(wlc->wiphy, "pktpend inc %d to %d\n",
7333 txpktpend, wlc->core->txpktpend[fifo]);
7334 }
7335
7336 /* Commit BCMC sequence number in the SHM frame ID location */
7337 if (frameid != INVALIDFID) {
7338 /*
7339 * To inform the ucode of the last mcast frame posted
7340 * so that it can clear moredata bit
7341 */
7342 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
7343 }
7344
7345 if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0)
7346 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
7347}
7348
7349u32
7350brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
7351 bool use_rspec, u16 mimo_ctlchbw)
7352{
7353 u32 rts_rspec = 0;
7354
7355 if (use_rspec)
7356 /* use frame rate as rts rate */
7357 rts_rspec = rspec;
7358 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
7359 /* Use 11Mbps as the g protection RTS target rate and fallback.
7360 * Use the brcms_basic_rate() lookup to find the best basic rate
7361 * under the target in case 11 Mbps is not Basic.
7362 * 6 and 9 Mbps are not usually selected by rate selection, but
7363 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
7364 * is more robust.
7365 */
7366 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
7367 else
7368 /* calculate RTS rate and fallback rate based on the frame rate
7369 * RTS must be sent at a basic rate since it is a
7370 * control frame, sec 9.6 of 802.11 spec
7371 */
7372 rts_rspec = brcms_basic_rate(wlc, rspec);
7373
7374 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7375 /* set rts txbw to correct side band */
7376 rts_rspec &= ~RSPEC_BW_MASK;
7377
7378 /*
7379 * if rspec/rspec_fallback is 40MHz, then send RTS on both
7380 * 20MHz channel (DUP), otherwise send RTS on control channel
7381 */
7382 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
7383 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
7384 else
7385 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
7386
7387 /* pick siso/cdd as default for ofdm */
7388 if (is_ofdm_rate(rts_rspec)) {
7389 rts_rspec &= ~RSPEC_STF_MASK;
7390 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
7391 }
7392 }
7393 return rts_rspec;
7394}
7395
7396void
7397brcms_c_txfifo_complete(struct brcms_c_info *wlc, uint fifo, s8 txpktpend)
7398{
7399 wlc->core->txpktpend[fifo] -= txpktpend;
7400 BCMMSG(wlc->wiphy, "pktpend dec %d to %d\n", txpktpend,
7401 wlc->core->txpktpend[fifo]);
7402
7403 /* There is more room; mark precedences related to this FIFO sendable */
7404 wlc->tx_prec_map |= wlc->fifo2prec_map[fifo];
7405
7406 /* figure out which bsscfg is being worked on... */
7407}
7408
7409/* Update beacon listen interval in shared memory */
7410static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7411{
7412 /* wake up every DTIM is the default */
7413 if (wlc->bcn_li_dtim == 1)
7414 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7415 else
7416 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7417 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7418}
7419
7420static void
7421brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7422 u32 *tsf_h_ptr)
7423{
7424 struct bcma_device *core = wlc_hw->d11core;
7425
7426 /* read the tsf timer low, then high to get an atomic read */
7427 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7428 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7429}
7430
7431/*
7432 * recover 64bit TSF value from the 16bit TSF value in the rx header
7433 * given the assumption that the TSF passed in header is within 65ms
7434 * of the current tsf.
7435 *
7436 * 6 5 4 4 3 2 1
7437 * 3.......6.......8.......0.......2.......4.......6.......8......0
7438 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7439 *
7440 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7441 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7442 * receive call sequence after rx interrupt. Only the higher 16 bits
7443 * are used. Finally, the tsf_h is read from the tsf register.
7444 */
7445static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7446 struct d11rxhdr *rxh)
7447{
7448 u32 tsf_h, tsf_l;
7449 u16 rx_tsf_0_15, rx_tsf_16_31;
7450
7451 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7452
7453 rx_tsf_16_31 = (u16)(tsf_l >> 16);
7454 rx_tsf_0_15 = rxh->RxTSFTime;
7455
7456 /*
7457 * a greater tsf time indicates the low 16 bits of
7458 * tsf_l wrapped, so decrement the high 16 bits.
7459 */
7460 if ((u16)tsf_l < rx_tsf_0_15) {
7461 rx_tsf_16_31 -= 1;
7462 if (rx_tsf_16_31 == 0xffff)
7463 tsf_h -= 1;
7464 }
7465
7466 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7467}
7468
7469static void
7470prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7471 struct sk_buff *p,
7472 struct ieee80211_rx_status *rx_status)
7473{
7474 int preamble;
7475 int channel;
7476 u32 rspec;
7477 unsigned char *plcp;
7478
7479 /* fill in TSF and flag its presence */
7480 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7481 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
7482
7483 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7484
7485 if (channel > 14) {
7486 rx_status->band = IEEE80211_BAND_5GHZ;
7487 rx_status->freq = ieee80211_ofdm_chan_to_freq(
7488 WF_CHAN_FACTOR_5_G/2, channel);
7489
7490 } else {
7491 rx_status->band = IEEE80211_BAND_2GHZ;
7492 rx_status->freq = ieee80211_dsss_chan_to_freq(channel);
7493 }
7494
7495 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7496
7497 /* noise */
7498 /* qual */
7499 rx_status->antenna =
7500 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7501
7502 plcp = p->data;
7503
7504 rspec = brcms_c_compute_rspec(rxh, plcp);
7505 if (is_mcs_rate(rspec)) {
7506 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7507 rx_status->flag |= RX_FLAG_HT;
7508 if (rspec_is40mhz(rspec))
7509 rx_status->flag |= RX_FLAG_40MHZ;
7510 } else {
7511 switch (rspec2rate(rspec)) {
7512 case BRCM_RATE_1M:
7513 rx_status->rate_idx = 0;
7514 break;
7515 case BRCM_RATE_2M:
7516 rx_status->rate_idx = 1;
7517 break;
7518 case BRCM_RATE_5M5:
7519 rx_status->rate_idx = 2;
7520 break;
7521 case BRCM_RATE_11M:
7522 rx_status->rate_idx = 3;
7523 break;
7524 case BRCM_RATE_6M:
7525 rx_status->rate_idx = 4;
7526 break;
7527 case BRCM_RATE_9M:
7528 rx_status->rate_idx = 5;
7529 break;
7530 case BRCM_RATE_12M:
7531 rx_status->rate_idx = 6;
7532 break;
7533 case BRCM_RATE_18M:
7534 rx_status->rate_idx = 7;
7535 break;
7536 case BRCM_RATE_24M:
7537 rx_status->rate_idx = 8;
7538 break;
7539 case BRCM_RATE_36M:
7540 rx_status->rate_idx = 9;
7541 break;
7542 case BRCM_RATE_48M:
7543 rx_status->rate_idx = 10;
7544 break;
7545 case BRCM_RATE_54M:
7546 rx_status->rate_idx = 11;
7547 break;
7548 default:
7549 wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__);
7550 }
7551
7552 /*
7553 * For 5GHz, we should decrease the index as it is
7554 * a subset of the 2.4G rates. See bitrates field
7555 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7556 */
7557 if (rx_status->band == IEEE80211_BAND_5GHZ)
7558 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7559
7560 /* Determine short preamble and rate_idx */
7561 preamble = 0;
7562 if (is_cck_rate(rspec)) {
7563 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7564 rx_status->flag |= RX_FLAG_SHORTPRE;
7565 } else if (is_ofdm_rate(rspec)) {
7566 rx_status->flag |= RX_FLAG_SHORTPRE;
7567 } else {
7568 wiphy_err(wlc->wiphy, "%s: Unknown modulation\n",
7569 __func__);
7570 }
7571 }
7572
7573 if (plcp3_issgi(plcp[3]))
7574 rx_status->flag |= RX_FLAG_SHORT_GI;
7575
7576 if (rxh->RxStatus1 & RXS_DECERR) {
7577 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7578 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7579 __func__);
7580 }
7581 if (rxh->RxStatus1 & RXS_FCSERR) {
7582 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7583 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7584 __func__);
7585 }
7586}
7587
7588static void
7589brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7590 struct sk_buff *p)
7591{
7592 int len_mpdu;
7593 struct ieee80211_rx_status rx_status;
7594 struct ieee80211_hdr *hdr;
7595
7596 memset(&rx_status, 0, sizeof(rx_status));
7597 prep_mac80211_status(wlc, rxh, p, &rx_status);
7598
7599 /* mac header+body length, exclude CRC and plcp header */
7600 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7601 skb_pull(p, D11_PHY_HDR_LEN);
7602 __skb_trim(p, len_mpdu);
7603
7604 /* unmute transmit */
7605 if (wlc->hw->suspended_fifos) {
7606 hdr = (struct ieee80211_hdr *)p->data;
7607 if (ieee80211_is_beacon(hdr->frame_control))
7608 brcms_b_mute(wlc->hw, false);
7609 }
7610
7611 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7612 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7613}
7614
7615/* calculate frame duration for Mixed-mode L-SIG spoofing, return
7616 * number of bytes goes in the length field
7617 *
7618 * Formula given by HT PHY Spec v 1.13
7619 * len = 3(nsyms + nstream + 3) - 3
7620 */
7621u16
7622brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7623 uint mac_len)
7624{
7625 uint nsyms, len = 0, kNdps;
7626
7627 BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n",
7628 wlc->pub->unit, rspec2rate(ratespec), mac_len);
7629
7630 if (is_mcs_rate(ratespec)) {
7631 uint mcs = ratespec & RSPEC_RATE_MASK;
7632 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7633 rspec_stc(ratespec);
7634
7635 /*
7636 * the payload duration calculation matches that
7637 * of regular ofdm
7638 */
7639 /* 1000Ndbps = kbps * 4 */
7640 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7641 rspec_issgi(ratespec)) * 4;
7642
7643 if (rspec_stc(ratespec) == 0)
7644 nsyms =
7645 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7646 APHY_TAIL_NBITS) * 1000, kNdps);
7647 else
7648 /* STBC needs to have even number of symbols */
7649 nsyms =
7650 2 *
7651 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7652 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7653
7654 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7655 nsyms += (tot_streams + 3);
7656 /*
7657 * 3 bytes/symbol @ legacy 6Mbps rate
7658 * (-3) excluding service bits and tail bits
7659 */
7660 len = (3 * nsyms) - 3;
7661 }
7662
7663 return (u16) len;
7664}
7665
7666static void
7667brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7668{
7669 const struct brcms_c_rateset *rs_dflt;
7670 struct brcms_c_rateset rs;
7671 u8 rate;
7672 u16 entry_ptr;
7673 u8 plcp[D11_PHY_HDR_LEN];
7674 u16 dur, sifs;
7675 uint i;
7676
7677 sifs = get_sifs(wlc->band);
7678
7679 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7680
7681 brcms_c_rateset_copy(rs_dflt, &rs);
7682 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7683
7684 /*
7685 * walk the phy rate table and update MAC core SHM
7686 * basic rate table entries
7687 */
7688 for (i = 0; i < rs.count; i++) {
7689 rate = rs.rates[i] & BRCMS_RATE_MASK;
7690
7691 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7692
7693 /* Calculate the Probe Response PLCP for the given rate */
7694 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7695
7696 /*
7697 * Calculate the duration of the Probe Response
7698 * frame plus SIFS for the MAC
7699 */
7700 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7701 BRCMS_LONG_PREAMBLE, frame_len);
7702 dur += sifs;
7703
7704 /* Update the SHM Rate Table entry Probe Response values */
7705 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7706 (u16) (plcp[0] + (plcp[1] << 8)));
7707 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7708 (u16) (plcp[2] + (plcp[3] << 8)));
7709 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7710 }
7711}
7712
7713/* Max buffering needed for beacon template/prb resp template is 142 bytes.
7714 *
7715 * PLCP header is 6 bytes.
7716 * 802.11 A3 header is 24 bytes.
7717 * Max beacon frame body template length is 112 bytes.
7718 * Max probe resp frame body template length is 110 bytes.
7719 *
7720 * *len on input contains the max length of the packet available.
7721 *
7722 * The *len value is set to the number of bytes in buf used, and starts
7723 * with the PLCP and included up to, but not including, the 4 byte FCS.
7724 */
7725static void
7726brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
7727 u32 bcn_rspec,
7728 struct brcms_bss_cfg *cfg, u16 *buf, int *len)
7729{
7730 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
7731 struct cck_phy_hdr *plcp;
7732 struct ieee80211_mgmt *h;
7733 int hdr_len, body_len;
7734
7735 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
7736
7737 /* calc buffer size provided for frame body */
7738 body_len = *len - hdr_len;
7739 /* return actual size */
7740 *len = hdr_len + body_len;
7741
7742 /* format PHY and MAC headers */
7743 memset((char *)buf, 0, hdr_len);
7744
7745 plcp = (struct cck_phy_hdr *) buf;
7746
7747 /*
7748 * PLCP for Probe Response frames are filled in from
7749 * core's rate table
7750 */
7751 if (type == IEEE80211_STYPE_BEACON)
7752 /* fill in PLCP */
7753 brcms_c_compute_plcp(wlc, bcn_rspec,
7754 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
7755 (u8 *) plcp);
7756
7757 /* "Regular" and 16 MBSS but not for 4 MBSS */
7758 /* Update the phytxctl for the beacon based on the rspec */
7759 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
7760
7761 h = (struct ieee80211_mgmt *)&plcp[1];
7762
7763 /* fill in 802.11 header */
7764 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
7765
7766 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7767 /* A1 filled in by MAC for prb resp, broadcast for bcn */
7768 if (type == IEEE80211_STYPE_BEACON)
7769 memcpy(&h->da, ðer_bcast, ETH_ALEN);
7770 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
7771 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
7772
7773 /* SEQ filled in by MAC */
7774}
7775
7776int brcms_c_get_header_len(void)
7777{
7778 return TXOFF;
7779}
7780
7781/*
7782 * Update all beacons for the system.
7783 */
7784void brcms_c_update_beacon(struct brcms_c_info *wlc)
7785{
7786 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7787
7788 if (bsscfg->up && !bsscfg->BSS)
7789 /* Clear the soft intmask */
7790 wlc->defmacintmask &= ~MI_BCNTPL;
7791}
7792
7793/* Write ssid into shared memory */
7794static void
7795brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7796{
7797 u8 *ssidptr = cfg->SSID;
7798 u16 base = M_SSID;
7799 u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7800
7801 /* padding the ssid with zero and copy it into shm */
7802 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7803 memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7804
7805 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7806 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7807}
7808
7809static void
7810brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7811 struct brcms_bss_cfg *cfg,
7812 bool suspend)
7813{
7814 u16 prb_resp[BCN_TMPL_LEN / 2];
7815 int len = BCN_TMPL_LEN;
7816
7817 /*
7818 * write the probe response to hardware, or save in
7819 * the config structure
7820 */
7821
7822 /* create the probe response template */
7823 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
7824 cfg, prb_resp, &len);
7825
7826 if (suspend)
7827 brcms_c_suspend_mac_and_wait(wlc);
7828
7829 /* write the probe response into the template region */
7830 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7831 (len + 3) & ~3, prb_resp);
7832
7833 /* write the length of the probe response frame (+PLCP/-FCS) */
7834 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7835
7836 /* write the SSID and SSID length */
7837 brcms_c_shm_ssid_upd(wlc, cfg);
7838
7839 /*
7840 * Write PLCP headers and durations for probe response frames
7841 * at all rates. Use the actual frame length covered by the
7842 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7843 * by subtracting the PLCP len and adding the FCS.
7844 */
7845 len += (-D11_PHY_HDR_LEN + FCS_LEN);
7846 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
7847
7848 if (suspend)
7849 brcms_c_enable_mac(wlc);
7850}
7851
7852void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7853{
7854 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7855
7856 /* update AP or IBSS probe responses */
7857 if (bsscfg->up && !bsscfg->BSS)
7858 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
7859}
7860
7861/* prepares pdu for transmission. returns BCM error codes */
7862int brcms_c_prep_pdu(struct brcms_c_info *wlc, struct sk_buff *pdu, uint *fifop)
7863{
7864 uint fifo;
7865 struct d11txh *txh;
7866 struct ieee80211_hdr *h;
7867 struct scb *scb;
7868
7869 txh = (struct d11txh *) (pdu->data);
7870 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
7871
7872 /* get the pkt queue info. This was put at brcms_c_sendctl or
7873 * brcms_c_send for PDU */
7874 fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
7875
7876 scb = NULL;
7877
7878 *fifop = fifo;
7879
7880 /* return if insufficient dma resources */
7881 if (*wlc->core->txavail[fifo] < MAX_DMA_SEGS) {
7882 /* Mark precedences related to this FIFO, unsendable */
7883 /* A fifo is full. Clear precedences related to that FIFO */
7884 wlc->tx_prec_map &= ~(wlc->fifo2prec_map[fifo]);
7885 return -EBUSY;
7886 }
7887 return 0;
7888}
7889
7890int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7891 uint *blocks)
7892{
7893 if (fifo >= NFIFO)
7894 return -EINVAL;
7895
7896 *blocks = wlc_hw->xmtfifo_sz[fifo];
7897
7898 return 0;
7899}
7900
7901void
7902brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7903 const u8 *addr)
7904{
7905 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7906 if (match_reg_offset == RCM_BSSID_OFFSET)
7907 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7908}
7909
7910/*
7911 * Flag 'scan in progress' to withhold dynamic phy calibration
7912 */
7913void brcms_c_scan_start(struct brcms_c_info *wlc)
7914{
7915 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7916}
7917
7918void brcms_c_scan_stop(struct brcms_c_info *wlc)
7919{
7920 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7921}
7922
7923void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7924{
7925 wlc->pub->associated = state;
7926 wlc->bsscfg->associated = state;
7927}
7928
7929/*
7930 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7931 * AMPDU traffic, packets pending in hardware have to be invalidated so that
7932 * when later on hardware releases them, they can be handled appropriately.
7933 */
7934void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7935 struct ieee80211_sta *sta,
7936 void (*dma_callback_fn))
7937{
7938 struct dma_pub *dmah;
7939 int i;
7940 for (i = 0; i < NFIFO; i++) {
7941 dmah = hw->di[i];
7942 if (dmah != NULL)
7943 dma_walk_packets(dmah, dma_callback_fn, sta);
7944 }
7945}
7946
7947int brcms_c_get_curband(struct brcms_c_info *wlc)
7948{
7949 return wlc->band->bandunit;
7950}
7951
7952void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop)
7953{
7954 int timeout = 20;
7955
7956 /* flush packet queue when requested */
7957 if (drop)
7958 brcmu_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL);
7959
7960 /* wait for queue and DMA fifos to run dry */
7961 while (!pktq_empty(&wlc->pkt_queue->q) || brcms_txpktpendtot(wlc) > 0) {
7962 brcms_msleep(wlc->wl, 1);
7963
7964 if (--timeout == 0)
7965 break;
7966 }
7967
7968 WARN_ON_ONCE(timeout == 0);
7969}
7970
7971void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7972{
7973 wlc->bcn_li_bcn = interval;
7974 if (wlc->pub->up)
7975 brcms_c_bcn_li_upd(wlc);
7976}
7977
7978int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7979{
7980 uint qdbm;
7981
7982 /* Remove override bit and clip to max qdbm value */
7983 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7984 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7985}
7986
7987int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7988{
7989 uint qdbm;
7990 bool override;
7991
7992 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7993
7994 /* Return qdbm units */
7995 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7996}
7997
7998/* Process received frames */
7999/*
8000 * Return true if more frames need to be processed. false otherwise.
8001 * Param 'bound' indicates max. # frames to process before break out.
8002 */
8003static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
8004{
8005 struct d11rxhdr *rxh;
8006 struct ieee80211_hdr *h;
8007 uint len;
8008 bool is_amsdu;
8009
8010 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
8011
8012 /* frame starts with rxhdr */
8013 rxh = (struct d11rxhdr *) (p->data);
8014
8015 /* strip off rxhdr */
8016 skb_pull(p, BRCMS_HWRXOFF);
8017
8018 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
8019 if (rxh->RxStatus1 & RXS_PBPRES) {
8020 if (p->len < 2) {
8021 wiphy_err(wlc->wiphy, "wl%d: recv: rcvd runt of "
8022 "len %d\n", wlc->pub->unit, p->len);
8023 goto toss;
8024 }
8025 skb_pull(p, 2);
8026 }
8027
8028 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
8029 len = p->len;
8030
8031 if (rxh->RxStatus1 & RXS_FCSERR) {
8032 if (!(wlc->filter_flags & FIF_FCSFAIL))
8033 goto toss;
8034 }
8035
8036 /* check received pkt has at least frame control field */
8037 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
8038 goto toss;
8039
8040 /* not supporting A-MSDU */
8041 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
8042 if (is_amsdu)
8043 goto toss;
8044
8045 brcms_c_recvctl(wlc, rxh, p);
8046 return;
8047
8048 toss:
8049 brcmu_pkt_buf_free_skb(p);
8050}
8051
8052/* Process received frames */
8053/*
8054 * Return true if more frames need to be processed. false otherwise.
8055 * Param 'bound' indicates max. # frames to process before break out.
8056 */
8057static bool
8058brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
8059{
8060 struct sk_buff *p;
8061 struct sk_buff *next = NULL;
8062 struct sk_buff_head recv_frames;
8063
8064 uint n = 0;
8065 uint bound_limit = bound ? RXBND : -1;
8066
8067 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
8068 skb_queue_head_init(&recv_frames);
8069
8070 /* gather received frames */
8071 while (dma_rx(wlc_hw->di[fifo], &recv_frames)) {
8072
8073 /* !give others some time to run! */
8074 if (++n >= bound_limit)
8075 break;
8076 }
8077
8078 /* post more rbufs */
8079 dma_rxfill(wlc_hw->di[fifo]);
8080
8081 /* process each frame */
8082 skb_queue_walk_safe(&recv_frames, p, next) {
8083 struct d11rxhdr_le *rxh_le;
8084 struct d11rxhdr *rxh;
8085
8086 skb_unlink(p, &recv_frames);
8087 rxh_le = (struct d11rxhdr_le *)p->data;
8088 rxh = (struct d11rxhdr *)p->data;
8089
8090 /* fixup rx header endianness */
8091 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
8092 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
8093 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
8094 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
8095 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
8096 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
8097 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
8098 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
8099 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
8100 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
8101 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
8102
8103 brcms_c_recv(wlc_hw->wlc, p);
8104 }
8105
8106 return n >= bound_limit;
8107}
8108
8109/* second-level interrupt processing
8110 * Return true if another dpc needs to be re-scheduled. false otherwise.
8111 * Param 'bounded' indicates if applicable loops should be bounded.
8112 */
8113bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8114{
8115 u32 macintstatus;
8116 struct brcms_hardware *wlc_hw = wlc->hw;
8117 struct bcma_device *core = wlc_hw->d11core;
8118 struct wiphy *wiphy = wlc->wiphy;
8119
8120 if (brcms_deviceremoved(wlc)) {
8121 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
8122 __func__);
8123 brcms_down(wlc->wl);
8124 return false;
8125 }
8126
8127 /* grab and clear the saved software intstatus bits */
8128 macintstatus = wlc->macintstatus;
8129 wlc->macintstatus = 0;
8130
8131 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
8132 wlc_hw->unit, macintstatus);
8133
8134 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
8135
8136 /* tx status */
8137 if (macintstatus & MI_TFS) {
8138 bool fatal;
8139 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
8140 wlc->macintstatus |= MI_TFS;
8141 if (fatal) {
8142 wiphy_err(wiphy, "MI_TFS: fatal\n");
8143 goto fatal;
8144 }
8145 }
8146
8147 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
8148 brcms_c_tbtt(wlc);
8149
8150 /* ATIM window end */
8151 if (macintstatus & MI_ATIMWINEND) {
8152 BCMMSG(wlc->wiphy, "end of ATIM window\n");
8153 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
8154 wlc->qvalid = 0;
8155 }
8156
8157 /*
8158 * received data or control frame, MI_DMAINT is
8159 * indication of RX_FIFO interrupt
8160 */
8161 if (macintstatus & MI_DMAINT)
8162 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
8163 wlc->macintstatus |= MI_DMAINT;
8164
8165 /* noise sample collected */
8166 if (macintstatus & MI_BG_NOISE)
8167 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
8168
8169 if (macintstatus & MI_GP0) {
8170 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
8171 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
8172
8173 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
8174 __func__, ai_get_chip_id(wlc_hw->sih),
8175 ai_get_chiprev(wlc_hw->sih));
8176 brcms_fatal_error(wlc_hw->wlc->wl);
8177 }
8178
8179 /* gptimer timeout */
8180 if (macintstatus & MI_TO)
8181 bcma_write32(core, D11REGOFFS(gptimer), 0);
8182
8183 if (macintstatus & MI_RFDISABLE) {
8184 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
8185 " RF Disable Input\n", wlc_hw->unit);
8186 brcms_rfkill_set_hw_state(wlc->wl);
8187 }
8188
8189 /* send any enq'd tx packets. Just makes sure to jump start tx */
8190 if (!pktq_empty(&wlc->pkt_queue->q))
8191 brcms_c_send_q(wlc);
8192
8193 /* it isn't done and needs to be resched if macintstatus is non-zero */
8194 return wlc->macintstatus != 0;
8195
8196 fatal:
8197 brcms_fatal_error(wlc_hw->wlc->wl);
8198 return wlc->macintstatus != 0;
8199}
8200
8201void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
8202{
8203 struct bcma_device *core = wlc->hw->d11core;
8204 u16 chanspec;
8205
8206 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
8207
8208 /*
8209 * This will happen if a big-hammer was executed. In
8210 * that case, we want to go back to the channel that
8211 * we were on and not new channel
8212 */
8213 if (wlc->pub->associated)
8214 chanspec = wlc->home_chanspec;
8215 else
8216 chanspec = brcms_c_init_chanspec(wlc);
8217
8218 brcms_b_init(wlc->hw, chanspec);
8219
8220 /* update beacon listen interval */
8221 brcms_c_bcn_li_upd(wlc);
8222
8223 /* write ethernet address to core */
8224 brcms_c_set_mac(wlc->bsscfg);
8225 brcms_c_set_bssid(wlc->bsscfg);
8226
8227 /* Update tsf_cfprep if associated and up */
8228 if (wlc->pub->associated && wlc->bsscfg->up) {
8229 u32 bi;
8230
8231 /* get beacon period and convert to uS */
8232 bi = wlc->bsscfg->current_bss->beacon_period << 10;
8233 /*
8234 * update since init path would reset
8235 * to default value
8236 */
8237 bcma_write32(core, D11REGOFFS(tsf_cfprep),
8238 bi << CFPREP_CBI_SHIFT);
8239
8240 /* Update maccontrol PM related bits */
8241 brcms_c_set_ps_ctrl(wlc);
8242 }
8243
8244 brcms_c_bandinit_ordered(wlc, chanspec);
8245
8246 /* init probe response timeout */
8247 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
8248
8249 /* init max burst txop (framebursting) */
8250 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
8251 (wlc->
8252 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
8253
8254 /* initialize maximum allowed duty cycle */
8255 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
8256 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
8257
8258 /*
8259 * Update some shared memory locations related to
8260 * max AMPDU size allowed to received
8261 */
8262 brcms_c_ampdu_shm_upd(wlc->ampdu);
8263
8264 /* band-specific inits */
8265 brcms_c_bsinit(wlc);
8266
8267 /* Enable EDCF mode (while the MAC is suspended) */
8268 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
8269 brcms_c_edcf_setparams(wlc, false);
8270
8271 /* Init precedence maps for empty FIFOs */
8272 brcms_c_tx_prec_map_init(wlc);
8273
8274 /* read the ucode version if we have not yet done so */
8275 if (wlc->ucode_rev == 0) {
8276 wlc->ucode_rev =
8277 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
8278 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
8279 }
8280
8281 /* ..now really unleash hell (allow the MAC out of suspend) */
8282 brcms_c_enable_mac(wlc);
8283
8284 /* suspend the tx fifos and mute the phy for preism cac time */
8285 if (mute_tx)
8286 brcms_b_mute(wlc->hw, true);
8287
8288 /* clear tx flow control */
8289 brcms_c_txflowcontrol_reset(wlc);
8290
8291 /* enable the RF Disable Delay timer */
8292 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
8293
8294 /*
8295 * Initialize WME parameters; if they haven't been set by some other
8296 * mechanism (IOVar, etc) then read them from the hardware.
8297 */
8298 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
8299 /* Uninitialized; read from HW */
8300 int ac;
8301
8302 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
8303 wlc->wme_retries[ac] =
8304 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
8305 }
8306}
8307
8308/*
8309 * The common driver entry routine. Error codes should be unique
8310 */
8311struct brcms_c_info *
8312brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
8313 bool piomode, uint *perr)
8314{
8315 struct brcms_c_info *wlc;
8316 uint err = 0;
8317 uint i, j;
8318 struct brcms_pub *pub;
8319
8320 /* allocate struct brcms_c_info state and its substructures */
8321 wlc = (struct brcms_c_info *) brcms_c_attach_malloc(unit, &err, 0);
8322 if (wlc == NULL)
8323 goto fail;
8324 wlc->wiphy = wl->wiphy;
8325 pub = wlc->pub;
8326
8327#if defined(DEBUG)
8328 wlc_info_dbg = wlc;
8329#endif
8330
8331 wlc->band = wlc->bandstate[0];
8332 wlc->core = wlc->corestate;
8333 wlc->wl = wl;
8334 pub->unit = unit;
8335 pub->_piomode = piomode;
8336 wlc->bandinit_pending = false;
8337
8338 /* populate struct brcms_c_info with default values */
8339 brcms_c_info_init(wlc, unit);
8340
8341 /* update sta/ap related parameters */
8342 brcms_c_ap_upd(wlc);
8343
8344 /*
8345 * low level attach steps(all hw accesses go
8346 * inside, no more in rest of the attach)
8347 */
8348 err = brcms_b_attach(wlc, core, unit, piomode);
8349 if (err)
8350 goto fail;
8351
8352 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
8353
8354 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
8355
8356 /* disable allowed duty cycle */
8357 wlc->tx_duty_cycle_ofdm = 0;
8358 wlc->tx_duty_cycle_cck = 0;
8359
8360 brcms_c_stf_phy_chain_calc(wlc);
8361
8362 /* txchain 1: txant 0, txchain 2: txant 1 */
8363 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
8364 wlc->stf->txant = wlc->stf->hw_txchain - 1;
8365
8366 /* push to BMAC driver */
8367 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
8368 wlc->stf->hw_rxchain);
8369
8370 /* pull up some info resulting from the low attach */
8371 for (i = 0; i < NFIFO; i++)
8372 wlc->core->txavail[i] = wlc->hw->txavail[i];
8373
8374 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8375 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8376
8377 for (j = 0; j < wlc->pub->_nbands; j++) {
8378 wlc->band = wlc->bandstate[j];
8379
8380 if (!brcms_c_attach_stf_ant_init(wlc)) {
8381 err = 24;
8382 goto fail;
8383 }
8384
8385 /* default contention windows size limits */
8386 wlc->band->CWmin = APHY_CWMIN;
8387 wlc->band->CWmax = PHY_CWMAX;
8388
8389 /* init gmode value */
8390 if (wlc->band->bandtype == BRCM_BAND_2G) {
8391 wlc->band->gmode = GMODE_AUTO;
8392 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
8393 wlc->band->gmode);
8394 }
8395
8396 /* init _n_enab supported mode */
8397 if (BRCMS_PHY_11N_CAP(wlc->band)) {
8398 pub->_n_enab = SUPPORT_11N;
8399 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
8400 ((pub->_n_enab ==
8401 SUPPORT_11N) ? WL_11N_2x2 :
8402 WL_11N_3x3));
8403 }
8404
8405 /* init per-band default rateset, depend on band->gmode */
8406 brcms_default_rateset(wlc, &wlc->band->defrateset);
8407
8408 /* fill in hw_rateset */
8409 brcms_c_rateset_filter(&wlc->band->defrateset,
8410 &wlc->band->hw_rateset, false,
8411 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
8412 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
8413 }
8414
8415 /*
8416 * update antenna config due to
8417 * wlc->stf->txant/txchain/ant_rx_ovr change
8418 */
8419 brcms_c_stf_phy_txant_upd(wlc);
8420
8421 /* attach each modules */
8422 err = brcms_c_attach_module(wlc);
8423 if (err != 0)
8424 goto fail;
8425
8426 if (!brcms_c_timers_init(wlc, unit)) {
8427 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
8428 __func__);
8429 err = 32;
8430 goto fail;
8431 }
8432
8433 /* depend on rateset, gmode */
8434 wlc->cmi = brcms_c_channel_mgr_attach(wlc);
8435 if (!wlc->cmi) {
8436 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
8437 "\n", unit, __func__);
8438 err = 33;
8439 goto fail;
8440 }
8441
8442 /* init default when all parameters are ready, i.e. ->rateset */
8443 brcms_c_bss_default_init(wlc);
8444
8445 /*
8446 * Complete the wlc default state initializations..
8447 */
8448
8449 /* allocate our initial queue */
8450 wlc->pkt_queue = brcms_c_txq_alloc(wlc);
8451 if (wlc->pkt_queue == NULL) {
8452 wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n",
8453 unit, __func__);
8454 err = 100;
8455 goto fail;
8456 }
8457
8458 wlc->bsscfg->wlc = wlc;
8459
8460 wlc->mimoft = FT_HT;
8461 wlc->mimo_40txbw = AUTO;
8462 wlc->ofdm_40txbw = AUTO;
8463 wlc->cck_40txbw = AUTO;
8464 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8465
8466 /* Set default values of SGI */
8467 if (BRCMS_SGI_CAP_PHY(wlc)) {
8468 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8469 BRCMS_N_SGI_40));
8470 } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8471 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8472 BRCMS_N_SGI_40));
8473 } else {
8474 brcms_c_ht_update_sgi_rx(wlc, 0);
8475 }
8476
8477 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8478
8479 if (perr)
8480 *perr = 0;
8481
8482 return wlc;
8483
8484 fail:
8485 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8486 unit, __func__, err);
8487 if (wlc)
8488 brcms_c_detach(wlc);
8489
8490 if (perr)
8491 *perr = err;
8492 return NULL;
8493}