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1/*
2 * NAND flash simulator.
3 *
4 * Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org>
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 *
8 * Note: NS means "NAND Simulator".
9 * Note: Input means input TO flash chip, output means output FROM chip.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2, or (at your option) any later
14 * version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
19 * Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
24 */
25
26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/vmalloc.h>
31#include <linux/math64.h>
32#include <linux/slab.h>
33#include <linux/errno.h>
34#include <linux/string.h>
35#include <linux/mtd/mtd.h>
36#include <linux/mtd/nand.h>
37#include <linux/mtd/nand_bch.h>
38#include <linux/mtd/partitions.h>
39#include <linux/delay.h>
40#include <linux/list.h>
41#include <linux/random.h>
42#include <linux/sched.h>
43#include <linux/fs.h>
44#include <linux/pagemap.h>
45
46/* Default simulator parameters values */
47#if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \
48 !defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \
49 !defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \
50 !defined(CONFIG_NANDSIM_FOURTH_ID_BYTE)
51#define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98
52#define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39
53#define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */
54#define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */
55#endif
56
57#ifndef CONFIG_NANDSIM_ACCESS_DELAY
58#define CONFIG_NANDSIM_ACCESS_DELAY 25
59#endif
60#ifndef CONFIG_NANDSIM_PROGRAMM_DELAY
61#define CONFIG_NANDSIM_PROGRAMM_DELAY 200
62#endif
63#ifndef CONFIG_NANDSIM_ERASE_DELAY
64#define CONFIG_NANDSIM_ERASE_DELAY 2
65#endif
66#ifndef CONFIG_NANDSIM_OUTPUT_CYCLE
67#define CONFIG_NANDSIM_OUTPUT_CYCLE 40
68#endif
69#ifndef CONFIG_NANDSIM_INPUT_CYCLE
70#define CONFIG_NANDSIM_INPUT_CYCLE 50
71#endif
72#ifndef CONFIG_NANDSIM_BUS_WIDTH
73#define CONFIG_NANDSIM_BUS_WIDTH 8
74#endif
75#ifndef CONFIG_NANDSIM_DO_DELAYS
76#define CONFIG_NANDSIM_DO_DELAYS 0
77#endif
78#ifndef CONFIG_NANDSIM_LOG
79#define CONFIG_NANDSIM_LOG 0
80#endif
81#ifndef CONFIG_NANDSIM_DBG
82#define CONFIG_NANDSIM_DBG 0
83#endif
84#ifndef CONFIG_NANDSIM_MAX_PARTS
85#define CONFIG_NANDSIM_MAX_PARTS 32
86#endif
87
88static uint first_id_byte = CONFIG_NANDSIM_FIRST_ID_BYTE;
89static uint second_id_byte = CONFIG_NANDSIM_SECOND_ID_BYTE;
90static uint third_id_byte = CONFIG_NANDSIM_THIRD_ID_BYTE;
91static uint fourth_id_byte = CONFIG_NANDSIM_FOURTH_ID_BYTE;
92static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY;
93static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY;
94static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY;
95static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE;
96static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE;
97static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH;
98static uint do_delays = CONFIG_NANDSIM_DO_DELAYS;
99static uint log = CONFIG_NANDSIM_LOG;
100static uint dbg = CONFIG_NANDSIM_DBG;
101static unsigned long parts[CONFIG_NANDSIM_MAX_PARTS];
102static unsigned int parts_num;
103static char *badblocks = NULL;
104static char *weakblocks = NULL;
105static char *weakpages = NULL;
106static unsigned int bitflips = 0;
107static char *gravepages = NULL;
108static unsigned int rptwear = 0;
109static unsigned int overridesize = 0;
110static char *cache_file = NULL;
111static unsigned int bbt;
112static unsigned int bch;
113
114module_param(first_id_byte, uint, 0400);
115module_param(second_id_byte, uint, 0400);
116module_param(third_id_byte, uint, 0400);
117module_param(fourth_id_byte, uint, 0400);
118module_param(access_delay, uint, 0400);
119module_param(programm_delay, uint, 0400);
120module_param(erase_delay, uint, 0400);
121module_param(output_cycle, uint, 0400);
122module_param(input_cycle, uint, 0400);
123module_param(bus_width, uint, 0400);
124module_param(do_delays, uint, 0400);
125module_param(log, uint, 0400);
126module_param(dbg, uint, 0400);
127module_param_array(parts, ulong, &parts_num, 0400);
128module_param(badblocks, charp, 0400);
129module_param(weakblocks, charp, 0400);
130module_param(weakpages, charp, 0400);
131module_param(bitflips, uint, 0400);
132module_param(gravepages, charp, 0400);
133module_param(rptwear, uint, 0400);
134module_param(overridesize, uint, 0400);
135module_param(cache_file, charp, 0400);
136module_param(bbt, uint, 0400);
137module_param(bch, uint, 0400);
138
139MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufacturer ID)");
140MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID)");
141MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command");
142MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command");
143MODULE_PARM_DESC(access_delay, "Initial page access delay (microseconds)");
144MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds");
145MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
146MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanoseconds)");
147MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanoseconds)");
148MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
149MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
150MODULE_PARM_DESC(log, "Perform logging if not zero");
151MODULE_PARM_DESC(dbg, "Output debug information if not zero");
152MODULE_PARM_DESC(parts, "Partition sizes (in erase blocks) separated by commas");
153/* Page and erase block positions for the following parameters are independent of any partitions */
154MODULE_PARM_DESC(badblocks, "Erase blocks that are initially marked bad, separated by commas");
155MODULE_PARM_DESC(weakblocks, "Weak erase blocks [: remaining erase cycles (defaults to 3)]"
156 " separated by commas e.g. 113:2 means eb 113"
157 " can be erased only twice before failing");
158MODULE_PARM_DESC(weakpages, "Weak pages [: maximum writes (defaults to 3)]"
159 " separated by commas e.g. 1401:2 means page 1401"
160 " can be written only twice before failing");
161MODULE_PARM_DESC(bitflips, "Maximum number of random bit flips per page (zero by default)");
162MODULE_PARM_DESC(gravepages, "Pages that lose data [: maximum reads (defaults to 3)]"
163 " separated by commas e.g. 1401:2 means page 1401"
164 " can be read only twice before failing");
165MODULE_PARM_DESC(rptwear, "Number of erases between reporting wear, if not zero");
166MODULE_PARM_DESC(overridesize, "Specifies the NAND Flash size overriding the ID bytes. "
167 "The size is specified in erase blocks and as the exponent of a power of two"
168 " e.g. 5 means a size of 32 erase blocks");
169MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
170MODULE_PARM_DESC(bbt, "0 OOB, 1 BBT with marker in OOB, 2 BBT with marker in data area");
171MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should "
172 "be correctable in 512-byte blocks");
173
174/* The largest possible page size */
175#define NS_LARGEST_PAGE_SIZE 4096
176
177/* The prefix for simulator output */
178#define NS_OUTPUT_PREFIX "[nandsim]"
179
180/* Simulator's output macros (logging, debugging, warning, error) */
181#define NS_LOG(args...) \
182 do { if (log) printk(KERN_DEBUG NS_OUTPUT_PREFIX " log: " args); } while(0)
183#define NS_DBG(args...) \
184 do { if (dbg) printk(KERN_DEBUG NS_OUTPUT_PREFIX " debug: " args); } while(0)
185#define NS_WARN(args...) \
186 do { printk(KERN_WARNING NS_OUTPUT_PREFIX " warning: " args); } while(0)
187#define NS_ERR(args...) \
188 do { printk(KERN_ERR NS_OUTPUT_PREFIX " error: " args); } while(0)
189#define NS_INFO(args...) \
190 do { printk(KERN_INFO NS_OUTPUT_PREFIX " " args); } while(0)
191
192/* Busy-wait delay macros (microseconds, milliseconds) */
193#define NS_UDELAY(us) \
194 do { if (do_delays) udelay(us); } while(0)
195#define NS_MDELAY(us) \
196 do { if (do_delays) mdelay(us); } while(0)
197
198/* Is the nandsim structure initialized ? */
199#define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0)
200
201/* Good operation completion status */
202#define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
203
204/* Operation failed completion status */
205#define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns))
206
207/* Calculate the page offset in flash RAM image by (row, column) address */
208#define NS_RAW_OFFSET(ns) \
209 (((ns)->regs.row << (ns)->geom.pgshift) + ((ns)->regs.row * (ns)->geom.oobsz) + (ns)->regs.column)
210
211/* Calculate the OOB offset in flash RAM image by (row, column) address */
212#define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz)
213
214/* After a command is input, the simulator goes to one of the following states */
215#define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */
216#define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */
217#define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */
218#define STATE_CMD_PAGEPROG 0x00000004 /* start page program */
219#define STATE_CMD_READOOB 0x00000005 /* read OOB area */
220#define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */
221#define STATE_CMD_STATUS 0x00000007 /* read status */
222#define STATE_CMD_STATUS_M 0x00000008 /* read multi-plane status (isn't implemented) */
223#define STATE_CMD_SEQIN 0x00000009 /* sequential data input */
224#define STATE_CMD_READID 0x0000000A /* read ID */
225#define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */
226#define STATE_CMD_RESET 0x0000000C /* reset */
227#define STATE_CMD_RNDOUT 0x0000000D /* random output command */
228#define STATE_CMD_RNDOUTSTART 0x0000000E /* random output start command */
229#define STATE_CMD_MASK 0x0000000F /* command states mask */
230
231/* After an address is input, the simulator goes to one of these states */
232#define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */
233#define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */
234#define STATE_ADDR_COLUMN 0x00000030 /* column address was accepted */
235#define STATE_ADDR_ZERO 0x00000040 /* one byte zero address was accepted */
236#define STATE_ADDR_MASK 0x00000070 /* address states mask */
237
238/* During data input/output the simulator is in these states */
239#define STATE_DATAIN 0x00000100 /* waiting for data input */
240#define STATE_DATAIN_MASK 0x00000100 /* data input states mask */
241
242#define STATE_DATAOUT 0x00001000 /* waiting for page data output */
243#define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */
244#define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */
245#define STATE_DATAOUT_STATUS_M 0x00004000 /* waiting for multi-plane status output */
246#define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */
247
248/* Previous operation is done, ready to accept new requests */
249#define STATE_READY 0x00000000
250
251/* This state is used to mark that the next state isn't known yet */
252#define STATE_UNKNOWN 0x10000000
253
254/* Simulator's actions bit masks */
255#define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */
256#define ACTION_PRGPAGE 0x00200000 /* program the internal buffer to flash */
257#define ACTION_SECERASE 0x00300000 /* erase sector */
258#define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */
259#define ACTION_HALFOFF 0x00500000 /* add to address half of page */
260#define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */
261#define ACTION_MASK 0x00700000 /* action mask */
262
263#define NS_OPER_NUM 13 /* Number of operations supported by the simulator */
264#define NS_OPER_STATES 6 /* Maximum number of states in operation */
265
266#define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */
267#define OPT_PAGE256 0x00000001 /* 256-byte page chips */
268#define OPT_PAGE512 0x00000002 /* 512-byte page chips */
269#define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */
270#define OPT_SMARTMEDIA 0x00000010 /* SmartMedia technology chips */
271#define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
272#define OPT_PAGE4096 0x00000080 /* 4096-byte page chips */
273#define OPT_LARGEPAGE (OPT_PAGE2048 | OPT_PAGE4096) /* 2048 & 4096-byte page chips */
274#define OPT_SMALLPAGE (OPT_PAGE256 | OPT_PAGE512) /* 256 and 512-byte page chips */
275
276/* Remove action bits from state */
277#define NS_STATE(x) ((x) & ~ACTION_MASK)
278
279/*
280 * Maximum previous states which need to be saved. Currently saving is
281 * only needed for page program operation with preceded read command
282 * (which is only valid for 512-byte pages).
283 */
284#define NS_MAX_PREVSTATES 1
285
286/* Maximum page cache pages needed to read or write a NAND page to the cache_file */
287#define NS_MAX_HELD_PAGES 16
288
289/*
290 * A union to represent flash memory contents and flash buffer.
291 */
292union ns_mem {
293 u_char *byte; /* for byte access */
294 uint16_t *word; /* for 16-bit word access */
295};
296
297/*
298 * The structure which describes all the internal simulator data.
299 */
300struct nandsim {
301 struct mtd_partition partitions[CONFIG_NANDSIM_MAX_PARTS];
302 unsigned int nbparts;
303
304 uint busw; /* flash chip bus width (8 or 16) */
305 u_char ids[4]; /* chip's ID bytes */
306 uint32_t options; /* chip's characteristic bits */
307 uint32_t state; /* current chip state */
308 uint32_t nxstate; /* next expected state */
309
310 uint32_t *op; /* current operation, NULL operations isn't known yet */
311 uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */
312 uint16_t npstates; /* number of previous states saved */
313 uint16_t stateidx; /* current state index */
314
315 /* The simulated NAND flash pages array */
316 union ns_mem *pages;
317
318 /* Slab allocator for nand pages */
319 struct kmem_cache *nand_pages_slab;
320
321 /* Internal buffer of page + OOB size bytes */
322 union ns_mem buf;
323
324 /* NAND flash "geometry" */
325 struct {
326 uint64_t totsz; /* total flash size, bytes */
327 uint32_t secsz; /* flash sector (erase block) size, bytes */
328 uint pgsz; /* NAND flash page size, bytes */
329 uint oobsz; /* page OOB area size, bytes */
330 uint64_t totszoob; /* total flash size including OOB, bytes */
331 uint pgszoob; /* page size including OOB , bytes*/
332 uint secszoob; /* sector size including OOB, bytes */
333 uint pgnum; /* total number of pages */
334 uint pgsec; /* number of pages per sector */
335 uint secshift; /* bits number in sector size */
336 uint pgshift; /* bits number in page size */
337 uint oobshift; /* bits number in OOB size */
338 uint pgaddrbytes; /* bytes per page address */
339 uint secaddrbytes; /* bytes per sector address */
340 uint idbytes; /* the number ID bytes that this chip outputs */
341 } geom;
342
343 /* NAND flash internal registers */
344 struct {
345 unsigned command; /* the command register */
346 u_char status; /* the status register */
347 uint row; /* the page number */
348 uint column; /* the offset within page */
349 uint count; /* internal counter */
350 uint num; /* number of bytes which must be processed */
351 uint off; /* fixed page offset */
352 } regs;
353
354 /* NAND flash lines state */
355 struct {
356 int ce; /* chip Enable */
357 int cle; /* command Latch Enable */
358 int ale; /* address Latch Enable */
359 int wp; /* write Protect */
360 } lines;
361
362 /* Fields needed when using a cache file */
363 struct file *cfile; /* Open file */
364 unsigned char *pages_written; /* Which pages have been written */
365 void *file_buf;
366 struct page *held_pages[NS_MAX_HELD_PAGES];
367 int held_cnt;
368};
369
370/*
371 * Operations array. To perform any operation the simulator must pass
372 * through the correspondent states chain.
373 */
374static struct nandsim_operations {
375 uint32_t reqopts; /* options which are required to perform the operation */
376 uint32_t states[NS_OPER_STATES]; /* operation's states */
377} ops[NS_OPER_NUM] = {
378 /* Read page + OOB from the beginning */
379 {OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY,
380 STATE_DATAOUT, STATE_READY}},
381 /* Read page + OOB from the second half */
382 {OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY,
383 STATE_DATAOUT, STATE_READY}},
384 /* Read OOB */
385 {OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY,
386 STATE_DATAOUT, STATE_READY}},
387 /* Program page starting from the beginning */
388 {OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN,
389 STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
390 /* Program page starting from the beginning */
391 {OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE,
392 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
393 /* Program page starting from the second half */
394 {OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE,
395 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
396 /* Program OOB */
397 {OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE,
398 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
399 /* Erase sector */
400 {OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}},
401 /* Read status */
402 {OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}},
403 /* Read multi-plane status */
404 {OPT_SMARTMEDIA, {STATE_CMD_STATUS_M, STATE_DATAOUT_STATUS_M, STATE_READY}},
405 /* Read ID */
406 {OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}},
407 /* Large page devices read page */
408 {OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY,
409 STATE_DATAOUT, STATE_READY}},
410 /* Large page devices random page read */
411 {OPT_LARGEPAGE, {STATE_CMD_RNDOUT, STATE_ADDR_COLUMN, STATE_CMD_RNDOUTSTART | ACTION_CPY,
412 STATE_DATAOUT, STATE_READY}},
413};
414
415struct weak_block {
416 struct list_head list;
417 unsigned int erase_block_no;
418 unsigned int max_erases;
419 unsigned int erases_done;
420};
421
422static LIST_HEAD(weak_blocks);
423
424struct weak_page {
425 struct list_head list;
426 unsigned int page_no;
427 unsigned int max_writes;
428 unsigned int writes_done;
429};
430
431static LIST_HEAD(weak_pages);
432
433struct grave_page {
434 struct list_head list;
435 unsigned int page_no;
436 unsigned int max_reads;
437 unsigned int reads_done;
438};
439
440static LIST_HEAD(grave_pages);
441
442static unsigned long *erase_block_wear = NULL;
443static unsigned int wear_eb_count = 0;
444static unsigned long total_wear = 0;
445static unsigned int rptwear_cnt = 0;
446
447/* MTD structure for NAND controller */
448static struct mtd_info *nsmtd;
449
450static u_char ns_verify_buf[NS_LARGEST_PAGE_SIZE];
451
452/*
453 * Allocate array of page pointers, create slab allocation for an array
454 * and initialize the array by NULL pointers.
455 *
456 * RETURNS: 0 if success, -ENOMEM if memory alloc fails.
457 */
458static int alloc_device(struct nandsim *ns)
459{
460 struct file *cfile;
461 int i, err;
462
463 if (cache_file) {
464 cfile = filp_open(cache_file, O_CREAT | O_RDWR | O_LARGEFILE, 0600);
465 if (IS_ERR(cfile))
466 return PTR_ERR(cfile);
467 if (!cfile->f_op || (!cfile->f_op->read && !cfile->f_op->aio_read)) {
468 NS_ERR("alloc_device: cache file not readable\n");
469 err = -EINVAL;
470 goto err_close;
471 }
472 if (!cfile->f_op->write && !cfile->f_op->aio_write) {
473 NS_ERR("alloc_device: cache file not writeable\n");
474 err = -EINVAL;
475 goto err_close;
476 }
477 ns->pages_written = vzalloc(ns->geom.pgnum);
478 if (!ns->pages_written) {
479 NS_ERR("alloc_device: unable to allocate pages written array\n");
480 err = -ENOMEM;
481 goto err_close;
482 }
483 ns->file_buf = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
484 if (!ns->file_buf) {
485 NS_ERR("alloc_device: unable to allocate file buf\n");
486 err = -ENOMEM;
487 goto err_free;
488 }
489 ns->cfile = cfile;
490 return 0;
491 }
492
493 ns->pages = vmalloc(ns->geom.pgnum * sizeof(union ns_mem));
494 if (!ns->pages) {
495 NS_ERR("alloc_device: unable to allocate page array\n");
496 return -ENOMEM;
497 }
498 for (i = 0; i < ns->geom.pgnum; i++) {
499 ns->pages[i].byte = NULL;
500 }
501 ns->nand_pages_slab = kmem_cache_create("nandsim",
502 ns->geom.pgszoob, 0, 0, NULL);
503 if (!ns->nand_pages_slab) {
504 NS_ERR("cache_create: unable to create kmem_cache\n");
505 return -ENOMEM;
506 }
507
508 return 0;
509
510err_free:
511 vfree(ns->pages_written);
512err_close:
513 filp_close(cfile, NULL);
514 return err;
515}
516
517/*
518 * Free any allocated pages, and free the array of page pointers.
519 */
520static void free_device(struct nandsim *ns)
521{
522 int i;
523
524 if (ns->cfile) {
525 kfree(ns->file_buf);
526 vfree(ns->pages_written);
527 filp_close(ns->cfile, NULL);
528 return;
529 }
530
531 if (ns->pages) {
532 for (i = 0; i < ns->geom.pgnum; i++) {
533 if (ns->pages[i].byte)
534 kmem_cache_free(ns->nand_pages_slab,
535 ns->pages[i].byte);
536 }
537 kmem_cache_destroy(ns->nand_pages_slab);
538 vfree(ns->pages);
539 }
540}
541
542static char *get_partition_name(int i)
543{
544 char buf[64];
545 sprintf(buf, "NAND simulator partition %d", i);
546 return kstrdup(buf, GFP_KERNEL);
547}
548
549/*
550 * Initialize the nandsim structure.
551 *
552 * RETURNS: 0 if success, -ERRNO if failure.
553 */
554static int init_nandsim(struct mtd_info *mtd)
555{
556 struct nand_chip *chip = mtd->priv;
557 struct nandsim *ns = chip->priv;
558 int i, ret = 0;
559 uint64_t remains;
560 uint64_t next_offset;
561
562 if (NS_IS_INITIALIZED(ns)) {
563 NS_ERR("init_nandsim: nandsim is already initialized\n");
564 return -EIO;
565 }
566
567 /* Force mtd to not do delays */
568 chip->chip_delay = 0;
569
570 /* Initialize the NAND flash parameters */
571 ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
572 ns->geom.totsz = mtd->size;
573 ns->geom.pgsz = mtd->writesize;
574 ns->geom.oobsz = mtd->oobsize;
575 ns->geom.secsz = mtd->erasesize;
576 ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz;
577 ns->geom.pgnum = div_u64(ns->geom.totsz, ns->geom.pgsz);
578 ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz;
579 ns->geom.secshift = ffs(ns->geom.secsz) - 1;
580 ns->geom.pgshift = chip->page_shift;
581 ns->geom.oobshift = ffs(ns->geom.oobsz) - 1;
582 ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz;
583 ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec;
584 ns->options = 0;
585
586 if (ns->geom.pgsz == 256) {
587 ns->options |= OPT_PAGE256;
588 }
589 else if (ns->geom.pgsz == 512) {
590 ns->options |= OPT_PAGE512;
591 if (ns->busw == 8)
592 ns->options |= OPT_PAGE512_8BIT;
593 } else if (ns->geom.pgsz == 2048) {
594 ns->options |= OPT_PAGE2048;
595 } else if (ns->geom.pgsz == 4096) {
596 ns->options |= OPT_PAGE4096;
597 } else {
598 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz);
599 return -EIO;
600 }
601
602 if (ns->options & OPT_SMALLPAGE) {
603 if (ns->geom.totsz <= (32 << 20)) {
604 ns->geom.pgaddrbytes = 3;
605 ns->geom.secaddrbytes = 2;
606 } else {
607 ns->geom.pgaddrbytes = 4;
608 ns->geom.secaddrbytes = 3;
609 }
610 } else {
611 if (ns->geom.totsz <= (128 << 20)) {
612 ns->geom.pgaddrbytes = 4;
613 ns->geom.secaddrbytes = 2;
614 } else {
615 ns->geom.pgaddrbytes = 5;
616 ns->geom.secaddrbytes = 3;
617 }
618 }
619
620 /* Fill the partition_info structure */
621 if (parts_num > ARRAY_SIZE(ns->partitions)) {
622 NS_ERR("too many partitions.\n");
623 ret = -EINVAL;
624 goto error;
625 }
626 remains = ns->geom.totsz;
627 next_offset = 0;
628 for (i = 0; i < parts_num; ++i) {
629 uint64_t part_sz = (uint64_t)parts[i] * ns->geom.secsz;
630
631 if (!part_sz || part_sz > remains) {
632 NS_ERR("bad partition size.\n");
633 ret = -EINVAL;
634 goto error;
635 }
636 ns->partitions[i].name = get_partition_name(i);
637 ns->partitions[i].offset = next_offset;
638 ns->partitions[i].size = part_sz;
639 next_offset += ns->partitions[i].size;
640 remains -= ns->partitions[i].size;
641 }
642 ns->nbparts = parts_num;
643 if (remains) {
644 if (parts_num + 1 > ARRAY_SIZE(ns->partitions)) {
645 NS_ERR("too many partitions.\n");
646 ret = -EINVAL;
647 goto error;
648 }
649 ns->partitions[i].name = get_partition_name(i);
650 ns->partitions[i].offset = next_offset;
651 ns->partitions[i].size = remains;
652 ns->nbparts += 1;
653 }
654
655 /* Detect how many ID bytes the NAND chip outputs */
656 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
657 if (second_id_byte != nand_flash_ids[i].id)
658 continue;
659 }
660
661 if (ns->busw == 16)
662 NS_WARN("16-bit flashes support wasn't tested\n");
663
664 printk("flash size: %llu MiB\n",
665 (unsigned long long)ns->geom.totsz >> 20);
666 printk("page size: %u bytes\n", ns->geom.pgsz);
667 printk("OOB area size: %u bytes\n", ns->geom.oobsz);
668 printk("sector size: %u KiB\n", ns->geom.secsz >> 10);
669 printk("pages number: %u\n", ns->geom.pgnum);
670 printk("pages per sector: %u\n", ns->geom.pgsec);
671 printk("bus width: %u\n", ns->busw);
672 printk("bits in sector size: %u\n", ns->geom.secshift);
673 printk("bits in page size: %u\n", ns->geom.pgshift);
674 printk("bits in OOB size: %u\n", ns->geom.oobshift);
675 printk("flash size with OOB: %llu KiB\n",
676 (unsigned long long)ns->geom.totszoob >> 10);
677 printk("page address bytes: %u\n", ns->geom.pgaddrbytes);
678 printk("sector address bytes: %u\n", ns->geom.secaddrbytes);
679 printk("options: %#x\n", ns->options);
680
681 if ((ret = alloc_device(ns)) != 0)
682 goto error;
683
684 /* Allocate / initialize the internal buffer */
685 ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
686 if (!ns->buf.byte) {
687 NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n",
688 ns->geom.pgszoob);
689 ret = -ENOMEM;
690 goto error;
691 }
692 memset(ns->buf.byte, 0xFF, ns->geom.pgszoob);
693
694 return 0;
695
696error:
697 free_device(ns);
698
699 return ret;
700}
701
702/*
703 * Free the nandsim structure.
704 */
705static void free_nandsim(struct nandsim *ns)
706{
707 kfree(ns->buf.byte);
708 free_device(ns);
709
710 return;
711}
712
713static int parse_badblocks(struct nandsim *ns, struct mtd_info *mtd)
714{
715 char *w;
716 int zero_ok;
717 unsigned int erase_block_no;
718 loff_t offset;
719
720 if (!badblocks)
721 return 0;
722 w = badblocks;
723 do {
724 zero_ok = (*w == '0' ? 1 : 0);
725 erase_block_no = simple_strtoul(w, &w, 0);
726 if (!zero_ok && !erase_block_no) {
727 NS_ERR("invalid badblocks.\n");
728 return -EINVAL;
729 }
730 offset = erase_block_no * ns->geom.secsz;
731 if (mtd_block_markbad(mtd, offset)) {
732 NS_ERR("invalid badblocks.\n");
733 return -EINVAL;
734 }
735 if (*w == ',')
736 w += 1;
737 } while (*w);
738 return 0;
739}
740
741static int parse_weakblocks(void)
742{
743 char *w;
744 int zero_ok;
745 unsigned int erase_block_no;
746 unsigned int max_erases;
747 struct weak_block *wb;
748
749 if (!weakblocks)
750 return 0;
751 w = weakblocks;
752 do {
753 zero_ok = (*w == '0' ? 1 : 0);
754 erase_block_no = simple_strtoul(w, &w, 0);
755 if (!zero_ok && !erase_block_no) {
756 NS_ERR("invalid weakblocks.\n");
757 return -EINVAL;
758 }
759 max_erases = 3;
760 if (*w == ':') {
761 w += 1;
762 max_erases = simple_strtoul(w, &w, 0);
763 }
764 if (*w == ',')
765 w += 1;
766 wb = kzalloc(sizeof(*wb), GFP_KERNEL);
767 if (!wb) {
768 NS_ERR("unable to allocate memory.\n");
769 return -ENOMEM;
770 }
771 wb->erase_block_no = erase_block_no;
772 wb->max_erases = max_erases;
773 list_add(&wb->list, &weak_blocks);
774 } while (*w);
775 return 0;
776}
777
778static int erase_error(unsigned int erase_block_no)
779{
780 struct weak_block *wb;
781
782 list_for_each_entry(wb, &weak_blocks, list)
783 if (wb->erase_block_no == erase_block_no) {
784 if (wb->erases_done >= wb->max_erases)
785 return 1;
786 wb->erases_done += 1;
787 return 0;
788 }
789 return 0;
790}
791
792static int parse_weakpages(void)
793{
794 char *w;
795 int zero_ok;
796 unsigned int page_no;
797 unsigned int max_writes;
798 struct weak_page *wp;
799
800 if (!weakpages)
801 return 0;
802 w = weakpages;
803 do {
804 zero_ok = (*w == '0' ? 1 : 0);
805 page_no = simple_strtoul(w, &w, 0);
806 if (!zero_ok && !page_no) {
807 NS_ERR("invalid weakpagess.\n");
808 return -EINVAL;
809 }
810 max_writes = 3;
811 if (*w == ':') {
812 w += 1;
813 max_writes = simple_strtoul(w, &w, 0);
814 }
815 if (*w == ',')
816 w += 1;
817 wp = kzalloc(sizeof(*wp), GFP_KERNEL);
818 if (!wp) {
819 NS_ERR("unable to allocate memory.\n");
820 return -ENOMEM;
821 }
822 wp->page_no = page_no;
823 wp->max_writes = max_writes;
824 list_add(&wp->list, &weak_pages);
825 } while (*w);
826 return 0;
827}
828
829static int write_error(unsigned int page_no)
830{
831 struct weak_page *wp;
832
833 list_for_each_entry(wp, &weak_pages, list)
834 if (wp->page_no == page_no) {
835 if (wp->writes_done >= wp->max_writes)
836 return 1;
837 wp->writes_done += 1;
838 return 0;
839 }
840 return 0;
841}
842
843static int parse_gravepages(void)
844{
845 char *g;
846 int zero_ok;
847 unsigned int page_no;
848 unsigned int max_reads;
849 struct grave_page *gp;
850
851 if (!gravepages)
852 return 0;
853 g = gravepages;
854 do {
855 zero_ok = (*g == '0' ? 1 : 0);
856 page_no = simple_strtoul(g, &g, 0);
857 if (!zero_ok && !page_no) {
858 NS_ERR("invalid gravepagess.\n");
859 return -EINVAL;
860 }
861 max_reads = 3;
862 if (*g == ':') {
863 g += 1;
864 max_reads = simple_strtoul(g, &g, 0);
865 }
866 if (*g == ',')
867 g += 1;
868 gp = kzalloc(sizeof(*gp), GFP_KERNEL);
869 if (!gp) {
870 NS_ERR("unable to allocate memory.\n");
871 return -ENOMEM;
872 }
873 gp->page_no = page_no;
874 gp->max_reads = max_reads;
875 list_add(&gp->list, &grave_pages);
876 } while (*g);
877 return 0;
878}
879
880static int read_error(unsigned int page_no)
881{
882 struct grave_page *gp;
883
884 list_for_each_entry(gp, &grave_pages, list)
885 if (gp->page_no == page_no) {
886 if (gp->reads_done >= gp->max_reads)
887 return 1;
888 gp->reads_done += 1;
889 return 0;
890 }
891 return 0;
892}
893
894static void free_lists(void)
895{
896 struct list_head *pos, *n;
897 list_for_each_safe(pos, n, &weak_blocks) {
898 list_del(pos);
899 kfree(list_entry(pos, struct weak_block, list));
900 }
901 list_for_each_safe(pos, n, &weak_pages) {
902 list_del(pos);
903 kfree(list_entry(pos, struct weak_page, list));
904 }
905 list_for_each_safe(pos, n, &grave_pages) {
906 list_del(pos);
907 kfree(list_entry(pos, struct grave_page, list));
908 }
909 kfree(erase_block_wear);
910}
911
912static int setup_wear_reporting(struct mtd_info *mtd)
913{
914 size_t mem;
915
916 if (!rptwear)
917 return 0;
918 wear_eb_count = div_u64(mtd->size, mtd->erasesize);
919 mem = wear_eb_count * sizeof(unsigned long);
920 if (mem / sizeof(unsigned long) != wear_eb_count) {
921 NS_ERR("Too many erase blocks for wear reporting\n");
922 return -ENOMEM;
923 }
924 erase_block_wear = kzalloc(mem, GFP_KERNEL);
925 if (!erase_block_wear) {
926 NS_ERR("Too many erase blocks for wear reporting\n");
927 return -ENOMEM;
928 }
929 return 0;
930}
931
932static void update_wear(unsigned int erase_block_no)
933{
934 unsigned long wmin = -1, wmax = 0, avg;
935 unsigned long deciles[10], decile_max[10], tot = 0;
936 unsigned int i;
937
938 if (!erase_block_wear)
939 return;
940 total_wear += 1;
941 if (total_wear == 0)
942 NS_ERR("Erase counter total overflow\n");
943 erase_block_wear[erase_block_no] += 1;
944 if (erase_block_wear[erase_block_no] == 0)
945 NS_ERR("Erase counter overflow for erase block %u\n", erase_block_no);
946 rptwear_cnt += 1;
947 if (rptwear_cnt < rptwear)
948 return;
949 rptwear_cnt = 0;
950 /* Calc wear stats */
951 for (i = 0; i < wear_eb_count; ++i) {
952 unsigned long wear = erase_block_wear[i];
953 if (wear < wmin)
954 wmin = wear;
955 if (wear > wmax)
956 wmax = wear;
957 tot += wear;
958 }
959 for (i = 0; i < 9; ++i) {
960 deciles[i] = 0;
961 decile_max[i] = (wmax * (i + 1) + 5) / 10;
962 }
963 deciles[9] = 0;
964 decile_max[9] = wmax;
965 for (i = 0; i < wear_eb_count; ++i) {
966 int d;
967 unsigned long wear = erase_block_wear[i];
968 for (d = 0; d < 10; ++d)
969 if (wear <= decile_max[d]) {
970 deciles[d] += 1;
971 break;
972 }
973 }
974 avg = tot / wear_eb_count;
975 /* Output wear report */
976 NS_INFO("*** Wear Report ***\n");
977 NS_INFO("Total numbers of erases: %lu\n", tot);
978 NS_INFO("Number of erase blocks: %u\n", wear_eb_count);
979 NS_INFO("Average number of erases: %lu\n", avg);
980 NS_INFO("Maximum number of erases: %lu\n", wmax);
981 NS_INFO("Minimum number of erases: %lu\n", wmin);
982 for (i = 0; i < 10; ++i) {
983 unsigned long from = (i ? decile_max[i - 1] + 1 : 0);
984 if (from > decile_max[i])
985 continue;
986 NS_INFO("Number of ebs with erase counts from %lu to %lu : %lu\n",
987 from,
988 decile_max[i],
989 deciles[i]);
990 }
991 NS_INFO("*** End of Wear Report ***\n");
992}
993
994/*
995 * Returns the string representation of 'state' state.
996 */
997static char *get_state_name(uint32_t state)
998{
999 switch (NS_STATE(state)) {
1000 case STATE_CMD_READ0:
1001 return "STATE_CMD_READ0";
1002 case STATE_CMD_READ1:
1003 return "STATE_CMD_READ1";
1004 case STATE_CMD_PAGEPROG:
1005 return "STATE_CMD_PAGEPROG";
1006 case STATE_CMD_READOOB:
1007 return "STATE_CMD_READOOB";
1008 case STATE_CMD_READSTART:
1009 return "STATE_CMD_READSTART";
1010 case STATE_CMD_ERASE1:
1011 return "STATE_CMD_ERASE1";
1012 case STATE_CMD_STATUS:
1013 return "STATE_CMD_STATUS";
1014 case STATE_CMD_STATUS_M:
1015 return "STATE_CMD_STATUS_M";
1016 case STATE_CMD_SEQIN:
1017 return "STATE_CMD_SEQIN";
1018 case STATE_CMD_READID:
1019 return "STATE_CMD_READID";
1020 case STATE_CMD_ERASE2:
1021 return "STATE_CMD_ERASE2";
1022 case STATE_CMD_RESET:
1023 return "STATE_CMD_RESET";
1024 case STATE_CMD_RNDOUT:
1025 return "STATE_CMD_RNDOUT";
1026 case STATE_CMD_RNDOUTSTART:
1027 return "STATE_CMD_RNDOUTSTART";
1028 case STATE_ADDR_PAGE:
1029 return "STATE_ADDR_PAGE";
1030 case STATE_ADDR_SEC:
1031 return "STATE_ADDR_SEC";
1032 case STATE_ADDR_ZERO:
1033 return "STATE_ADDR_ZERO";
1034 case STATE_ADDR_COLUMN:
1035 return "STATE_ADDR_COLUMN";
1036 case STATE_DATAIN:
1037 return "STATE_DATAIN";
1038 case STATE_DATAOUT:
1039 return "STATE_DATAOUT";
1040 case STATE_DATAOUT_ID:
1041 return "STATE_DATAOUT_ID";
1042 case STATE_DATAOUT_STATUS:
1043 return "STATE_DATAOUT_STATUS";
1044 case STATE_DATAOUT_STATUS_M:
1045 return "STATE_DATAOUT_STATUS_M";
1046 case STATE_READY:
1047 return "STATE_READY";
1048 case STATE_UNKNOWN:
1049 return "STATE_UNKNOWN";
1050 }
1051
1052 NS_ERR("get_state_name: unknown state, BUG\n");
1053 return NULL;
1054}
1055
1056/*
1057 * Check if command is valid.
1058 *
1059 * RETURNS: 1 if wrong command, 0 if right.
1060 */
1061static int check_command(int cmd)
1062{
1063 switch (cmd) {
1064
1065 case NAND_CMD_READ0:
1066 case NAND_CMD_READ1:
1067 case NAND_CMD_READSTART:
1068 case NAND_CMD_PAGEPROG:
1069 case NAND_CMD_READOOB:
1070 case NAND_CMD_ERASE1:
1071 case NAND_CMD_STATUS:
1072 case NAND_CMD_SEQIN:
1073 case NAND_CMD_READID:
1074 case NAND_CMD_ERASE2:
1075 case NAND_CMD_RESET:
1076 case NAND_CMD_RNDOUT:
1077 case NAND_CMD_RNDOUTSTART:
1078 return 0;
1079
1080 case NAND_CMD_STATUS_MULTI:
1081 default:
1082 return 1;
1083 }
1084}
1085
1086/*
1087 * Returns state after command is accepted by command number.
1088 */
1089static uint32_t get_state_by_command(unsigned command)
1090{
1091 switch (command) {
1092 case NAND_CMD_READ0:
1093 return STATE_CMD_READ0;
1094 case NAND_CMD_READ1:
1095 return STATE_CMD_READ1;
1096 case NAND_CMD_PAGEPROG:
1097 return STATE_CMD_PAGEPROG;
1098 case NAND_CMD_READSTART:
1099 return STATE_CMD_READSTART;
1100 case NAND_CMD_READOOB:
1101 return STATE_CMD_READOOB;
1102 case NAND_CMD_ERASE1:
1103 return STATE_CMD_ERASE1;
1104 case NAND_CMD_STATUS:
1105 return STATE_CMD_STATUS;
1106 case NAND_CMD_STATUS_MULTI:
1107 return STATE_CMD_STATUS_M;
1108 case NAND_CMD_SEQIN:
1109 return STATE_CMD_SEQIN;
1110 case NAND_CMD_READID:
1111 return STATE_CMD_READID;
1112 case NAND_CMD_ERASE2:
1113 return STATE_CMD_ERASE2;
1114 case NAND_CMD_RESET:
1115 return STATE_CMD_RESET;
1116 case NAND_CMD_RNDOUT:
1117 return STATE_CMD_RNDOUT;
1118 case NAND_CMD_RNDOUTSTART:
1119 return STATE_CMD_RNDOUTSTART;
1120 }
1121
1122 NS_ERR("get_state_by_command: unknown command, BUG\n");
1123 return 0;
1124}
1125
1126/*
1127 * Move an address byte to the correspondent internal register.
1128 */
1129static inline void accept_addr_byte(struct nandsim *ns, u_char bt)
1130{
1131 uint byte = (uint)bt;
1132
1133 if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes))
1134 ns->regs.column |= (byte << 8 * ns->regs.count);
1135 else {
1136 ns->regs.row |= (byte << 8 * (ns->regs.count -
1137 ns->geom.pgaddrbytes +
1138 ns->geom.secaddrbytes));
1139 }
1140
1141 return;
1142}
1143
1144/*
1145 * Switch to STATE_READY state.
1146 */
1147static inline void switch_to_ready_state(struct nandsim *ns, u_char status)
1148{
1149 NS_DBG("switch_to_ready_state: switch to %s state\n", get_state_name(STATE_READY));
1150
1151 ns->state = STATE_READY;
1152 ns->nxstate = STATE_UNKNOWN;
1153 ns->op = NULL;
1154 ns->npstates = 0;
1155 ns->stateidx = 0;
1156 ns->regs.num = 0;
1157 ns->regs.count = 0;
1158 ns->regs.off = 0;
1159 ns->regs.row = 0;
1160 ns->regs.column = 0;
1161 ns->regs.status = status;
1162}
1163
1164/*
1165 * If the operation isn't known yet, try to find it in the global array
1166 * of supported operations.
1167 *
1168 * Operation can be unknown because of the following.
1169 * 1. New command was accepted and this is the first call to find the
1170 * correspondent states chain. In this case ns->npstates = 0;
1171 * 2. There are several operations which begin with the same command(s)
1172 * (for example program from the second half and read from the
1173 * second half operations both begin with the READ1 command). In this
1174 * case the ns->pstates[] array contains previous states.
1175 *
1176 * Thus, the function tries to find operation containing the following
1177 * states (if the 'flag' parameter is 0):
1178 * ns->pstates[0], ... ns->pstates[ns->npstates], ns->state
1179 *
1180 * If (one and only one) matching operation is found, it is accepted (
1181 * ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is
1182 * zeroed).
1183 *
1184 * If there are several matches, the current state is pushed to the
1185 * ns->pstates.
1186 *
1187 * The operation can be unknown only while commands are input to the chip.
1188 * As soon as address command is accepted, the operation must be known.
1189 * In such situation the function is called with 'flag' != 0, and the
1190 * operation is searched using the following pattern:
1191 * ns->pstates[0], ... ns->pstates[ns->npstates], <address input>
1192 *
1193 * It is supposed that this pattern must either match one operation or
1194 * none. There can't be ambiguity in that case.
1195 *
1196 * If no matches found, the function does the following:
1197 * 1. if there are saved states present, try to ignore them and search
1198 * again only using the last command. If nothing was found, switch
1199 * to the STATE_READY state.
1200 * 2. if there are no saved states, switch to the STATE_READY state.
1201 *
1202 * RETURNS: -2 - no matched operations found.
1203 * -1 - several matches.
1204 * 0 - operation is found.
1205 */
1206static int find_operation(struct nandsim *ns, uint32_t flag)
1207{
1208 int opsfound = 0;
1209 int i, j, idx = 0;
1210
1211 for (i = 0; i < NS_OPER_NUM; i++) {
1212
1213 int found = 1;
1214
1215 if (!(ns->options & ops[i].reqopts))
1216 /* Ignore operations we can't perform */
1217 continue;
1218
1219 if (flag) {
1220 if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK))
1221 continue;
1222 } else {
1223 if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates]))
1224 continue;
1225 }
1226
1227 for (j = 0; j < ns->npstates; j++)
1228 if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j])
1229 && (ns->options & ops[idx].reqopts)) {
1230 found = 0;
1231 break;
1232 }
1233
1234 if (found) {
1235 idx = i;
1236 opsfound += 1;
1237 }
1238 }
1239
1240 if (opsfound == 1) {
1241 /* Exact match */
1242 ns->op = &ops[idx].states[0];
1243 if (flag) {
1244 /*
1245 * In this case the find_operation function was
1246 * called when address has just began input. But it isn't
1247 * yet fully input and the current state must
1248 * not be one of STATE_ADDR_*, but the STATE_ADDR_*
1249 * state must be the next state (ns->nxstate).
1250 */
1251 ns->stateidx = ns->npstates - 1;
1252 } else {
1253 ns->stateidx = ns->npstates;
1254 }
1255 ns->npstates = 0;
1256 ns->state = ns->op[ns->stateidx];
1257 ns->nxstate = ns->op[ns->stateidx + 1];
1258 NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n",
1259 idx, get_state_name(ns->state), get_state_name(ns->nxstate));
1260 return 0;
1261 }
1262
1263 if (opsfound == 0) {
1264 /* Nothing was found. Try to ignore previous commands (if any) and search again */
1265 if (ns->npstates != 0) {
1266 NS_DBG("find_operation: no operation found, try again with state %s\n",
1267 get_state_name(ns->state));
1268 ns->npstates = 0;
1269 return find_operation(ns, 0);
1270
1271 }
1272 NS_DBG("find_operation: no operations found\n");
1273 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1274 return -2;
1275 }
1276
1277 if (flag) {
1278 /* This shouldn't happen */
1279 NS_DBG("find_operation: BUG, operation must be known if address is input\n");
1280 return -2;
1281 }
1282
1283 NS_DBG("find_operation: there is still ambiguity\n");
1284
1285 ns->pstates[ns->npstates++] = ns->state;
1286
1287 return -1;
1288}
1289
1290static void put_pages(struct nandsim *ns)
1291{
1292 int i;
1293
1294 for (i = 0; i < ns->held_cnt; i++)
1295 page_cache_release(ns->held_pages[i]);
1296}
1297
1298/* Get page cache pages in advance to provide NOFS memory allocation */
1299static int get_pages(struct nandsim *ns, struct file *file, size_t count, loff_t pos)
1300{
1301 pgoff_t index, start_index, end_index;
1302 struct page *page;
1303 struct address_space *mapping = file->f_mapping;
1304
1305 start_index = pos >> PAGE_CACHE_SHIFT;
1306 end_index = (pos + count - 1) >> PAGE_CACHE_SHIFT;
1307 if (end_index - start_index + 1 > NS_MAX_HELD_PAGES)
1308 return -EINVAL;
1309 ns->held_cnt = 0;
1310 for (index = start_index; index <= end_index; index++) {
1311 page = find_get_page(mapping, index);
1312 if (page == NULL) {
1313 page = find_or_create_page(mapping, index, GFP_NOFS);
1314 if (page == NULL) {
1315 write_inode_now(mapping->host, 1);
1316 page = find_or_create_page(mapping, index, GFP_NOFS);
1317 }
1318 if (page == NULL) {
1319 put_pages(ns);
1320 return -ENOMEM;
1321 }
1322 unlock_page(page);
1323 }
1324 ns->held_pages[ns->held_cnt++] = page;
1325 }
1326 return 0;
1327}
1328
1329static int set_memalloc(void)
1330{
1331 if (current->flags & PF_MEMALLOC)
1332 return 0;
1333 current->flags |= PF_MEMALLOC;
1334 return 1;
1335}
1336
1337static void clear_memalloc(int memalloc)
1338{
1339 if (memalloc)
1340 current->flags &= ~PF_MEMALLOC;
1341}
1342
1343static ssize_t read_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t *pos)
1344{
1345 mm_segment_t old_fs;
1346 ssize_t tx;
1347 int err, memalloc;
1348
1349 err = get_pages(ns, file, count, *pos);
1350 if (err)
1351 return err;
1352 old_fs = get_fs();
1353 set_fs(get_ds());
1354 memalloc = set_memalloc();
1355 tx = vfs_read(file, (char __user *)buf, count, pos);
1356 clear_memalloc(memalloc);
1357 set_fs(old_fs);
1358 put_pages(ns);
1359 return tx;
1360}
1361
1362static ssize_t write_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t *pos)
1363{
1364 mm_segment_t old_fs;
1365 ssize_t tx;
1366 int err, memalloc;
1367
1368 err = get_pages(ns, file, count, *pos);
1369 if (err)
1370 return err;
1371 old_fs = get_fs();
1372 set_fs(get_ds());
1373 memalloc = set_memalloc();
1374 tx = vfs_write(file, (char __user *)buf, count, pos);
1375 clear_memalloc(memalloc);
1376 set_fs(old_fs);
1377 put_pages(ns);
1378 return tx;
1379}
1380
1381/*
1382 * Returns a pointer to the current page.
1383 */
1384static inline union ns_mem *NS_GET_PAGE(struct nandsim *ns)
1385{
1386 return &(ns->pages[ns->regs.row]);
1387}
1388
1389/*
1390 * Retuns a pointer to the current byte, within the current page.
1391 */
1392static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns)
1393{
1394 return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off;
1395}
1396
1397int do_read_error(struct nandsim *ns, int num)
1398{
1399 unsigned int page_no = ns->regs.row;
1400
1401 if (read_error(page_no)) {
1402 int i;
1403 memset(ns->buf.byte, 0xFF, num);
1404 for (i = 0; i < num; ++i)
1405 ns->buf.byte[i] = random32();
1406 NS_WARN("simulating read error in page %u\n", page_no);
1407 return 1;
1408 }
1409 return 0;
1410}
1411
1412void do_bit_flips(struct nandsim *ns, int num)
1413{
1414 if (bitflips && random32() < (1 << 22)) {
1415 int flips = 1;
1416 if (bitflips > 1)
1417 flips = (random32() % (int) bitflips) + 1;
1418 while (flips--) {
1419 int pos = random32() % (num * 8);
1420 ns->buf.byte[pos / 8] ^= (1 << (pos % 8));
1421 NS_WARN("read_page: flipping bit %d in page %d "
1422 "reading from %d ecc: corrected=%u failed=%u\n",
1423 pos, ns->regs.row, ns->regs.column + ns->regs.off,
1424 nsmtd->ecc_stats.corrected, nsmtd->ecc_stats.failed);
1425 }
1426 }
1427}
1428
1429/*
1430 * Fill the NAND buffer with data read from the specified page.
1431 */
1432static void read_page(struct nandsim *ns, int num)
1433{
1434 union ns_mem *mypage;
1435
1436 if (ns->cfile) {
1437 if (!ns->pages_written[ns->regs.row]) {
1438 NS_DBG("read_page: page %d not written\n", ns->regs.row);
1439 memset(ns->buf.byte, 0xFF, num);
1440 } else {
1441 loff_t pos;
1442 ssize_t tx;
1443
1444 NS_DBG("read_page: page %d written, reading from %d\n",
1445 ns->regs.row, ns->regs.column + ns->regs.off);
1446 if (do_read_error(ns, num))
1447 return;
1448 pos = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1449 tx = read_file(ns, ns->cfile, ns->buf.byte, num, &pos);
1450 if (tx != num) {
1451 NS_ERR("read_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1452 return;
1453 }
1454 do_bit_flips(ns, num);
1455 }
1456 return;
1457 }
1458
1459 mypage = NS_GET_PAGE(ns);
1460 if (mypage->byte == NULL) {
1461 NS_DBG("read_page: page %d not allocated\n", ns->regs.row);
1462 memset(ns->buf.byte, 0xFF, num);
1463 } else {
1464 NS_DBG("read_page: page %d allocated, reading from %d\n",
1465 ns->regs.row, ns->regs.column + ns->regs.off);
1466 if (do_read_error(ns, num))
1467 return;
1468 memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num);
1469 do_bit_flips(ns, num);
1470 }
1471}
1472
1473/*
1474 * Erase all pages in the specified sector.
1475 */
1476static void erase_sector(struct nandsim *ns)
1477{
1478 union ns_mem *mypage;
1479 int i;
1480
1481 if (ns->cfile) {
1482 for (i = 0; i < ns->geom.pgsec; i++)
1483 if (ns->pages_written[ns->regs.row + i]) {
1484 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row + i);
1485 ns->pages_written[ns->regs.row + i] = 0;
1486 }
1487 return;
1488 }
1489
1490 mypage = NS_GET_PAGE(ns);
1491 for (i = 0; i < ns->geom.pgsec; i++) {
1492 if (mypage->byte != NULL) {
1493 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row+i);
1494 kmem_cache_free(ns->nand_pages_slab, mypage->byte);
1495 mypage->byte = NULL;
1496 }
1497 mypage++;
1498 }
1499}
1500
1501/*
1502 * Program the specified page with the contents from the NAND buffer.
1503 */
1504static int prog_page(struct nandsim *ns, int num)
1505{
1506 int i;
1507 union ns_mem *mypage;
1508 u_char *pg_off;
1509
1510 if (ns->cfile) {
1511 loff_t off, pos;
1512 ssize_t tx;
1513 int all;
1514
1515 NS_DBG("prog_page: writing page %d\n", ns->regs.row);
1516 pg_off = ns->file_buf + ns->regs.column + ns->regs.off;
1517 off = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1518 if (!ns->pages_written[ns->regs.row]) {
1519 all = 1;
1520 memset(ns->file_buf, 0xff, ns->geom.pgszoob);
1521 } else {
1522 all = 0;
1523 pos = off;
1524 tx = read_file(ns, ns->cfile, pg_off, num, &pos);
1525 if (tx != num) {
1526 NS_ERR("prog_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1527 return -1;
1528 }
1529 }
1530 for (i = 0; i < num; i++)
1531 pg_off[i] &= ns->buf.byte[i];
1532 if (all) {
1533 pos = (loff_t)ns->regs.row * ns->geom.pgszoob;
1534 tx = write_file(ns, ns->cfile, ns->file_buf, ns->geom.pgszoob, &pos);
1535 if (tx != ns->geom.pgszoob) {
1536 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1537 return -1;
1538 }
1539 ns->pages_written[ns->regs.row] = 1;
1540 } else {
1541 pos = off;
1542 tx = write_file(ns, ns->cfile, pg_off, num, &pos);
1543 if (tx != num) {
1544 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1545 return -1;
1546 }
1547 }
1548 return 0;
1549 }
1550
1551 mypage = NS_GET_PAGE(ns);
1552 if (mypage->byte == NULL) {
1553 NS_DBG("prog_page: allocating page %d\n", ns->regs.row);
1554 /*
1555 * We allocate memory with GFP_NOFS because a flash FS may
1556 * utilize this. If it is holding an FS lock, then gets here,
1557 * then kernel memory alloc runs writeback which goes to the FS
1558 * again and deadlocks. This was seen in practice.
1559 */
1560 mypage->byte = kmem_cache_alloc(ns->nand_pages_slab, GFP_NOFS);
1561 if (mypage->byte == NULL) {
1562 NS_ERR("prog_page: error allocating memory for page %d\n", ns->regs.row);
1563 return -1;
1564 }
1565 memset(mypage->byte, 0xFF, ns->geom.pgszoob);
1566 }
1567
1568 pg_off = NS_PAGE_BYTE_OFF(ns);
1569 for (i = 0; i < num; i++)
1570 pg_off[i] &= ns->buf.byte[i];
1571
1572 return 0;
1573}
1574
1575/*
1576 * If state has any action bit, perform this action.
1577 *
1578 * RETURNS: 0 if success, -1 if error.
1579 */
1580static int do_state_action(struct nandsim *ns, uint32_t action)
1581{
1582 int num;
1583 int busdiv = ns->busw == 8 ? 1 : 2;
1584 unsigned int erase_block_no, page_no;
1585
1586 action &= ACTION_MASK;
1587
1588 /* Check that page address input is correct */
1589 if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) {
1590 NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row);
1591 return -1;
1592 }
1593
1594 switch (action) {
1595
1596 case ACTION_CPY:
1597 /*
1598 * Copy page data to the internal buffer.
1599 */
1600
1601 /* Column shouldn't be very large */
1602 if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) {
1603 NS_ERR("do_state_action: column number is too large\n");
1604 break;
1605 }
1606 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1607 read_page(ns, num);
1608
1609 NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n",
1610 num, NS_RAW_OFFSET(ns) + ns->regs.off);
1611
1612 if (ns->regs.off == 0)
1613 NS_LOG("read page %d\n", ns->regs.row);
1614 else if (ns->regs.off < ns->geom.pgsz)
1615 NS_LOG("read page %d (second half)\n", ns->regs.row);
1616 else
1617 NS_LOG("read OOB of page %d\n", ns->regs.row);
1618
1619 NS_UDELAY(access_delay);
1620 NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv);
1621
1622 break;
1623
1624 case ACTION_SECERASE:
1625 /*
1626 * Erase sector.
1627 */
1628
1629 if (ns->lines.wp) {
1630 NS_ERR("do_state_action: device is write-protected, ignore sector erase\n");
1631 return -1;
1632 }
1633
1634 if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec
1635 || (ns->regs.row & ~(ns->geom.secsz - 1))) {
1636 NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row);
1637 return -1;
1638 }
1639
1640 ns->regs.row = (ns->regs.row <<
1641 8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column;
1642 ns->regs.column = 0;
1643
1644 erase_block_no = ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift);
1645
1646 NS_DBG("do_state_action: erase sector at address %#x, off = %d\n",
1647 ns->regs.row, NS_RAW_OFFSET(ns));
1648 NS_LOG("erase sector %u\n", erase_block_no);
1649
1650 erase_sector(ns);
1651
1652 NS_MDELAY(erase_delay);
1653
1654 if (erase_block_wear)
1655 update_wear(erase_block_no);
1656
1657 if (erase_error(erase_block_no)) {
1658 NS_WARN("simulating erase failure in erase block %u\n", erase_block_no);
1659 return -1;
1660 }
1661
1662 break;
1663
1664 case ACTION_PRGPAGE:
1665 /*
1666 * Program page - move internal buffer data to the page.
1667 */
1668
1669 if (ns->lines.wp) {
1670 NS_WARN("do_state_action: device is write-protected, programm\n");
1671 return -1;
1672 }
1673
1674 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1675 if (num != ns->regs.count) {
1676 NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n",
1677 ns->regs.count, num);
1678 return -1;
1679 }
1680
1681 if (prog_page(ns, num) == -1)
1682 return -1;
1683
1684 page_no = ns->regs.row;
1685
1686 NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n",
1687 num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off);
1688 NS_LOG("programm page %d\n", ns->regs.row);
1689
1690 NS_UDELAY(programm_delay);
1691 NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv);
1692
1693 if (write_error(page_no)) {
1694 NS_WARN("simulating write failure in page %u\n", page_no);
1695 return -1;
1696 }
1697
1698 break;
1699
1700 case ACTION_ZEROOFF:
1701 NS_DBG("do_state_action: set internal offset to 0\n");
1702 ns->regs.off = 0;
1703 break;
1704
1705 case ACTION_HALFOFF:
1706 if (!(ns->options & OPT_PAGE512_8BIT)) {
1707 NS_ERR("do_state_action: BUG! can't skip half of page for non-512"
1708 "byte page size 8x chips\n");
1709 return -1;
1710 }
1711 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2);
1712 ns->regs.off = ns->geom.pgsz/2;
1713 break;
1714
1715 case ACTION_OOBOFF:
1716 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz);
1717 ns->regs.off = ns->geom.pgsz;
1718 break;
1719
1720 default:
1721 NS_DBG("do_state_action: BUG! unknown action\n");
1722 }
1723
1724 return 0;
1725}
1726
1727/*
1728 * Switch simulator's state.
1729 */
1730static void switch_state(struct nandsim *ns)
1731{
1732 if (ns->op) {
1733 /*
1734 * The current operation have already been identified.
1735 * Just follow the states chain.
1736 */
1737
1738 ns->stateidx += 1;
1739 ns->state = ns->nxstate;
1740 ns->nxstate = ns->op[ns->stateidx + 1];
1741
1742 NS_DBG("switch_state: operation is known, switch to the next state, "
1743 "state: %s, nxstate: %s\n",
1744 get_state_name(ns->state), get_state_name(ns->nxstate));
1745
1746 /* See, whether we need to do some action */
1747 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1748 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1749 return;
1750 }
1751
1752 } else {
1753 /*
1754 * We don't yet know which operation we perform.
1755 * Try to identify it.
1756 */
1757
1758 /*
1759 * The only event causing the switch_state function to
1760 * be called with yet unknown operation is new command.
1761 */
1762 ns->state = get_state_by_command(ns->regs.command);
1763
1764 NS_DBG("switch_state: operation is unknown, try to find it\n");
1765
1766 if (find_operation(ns, 0) != 0)
1767 return;
1768
1769 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1770 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1771 return;
1772 }
1773 }
1774
1775 /* For 16x devices column means the page offset in words */
1776 if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) {
1777 NS_DBG("switch_state: double the column number for 16x device\n");
1778 ns->regs.column <<= 1;
1779 }
1780
1781 if (NS_STATE(ns->nxstate) == STATE_READY) {
1782 /*
1783 * The current state is the last. Return to STATE_READY
1784 */
1785
1786 u_char status = NS_STATUS_OK(ns);
1787
1788 /* In case of data states, see if all bytes were input/output */
1789 if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK))
1790 && ns->regs.count != ns->regs.num) {
1791 NS_WARN("switch_state: not all bytes were processed, %d left\n",
1792 ns->regs.num - ns->regs.count);
1793 status = NS_STATUS_FAILED(ns);
1794 }
1795
1796 NS_DBG("switch_state: operation complete, switch to STATE_READY state\n");
1797
1798 switch_to_ready_state(ns, status);
1799
1800 return;
1801 } else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) {
1802 /*
1803 * If the next state is data input/output, switch to it now
1804 */
1805
1806 ns->state = ns->nxstate;
1807 ns->nxstate = ns->op[++ns->stateidx + 1];
1808 ns->regs.num = ns->regs.count = 0;
1809
1810 NS_DBG("switch_state: the next state is data I/O, switch, "
1811 "state: %s, nxstate: %s\n",
1812 get_state_name(ns->state), get_state_name(ns->nxstate));
1813
1814 /*
1815 * Set the internal register to the count of bytes which
1816 * are expected to be input or output
1817 */
1818 switch (NS_STATE(ns->state)) {
1819 case STATE_DATAIN:
1820 case STATE_DATAOUT:
1821 ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1822 break;
1823
1824 case STATE_DATAOUT_ID:
1825 ns->regs.num = ns->geom.idbytes;
1826 break;
1827
1828 case STATE_DATAOUT_STATUS:
1829 case STATE_DATAOUT_STATUS_M:
1830 ns->regs.count = ns->regs.num = 0;
1831 break;
1832
1833 default:
1834 NS_ERR("switch_state: BUG! unknown data state\n");
1835 }
1836
1837 } else if (ns->nxstate & STATE_ADDR_MASK) {
1838 /*
1839 * If the next state is address input, set the internal
1840 * register to the number of expected address bytes
1841 */
1842
1843 ns->regs.count = 0;
1844
1845 switch (NS_STATE(ns->nxstate)) {
1846 case STATE_ADDR_PAGE:
1847 ns->regs.num = ns->geom.pgaddrbytes;
1848
1849 break;
1850 case STATE_ADDR_SEC:
1851 ns->regs.num = ns->geom.secaddrbytes;
1852 break;
1853
1854 case STATE_ADDR_ZERO:
1855 ns->regs.num = 1;
1856 break;
1857
1858 case STATE_ADDR_COLUMN:
1859 /* Column address is always 2 bytes */
1860 ns->regs.num = ns->geom.pgaddrbytes - ns->geom.secaddrbytes;
1861 break;
1862
1863 default:
1864 NS_ERR("switch_state: BUG! unknown address state\n");
1865 }
1866 } else {
1867 /*
1868 * Just reset internal counters.
1869 */
1870
1871 ns->regs.num = 0;
1872 ns->regs.count = 0;
1873 }
1874}
1875
1876static u_char ns_nand_read_byte(struct mtd_info *mtd)
1877{
1878 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1879 u_char outb = 0x00;
1880
1881 /* Sanity and correctness checks */
1882 if (!ns->lines.ce) {
1883 NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb);
1884 return outb;
1885 }
1886 if (ns->lines.ale || ns->lines.cle) {
1887 NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb);
1888 return outb;
1889 }
1890 if (!(ns->state & STATE_DATAOUT_MASK)) {
1891 NS_WARN("read_byte: unexpected data output cycle, state is %s "
1892 "return %#x\n", get_state_name(ns->state), (uint)outb);
1893 return outb;
1894 }
1895
1896 /* Status register may be read as many times as it is wanted */
1897 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) {
1898 NS_DBG("read_byte: return %#x status\n", ns->regs.status);
1899 return ns->regs.status;
1900 }
1901
1902 /* Check if there is any data in the internal buffer which may be read */
1903 if (ns->regs.count == ns->regs.num) {
1904 NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb);
1905 return outb;
1906 }
1907
1908 switch (NS_STATE(ns->state)) {
1909 case STATE_DATAOUT:
1910 if (ns->busw == 8) {
1911 outb = ns->buf.byte[ns->regs.count];
1912 ns->regs.count += 1;
1913 } else {
1914 outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]);
1915 ns->regs.count += 2;
1916 }
1917 break;
1918 case STATE_DATAOUT_ID:
1919 NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num);
1920 outb = ns->ids[ns->regs.count];
1921 ns->regs.count += 1;
1922 break;
1923 default:
1924 BUG();
1925 }
1926
1927 if (ns->regs.count == ns->regs.num) {
1928 NS_DBG("read_byte: all bytes were read\n");
1929
1930 if (NS_STATE(ns->nxstate) == STATE_READY)
1931 switch_state(ns);
1932 }
1933
1934 return outb;
1935}
1936
1937static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte)
1938{
1939 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1940
1941 /* Sanity and correctness checks */
1942 if (!ns->lines.ce) {
1943 NS_ERR("write_byte: chip is disabled, ignore write\n");
1944 return;
1945 }
1946 if (ns->lines.ale && ns->lines.cle) {
1947 NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n");
1948 return;
1949 }
1950
1951 if (ns->lines.cle == 1) {
1952 /*
1953 * The byte written is a command.
1954 */
1955
1956 if (byte == NAND_CMD_RESET) {
1957 NS_LOG("reset chip\n");
1958 switch_to_ready_state(ns, NS_STATUS_OK(ns));
1959 return;
1960 }
1961
1962 /* Check that the command byte is correct */
1963 if (check_command(byte)) {
1964 NS_ERR("write_byte: unknown command %#x\n", (uint)byte);
1965 return;
1966 }
1967
1968 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS
1969 || NS_STATE(ns->state) == STATE_DATAOUT_STATUS_M
1970 || NS_STATE(ns->state) == STATE_DATAOUT) {
1971 int row = ns->regs.row;
1972
1973 switch_state(ns);
1974 if (byte == NAND_CMD_RNDOUT)
1975 ns->regs.row = row;
1976 }
1977
1978 /* Check if chip is expecting command */
1979 if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) {
1980 /* Do not warn if only 2 id bytes are read */
1981 if (!(ns->regs.command == NAND_CMD_READID &&
1982 NS_STATE(ns->state) == STATE_DATAOUT_ID && ns->regs.count == 2)) {
1983 /*
1984 * We are in situation when something else (not command)
1985 * was expected but command was input. In this case ignore
1986 * previous command(s)/state(s) and accept the last one.
1987 */
1988 NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, "
1989 "ignore previous states\n", (uint)byte, get_state_name(ns->nxstate));
1990 }
1991 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1992 }
1993
1994 NS_DBG("command byte corresponding to %s state accepted\n",
1995 get_state_name(get_state_by_command(byte)));
1996 ns->regs.command = byte;
1997 switch_state(ns);
1998
1999 } else if (ns->lines.ale == 1) {
2000 /*
2001 * The byte written is an address.
2002 */
2003
2004 if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) {
2005
2006 NS_DBG("write_byte: operation isn't known yet, identify it\n");
2007
2008 if (find_operation(ns, 1) < 0)
2009 return;
2010
2011 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
2012 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2013 return;
2014 }
2015
2016 ns->regs.count = 0;
2017 switch (NS_STATE(ns->nxstate)) {
2018 case STATE_ADDR_PAGE:
2019 ns->regs.num = ns->geom.pgaddrbytes;
2020 break;
2021 case STATE_ADDR_SEC:
2022 ns->regs.num = ns->geom.secaddrbytes;
2023 break;
2024 case STATE_ADDR_ZERO:
2025 ns->regs.num = 1;
2026 break;
2027 default:
2028 BUG();
2029 }
2030 }
2031
2032 /* Check that chip is expecting address */
2033 if (!(ns->nxstate & STATE_ADDR_MASK)) {
2034 NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, "
2035 "switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate));
2036 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2037 return;
2038 }
2039
2040 /* Check if this is expected byte */
2041 if (ns->regs.count == ns->regs.num) {
2042 NS_ERR("write_byte: no more address bytes expected\n");
2043 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2044 return;
2045 }
2046
2047 accept_addr_byte(ns, byte);
2048
2049 ns->regs.count += 1;
2050
2051 NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n",
2052 (uint)byte, ns->regs.count, ns->regs.num);
2053
2054 if (ns->regs.count == ns->regs.num) {
2055 NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column);
2056 switch_state(ns);
2057 }
2058
2059 } else {
2060 /*
2061 * The byte written is an input data.
2062 */
2063
2064 /* Check that chip is expecting data input */
2065 if (!(ns->state & STATE_DATAIN_MASK)) {
2066 NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, "
2067 "switch to %s\n", (uint)byte,
2068 get_state_name(ns->state), get_state_name(STATE_READY));
2069 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2070 return;
2071 }
2072
2073 /* Check if this is expected byte */
2074 if (ns->regs.count == ns->regs.num) {
2075 NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n",
2076 ns->regs.num);
2077 return;
2078 }
2079
2080 if (ns->busw == 8) {
2081 ns->buf.byte[ns->regs.count] = byte;
2082 ns->regs.count += 1;
2083 } else {
2084 ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte);
2085 ns->regs.count += 2;
2086 }
2087 }
2088
2089 return;
2090}
2091
2092static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask)
2093{
2094 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2095
2096 ns->lines.cle = bitmask & NAND_CLE ? 1 : 0;
2097 ns->lines.ale = bitmask & NAND_ALE ? 1 : 0;
2098 ns->lines.ce = bitmask & NAND_NCE ? 1 : 0;
2099
2100 if (cmd != NAND_CMD_NONE)
2101 ns_nand_write_byte(mtd, cmd);
2102}
2103
2104static int ns_device_ready(struct mtd_info *mtd)
2105{
2106 NS_DBG("device_ready\n");
2107 return 1;
2108}
2109
2110static uint16_t ns_nand_read_word(struct mtd_info *mtd)
2111{
2112 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
2113
2114 NS_DBG("read_word\n");
2115
2116 return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8);
2117}
2118
2119static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
2120{
2121 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2122
2123 /* Check that chip is expecting data input */
2124 if (!(ns->state & STATE_DATAIN_MASK)) {
2125 NS_ERR("write_buf: data input isn't expected, state is %s, "
2126 "switch to STATE_READY\n", get_state_name(ns->state));
2127 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2128 return;
2129 }
2130
2131 /* Check if these are expected bytes */
2132 if (ns->regs.count + len > ns->regs.num) {
2133 NS_ERR("write_buf: too many input bytes\n");
2134 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2135 return;
2136 }
2137
2138 memcpy(ns->buf.byte + ns->regs.count, buf, len);
2139 ns->regs.count += len;
2140
2141 if (ns->regs.count == ns->regs.num) {
2142 NS_DBG("write_buf: %d bytes were written\n", ns->regs.count);
2143 }
2144}
2145
2146static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
2147{
2148 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2149
2150 /* Sanity and correctness checks */
2151 if (!ns->lines.ce) {
2152 NS_ERR("read_buf: chip is disabled\n");
2153 return;
2154 }
2155 if (ns->lines.ale || ns->lines.cle) {
2156 NS_ERR("read_buf: ALE or CLE pin is high\n");
2157 return;
2158 }
2159 if (!(ns->state & STATE_DATAOUT_MASK)) {
2160 NS_WARN("read_buf: unexpected data output cycle, current state is %s\n",
2161 get_state_name(ns->state));
2162 return;
2163 }
2164
2165 if (NS_STATE(ns->state) != STATE_DATAOUT) {
2166 int i;
2167
2168 for (i = 0; i < len; i++)
2169 buf[i] = ((struct nand_chip *)mtd->priv)->read_byte(mtd);
2170
2171 return;
2172 }
2173
2174 /* Check if these are expected bytes */
2175 if (ns->regs.count + len > ns->regs.num) {
2176 NS_ERR("read_buf: too many bytes to read\n");
2177 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2178 return;
2179 }
2180
2181 memcpy(buf, ns->buf.byte + ns->regs.count, len);
2182 ns->regs.count += len;
2183
2184 if (ns->regs.count == ns->regs.num) {
2185 if (NS_STATE(ns->nxstate) == STATE_READY)
2186 switch_state(ns);
2187 }
2188
2189 return;
2190}
2191
2192static int ns_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
2193{
2194 ns_nand_read_buf(mtd, (u_char *)&ns_verify_buf[0], len);
2195
2196 if (!memcmp(buf, &ns_verify_buf[0], len)) {
2197 NS_DBG("verify_buf: the buffer is OK\n");
2198 return 0;
2199 } else {
2200 NS_DBG("verify_buf: the buffer is wrong\n");
2201 return -EFAULT;
2202 }
2203}
2204
2205/*
2206 * Module initialization function
2207 */
2208static int __init ns_init_module(void)
2209{
2210 struct nand_chip *chip;
2211 struct nandsim *nand;
2212 int retval = -ENOMEM, i;
2213
2214 if (bus_width != 8 && bus_width != 16) {
2215 NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width);
2216 return -EINVAL;
2217 }
2218
2219 /* Allocate and initialize mtd_info, nand_chip and nandsim structures */
2220 nsmtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip)
2221 + sizeof(struct nandsim), GFP_KERNEL);
2222 if (!nsmtd) {
2223 NS_ERR("unable to allocate core structures.\n");
2224 return -ENOMEM;
2225 }
2226 chip = (struct nand_chip *)(nsmtd + 1);
2227 nsmtd->priv = (void *)chip;
2228 nand = (struct nandsim *)(chip + 1);
2229 chip->priv = (void *)nand;
2230
2231 /*
2232 * Register simulator's callbacks.
2233 */
2234 chip->cmd_ctrl = ns_hwcontrol;
2235 chip->read_byte = ns_nand_read_byte;
2236 chip->dev_ready = ns_device_ready;
2237 chip->write_buf = ns_nand_write_buf;
2238 chip->read_buf = ns_nand_read_buf;
2239 chip->verify_buf = ns_nand_verify_buf;
2240 chip->read_word = ns_nand_read_word;
2241 chip->ecc.mode = NAND_ECC_SOFT;
2242 /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
2243 /* and 'badblocks' parameters to work */
2244 chip->options |= NAND_SKIP_BBTSCAN;
2245
2246 switch (bbt) {
2247 case 2:
2248 chip->bbt_options |= NAND_BBT_NO_OOB;
2249 case 1:
2250 chip->bbt_options |= NAND_BBT_USE_FLASH;
2251 case 0:
2252 break;
2253 default:
2254 NS_ERR("bbt has to be 0..2\n");
2255 retval = -EINVAL;
2256 goto error;
2257 }
2258 /*
2259 * Perform minimum nandsim structure initialization to handle
2260 * the initial ID read command correctly
2261 */
2262 if (third_id_byte != 0xFF || fourth_id_byte != 0xFF)
2263 nand->geom.idbytes = 4;
2264 else
2265 nand->geom.idbytes = 2;
2266 nand->regs.status = NS_STATUS_OK(nand);
2267 nand->nxstate = STATE_UNKNOWN;
2268 nand->options |= OPT_PAGE256; /* temporary value */
2269 nand->ids[0] = first_id_byte;
2270 nand->ids[1] = second_id_byte;
2271 nand->ids[2] = third_id_byte;
2272 nand->ids[3] = fourth_id_byte;
2273 if (bus_width == 16) {
2274 nand->busw = 16;
2275 chip->options |= NAND_BUSWIDTH_16;
2276 }
2277
2278 nsmtd->owner = THIS_MODULE;
2279
2280 if ((retval = parse_weakblocks()) != 0)
2281 goto error;
2282
2283 if ((retval = parse_weakpages()) != 0)
2284 goto error;
2285
2286 if ((retval = parse_gravepages()) != 0)
2287 goto error;
2288
2289 retval = nand_scan_ident(nsmtd, 1, NULL);
2290 if (retval) {
2291 NS_ERR("cannot scan NAND Simulator device\n");
2292 if (retval > 0)
2293 retval = -ENXIO;
2294 goto error;
2295 }
2296
2297 if (bch) {
2298 unsigned int eccsteps, eccbytes;
2299 if (!mtd_nand_has_bch()) {
2300 NS_ERR("BCH ECC support is disabled\n");
2301 retval = -EINVAL;
2302 goto error;
2303 }
2304 /* use 512-byte ecc blocks */
2305 eccsteps = nsmtd->writesize/512;
2306 eccbytes = (bch*13+7)/8;
2307 /* do not bother supporting small page devices */
2308 if ((nsmtd->oobsize < 64) || !eccsteps) {
2309 NS_ERR("bch not available on small page devices\n");
2310 retval = -EINVAL;
2311 goto error;
2312 }
2313 if ((eccbytes*eccsteps+2) > nsmtd->oobsize) {
2314 NS_ERR("invalid bch value %u\n", bch);
2315 retval = -EINVAL;
2316 goto error;
2317 }
2318 chip->ecc.mode = NAND_ECC_SOFT_BCH;
2319 chip->ecc.size = 512;
2320 chip->ecc.bytes = eccbytes;
2321 NS_INFO("using %u-bit/%u bytes BCH ECC\n", bch, chip->ecc.size);
2322 }
2323
2324 retval = nand_scan_tail(nsmtd);
2325 if (retval) {
2326 NS_ERR("can't register NAND Simulator\n");
2327 if (retval > 0)
2328 retval = -ENXIO;
2329 goto error;
2330 }
2331
2332 if (overridesize) {
2333 uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
2334 if (new_size >> overridesize != nsmtd->erasesize) {
2335 NS_ERR("overridesize is too big\n");
2336 goto err_exit;
2337 }
2338 /* N.B. This relies on nand_scan not doing anything with the size before we change it */
2339 nsmtd->size = new_size;
2340 chip->chipsize = new_size;
2341 chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
2342 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2343 }
2344
2345 if ((retval = setup_wear_reporting(nsmtd)) != 0)
2346 goto err_exit;
2347
2348 if ((retval = init_nandsim(nsmtd)) != 0)
2349 goto err_exit;
2350
2351 if ((retval = nand_default_bbt(nsmtd)) != 0)
2352 goto err_exit;
2353
2354 if ((retval = parse_badblocks(nand, nsmtd)) != 0)
2355 goto err_exit;
2356
2357 /* Register NAND partitions */
2358 retval = mtd_device_register(nsmtd, &nand->partitions[0],
2359 nand->nbparts);
2360 if (retval != 0)
2361 goto err_exit;
2362
2363 return 0;
2364
2365err_exit:
2366 free_nandsim(nand);
2367 nand_release(nsmtd);
2368 for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i)
2369 kfree(nand->partitions[i].name);
2370error:
2371 kfree(nsmtd);
2372 free_lists();
2373
2374 return retval;
2375}
2376
2377module_init(ns_init_module);
2378
2379/*
2380 * Module clean-up function
2381 */
2382static void __exit ns_cleanup_module(void)
2383{
2384 struct nandsim *ns = ((struct nand_chip *)nsmtd->priv)->priv;
2385 int i;
2386
2387 free_nandsim(ns); /* Free nandsim private resources */
2388 nand_release(nsmtd); /* Unregister driver */
2389 for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i)
2390 kfree(ns->partitions[i].name);
2391 kfree(nsmtd); /* Free other structures */
2392 free_lists();
2393}
2394
2395module_exit(ns_cleanup_module);
2396
2397MODULE_LICENSE ("GPL");
2398MODULE_AUTHOR ("Artem B. Bityuckiy");
2399MODULE_DESCRIPTION ("The NAND flash simulator");