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1/*
2 * Freescale Integrated Flash Controller NAND driver
3 *
4 * Copyright 2011-2012 Freescale Semiconductor, Inc
5 *
6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/module.h>
24#include <linux/types.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/partitions.h>
31#include <linux/mtd/nand_ecc.h>
32#include <asm/fsl_ifc.h>
33
34#define ERR_BYTE 0xFF /* Value returned for read
35 bytes when read failed */
36#define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
37 for IFC NAND Machine */
38
39struct fsl_ifc_ctrl;
40
41/* mtd information per set */
42struct fsl_ifc_mtd {
43 struct mtd_info mtd;
44 struct nand_chip chip;
45 struct fsl_ifc_ctrl *ctrl;
46
47 struct device *dev;
48 int bank; /* Chip select bank number */
49 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
50 u8 __iomem *vbase; /* Chip select base virtual address */
51};
52
53/* overview of the fsl ifc controller */
54struct fsl_ifc_nand_ctrl {
55 struct nand_hw_control controller;
56 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
57
58 u8 __iomem *addr; /* Address of assigned IFC buffer */
59 unsigned int page; /* Last page written to / read from */
60 unsigned int read_bytes;/* Number of bytes read during command */
61 unsigned int column; /* Saved column from SEQIN */
62 unsigned int index; /* Pointer to next byte to 'read' */
63 unsigned int oob; /* Non zero if operating on OOB data */
64 unsigned int eccread; /* Non zero for a full-page ECC read */
65 unsigned int counter; /* counter for the initializations */
66 unsigned int max_bitflips; /* Saved during READ0 cmd */
67};
68
69static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
70
71/* 512-byte page with 4-bit ECC, 8-bit */
72static struct nand_ecclayout oob_512_8bit_ecc4 = {
73 .eccbytes = 8,
74 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
75 .oobfree = { {0, 5}, {6, 2} },
76};
77
78/* 512-byte page with 4-bit ECC, 16-bit */
79static struct nand_ecclayout oob_512_16bit_ecc4 = {
80 .eccbytes = 8,
81 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
82 .oobfree = { {2, 6}, },
83};
84
85/* 2048-byte page size with 4-bit ECC */
86static struct nand_ecclayout oob_2048_ecc4 = {
87 .eccbytes = 32,
88 .eccpos = {
89 8, 9, 10, 11, 12, 13, 14, 15,
90 16, 17, 18, 19, 20, 21, 22, 23,
91 24, 25, 26, 27, 28, 29, 30, 31,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 },
94 .oobfree = { {2, 6}, {40, 24} },
95};
96
97/* 4096-byte page size with 4-bit ECC */
98static struct nand_ecclayout oob_4096_ecc4 = {
99 .eccbytes = 64,
100 .eccpos = {
101 8, 9, 10, 11, 12, 13, 14, 15,
102 16, 17, 18, 19, 20, 21, 22, 23,
103 24, 25, 26, 27, 28, 29, 30, 31,
104 32, 33, 34, 35, 36, 37, 38, 39,
105 40, 41, 42, 43, 44, 45, 46, 47,
106 48, 49, 50, 51, 52, 53, 54, 55,
107 56, 57, 58, 59, 60, 61, 62, 63,
108 64, 65, 66, 67, 68, 69, 70, 71,
109 },
110 .oobfree = { {2, 6}, {72, 56} },
111};
112
113/* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
114static struct nand_ecclayout oob_4096_ecc8 = {
115 .eccbytes = 128,
116 .eccpos = {
117 8, 9, 10, 11, 12, 13, 14, 15,
118 16, 17, 18, 19, 20, 21, 22, 23,
119 24, 25, 26, 27, 28, 29, 30, 31,
120 32, 33, 34, 35, 36, 37, 38, 39,
121 40, 41, 42, 43, 44, 45, 46, 47,
122 48, 49, 50, 51, 52, 53, 54, 55,
123 56, 57, 58, 59, 60, 61, 62, 63,
124 64, 65, 66, 67, 68, 69, 70, 71,
125 72, 73, 74, 75, 76, 77, 78, 79,
126 80, 81, 82, 83, 84, 85, 86, 87,
127 88, 89, 90, 91, 92, 93, 94, 95,
128 96, 97, 98, 99, 100, 101, 102, 103,
129 104, 105, 106, 107, 108, 109, 110, 111,
130 112, 113, 114, 115, 116, 117, 118, 119,
131 120, 121, 122, 123, 124, 125, 126, 127,
132 128, 129, 130, 131, 132, 133, 134, 135,
133 },
134 .oobfree = { {2, 6}, {136, 82} },
135};
136
137
138/*
139 * Generic flash bbt descriptors
140 */
141static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
142static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
143
144static struct nand_bbt_descr bbt_main_descr = {
145 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
146 NAND_BBT_2BIT | NAND_BBT_VERSION,
147 .offs = 2, /* 0 on 8-bit small page */
148 .len = 4,
149 .veroffs = 6,
150 .maxblocks = 4,
151 .pattern = bbt_pattern,
152};
153
154static struct nand_bbt_descr bbt_mirror_descr = {
155 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
156 NAND_BBT_2BIT | NAND_BBT_VERSION,
157 .offs = 2, /* 0 on 8-bit small page */
158 .len = 4,
159 .veroffs = 6,
160 .maxblocks = 4,
161 .pattern = mirror_pattern,
162};
163
164/*
165 * Set up the IFC hardware block and page address fields, and the ifc nand
166 * structure addr field to point to the correct IFC buffer in memory
167 */
168static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
169{
170 struct nand_chip *chip = mtd->priv;
171 struct fsl_ifc_mtd *priv = chip->priv;
172 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
173 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
174 int buf_num;
175
176 ifc_nand_ctrl->page = page_addr;
177 /* Program ROW0/COL0 */
178 out_be32(&ifc->ifc_nand.row0, page_addr);
179 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
180
181 buf_num = page_addr & priv->bufnum_mask;
182
183 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
184 ifc_nand_ctrl->index = column;
185
186 /* for OOB data point to the second half of the buffer */
187 if (oob)
188 ifc_nand_ctrl->index += mtd->writesize;
189}
190
191static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
192{
193 struct nand_chip *chip = mtd->priv;
194 struct fsl_ifc_mtd *priv = chip->priv;
195 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
196 u32 __iomem *mainarea = (u32 *)addr;
197 u8 __iomem *oob = addr + mtd->writesize;
198 int i;
199
200 for (i = 0; i < mtd->writesize / 4; i++) {
201 if (__raw_readl(&mainarea[i]) != 0xffffffff)
202 return 0;
203 }
204
205 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
206 int pos = chip->ecc.layout->eccpos[i];
207
208 if (__raw_readb(&oob[pos]) != 0xff)
209 return 0;
210 }
211
212 return 1;
213}
214
215/* returns nonzero if entire page is blank */
216static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
217 u32 *eccstat, unsigned int bufnum)
218{
219 u32 reg = eccstat[bufnum / 4];
220 int errors;
221
222 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
223
224 return errors;
225}
226
227/*
228 * execute IFC NAND command and wait for it to complete
229 */
230static void fsl_ifc_run_command(struct mtd_info *mtd)
231{
232 struct nand_chip *chip = mtd->priv;
233 struct fsl_ifc_mtd *priv = chip->priv;
234 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
235 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
236 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
237 u32 eccstat[4];
238 int i;
239
240 /* set the chip select for NAND Transaction */
241 out_be32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
242
243 dev_vdbg(priv->dev,
244 "%s: fir0=%08x fcr0=%08x\n",
245 __func__,
246 in_be32(&ifc->ifc_nand.nand_fir0),
247 in_be32(&ifc->ifc_nand.nand_fcr0));
248
249 ctrl->nand_stat = 0;
250
251 /* start read/write seq */
252 out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
253
254 /* wait for command complete flag or timeout */
255 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
256 IFC_TIMEOUT_MSECS * HZ/1000);
257
258 /* ctrl->nand_stat will be updated from IRQ context */
259 if (!ctrl->nand_stat)
260 dev_err(priv->dev, "Controller is not responding\n");
261 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
262 dev_err(priv->dev, "NAND Flash Timeout Error\n");
263 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
264 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
265
266 nctrl->max_bitflips = 0;
267
268 if (nctrl->eccread) {
269 int errors;
270 int bufnum = nctrl->page & priv->bufnum_mask;
271 int sector = bufnum * chip->ecc.steps;
272 int sector_end = sector + chip->ecc.steps - 1;
273
274 for (i = sector / 4; i <= sector_end / 4; i++)
275 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
276
277 for (i = sector; i <= sector_end; i++) {
278 errors = check_read_ecc(mtd, ctrl, eccstat, i);
279
280 if (errors == 15) {
281 /*
282 * Uncorrectable error.
283 * OK only if the whole page is blank.
284 *
285 * We disable ECCER reporting due to...
286 * erratum IFC-A002770 -- so report it now if we
287 * see an uncorrectable error in ECCSTAT.
288 */
289 if (!is_blank(mtd, bufnum))
290 ctrl->nand_stat |=
291 IFC_NAND_EVTER_STAT_ECCER;
292 break;
293 }
294
295 mtd->ecc_stats.corrected += errors;
296 nctrl->max_bitflips = max_t(unsigned int,
297 nctrl->max_bitflips,
298 errors);
299 }
300
301 nctrl->eccread = 0;
302 }
303}
304
305static void fsl_ifc_do_read(struct nand_chip *chip,
306 int oob,
307 struct mtd_info *mtd)
308{
309 struct fsl_ifc_mtd *priv = chip->priv;
310 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
311 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
312
313 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
314 if (mtd->writesize > 512) {
315 out_be32(&ifc->ifc_nand.nand_fir0,
316 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
317 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
318 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
319 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
320 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
321 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
322
323 out_be32(&ifc->ifc_nand.nand_fcr0,
324 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
325 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
326 } else {
327 out_be32(&ifc->ifc_nand.nand_fir0,
328 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
329 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
330 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
331 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
332 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
333
334 if (oob)
335 out_be32(&ifc->ifc_nand.nand_fcr0,
336 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
337 else
338 out_be32(&ifc->ifc_nand.nand_fcr0,
339 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
340 }
341}
342
343/* cmdfunc send commands to the IFC NAND Machine */
344static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
345 int column, int page_addr) {
346 struct nand_chip *chip = mtd->priv;
347 struct fsl_ifc_mtd *priv = chip->priv;
348 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
349 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
350
351 /* clear the read buffer */
352 ifc_nand_ctrl->read_bytes = 0;
353 if (command != NAND_CMD_PAGEPROG)
354 ifc_nand_ctrl->index = 0;
355
356 switch (command) {
357 /* READ0 read the entire buffer to use hardware ECC. */
358 case NAND_CMD_READ0:
359 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
360 set_addr(mtd, 0, page_addr, 0);
361
362 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
363 ifc_nand_ctrl->index += column;
364
365 if (chip->ecc.mode == NAND_ECC_HW)
366 ifc_nand_ctrl->eccread = 1;
367
368 fsl_ifc_do_read(chip, 0, mtd);
369 fsl_ifc_run_command(mtd);
370 return;
371
372 /* READOOB reads only the OOB because no ECC is performed. */
373 case NAND_CMD_READOOB:
374 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
375 set_addr(mtd, column, page_addr, 1);
376
377 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
378
379 fsl_ifc_do_read(chip, 1, mtd);
380 fsl_ifc_run_command(mtd);
381
382 return;
383
384 case NAND_CMD_READID:
385 case NAND_CMD_PARAM: {
386 int timing = IFC_FIR_OP_RB;
387 if (command == NAND_CMD_PARAM)
388 timing = IFC_FIR_OP_RBCD;
389
390 out_be32(&ifc->ifc_nand.nand_fir0,
391 (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
392 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
393 (timing << IFC_NAND_FIR0_OP2_SHIFT));
394 out_be32(&ifc->ifc_nand.nand_fcr0,
395 command << IFC_NAND_FCR0_CMD0_SHIFT);
396 out_be32(&ifc->ifc_nand.row3, column);
397
398 /*
399 * although currently it's 8 bytes for READID, we always read
400 * the maximum 256 bytes(for PARAM)
401 */
402 out_be32(&ifc->ifc_nand.nand_fbcr, 256);
403 ifc_nand_ctrl->read_bytes = 256;
404
405 set_addr(mtd, 0, 0, 0);
406 fsl_ifc_run_command(mtd);
407 return;
408 }
409
410 /* ERASE1 stores the block and page address */
411 case NAND_CMD_ERASE1:
412 set_addr(mtd, 0, page_addr, 0);
413 return;
414
415 /* ERASE2 uses the block and page address from ERASE1 */
416 case NAND_CMD_ERASE2:
417 out_be32(&ifc->ifc_nand.nand_fir0,
418 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
419 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
420 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
421
422 out_be32(&ifc->ifc_nand.nand_fcr0,
423 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
424 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
425
426 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
427 ifc_nand_ctrl->read_bytes = 0;
428 fsl_ifc_run_command(mtd);
429 return;
430
431 /* SEQIN sets up the addr buffer and all registers except the length */
432 case NAND_CMD_SEQIN: {
433 u32 nand_fcr0;
434 ifc_nand_ctrl->column = column;
435 ifc_nand_ctrl->oob = 0;
436
437 if (mtd->writesize > 512) {
438 nand_fcr0 =
439 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
440 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
441
442 out_be32(&ifc->ifc_nand.nand_fir0,
443 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
444 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
445 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
446 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
447 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
448 } else {
449 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
450 IFC_NAND_FCR0_CMD1_SHIFT) |
451 (NAND_CMD_SEQIN <<
452 IFC_NAND_FCR0_CMD2_SHIFT));
453
454 out_be32(&ifc->ifc_nand.nand_fir0,
455 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
456 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
457 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
458 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
459 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
460 out_be32(&ifc->ifc_nand.nand_fir1,
461 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
462
463 if (column >= mtd->writesize)
464 nand_fcr0 |=
465 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
466 else
467 nand_fcr0 |=
468 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
469 }
470
471 if (column >= mtd->writesize) {
472 /* OOB area --> READOOB */
473 column -= mtd->writesize;
474 ifc_nand_ctrl->oob = 1;
475 }
476 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
477 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
478 return;
479 }
480
481 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
482 case NAND_CMD_PAGEPROG: {
483 if (ifc_nand_ctrl->oob) {
484 out_be32(&ifc->ifc_nand.nand_fbcr,
485 ifc_nand_ctrl->index - ifc_nand_ctrl->column);
486 } else {
487 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
488 }
489
490 fsl_ifc_run_command(mtd);
491 return;
492 }
493
494 case NAND_CMD_STATUS:
495 out_be32(&ifc->ifc_nand.nand_fir0,
496 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
497 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
498 out_be32(&ifc->ifc_nand.nand_fcr0,
499 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
500 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
501 set_addr(mtd, 0, 0, 0);
502 ifc_nand_ctrl->read_bytes = 1;
503
504 fsl_ifc_run_command(mtd);
505
506 /*
507 * The chip always seems to report that it is
508 * write-protected, even when it is not.
509 */
510 setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
511 return;
512
513 case NAND_CMD_RESET:
514 out_be32(&ifc->ifc_nand.nand_fir0,
515 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
516 out_be32(&ifc->ifc_nand.nand_fcr0,
517 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
518 fsl_ifc_run_command(mtd);
519 return;
520
521 default:
522 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
523 __func__, command);
524 }
525}
526
527static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
528{
529 /* The hardware does not seem to support multiple
530 * chips per bank.
531 */
532}
533
534/*
535 * Write buf to the IFC NAND Controller Data Buffer
536 */
537static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
538{
539 struct nand_chip *chip = mtd->priv;
540 struct fsl_ifc_mtd *priv = chip->priv;
541 unsigned int bufsize = mtd->writesize + mtd->oobsize;
542
543 if (len <= 0) {
544 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
545 return;
546 }
547
548 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
549 dev_err(priv->dev,
550 "%s: beyond end of buffer (%d requested, %u available)\n",
551 __func__, len, bufsize - ifc_nand_ctrl->index);
552 len = bufsize - ifc_nand_ctrl->index;
553 }
554
555 memcpy_toio(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index], buf, len);
556 ifc_nand_ctrl->index += len;
557}
558
559/*
560 * Read a byte from either the IFC hardware buffer
561 * read function for 8-bit buswidth
562 */
563static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
564{
565 struct nand_chip *chip = mtd->priv;
566 struct fsl_ifc_mtd *priv = chip->priv;
567
568 /*
569 * If there are still bytes in the IFC buffer, then use the
570 * next byte.
571 */
572 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes)
573 return in_8(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index++]);
574
575 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
576 return ERR_BYTE;
577}
578
579/*
580 * Read two bytes from the IFC hardware buffer
581 * read function for 16-bit buswith
582 */
583static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
584{
585 struct nand_chip *chip = mtd->priv;
586 struct fsl_ifc_mtd *priv = chip->priv;
587 uint16_t data;
588
589 /*
590 * If there are still bytes in the IFC buffer, then use the
591 * next byte.
592 */
593 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
594 data = in_be16((uint16_t *)&ifc_nand_ctrl->
595 addr[ifc_nand_ctrl->index]);
596 ifc_nand_ctrl->index += 2;
597 return (uint8_t) data;
598 }
599
600 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
601 return ERR_BYTE;
602}
603
604/*
605 * Read from the IFC Controller Data Buffer
606 */
607static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
608{
609 struct nand_chip *chip = mtd->priv;
610 struct fsl_ifc_mtd *priv = chip->priv;
611 int avail;
612
613 if (len < 0) {
614 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
615 return;
616 }
617
618 avail = min((unsigned int)len,
619 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
620 memcpy_fromio(buf, &ifc_nand_ctrl->addr[ifc_nand_ctrl->index], avail);
621 ifc_nand_ctrl->index += avail;
622
623 if (len > avail)
624 dev_err(priv->dev,
625 "%s: beyond end of buffer (%d requested, %d available)\n",
626 __func__, len, avail);
627}
628
629/*
630 * Verify buffer against the IFC Controller Data Buffer
631 */
632static int fsl_ifc_verify_buf(struct mtd_info *mtd,
633 const u_char *buf, int len)
634{
635 struct nand_chip *chip = mtd->priv;
636 struct fsl_ifc_mtd *priv = chip->priv;
637 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
638 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
639 int i;
640
641 if (len < 0) {
642 dev_err(priv->dev, "%s: write_buf of %d bytes", __func__, len);
643 return -EINVAL;
644 }
645
646 if ((unsigned int)len > nctrl->read_bytes - nctrl->index) {
647 dev_err(priv->dev,
648 "%s: beyond end of buffer (%d requested, %u available)\n",
649 __func__, len, nctrl->read_bytes - nctrl->index);
650
651 nctrl->index = nctrl->read_bytes;
652 return -EINVAL;
653 }
654
655 for (i = 0; i < len; i++)
656 if (in_8(&nctrl->addr[nctrl->index + i]) != buf[i])
657 break;
658
659 nctrl->index += len;
660
661 if (i != len)
662 return -EIO;
663 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
664 return -EIO;
665
666 return 0;
667}
668
669/*
670 * This function is called after Program and Erase Operations to
671 * check for success or failure.
672 */
673static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
674{
675 struct fsl_ifc_mtd *priv = chip->priv;
676 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
677 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
678 u32 nand_fsr;
679
680 /* Use READ_STATUS command, but wait for the device to be ready */
681 out_be32(&ifc->ifc_nand.nand_fir0,
682 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
683 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
684 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
685 IFC_NAND_FCR0_CMD0_SHIFT);
686 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
687 set_addr(mtd, 0, 0, 0);
688 ifc_nand_ctrl->read_bytes = 1;
689
690 fsl_ifc_run_command(mtd);
691
692 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
693
694 /*
695 * The chip always seems to report that it is
696 * write-protected, even when it is not.
697 */
698 return nand_fsr | NAND_STATUS_WP;
699}
700
701static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
702 uint8_t *buf, int oob_required, int page)
703{
704 struct fsl_ifc_mtd *priv = chip->priv;
705 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
706 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
707
708 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
709 if (oob_required)
710 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
711
712 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
713 dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
714
715 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
716 mtd->ecc_stats.failed++;
717
718 return nctrl->max_bitflips;
719}
720
721/* ECC will be calculated automatically, and errors will be detected in
722 * waitfunc.
723 */
724static void fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
725 const uint8_t *buf, int oob_required)
726{
727 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
728 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
729}
730
731static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
732{
733 struct nand_chip *chip = mtd->priv;
734 struct fsl_ifc_mtd *priv = chip->priv;
735
736 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
737 chip->numchips);
738 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
739 chip->chipsize);
740 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
741 chip->pagemask);
742 dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
743 chip->chip_delay);
744 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
745 chip->badblockpos);
746 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
747 chip->chip_shift);
748 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
749 chip->page_shift);
750 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
751 chip->phys_erase_shift);
752 dev_dbg(priv->dev, "%s: nand->ecclayout = %p\n", __func__,
753 chip->ecclayout);
754 dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
755 chip->ecc.mode);
756 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
757 chip->ecc.steps);
758 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
759 chip->ecc.bytes);
760 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
761 chip->ecc.total);
762 dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
763 chip->ecc.layout);
764 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
765 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
766 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
767 mtd->erasesize);
768 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
769 mtd->writesize);
770 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
771 mtd->oobsize);
772
773 return 0;
774}
775
776static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
777{
778 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
779 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
780 struct nand_chip *chip = &priv->chip;
781 struct nand_ecclayout *layout;
782 u32 csor;
783
784 /* Fill in fsl_ifc_mtd structure */
785 priv->mtd.priv = chip;
786 priv->mtd.owner = THIS_MODULE;
787
788 /* fill in nand_chip structure */
789 /* set up function call table */
790 if ((in_be32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
791 chip->read_byte = fsl_ifc_read_byte16;
792 else
793 chip->read_byte = fsl_ifc_read_byte;
794
795 chip->write_buf = fsl_ifc_write_buf;
796 chip->read_buf = fsl_ifc_read_buf;
797 chip->verify_buf = fsl_ifc_verify_buf;
798 chip->select_chip = fsl_ifc_select_chip;
799 chip->cmdfunc = fsl_ifc_cmdfunc;
800 chip->waitfunc = fsl_ifc_wait;
801
802 chip->bbt_td = &bbt_main_descr;
803 chip->bbt_md = &bbt_mirror_descr;
804
805 out_be32(&ifc->ifc_nand.ncfgr, 0x0);
806
807 /* set up nand options */
808 chip->options = NAND_NO_READRDY;
809 chip->bbt_options = NAND_BBT_USE_FLASH;
810
811
812 if (in_be32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
813 chip->read_byte = fsl_ifc_read_byte16;
814 chip->options |= NAND_BUSWIDTH_16;
815 } else {
816 chip->read_byte = fsl_ifc_read_byte;
817 }
818
819 chip->controller = &ifc_nand_ctrl->controller;
820 chip->priv = priv;
821
822 chip->ecc.read_page = fsl_ifc_read_page;
823 chip->ecc.write_page = fsl_ifc_write_page;
824
825 csor = in_be32(&ifc->csor_cs[priv->bank].csor);
826
827 /* Hardware generates ECC per 512 Bytes */
828 chip->ecc.size = 512;
829 chip->ecc.bytes = 8;
830 chip->ecc.strength = 4;
831
832 switch (csor & CSOR_NAND_PGS_MASK) {
833 case CSOR_NAND_PGS_512:
834 if (chip->options & NAND_BUSWIDTH_16) {
835 layout = &oob_512_16bit_ecc4;
836 } else {
837 layout = &oob_512_8bit_ecc4;
838
839 /* Avoid conflict with bad block marker */
840 bbt_main_descr.offs = 0;
841 bbt_mirror_descr.offs = 0;
842 }
843
844 priv->bufnum_mask = 15;
845 break;
846
847 case CSOR_NAND_PGS_2K:
848 layout = &oob_2048_ecc4;
849 priv->bufnum_mask = 3;
850 break;
851
852 case CSOR_NAND_PGS_4K:
853 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
854 CSOR_NAND_ECC_MODE_4) {
855 layout = &oob_4096_ecc4;
856 } else {
857 layout = &oob_4096_ecc8;
858 chip->ecc.bytes = 16;
859 }
860
861 priv->bufnum_mask = 1;
862 break;
863
864 default:
865 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
866 return -ENODEV;
867 }
868
869 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
870 if (csor & CSOR_NAND_ECC_DEC_EN) {
871 chip->ecc.mode = NAND_ECC_HW;
872 chip->ecc.layout = layout;
873 } else {
874 chip->ecc.mode = NAND_ECC_SOFT;
875 }
876
877 return 0;
878}
879
880static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
881{
882 nand_release(&priv->mtd);
883
884 kfree(priv->mtd.name);
885
886 if (priv->vbase)
887 iounmap(priv->vbase);
888
889 ifc_nand_ctrl->chips[priv->bank] = NULL;
890 dev_set_drvdata(priv->dev, NULL);
891 kfree(priv);
892
893 return 0;
894}
895
896static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
897 phys_addr_t addr)
898{
899 u32 cspr = in_be32(&ifc->cspr_cs[bank].cspr);
900
901 if (!(cspr & CSPR_V))
902 return 0;
903 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
904 return 0;
905
906 return (cspr & CSPR_BA) == convert_ifc_address(addr);
907}
908
909static DEFINE_MUTEX(fsl_ifc_nand_mutex);
910
911static int __devinit fsl_ifc_nand_probe(struct platform_device *dev)
912{
913 struct fsl_ifc_regs __iomem *ifc;
914 struct fsl_ifc_mtd *priv;
915 struct resource res;
916 static const char *part_probe_types[]
917 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
918 int ret;
919 int bank;
920 struct device_node *node = dev->dev.of_node;
921 struct mtd_part_parser_data ppdata;
922
923 ppdata.of_node = dev->dev.of_node;
924 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
925 return -ENODEV;
926 ifc = fsl_ifc_ctrl_dev->regs;
927
928 /* get, allocate and map the memory resource */
929 ret = of_address_to_resource(node, 0, &res);
930 if (ret) {
931 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
932 return ret;
933 }
934
935 /* find which chip select it is connected to */
936 for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) {
937 if (match_bank(ifc, bank, res.start))
938 break;
939 }
940
941 if (bank >= FSL_IFC_BANK_COUNT) {
942 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
943 __func__);
944 return -ENODEV;
945 }
946
947 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
948 if (!priv)
949 return -ENOMEM;
950
951 mutex_lock(&fsl_ifc_nand_mutex);
952 if (!fsl_ifc_ctrl_dev->nand) {
953 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
954 if (!ifc_nand_ctrl) {
955 dev_err(&dev->dev, "failed to allocate memory\n");
956 mutex_unlock(&fsl_ifc_nand_mutex);
957 return -ENOMEM;
958 }
959
960 ifc_nand_ctrl->read_bytes = 0;
961 ifc_nand_ctrl->index = 0;
962 ifc_nand_ctrl->addr = NULL;
963 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
964
965 spin_lock_init(&ifc_nand_ctrl->controller.lock);
966 init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
967 } else {
968 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
969 }
970 mutex_unlock(&fsl_ifc_nand_mutex);
971
972 ifc_nand_ctrl->chips[bank] = priv;
973 priv->bank = bank;
974 priv->ctrl = fsl_ifc_ctrl_dev;
975 priv->dev = &dev->dev;
976
977 priv->vbase = ioremap(res.start, resource_size(&res));
978 if (!priv->vbase) {
979 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
980 ret = -ENOMEM;
981 goto err;
982 }
983
984 dev_set_drvdata(priv->dev, priv);
985
986 out_be32(&ifc->ifc_nand.nand_evter_en,
987 IFC_NAND_EVTER_EN_OPC_EN |
988 IFC_NAND_EVTER_EN_FTOER_EN |
989 IFC_NAND_EVTER_EN_WPER_EN);
990
991 /* enable NAND Machine Interrupts */
992 out_be32(&ifc->ifc_nand.nand_evter_intr_en,
993 IFC_NAND_EVTER_INTR_OPCIR_EN |
994 IFC_NAND_EVTER_INTR_FTOERIR_EN |
995 IFC_NAND_EVTER_INTR_WPERIR_EN);
996
997 priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
998 if (!priv->mtd.name) {
999 ret = -ENOMEM;
1000 goto err;
1001 }
1002
1003 ret = fsl_ifc_chip_init(priv);
1004 if (ret)
1005 goto err;
1006
1007 ret = nand_scan_ident(&priv->mtd, 1, NULL);
1008 if (ret)
1009 goto err;
1010
1011 ret = fsl_ifc_chip_init_tail(&priv->mtd);
1012 if (ret)
1013 goto err;
1014
1015 ret = nand_scan_tail(&priv->mtd);
1016 if (ret)
1017 goto err;
1018
1019 /* First look for RedBoot table or partitions on the command
1020 * line, these take precedence over device tree information */
1021 mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
1022 NULL, 0);
1023
1024 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1025 (unsigned long long)res.start, priv->bank);
1026 return 0;
1027
1028err:
1029 fsl_ifc_chip_remove(priv);
1030 return ret;
1031}
1032
1033static int fsl_ifc_nand_remove(struct platform_device *dev)
1034{
1035 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1036
1037 fsl_ifc_chip_remove(priv);
1038
1039 mutex_lock(&fsl_ifc_nand_mutex);
1040 ifc_nand_ctrl->counter--;
1041 if (!ifc_nand_ctrl->counter) {
1042 fsl_ifc_ctrl_dev->nand = NULL;
1043 kfree(ifc_nand_ctrl);
1044 }
1045 mutex_unlock(&fsl_ifc_nand_mutex);
1046
1047 return 0;
1048}
1049
1050static const struct of_device_id fsl_ifc_nand_match[] = {
1051 {
1052 .compatible = "fsl,ifc-nand",
1053 },
1054 {}
1055};
1056
1057static struct platform_driver fsl_ifc_nand_driver = {
1058 .driver = {
1059 .name = "fsl,ifc-nand",
1060 .owner = THIS_MODULE,
1061 .of_match_table = fsl_ifc_nand_match,
1062 },
1063 .probe = fsl_ifc_nand_probe,
1064 .remove = fsl_ifc_nand_remove,
1065};
1066
1067static int __init fsl_ifc_nand_init(void)
1068{
1069 int ret;
1070
1071 ret = platform_driver_register(&fsl_ifc_nand_driver);
1072 if (ret)
1073 printk(KERN_ERR "fsl-ifc: Failed to register platform"
1074 "driver\n");
1075
1076 return ret;
1077}
1078
1079static void __exit fsl_ifc_nand_exit(void)
1080{
1081 platform_driver_unregister(&fsl_ifc_nand_driver);
1082}
1083
1084module_init(fsl_ifc_nand_init);
1085module_exit(fsl_ifc_nand_exit);
1086
1087MODULE_LICENSE("GPL");
1088MODULE_AUTHOR("Freescale");
1089MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");